3 comedi/drivers/adl_pci9111.c
5 Hardware driver for PCI9111 ADLink cards:
9 Copyright (C) 2002-2005 Emmanuel Pacaud <emmanuel.pacaud@univ-poitiers.fr>
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 Description: Adlink PCI-9111HR
29 Author: Emmanuel Pacaud <emmanuel.pacaud@univ-poitiers.fr>
30 Devices: [ADLink] PCI-9111HR (adl_pci9111)
39 - ai_do_cmd mode with the following sources:
42 - scan_begin_src TRIG_FOLLOW TRIG_TIMER TRIG_EXT
43 - convert_src TRIG_TIMER TRIG_EXT
44 - scan_end_src TRIG_COUNT
45 - stop_src TRIG_COUNT TRIG_NONE
47 The scanned channels must be consecutive and start from 0. They must
48 all have the same range and aref.
50 Configuration options: not applicable, uses PCI auto config
56 2005/02/17 Extend AI streaming capabilities. Now, scan_begin_arg can be
57 a multiple of chanlist_len*convert_arg.
58 2002/02/19 Fixed the two's complement conversion in pci9111_(hr_)ai_get_data.
59 2002/02/18 Added external trigger support for analog input.
63 - Really test implemented functionality.
64 - Add support for the PCI-9111DG with a probe routine to identify
65 the card type (perhaps with the help of the channel number readback
66 of the A/D Data register).
67 - Add external multiplexer support.
71 #include <linux/pci.h>
72 #include <linux/delay.h>
73 #include <linux/interrupt.h>
75 #include "../comedidev.h"
79 #include "comedi_fc.h"
81 #define PCI9111_DRIVER_NAME "adl_pci9111"
82 #define PCI9111_HR_DEVICE_ID 0x9111
84 #define PCI9111_FIFO_HALF_SIZE 512
86 #define PCI9111_AI_ACQUISITION_PERIOD_MIN_NS 10000
88 #define PCI9111_RANGE_SETTING_DELAY 10
89 #define PCI9111_AI_INSTANT_READ_UDELAY_US 2
90 #define PCI9111_AI_INSTANT_READ_TIMEOUT 100
92 #define PCI9111_8254_CLOCK_PERIOD_NS 500
95 * IO address map and bit defines
97 #define PCI9111_AI_FIFO_REG 0x00
98 #define PCI9111_AO_REG 0x00
99 #define PCI9111_DIO_REG 0x02
100 #define PCI9111_EDIO_REG 0x04
101 #define PCI9111_AI_CHANNEL_REG 0x06
102 #define PCI9111_AI_RANGE_STAT_REG 0x08
103 #define PCI9111_AI_STAT_AD_BUSY (1 << 7)
104 #define PCI9111_AI_STAT_FF_FF (1 << 6)
105 #define PCI9111_AI_STAT_FF_HF (1 << 5)
106 #define PCI9111_AI_STAT_FF_EF (1 << 4)
107 #define PCI9111_AI_RANGE_MASK (7 << 0)
108 #define PCI9111_AI_TRIG_CTRL_REG 0x0a
109 #define PCI9111_AI_TRIG_CTRL_TRGEVENT (1 << 5)
110 #define PCI9111_AI_TRIG_CTRL_POTRG (1 << 4)
111 #define PCI9111_AI_TRIG_CTRL_PTRG (1 << 3)
112 #define PCI9111_AI_TRIG_CTRL_ETIS (1 << 2)
113 #define PCI9111_AI_TRIG_CTRL_TPST (1 << 1)
114 #define PCI9111_AI_TRIG_CTRL_ASCAN (1 << 0)
115 #define PCI9111_INT_CTRL_REG 0x0c
116 #define PCI9111_INT_CTRL_ISC2 (1 << 3)
117 #define PCI9111_INT_CTRL_FFEN (1 << 2)
118 #define PCI9111_INT_CTRL_ISC1 (1 << 1)
119 #define PCI9111_INT_CTRL_ISC0 (1 << 0)
120 #define PCI9111_SOFT_TRIG_REG 0x0e
121 #define PCI9111_8254_BASE_REG 0x40
122 #define PCI9111_INT_CLR_REG 0x48
124 /* PLX 9052 Local Interrupt 1 enabled and active */
125 #define PCI9111_LI1_ACTIVE (PLX9052_INTCSR_LI1ENAB | \
126 PLX9052_INTCSR_LI1STAT)
128 /* PLX 9052 Local Interrupt 2 enabled and active */
129 #define PCI9111_LI2_ACTIVE (PLX9052_INTCSR_LI2ENAB | \
130 PLX9052_INTCSR_LI2STAT)
132 static const struct comedi_lrange pci9111_ai_range = {
143 struct pci9111_private_data {
144 unsigned long lcr_io_base;
149 unsigned int scan_delay;
150 unsigned int chanlist_len;
151 unsigned int chunk_counter;
152 unsigned int chunk_num_samples;
159 short ai_bounce_buffer[2 * PCI9111_FIFO_HALF_SIZE];
162 static void plx9050_interrupt_control(unsigned long io_base,
164 bool LINTi1_active_high,
166 bool LINTi2_active_high,
167 bool interrupt_enable)
172 flags |= PLX9052_INTCSR_LI1ENAB;
173 if (LINTi1_active_high)
174 flags |= PLX9052_INTCSR_LI1POL;
176 flags |= PLX9052_INTCSR_LI2ENAB;
177 if (LINTi2_active_high)
178 flags |= PLX9052_INTCSR_LI2POL;
180 if (interrupt_enable)
181 flags |= PLX9052_INTCSR_PCIENAB;
183 outb(flags, io_base + PLX9052_INTCSR);
186 static void pci9111_timer_set(struct comedi_device *dev)
188 struct pci9111_private_data *dev_private = dev->private;
189 unsigned long timer_base = dev->iobase + PCI9111_8254_BASE_REG;
191 i8254_set_mode(timer_base, 1, 0, I8254_MODE0 | I8254_BINARY);
192 i8254_set_mode(timer_base, 1, 1, I8254_MODE2 | I8254_BINARY);
193 i8254_set_mode(timer_base, 1, 2, I8254_MODE2 | I8254_BINARY);
197 i8254_write(timer_base, 1, 2, dev_private->div2);
198 i8254_write(timer_base, 1, 1, dev_private->div1);
201 enum pci9111_trigger_sources {
207 static void pci9111_trigger_source_set(struct comedi_device *dev,
208 enum pci9111_trigger_sources source)
212 /* Read the current trigger mode control bits */
213 flags = inb(dev->iobase + PCI9111_AI_TRIG_CTRL_REG);
214 /* Mask off the EITS and TPST bits */
222 flags |= PCI9111_AI_TRIG_CTRL_TPST;
226 flags |= PCI9111_AI_TRIG_CTRL_ETIS;
230 outb(flags, dev->iobase + PCI9111_AI_TRIG_CTRL_REG);
233 static void pci9111_pretrigger_set(struct comedi_device *dev, bool pretrigger)
237 /* Read the current trigger mode control bits */
238 flags = inb(dev->iobase + PCI9111_AI_TRIG_CTRL_REG);
239 /* Mask off the PTRG bit */
243 flags |= PCI9111_AI_TRIG_CTRL_PTRG;
245 outb(flags, dev->iobase + PCI9111_AI_TRIG_CTRL_REG);
248 static void pci9111_autoscan_set(struct comedi_device *dev, bool autoscan)
252 /* Read the current trigger mode control bits */
253 flags = inb(dev->iobase + PCI9111_AI_TRIG_CTRL_REG);
254 /* Mask off the ASCAN bit */
258 flags |= PCI9111_AI_TRIG_CTRL_ASCAN;
260 outb(flags, dev->iobase + PCI9111_AI_TRIG_CTRL_REG);
263 enum pci9111_ISC0_sources {
265 irq_on_fifo_half_full
268 enum pci9111_ISC1_sources {
270 irq_on_external_trigger
273 static void pci9111_interrupt_source_set(struct comedi_device *dev,
274 enum pci9111_ISC0_sources irq_0_source,
275 enum pci9111_ISC1_sources irq_1_source)
279 /* Read the current interrupt control bits */
280 flags = inb(dev->iobase + PCI9111_AI_TRIG_CTRL_REG);
281 /* Shift the bits so they are compatible with the write register */
283 /* Mask off the ISCx bits */
286 /* Now set the new ISCx bits */
287 if (irq_0_source == irq_on_fifo_half_full)
288 flags |= PCI9111_INT_CTRL_ISC0;
290 if (irq_1_source == irq_on_external_trigger)
291 flags |= PCI9111_INT_CTRL_ISC1;
293 outb(flags, dev->iobase + PCI9111_INT_CTRL_REG);
296 static void pci9111_fifo_reset(struct comedi_device *dev)
298 unsigned long int_ctrl_reg = dev->iobase + PCI9111_INT_CTRL_REG;
300 /* To reset the FIFO, set FFEN sequence as 0 -> 1 -> 0 */
301 outb(0, int_ctrl_reg);
302 outb(PCI9111_INT_CTRL_FFEN, int_ctrl_reg);
303 outb(0, int_ctrl_reg);
306 static int pci9111_ai_cancel(struct comedi_device *dev,
307 struct comedi_subdevice *s)
309 struct pci9111_private_data *dev_private = dev->private;
311 /* Disable interrupts */
312 plx9050_interrupt_control(dev_private->lcr_io_base, true, true, true,
315 pci9111_trigger_source_set(dev, software);
317 pci9111_autoscan_set(dev, false);
319 pci9111_fifo_reset(dev);
324 static int pci9111_ai_do_cmd_test(struct comedi_device *dev,
325 struct comedi_subdevice *s,
326 struct comedi_cmd *cmd)
328 struct pci9111_private_data *dev_private = dev->private;
331 int range, reference;
334 /* Step 1 : check if triggers are trivially valid */
336 error |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
337 error |= cfc_check_trigger_src(&cmd->scan_begin_src,
338 TRIG_TIMER | TRIG_FOLLOW | TRIG_EXT);
339 error |= cfc_check_trigger_src(&cmd->convert_src,
340 TRIG_TIMER | TRIG_EXT);
341 error |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
342 error |= cfc_check_trigger_src(&cmd->stop_src,
343 TRIG_COUNT | TRIG_NONE);
348 /* Step 2a : make sure trigger sources are unique */
350 error |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
351 error |= cfc_check_trigger_is_unique(cmd->convert_src);
352 error |= cfc_check_trigger_is_unique(cmd->stop_src);
354 /* Step 2b : and mutually compatible */
356 if ((cmd->convert_src == TRIG_TIMER) &&
357 !((cmd->scan_begin_src == TRIG_TIMER) ||
358 (cmd->scan_begin_src == TRIG_FOLLOW)))
360 if ((cmd->convert_src == TRIG_EXT) &&
361 !((cmd->scan_begin_src == TRIG_EXT) ||
362 (cmd->scan_begin_src == TRIG_FOLLOW)))
368 /* Step 3: check if arguments are trivially valid */
370 error |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
372 if (cmd->convert_src == TRIG_TIMER)
373 error |= cfc_check_trigger_arg_min(&cmd->convert_arg,
374 PCI9111_AI_ACQUISITION_PERIOD_MIN_NS);
376 error |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
378 if (cmd->scan_begin_src == TRIG_TIMER)
379 error |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
380 PCI9111_AI_ACQUISITION_PERIOD_MIN_NS);
381 else /* TRIG_FOLLOW || TRIG_EXT */
382 error |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
384 error |= cfc_check_trigger_arg_is(&cmd->scan_end_arg,
387 if (cmd->stop_src == TRIG_COUNT)
388 error |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
390 error |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
395 /* Step 4 : fix up any arguments */
397 if (cmd->convert_src == TRIG_TIMER) {
398 tmp = cmd->convert_arg;
399 i8253_cascade_ns_to_timer_2div(PCI9111_8254_CLOCK_PERIOD_NS,
403 cmd->flags & TRIG_ROUND_MASK);
404 if (tmp != cmd->convert_arg)
407 /* There's only one timer on this card, so the scan_begin timer must */
408 /* be a multiple of chanlist_len*convert_arg */
410 if (cmd->scan_begin_src == TRIG_TIMER) {
412 unsigned int scan_begin_min;
413 unsigned int scan_begin_arg;
414 unsigned int scan_factor;
416 scan_begin_min = cmd->chanlist_len * cmd->convert_arg;
418 if (cmd->scan_begin_arg != scan_begin_min) {
419 if (scan_begin_min < cmd->scan_begin_arg) {
421 cmd->scan_begin_arg / scan_begin_min;
422 scan_begin_arg = scan_factor * scan_begin_min;
423 if (cmd->scan_begin_arg != scan_begin_arg) {
424 cmd->scan_begin_arg = scan_begin_arg;
428 cmd->scan_begin_arg = scan_begin_min;
437 /* Step 5 : check channel list */
441 range = CR_RANGE(cmd->chanlist[0]);
442 reference = CR_AREF(cmd->chanlist[0]);
444 if (cmd->chanlist_len > 1) {
445 for (i = 0; i < cmd->chanlist_len; i++) {
446 if (CR_CHAN(cmd->chanlist[i]) != i) {
448 "entries in chanlist must be consecutive "
449 "channels,counting upwards from 0\n");
452 if (CR_RANGE(cmd->chanlist[i]) != range) {
454 "entries in chanlist must all have the same gain\n");
457 if (CR_AREF(cmd->chanlist[i]) != reference) {
459 "entries in chanlist must all have the same reference\n");
473 static int pci9111_ai_do_cmd(struct comedi_device *dev,
474 struct comedi_subdevice *s)
476 struct pci9111_private_data *dev_private = dev->private;
477 struct comedi_cmd *async_cmd = &s->async->cmd;
481 "no irq assigned for PCI9111, cannot do hardware conversion");
484 /* Set channel scan limit */
485 /* PCI9111 allows only scanning from channel 0 to channel n */
486 /* TODO: handle the case of an external multiplexer */
488 if (async_cmd->chanlist_len > 1) {
489 outb(async_cmd->chanlist_len - 1,
490 dev->iobase + PCI9111_AI_CHANNEL_REG);
491 pci9111_autoscan_set(dev, true);
493 outb(CR_CHAN(async_cmd->chanlist[0]),
494 dev->iobase + PCI9111_AI_CHANNEL_REG);
495 pci9111_autoscan_set(dev, false);
499 /* This is the same gain on every channel */
501 outb(CR_RANGE(async_cmd->chanlist[0]) & PCI9111_AI_RANGE_MASK,
502 dev->iobase + PCI9111_AI_RANGE_STAT_REG);
506 switch (async_cmd->stop_src) {
508 dev_private->stop_counter =
509 async_cmd->stop_arg * async_cmd->chanlist_len;
510 dev_private->stop_is_none = 0;
514 dev_private->stop_counter = 0;
515 dev_private->stop_is_none = 1;
519 comedi_error(dev, "Invalid stop trigger");
523 /* Set timer pacer */
525 dev_private->scan_delay = 0;
526 switch (async_cmd->convert_src) {
528 pci9111_trigger_source_set(dev, software);
529 pci9111_timer_set(dev);
530 pci9111_fifo_reset(dev);
531 pci9111_interrupt_source_set(dev, irq_on_fifo_half_full,
533 pci9111_trigger_source_set(dev, timer_pacer);
534 plx9050_interrupt_control(dev_private->lcr_io_base, true, true,
537 if (async_cmd->scan_begin_src == TRIG_TIMER) {
538 dev_private->scan_delay =
539 (async_cmd->scan_begin_arg /
540 (async_cmd->convert_arg *
541 async_cmd->chanlist_len)) - 1;
548 pci9111_trigger_source_set(dev, external);
549 pci9111_fifo_reset(dev);
550 pci9111_interrupt_source_set(dev, irq_on_fifo_half_full,
552 plx9050_interrupt_control(dev_private->lcr_io_base, true, true,
558 comedi_error(dev, "Invalid convert trigger");
562 dev_private->stop_counter *= (1 + dev_private->scan_delay);
563 dev_private->chanlist_len = async_cmd->chanlist_len;
564 dev_private->chunk_counter = 0;
565 dev_private->chunk_num_samples =
566 dev_private->chanlist_len * (1 + dev_private->scan_delay);
571 static void pci9111_ai_munge(struct comedi_device *dev,
572 struct comedi_subdevice *s, void *data,
573 unsigned int num_bytes,
574 unsigned int start_chan_index)
577 unsigned int maxdata = s->maxdata;
578 unsigned int invert = (maxdata + 1) >> 1;
579 unsigned int shift = (maxdata == 0xffff) ? 0 : 4;
580 unsigned int num_samples = num_bytes / sizeof(short);
583 for (i = 0; i < num_samples; i++)
584 array[i] = ((array[i] >> shift) & maxdata) ^ invert;
587 static irqreturn_t pci9111_interrupt(int irq, void *p_device)
589 struct comedi_device *dev = p_device;
590 struct pci9111_private_data *dev_private = dev->private;
591 struct comedi_subdevice *s = dev->read_subdev;
592 struct comedi_async *async;
594 unsigned long irq_flags;
595 unsigned char intcsr;
597 if (!dev->attached) {
598 /* Ignore interrupt before device fully attached. */
599 /* Might not even have allocated subdevices yet! */
605 spin_lock_irqsave(&dev->spinlock, irq_flags);
607 /* Check if we are source of interrupt */
608 intcsr = inb(dev_private->lcr_io_base + PLX9052_INTCSR);
609 if (!(((intcsr & PLX9052_INTCSR_PCIENAB) != 0) &&
610 (((intcsr & PCI9111_LI1_ACTIVE) == PCI9111_LI1_ACTIVE) ||
611 ((intcsr & PCI9111_LI2_ACTIVE) == PCI9111_LI2_ACTIVE)))) {
612 /* Not the source of the interrupt. */
613 /* (N.B. not using PLX9052_INTCSR_SOFTINT) */
614 spin_unlock_irqrestore(&dev->spinlock, irq_flags);
618 if ((intcsr & PCI9111_LI1_ACTIVE) == PCI9111_LI1_ACTIVE) {
619 /* Interrupt comes from fifo_half-full signal */
621 status = inb(dev->iobase + PCI9111_AI_RANGE_STAT_REG);
623 /* '0' means FIFO is full, data may have been lost */
624 if (!(status & PCI9111_AI_STAT_FF_FF)) {
625 spin_unlock_irqrestore(&dev->spinlock, irq_flags);
626 comedi_error(dev, PCI9111_DRIVER_NAME " fifo overflow");
627 outb(0, dev->iobase + PCI9111_INT_CLR_REG);
628 pci9111_ai_cancel(dev, s);
629 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
630 comedi_event(dev, s);
635 /* '0' means FIFO is half-full */
636 if (!(status & PCI9111_AI_STAT_FF_HF)) {
637 unsigned int num_samples;
638 unsigned int bytes_written = 0;
641 PCI9111_FIFO_HALF_SIZE >
642 dev_private->stop_counter
644 stop_is_none ? dev_private->stop_counter :
645 PCI9111_FIFO_HALF_SIZE;
646 insw(dev->iobase + PCI9111_AI_FIFO_REG,
647 dev_private->ai_bounce_buffer, num_samples);
649 if (dev_private->scan_delay < 1) {
651 cfc_write_array_to_buffer(s,
660 while (position < num_samples) {
661 if (dev_private->chunk_counter <
662 dev_private->chanlist_len) {
664 dev_private->chanlist_len -
665 dev_private->chunk_counter;
668 num_samples - position)
674 cfc_write_array_to_buffer
676 dev_private->ai_bounce_buffer
678 to_read * sizeof(short));
681 dev_private->chunk_num_samples
683 dev_private->chunk_counter;
685 num_samples - position)
691 sizeof(short) * to_read;
695 dev_private->chunk_counter += to_read;
697 if (dev_private->chunk_counter >=
698 dev_private->chunk_num_samples)
699 dev_private->chunk_counter = 0;
703 dev_private->stop_counter -=
704 bytes_written / sizeof(short);
708 if ((dev_private->stop_counter == 0) && (!dev_private->stop_is_none)) {
709 async->events |= COMEDI_CB_EOA;
710 pci9111_ai_cancel(dev, s);
713 outb(0, dev->iobase + PCI9111_INT_CLR_REG);
715 spin_unlock_irqrestore(&dev->spinlock, irq_flags);
717 comedi_event(dev, s);
722 static int pci9111_ai_insn_read(struct comedi_device *dev,
723 struct comedi_subdevice *s,
724 struct comedi_insn *insn, unsigned int *data)
726 unsigned int chan = CR_CHAN(insn->chanspec);
727 unsigned int range = CR_RANGE(insn->chanspec);
728 unsigned int maxdata = s->maxdata;
729 unsigned int invert = (maxdata + 1) >> 1;
730 unsigned int shift = (maxdata == 0xffff) ? 0 : 4;
735 outb(chan, dev->iobase + PCI9111_AI_CHANNEL_REG);
737 status = inb(dev->iobase + PCI9111_AI_RANGE_STAT_REG);
738 if ((status & PCI9111_AI_RANGE_MASK) != range) {
739 outb(range & PCI9111_AI_RANGE_MASK,
740 dev->iobase + PCI9111_AI_RANGE_STAT_REG);
743 pci9111_fifo_reset(dev);
745 for (i = 0; i < insn->n; i++) {
746 /* Generate a software trigger */
747 outb(0, dev->iobase + PCI9111_SOFT_TRIG_REG);
749 timeout = PCI9111_AI_INSTANT_READ_TIMEOUT;
752 status = inb(dev->iobase + PCI9111_AI_RANGE_STAT_REG);
753 /* '1' means FIFO is not empty */
754 if (status & PCI9111_AI_STAT_FF_EF)
755 goto conversion_done;
758 comedi_error(dev, "A/D read timeout");
760 pci9111_fifo_reset(dev);
765 data[i] = inw(dev->iobase + PCI9111_AI_FIFO_REG);
766 data[i] = ((data[i] >> shift) & maxdata) ^ invert;
772 static int pci9111_ao_insn_write(struct comedi_device *dev,
773 struct comedi_subdevice *s,
774 struct comedi_insn *insn,
777 struct pci9111_private_data *dev_private = dev->private;
778 unsigned int val = 0;
781 for (i = 0; i < insn->n; i++) {
783 outw(val, dev->iobase + PCI9111_AO_REG);
785 dev_private->ao_readback = val;
790 static int pci9111_ao_insn_read(struct comedi_device *dev,
791 struct comedi_subdevice *s,
792 struct comedi_insn *insn,
795 struct pci9111_private_data *dev_private = dev->private;
798 for (i = 0; i < insn->n; i++)
799 data[i] = dev_private->ao_readback;
804 static int pci9111_di_insn_bits(struct comedi_device *dev,
805 struct comedi_subdevice *s,
806 struct comedi_insn *insn,
809 data[1] = inw(dev->iobase + PCI9111_DIO_REG);
814 static int pci9111_do_insn_bits(struct comedi_device *dev,
815 struct comedi_subdevice *s,
816 struct comedi_insn *insn,
819 unsigned int mask = data[0];
820 unsigned int bits = data[1];
824 s->state |= (bits & mask);
826 outw(s->state, dev->iobase + PCI9111_DIO_REG);
834 static int pci9111_reset(struct comedi_device *dev)
836 struct pci9111_private_data *dev_private = dev->private;
838 /* Set trigger source to software */
839 plx9050_interrupt_control(dev_private->lcr_io_base, true, true, true,
842 pci9111_trigger_source_set(dev, software);
843 pci9111_pretrigger_set(dev, false);
844 pci9111_autoscan_set(dev, false);
846 /* Reset 8254 chip */
847 dev_private->div1 = 0;
848 dev_private->div2 = 0;
849 pci9111_timer_set(dev);
854 static int pci9111_auto_attach(struct comedi_device *dev,
855 unsigned long context_unused)
857 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
858 struct pci9111_private_data *dev_private;
859 struct comedi_subdevice *s;
862 dev_private = kzalloc(sizeof(*dev_private), GFP_KERNEL);
865 dev->private = dev_private;
867 ret = comedi_pci_enable(dev);
870 dev_private->lcr_io_base = pci_resource_start(pcidev, 1);
871 dev->iobase = pci_resource_start(pcidev, 2);
875 if (pcidev->irq > 0) {
876 ret = request_irq(dev->irq, pci9111_interrupt,
877 IRQF_SHARED, dev->board_name, dev);
880 dev->irq = pcidev->irq;
883 ret = comedi_alloc_subdevices(dev, 4);
887 s = &dev->subdevices[0];
888 dev->read_subdev = s;
889 s->type = COMEDI_SUBD_AI;
890 s->subdev_flags = SDF_READABLE | SDF_COMMON | SDF_CMD_READ;
893 s->len_chanlist = 16;
894 s->range_table = &pci9111_ai_range;
895 s->cancel = pci9111_ai_cancel;
896 s->insn_read = pci9111_ai_insn_read;
897 s->do_cmdtest = pci9111_ai_do_cmd_test;
898 s->do_cmd = pci9111_ai_do_cmd;
899 s->munge = pci9111_ai_munge;
901 s = &dev->subdevices[1];
902 s->type = COMEDI_SUBD_AO;
903 s->subdev_flags = SDF_WRITABLE | SDF_COMMON;
907 s->range_table = &range_bipolar10;
908 s->insn_write = pci9111_ao_insn_write;
909 s->insn_read = pci9111_ao_insn_read;
911 s = &dev->subdevices[2];
912 s->type = COMEDI_SUBD_DI;
913 s->subdev_flags = SDF_READABLE;
916 s->range_table = &range_digital;
917 s->insn_bits = pci9111_di_insn_bits;
919 s = &dev->subdevices[3];
920 s->type = COMEDI_SUBD_DO;
921 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
924 s->range_table = &range_digital;
925 s->insn_bits = pci9111_do_insn_bits;
927 dev_info(dev->class_dev, "%s attached\n", dev->board_name);
932 static void pci9111_detach(struct comedi_device *dev)
937 free_irq(dev->irq, dev);
938 comedi_pci_disable(dev);
941 static struct comedi_driver adl_pci9111_driver = {
942 .driver_name = "adl_pci9111",
943 .module = THIS_MODULE,
944 .auto_attach = pci9111_auto_attach,
945 .detach = pci9111_detach,
948 static int pci9111_pci_probe(struct pci_dev *dev,
949 const struct pci_device_id *id)
951 return comedi_pci_auto_config(dev, &adl_pci9111_driver,
955 static DEFINE_PCI_DEVICE_TABLE(pci9111_pci_table) = {
956 { PCI_DEVICE(PCI_VENDOR_ID_ADLINK, PCI9111_HR_DEVICE_ID) },
957 /* { PCI_DEVICE(PCI_VENDOR_ID_ADLINK, PCI9111_HG_DEVICE_ID) }, */
960 MODULE_DEVICE_TABLE(pci, pci9111_pci_table);
962 static struct pci_driver adl_pci9111_pci_driver = {
963 .name = "adl_pci9111",
964 .id_table = pci9111_pci_table,
965 .probe = pci9111_pci_probe,
966 .remove = comedi_pci_auto_unconfig,
968 module_comedi_pci_driver(adl_pci9111_driver, adl_pci9111_pci_driver);
970 MODULE_AUTHOR("Comedi http://www.comedi.org");
971 MODULE_DESCRIPTION("Comedi low-level driver");
972 MODULE_LICENSE("GPL");