2 * comedi/drivers/adl_pci9118.c
4 * hardware driver for ADLink cards:
5 * card: PCI-9118DG, PCI-9118HG, PCI-9118HR
6 * driver: pci9118dg, pci9118hg, pci9118hr
8 * Author: Michal Dobes <dobes@tesnet.cz>
14 * Description: Adlink PCI-9118DG, PCI-9118HG, PCI-9118HR
15 * Author: Michal Dobes <dobes@tesnet.cz>
16 * Devices: [ADLink] PCI-9118DG (pci9118dg), PCI-9118HG (pci9118hg),
17 * PCI-9118HR (pci9118hr)
20 * This driver supports AI, AO, DI and DO subdevices.
21 * AI subdevice supports cmd and insn interface,
22 * other subdevices support only insn interface.
24 * - If cmd->scan_begin_src=TRIG_EXT then trigger input is TGIN (pin 46).
25 * - If cmd->convert_src=TRIG_EXT then trigger input is EXTTRG (pin 44).
26 * - If cmd->start_src/stop_src=TRIG_EXT then trigger input is TGIN (pin 46).
27 * - It is not necessary to have cmd.scan_end_arg=cmd.chanlist_len but
28 * cmd.scan_end_arg modulo cmd.chanlist_len must by 0.
29 * - If return value of cmdtest is 5 then you've bad channel list
30 * (it isn't possible mixture S.E. and DIFF inputs or bipolar and unipolar
33 * There are some hardware limitations:
34 * a) You cann't use mixture of unipolar/bipoar ranges or differencial/single
36 * b) DMA transfers must have the length aligned to two samples (32 bit),
37 * so there is some problems if cmd->chanlist_len is odd. This driver tries
38 * bypass this with adding one sample to the end of the every scan and discard
39 * it on output but this can't be used if cmd->scan_begin_src=TRIG_FOLLOW
40 * and is used flag CMDF_WAKE_EOS, then driver switch to interrupt driven mode
41 * with interrupt after every sample.
42 * c) If isn't used DMA then you can use only mode where
43 * cmd->scan_begin_src=TRIG_FOLLOW.
45 * Configuration options:
46 * [0] - PCI bus of device (optional)
47 * [1] - PCI slot of device (optional)
48 * If bus/slot is not specified, then first available PCI
50 * [2] - 0= standard 8 DIFF/16 SE channels configuration
51 * n = external multiplexer connected, 1 <= n <= 256
53 * [4] - sample&hold signal - card can generate signal for external S&H board
54 * 0 = use SSHO(pin 45) signal is generated in onboard hardware S&H logic
55 * 0 != use ADCHN7(pin 23) signal is generated from driver, number say how
56 * long delay is requested in ns and sign polarity of the hold
57 * (in this case external multiplexor can serve only 128 channels)
64 * All the supported boards have the same PCI vendor and device IDs, so
65 * auto-attachment of PCI devices will always find the first board type.
67 * Perhaps the boards have different subdevice IDs that we could use to
70 * Need some device attributes so the board type can be corrected after
71 * attachment if necessary, and possibly to set other options supported by
75 #include <linux/module.h>
76 #include <linux/pci.h>
77 #include <linux/delay.h>
78 #include <linux/gfp.h>
79 #include <linux/interrupt.h>
82 #include "../comedidev.h"
84 #include "amcc_s5933.h"
86 #include "comedi_fc.h"
88 #define IORANGE_9118 64 /* I hope */
89 #define PCI9118_CHANLEN 255 /*
90 * len of chanlist, some source say 256,
91 * but reality looks like 255 :-(
95 * PCI BAR2 Register map (dev->iobase)
97 #define PCI9118_TIMER_REG(x) (0x00 + ((x) * 4))
98 #define PCI9118_TIMER_CTRL_REG 0x0c
99 #define PCI9118_AI_FIFO_REG 0x10
100 #define PCI9118_AO_REG(x) (0x10 + ((x) * 4))
101 #define PCI9118_AI_STATUS_REG 0x18
102 #define PCI9118_AI_STATUS_NFULL (1 << 8) /* 0=FIFO full (fatal) */
103 #define PCI9118_AI_STATUS_NHFULL (1 << 7) /* 0=FIFO half full */
104 #define PCI9118_AI_STATUS_NEPTY (1 << 6) /* 0=FIFO empty */
105 #define PCI9118_AI_STATUS_ACMP (1 << 5) /* 1=about trigger complete */
106 #define PCI9118_AI_STATUS_DTH (1 << 4) /* 1=ext. digital trigger */
107 #define PCI9118_AI_STATUS_BOVER (1 << 3) /* 1=burst overrun (fatal) */
108 #define PCI9118_AI_STATUS_ADOS (1 << 2) /* 1=A/D over speed (warn) */
109 #define PCI9118_AI_STATUS_ADOR (1 << 1) /* 1=A/D overrun (fatal) */
110 #define PCI9118_AI_STATUS_ADRDY (1 << 0) /* 1=A/D ready */
111 #define PCI9118_AI_CTRL_REG 0x18
112 #define PCI9118_AI_CTRL_UNIP (1 << 7) /* 1=unipolar */
113 #define PCI9118_AI_CTRL_DIFF (1 << 6) /* 1=differential inputs */
114 #define PCI9118_AI_CTRL_SOFTG (1 << 5) /* 1=8254 software gate */
115 #define PCI9118_AI_CTRL_EXTG (1 << 4) /* 1=8254 TGIN(pin 46) gate */
116 #define PCI9118_AI_CTRL_EXTM (1 << 3) /* 1=ext. trigger (pin 44) */
117 #define PCI9118_AI_CTRL_TMRTR (1 << 2) /* 1=8254 is trigger source */
118 #define PCI9118_AI_CTRL_INT (1 << 1) /* 1=enable interrupt */
119 #define PCI9118_AI_CTRL_DMA (1 << 0) /* 1=enable DMA */
120 #define PCI9118_DIO_REG 0x1c
121 #define PCI9118_SOFTTRG_REG 0x20
122 #define PCI9118_AI_CHANLIST_REG 0x24
123 #define PCI9118_AI_CHANLIST_RANGE(x) (((x) & 0x3) << 8)
124 #define PCI9118_AI_CHANLIST_CHAN(x) ((x) << 0)
125 #define PCI9118_AI_BURST_NUM_REG 0x28
126 #define PCI9118_AI_AUTOSCAN_MODE_REG 0x2c
127 #define PCI9118_AI_CFG_REG 0x30
128 #define PCI9118_AI_CFG_PDTRG (1 << 7) /* 1=positive trigger */
129 #define PCI9118_AI_CFG_PETRG (1 << 6) /* 1=positive ext. trigger */
130 #define PCI9118_AI_CFG_BSSH (1 << 5) /* 1=with sample & hold */
131 #define PCI9118_AI_CFG_BM (1 << 4) /* 1=burst mode */
132 #define PCI9118_AI_CFG_BS (1 << 3) /* 1=burst mode start */
133 #define PCI9118_AI_CFG_PM (1 << 2) /* 1=post trigger */
134 #define PCI9118_AI_CFG_AM (1 << 1) /* 1=about trigger */
135 #define PCI9118_AI_CFG_START (1 << 0) /* 1=trigger start */
136 #define PCI9118_FIFO_RESET_REG 0x34
137 #define PCI9118_INT_CTRL_REG 0x38
138 #define PCI9118_INT_CTRL_TIMER (1 << 3) /* timer interrupt */
139 #define PCI9118_INT_CTRL_ABOUT (1 << 2) /* about trigger complete */
140 #define PCI9118_INT_CTRL_HFULL (1 << 1) /* A/D FIFO half full */
141 #define PCI9118_INT_CTRL_DTRG (1 << 0) /* ext. digital trigger */
143 #define START_AI_EXT 0x01 /* start measure on external trigger */
144 #define STOP_AI_EXT 0x02 /* stop measure on external trigger */
145 #define STOP_AI_INT 0x08 /* stop measure on internal trigger */
147 #define PCI9118_HALF_FIFO_SZ (1024 / 2)
149 static const struct comedi_lrange pci9118_ai_range = {
162 static const struct comedi_lrange pci9118hg_ai_range = {
175 #define PCI9118_BIPOLAR_RANGES 4 /*
176 * used for test on mixture
180 enum pci9118_boardid {
186 struct pci9118_boardinfo {
188 unsigned int ai_is_16bit:1;
189 unsigned int is_hg:1;
192 static const struct pci9118_boardinfo pci9118_boards[] = {
193 [BOARD_PCI9118DG] = {
196 [BOARD_PCI9118HG] = {
200 [BOARD_PCI9118HR] = {
206 struct pci9118_dmabuf {
207 unsigned short *virt; /* virtual address of buffer */
208 dma_addr_t hw; /* hardware (bus) address of buffer */
209 unsigned int size; /* size of dma buffer in bytes */
210 unsigned int use_size; /* which size we may now use for transfer */
213 struct pci9118_private {
214 unsigned long iobase_a; /* base+size for AMCC chip */
215 unsigned int master:1;
216 unsigned int dma_doublebuf:1;
217 unsigned int ai_neverending:1;
218 unsigned int usedma:1;
219 unsigned int usemux:1;
220 unsigned char ai_ctrl;
221 unsigned char int_ctrl;
222 unsigned char ai_cfg;
223 unsigned int ai_do; /* what do AI? 0=nothing, 1 to 4 mode */
224 unsigned int ai_n_realscanlen; /*
225 * what we must transfer for one
226 * outgoing scan include front/back adds
228 unsigned int ai_act_dmapos; /* position in actual real stream */
229 unsigned int ai_add_front; /*
230 * how many channels we must add
231 * before scan to satisfy S&H?
233 unsigned int ai_add_back; /*
234 * how many channels we must add
235 * before scan to satisfy DMA?
237 unsigned int ai_flags;
238 char ai12_startstop; /*
239 * measure can start/stop
240 * on external trigger
242 unsigned int ai_divisor1, ai_divisor2; /*
243 * divisors for start of measure
246 unsigned int dma_actbuf; /* which buffer is used now */
247 struct pci9118_dmabuf dmabuf[2];
249 * >0 use software S&H,
250 * numer is requested delay in ns
252 unsigned char softsshsample; /*
253 * polarity of S&H signal
256 unsigned char softsshhold; /*
257 * polarity of S&H signal
260 unsigned int ai_ns_min;
263 static void pci9118_amcc_setup_dma(struct comedi_device *dev, unsigned int buf)
265 struct pci9118_private *devpriv = dev->private;
266 struct pci9118_dmabuf *dmabuf = &devpriv->dmabuf[buf];
268 /* set the master write address and transfer count */
269 outl(dmabuf->hw, devpriv->iobase_a + AMCC_OP_REG_MWAR);
270 outl(dmabuf->use_size, devpriv->iobase_a + AMCC_OP_REG_MWTC);
273 static void pci9118_amcc_dma_ena(struct comedi_device *dev, bool enable)
275 struct pci9118_private *devpriv = dev->private;
278 mcsr = inl(devpriv->iobase_a + AMCC_OP_REG_MCSR);
280 mcsr |= RESET_A2P_FLAGS | A2P_HI_PRIORITY | EN_A2P_TRANSFERS;
282 mcsr &= ~EN_A2P_TRANSFERS;
283 outl(mcsr, devpriv->iobase_a + AMCC_OP_REG_MCSR);
286 static void pci9118_amcc_int_ena(struct comedi_device *dev, bool enable)
288 struct pci9118_private *devpriv = dev->private;
291 /* enable/disable interrupt for AMCC Incoming Mailbox 4 (32-bit) */
292 intcsr = inl(devpriv->iobase_a + AMCC_OP_REG_INTCSR);
297 outl(intcsr, devpriv->iobase_a + AMCC_OP_REG_INTCSR);
300 static void pci9118_timer_write(struct comedi_device *dev,
301 unsigned int timer, unsigned int val)
303 outl(val & 0xff, dev->iobase + PCI9118_TIMER_REG(timer));
304 outl((val >> 8) & 0xff, dev->iobase + PCI9118_TIMER_REG(timer));
307 static void pci9118_timer_set_mode(struct comedi_device *dev,
308 unsigned int timer, unsigned int mode)
312 val = timer << 6; /* select timer */
313 val |= 0x30; /* load low then high byte */
314 val |= mode; /* set timer mode and BCD|binary */
315 outl(val, dev->iobase + PCI9118_TIMER_CTRL_REG);
318 static void pci9118_ai_reset_fifo(struct comedi_device *dev)
320 /* writing any value resets the A/D FIFO */
321 outl(0, dev->iobase + PCI9118_FIFO_RESET_REG);
324 static int check_channel_list(struct comedi_device *dev,
325 struct comedi_subdevice *s, int n_chan,
326 unsigned int *chanlist, int frontadd, int backadd)
328 struct pci9118_private *devpriv = dev->private;
329 unsigned int i, differencial = 0, bipolar = 0;
331 /* correct channel and range number check itself comedi/range.c */
333 dev_err(dev->class_dev, "range/channel list is empty!\n");
336 if ((frontadd + n_chan + backadd) > s->len_chanlist) {
337 dev_err(dev->class_dev,
338 "range/channel list is too long for actual configuration!\n");
342 if (CR_AREF(chanlist[0]) == AREF_DIFF)
343 differencial = 1; /* all input must be diff */
344 if (CR_RANGE(chanlist[0]) < PCI9118_BIPOLAR_RANGES)
345 bipolar = 1; /* all input must be bipolar */
347 for (i = 1; i < n_chan; i++) { /* check S.E/diff */
348 if ((CR_AREF(chanlist[i]) == AREF_DIFF) !=
350 dev_err(dev->class_dev,
351 "Differential and single ended inputs can't be mixed!\n");
354 if ((CR_RANGE(chanlist[i]) < PCI9118_BIPOLAR_RANGES) !=
356 dev_err(dev->class_dev,
357 "Bipolar and unipolar ranges can't be mixed!\n");
360 if (!devpriv->usemux && differencial &&
361 (CR_CHAN(chanlist[i]) >= (s->n_chan / 2))) {
362 dev_err(dev->class_dev,
363 "AREF_DIFF is only available for the first 8 channels!\n");
371 static void pci9118_set_chanlist(struct comedi_device *dev,
372 struct comedi_subdevice *s,
373 int n_chan, unsigned int *chanlist,
374 int frontadd, int backadd)
376 struct pci9118_private *devpriv = dev->private;
377 unsigned int chan0 = CR_CHAN(chanlist[0]);
378 unsigned int range0 = CR_RANGE(chanlist[0]);
379 unsigned int aref0 = CR_AREF(chanlist[0]);
380 unsigned int ssh = 0x00;
385 * Configure analog input based on the first chanlist entry.
386 * All entries are either unipolar or bipolar and single-ended
389 devpriv->ai_ctrl = 0;
390 if (comedi_range_is_unipolar(s, range0))
391 devpriv->ai_ctrl |= PCI9118_AI_CTRL_UNIP;
392 if (aref0 == AREF_DIFF)
393 devpriv->ai_ctrl |= PCI9118_AI_CTRL_DIFF;
394 outl(devpriv->ai_ctrl, dev->iobase + PCI9118_AI_CTRL_REG);
396 /* gods know why this sequence! */
397 outl(2, dev->iobase + PCI9118_AI_AUTOSCAN_MODE_REG);
398 outl(0, dev->iobase + PCI9118_AI_AUTOSCAN_MODE_REG);
399 outl(1, dev->iobase + PCI9118_AI_AUTOSCAN_MODE_REG);
401 /* insert channels for S&H */
403 val = PCI9118_AI_CHANLIST_CHAN(chan0) |
404 PCI9118_AI_CHANLIST_RANGE(range0);
405 ssh = devpriv->softsshsample;
406 for (i = 0; i < frontadd; i++) {
407 outl(val | ssh, dev->iobase + PCI9118_AI_CHANLIST_REG);
408 ssh = devpriv->softsshhold;
413 for (i = 0; i < n_chan; i++) {
414 unsigned int chan = CR_CHAN(chanlist[i]);
415 unsigned int range = CR_RANGE(chanlist[i]);
417 val = PCI9118_AI_CHANLIST_CHAN(chan) |
418 PCI9118_AI_CHANLIST_RANGE(range);
419 outl(val | ssh, dev->iobase + PCI9118_AI_CHANLIST_REG);
422 /* insert channels to fit onto 32bit DMA */
424 val = PCI9118_AI_CHANLIST_CHAN(chan0) |
425 PCI9118_AI_CHANLIST_RANGE(range0);
426 for (i = 0; i < backadd; i++)
427 outl(val | ssh, dev->iobase + PCI9118_AI_CHANLIST_REG);
429 /* close scan queue */
430 outl(0, dev->iobase + PCI9118_AI_AUTOSCAN_MODE_REG);
431 /* udelay(100); important delay, or first sample will be crippled */
434 static void interrupt_pci9118_ai_mode4_switch(struct comedi_device *dev,
435 unsigned int next_buf)
437 struct pci9118_private *devpriv = dev->private;
438 struct pci9118_dmabuf *dmabuf = &devpriv->dmabuf[next_buf];
440 devpriv->ai_cfg = PCI9118_AI_CFG_PDTRG | PCI9118_AI_CFG_PETRG |
442 outl(devpriv->ai_cfg, dev->iobase + PCI9118_AI_CFG_REG);
443 pci9118_timer_set_mode(dev, 0, I8254_MODE0);
444 pci9118_timer_write(dev, 0, dmabuf->hw >> 1);
445 devpriv->ai_cfg |= PCI9118_AI_CFG_START;
446 outl(devpriv->ai_cfg, dev->iobase + PCI9118_AI_CFG_REG);
449 static unsigned int valid_samples_in_act_dma_buf(struct comedi_device *dev,
450 struct comedi_subdevice *s,
451 unsigned int n_raw_samples)
453 struct pci9118_private *devpriv = dev->private;
454 struct comedi_cmd *cmd = &s->async->cmd;
455 unsigned int start_pos = devpriv->ai_add_front;
456 unsigned int stop_pos = start_pos + cmd->chanlist_len;
457 unsigned int span_len = stop_pos + devpriv->ai_add_back;
458 unsigned int dma_pos = devpriv->ai_act_dmapos;
459 unsigned int whole_spans, n_samples, x;
461 if (span_len == cmd->chanlist_len)
462 return n_raw_samples; /* use all samples */
465 * Not all samples are to be used. Buffer contents consist of a
466 * possibly non-whole number of spans and a region of each span
469 * Account for samples in whole number of spans.
471 whole_spans = n_raw_samples / span_len;
472 n_samples = whole_spans * cmd->chanlist_len;
473 n_raw_samples -= whole_spans * span_len;
476 * Deal with remaining samples which could overlap up to two spans.
478 while (n_raw_samples) {
479 if (dma_pos < start_pos) {
480 /* Skip samples before start position. */
481 x = start_pos - dma_pos;
482 if (x > n_raw_samples)
489 if (dma_pos < stop_pos) {
490 /* Include samples before stop position. */
491 x = stop_pos - dma_pos;
492 if (x > n_raw_samples)
498 /* Advance to next span. */
499 start_pos += span_len;
500 stop_pos += span_len;
505 static unsigned int defragment_dma_buffer(struct comedi_device *dev,
506 struct comedi_subdevice *s,
507 unsigned short *dma_buffer,
508 unsigned int num_samples)
510 struct pci9118_private *devpriv = dev->private;
511 struct comedi_cmd *cmd = &s->async->cmd;
512 unsigned int i = 0, j = 0;
513 unsigned int start_pos = devpriv->ai_add_front,
514 stop_pos = devpriv->ai_add_front + cmd->chanlist_len;
515 unsigned int raw_scanlen = devpriv->ai_add_front + cmd->chanlist_len +
516 devpriv->ai_add_back;
518 for (i = 0; i < num_samples; i++) {
519 if (devpriv->ai_act_dmapos >= start_pos &&
520 devpriv->ai_act_dmapos < stop_pos) {
521 dma_buffer[j++] = dma_buffer[i];
523 devpriv->ai_act_dmapos++;
524 devpriv->ai_act_dmapos %= raw_scanlen;
530 static void pci9118_exttrg_enable(struct comedi_device *dev, bool enable)
532 struct pci9118_private *devpriv = dev->private;
535 devpriv->int_ctrl |= PCI9118_INT_CTRL_DTRG;
537 devpriv->int_ctrl &= ~PCI9118_INT_CTRL_DTRG;
538 outl(devpriv->int_ctrl, dev->iobase + PCI9118_INT_CTRL_REG);
540 if (devpriv->int_ctrl)
541 pci9118_amcc_int_ena(dev, true);
543 pci9118_amcc_int_ena(dev, false);
546 static void pci9118_calc_divisors(struct comedi_device *dev,
547 struct comedi_subdevice *s,
548 unsigned int *tim1, unsigned int *tim2,
549 unsigned int flags, int chans,
550 unsigned int *div1, unsigned int *div2,
551 unsigned int chnsshfront)
553 struct comedi_cmd *cmd = &s->async->cmd;
555 *div1 = *tim2 / I8254_OSC_BASE_4MHZ; /* convert timer (burst) */
556 *div2 = *tim1 / I8254_OSC_BASE_4MHZ; /* scan timer */
557 *div2 = *div2 / *div1; /* major timer is c1*c2 */
561 *tim2 = *div1 * I8254_OSC_BASE_4MHZ; /* real convert timer */
563 if (cmd->convert_src == TRIG_NOW && !chnsshfront) {
564 /* use BSSH signal */
565 if (*div2 < (chans + 2))
569 *tim1 = *div1 * *div2 * I8254_OSC_BASE_4MHZ;
572 static void pci9118_start_pacer(struct comedi_device *dev, int mode)
574 struct pci9118_private *devpriv = dev->private;
576 pci9118_timer_set_mode(dev, 1, I8254_MODE2);
577 pci9118_timer_set_mode(dev, 2, I8254_MODE2);
580 if ((mode == 1) || (mode == 2) || (mode == 4)) {
581 pci9118_timer_write(dev, 2, devpriv->ai_divisor2);
582 pci9118_timer_write(dev, 1, devpriv->ai_divisor1);
586 static int pci9118_ai_cancel(struct comedi_device *dev,
587 struct comedi_subdevice *s)
589 struct pci9118_private *devpriv = dev->private;
592 pci9118_amcc_dma_ena(dev, false);
593 pci9118_exttrg_enable(dev, false);
594 pci9118_start_pacer(dev, 0); /* stop 8254 counters */
595 /* set default config (disable burst and triggers) */
596 devpriv->ai_cfg = PCI9118_AI_CFG_PDTRG | PCI9118_AI_CFG_PETRG;
597 outl(devpriv->ai_cfg, dev->iobase + PCI9118_AI_CFG_REG);
598 /* reset acqusition control */
599 devpriv->ai_ctrl = 0;
600 outl(devpriv->ai_ctrl, dev->iobase + PCI9118_AI_CTRL_REG);
601 outl(0, dev->iobase + PCI9118_AI_BURST_NUM_REG);
602 /* reset scan queue */
603 outl(1, dev->iobase + PCI9118_AI_AUTOSCAN_MODE_REG);
604 outl(2, dev->iobase + PCI9118_AI_AUTOSCAN_MODE_REG);
605 pci9118_ai_reset_fifo(dev);
607 devpriv->int_ctrl = 0;
608 outl(devpriv->int_ctrl, dev->iobase + PCI9118_INT_CTRL_REG);
609 pci9118_amcc_int_ena(dev, false);
614 devpriv->ai_act_dmapos = 0;
615 s->async->inttrig = NULL;
616 devpriv->ai_neverending = 0;
617 devpriv->dma_actbuf = 0;
622 static void pci9118_ai_munge(struct comedi_device *dev,
623 struct comedi_subdevice *s, void *data,
624 unsigned int num_bytes,
625 unsigned int start_chan_index)
627 struct pci9118_private *devpriv = dev->private;
628 unsigned short *array = data;
629 unsigned int num_samples = comedi_bytes_to_samples(s, num_bytes);
632 for (i = 0; i < num_samples; i++) {
634 array[i] = be16_to_cpu(array[i]);
635 if (s->maxdata == 0xffff)
638 array[i] = (array[i] >> 4) & 0x0fff;
643 static void interrupt_pci9118_ai_onesample(struct comedi_device *dev,
644 struct comedi_subdevice *s)
646 struct pci9118_private *devpriv = dev->private;
647 struct comedi_cmd *cmd = &s->async->cmd;
648 unsigned short sampl;
650 sampl = inl(dev->iobase + PCI9118_AI_FIFO_REG);
652 comedi_buf_write_samples(s, &sampl, 1);
654 if (!devpriv->ai_neverending) {
655 if (s->async->scans_done >= cmd->stop_arg)
656 s->async->events |= COMEDI_CB_EOA;
660 static void interrupt_pci9118_ai_dma(struct comedi_device *dev,
661 struct comedi_subdevice *s)
663 struct pci9118_private *devpriv = dev->private;
664 struct comedi_cmd *cmd = &s->async->cmd;
665 struct pci9118_dmabuf *dmabuf = &devpriv->dmabuf[devpriv->dma_actbuf];
666 unsigned int n_all = comedi_bytes_to_samples(s, dmabuf->use_size);
667 unsigned int n_valid;
670 /* determine whether more DMA buffers to do after this one */
671 n_valid = valid_samples_in_act_dma_buf(dev, s, n_all);
672 more_dma = n_valid < comedi_nsamples_left(s, n_valid + 1);
674 /* switch DMA buffers and restart DMA if double buffering */
675 if (more_dma && devpriv->dma_doublebuf) {
676 devpriv->dma_actbuf = 1 - devpriv->dma_actbuf;
677 pci9118_amcc_setup_dma(dev, devpriv->dma_actbuf);
678 if (devpriv->ai_do == 4) {
679 interrupt_pci9118_ai_mode4_switch(dev,
680 devpriv->dma_actbuf);
685 n_valid = defragment_dma_buffer(dev, s, dmabuf->virt, n_all);
686 comedi_buf_write_samples(s, dmabuf->virt, n_valid);
689 if (!devpriv->ai_neverending) {
690 if (s->async->scans_done >= cmd->stop_arg)
691 s->async->events |= COMEDI_CB_EOA;
694 if (s->async->events & COMEDI_CB_CANCEL_MASK)
697 /* restart DMA if not double buffering */
698 if (more_dma && !devpriv->dma_doublebuf) {
699 pci9118_amcc_setup_dma(dev, 0);
700 if (devpriv->ai_do == 4)
701 interrupt_pci9118_ai_mode4_switch(dev, 0);
705 static irqreturn_t pci9118_interrupt(int irq, void *d)
707 struct comedi_device *dev = d;
708 struct comedi_subdevice *s = dev->read_subdev;
709 struct pci9118_private *devpriv = dev->private;
710 unsigned int intsrc; /* IRQ reasons from card */
711 unsigned int intcsr; /* INT register from AMCC chip */
712 unsigned int adstat; /* STATUS register */
717 intsrc = inl(dev->iobase + PCI9118_INT_CTRL_REG) & 0xf;
718 intcsr = inl(devpriv->iobase_a + AMCC_OP_REG_INTCSR);
720 if (!intsrc && !(intcsr & ANY_S593X_INT))
723 outl(intcsr | 0x00ff0000, devpriv->iobase_a + AMCC_OP_REG_INTCSR);
725 if (intcsr & MASTER_ABORT_INT) {
726 dev_err(dev->class_dev, "AMCC IRQ - MASTER DMA ABORT!\n");
727 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
731 if (intcsr & TARGET_ABORT_INT) {
732 dev_err(dev->class_dev, "AMCC IRQ - TARGET DMA ABORT!\n");
733 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
737 adstat = inl(dev->iobase + PCI9118_AI_STATUS_REG);
738 if ((adstat & PCI9118_AI_STATUS_NFULL) == 0) {
739 dev_err(dev->class_dev,
740 "A/D FIFO Full status (Fatal Error!)\n");
741 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW;
744 if (adstat & PCI9118_AI_STATUS_BOVER) {
745 dev_err(dev->class_dev,
746 "A/D Burst Mode Overrun Status (Fatal Error!)\n");
747 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW;
750 if (adstat & PCI9118_AI_STATUS_ADOS) {
751 dev_err(dev->class_dev, "A/D Over Speed Status (Warning!)\n");
752 s->async->events |= COMEDI_CB_ERROR;
755 if (adstat & PCI9118_AI_STATUS_ADOR) {
756 dev_err(dev->class_dev, "A/D Overrun Status (Fatal Error!)\n");
757 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW;
764 if (devpriv->ai12_startstop) {
765 if ((adstat & PCI9118_AI_STATUS_DTH) &&
766 (intsrc & PCI9118_INT_CTRL_DTRG)) {
767 /* start/stop of measure */
768 if (devpriv->ai12_startstop & START_AI_EXT) {
769 /* deactivate EXT trigger */
770 devpriv->ai12_startstop &= ~START_AI_EXT;
771 if (!(devpriv->ai12_startstop & STOP_AI_EXT))
772 pci9118_exttrg_enable(dev, false);
775 pci9118_start_pacer(dev, devpriv->ai_do);
776 outl(devpriv->ai_ctrl,
777 dev->iobase + PCI9118_AI_CTRL_REG);
778 } else if (devpriv->ai12_startstop & STOP_AI_EXT) {
779 /* deactivate EXT trigger */
780 devpriv->ai12_startstop &= ~STOP_AI_EXT;
781 pci9118_exttrg_enable(dev, false);
783 /* on next interrupt measure will stop */
784 devpriv->ai_neverending = 0;
790 interrupt_pci9118_ai_dma(dev, s);
792 interrupt_pci9118_ai_onesample(dev, s);
795 comedi_handle_events(dev, s);
799 static void pci9118_ai_cmd_start(struct comedi_device *dev)
801 struct pci9118_private *devpriv = dev->private;
803 outl(devpriv->int_ctrl, dev->iobase + PCI9118_INT_CTRL_REG);
804 outl(devpriv->ai_cfg, dev->iobase + PCI9118_AI_CFG_REG);
805 if (devpriv->ai_do != 3) {
806 pci9118_start_pacer(dev, devpriv->ai_do);
807 devpriv->ai_ctrl |= PCI9118_AI_CTRL_SOFTG;
809 outl(devpriv->ai_ctrl, dev->iobase + PCI9118_AI_CTRL_REG);
812 static int pci9118_ai_inttrig(struct comedi_device *dev,
813 struct comedi_subdevice *s,
814 unsigned int trig_num)
816 struct comedi_cmd *cmd = &s->async->cmd;
818 if (trig_num != cmd->start_arg)
821 s->async->inttrig = NULL;
822 pci9118_ai_cmd_start(dev);
827 static int Compute_and_setup_dma(struct comedi_device *dev,
828 struct comedi_subdevice *s)
830 struct pci9118_private *devpriv = dev->private;
831 struct comedi_cmd *cmd = &s->async->cmd;
832 struct pci9118_dmabuf *dmabuf0 = &devpriv->dmabuf[0];
833 struct pci9118_dmabuf *dmabuf1 = &devpriv->dmabuf[1];
834 unsigned int dmalen0, dmalen1, i;
836 dmalen0 = dmabuf0->size;
837 dmalen1 = dmabuf1->size;
838 /* isn't output buff smaller that our DMA buff? */
839 if (dmalen0 > s->async->prealloc_bufsz) {
840 /* align to 32bit down */
841 dmalen0 = s->async->prealloc_bufsz & ~3L;
843 if (dmalen1 > s->async->prealloc_bufsz) {
844 /* align to 32bit down */
845 dmalen1 = s->async->prealloc_bufsz & ~3L;
848 /* we want wake up every scan? */
849 if (devpriv->ai_flags & CMDF_WAKE_EOS) {
850 if (dmalen0 < (devpriv->ai_n_realscanlen << 1)) {
851 /* uff, too short DMA buffer, disable EOS support! */
852 devpriv->ai_flags &= (~CMDF_WAKE_EOS);
853 dev_info(dev->class_dev,
854 "WAR: DMA0 buf too short, can't support CMDF_WAKE_EOS (%d<%d)\n",
855 dmalen0, devpriv->ai_n_realscanlen << 1);
857 /* short first DMA buffer to one scan */
858 dmalen0 = devpriv->ai_n_realscanlen << 1;
860 dev_info(dev->class_dev,
861 "ERR: DMA0 buf len bug? (%d<4)\n",
867 if (devpriv->ai_flags & CMDF_WAKE_EOS) {
868 if (dmalen1 < (devpriv->ai_n_realscanlen << 1)) {
869 /* uff, too short DMA buffer, disable EOS support! */
870 devpriv->ai_flags &= (~CMDF_WAKE_EOS);
871 dev_info(dev->class_dev,
872 "WAR: DMA1 buf too short, can't support CMDF_WAKE_EOS (%d<%d)\n",
873 dmalen1, devpriv->ai_n_realscanlen << 1);
875 /* short second DMA buffer to one scan */
876 dmalen1 = devpriv->ai_n_realscanlen << 1;
878 dev_info(dev->class_dev,
879 "ERR: DMA1 buf len bug? (%d<4)\n",
886 /* transfer without CMDF_WAKE_EOS */
887 if (!(devpriv->ai_flags & CMDF_WAKE_EOS)) {
888 /* if it's possible then align DMA buffers to length of scan */
891 (dmalen0 / (devpriv->ai_n_realscanlen << 1)) *
892 (devpriv->ai_n_realscanlen << 1);
895 dmalen0 = i; /* uff. very long scan? */
898 (dmalen1 / (devpriv->ai_n_realscanlen << 1)) *
899 (devpriv->ai_n_realscanlen << 1);
902 dmalen1 = i; /* uff. very long scan? */
904 * if measure isn't neverending then test, if it fits whole
905 * into one or two DMA buffers
907 if (!devpriv->ai_neverending) {
908 /* fits whole measure into one DMA buffer? */
910 ((devpriv->ai_n_realscanlen << 1) *
913 (devpriv->ai_n_realscanlen << 1) *
917 * fits whole measure into
921 ((devpriv->ai_n_realscanlen << 1) *
922 cmd->stop_arg - dmalen0))
924 (devpriv->ai_n_realscanlen << 1) *
925 cmd->stop_arg - dmalen0;
931 /* these DMA buffer size will be used */
932 devpriv->dma_actbuf = 0;
933 dmabuf0->use_size = dmalen0;
934 dmabuf1->use_size = dmalen1;
936 pci9118_amcc_dma_ena(dev, false);
937 pci9118_amcc_setup_dma(dev, 0);
938 /* init DMA transfer */
939 outl(0x00000000 | AINT_WRITE_COMPL,
940 devpriv->iobase_a + AMCC_OP_REG_INTCSR);
941 /* outl(0x02000000|AINT_WRITE_COMPL, devpriv->iobase_a+AMCC_OP_REG_INTCSR); */
942 pci9118_amcc_dma_ena(dev, true);
943 outl(inl(devpriv->iobase_a + AMCC_OP_REG_INTCSR) | EN_A2P_TRANSFERS,
944 devpriv->iobase_a + AMCC_OP_REG_INTCSR);
945 /* allow bus mastering */
950 static int pci9118_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
952 struct pci9118_private *devpriv = dev->private;
953 struct comedi_cmd *cmd = &s->async->cmd;
954 unsigned int addchans = 0;
956 devpriv->ai12_startstop = 0;
957 devpriv->ai_flags = cmd->flags;
958 devpriv->ai_add_front = 0;
959 devpriv->ai_add_back = 0;
961 /* prepare for start/stop conditions */
962 if (cmd->start_src == TRIG_EXT)
963 devpriv->ai12_startstop |= START_AI_EXT;
964 if (cmd->stop_src == TRIG_EXT) {
965 devpriv->ai_neverending = 1;
966 devpriv->ai12_startstop |= STOP_AI_EXT;
968 if (cmd->stop_src == TRIG_NONE)
969 devpriv->ai_neverending = 1;
970 if (cmd->stop_src == TRIG_COUNT)
971 devpriv->ai_neverending = 0;
974 * use additional sample at end of every scan
975 * to satisty DMA 32 bit transfer?
977 devpriv->ai_add_front = 0;
978 devpriv->ai_add_back = 0;
979 if (devpriv->master) {
981 if ((cmd->flags & CMDF_WAKE_EOS) &&
982 (cmd->scan_end_arg == 1)) {
983 if (cmd->convert_src == TRIG_NOW)
984 devpriv->ai_add_back = 1;
985 if (cmd->convert_src == TRIG_TIMER) {
988 * use INT transfer if scanlist
989 * have only one channel
993 if ((cmd->flags & CMDF_WAKE_EOS) &&
994 (cmd->scan_end_arg & 1) &&
995 (cmd->scan_end_arg > 1)) {
996 if (cmd->scan_begin_src == TRIG_FOLLOW) {
999 * XXX maybe can be corrected to use 16 bit DMA
1002 * well, we must insert one sample
1003 * to end of EOS to meet 32 bit transfer
1005 devpriv->ai_add_back = 1;
1008 } else { /* interrupt transfer don't need any correction */
1009 devpriv->usedma = 0;
1013 * we need software S&H signal?
1014 * It adds two samples before every scan as minimum
1016 if (cmd->convert_src == TRIG_NOW && devpriv->softsshdelay) {
1017 devpriv->ai_add_front = 2;
1018 if ((devpriv->usedma == 1) && (devpriv->ai_add_back == 1)) {
1019 /* move it to front */
1020 devpriv->ai_add_front++;
1021 devpriv->ai_add_back = 0;
1023 if (cmd->convert_arg < devpriv->ai_ns_min)
1024 cmd->convert_arg = devpriv->ai_ns_min;
1025 addchans = devpriv->softsshdelay / cmd->convert_arg;
1026 if (devpriv->softsshdelay % cmd->convert_arg)
1028 if (addchans > (devpriv->ai_add_front - 1)) {
1029 /* uff, still short */
1030 devpriv->ai_add_front = addchans + 1;
1031 if (devpriv->usedma == 1)
1032 if ((devpriv->ai_add_front +
1034 devpriv->ai_add_back) & 1)
1035 devpriv->ai_add_front++;
1036 /* round up to 32 bit */
1039 /* well, we now know what must be all added */
1040 devpriv->ai_n_realscanlen = /*
1041 * what we must take from card in real
1042 * to have cmd->scan_end_arg on output?
1044 (devpriv->ai_add_front + cmd->chanlist_len +
1045 devpriv->ai_add_back) * (cmd->scan_end_arg /
1048 /* check and setup channel list */
1049 if (!check_channel_list(dev, s, cmd->chanlist_len,
1050 cmd->chanlist, devpriv->ai_add_front,
1051 devpriv->ai_add_back))
1055 * Configure analog input and load the chanlist.
1056 * The acqusition control bits are enabled later.
1058 pci9118_set_chanlist(dev, s, cmd->chanlist_len, cmd->chanlist,
1059 devpriv->ai_add_front, devpriv->ai_add_back);
1061 /* Determine acqusition mode and calculate timing */
1063 if (cmd->scan_begin_src != TRIG_TIMER &&
1064 cmd->convert_src == TRIG_TIMER) {
1065 /* cascaded timers 1 and 2 are used for convert timing */
1066 if (cmd->scan_begin_src == TRIG_EXT)
1071 i8253_cascade_ns_to_timer(I8254_OSC_BASE_4MHZ,
1072 &devpriv->ai_divisor1,
1073 &devpriv->ai_divisor2,
1076 CMDF_ROUND_NEAREST);
1078 devpriv->ai_ctrl |= PCI9118_AI_CTRL_TMRTR;
1080 if (!devpriv->usedma) {
1081 devpriv->ai_ctrl |= PCI9118_AI_CTRL_INT;
1082 devpriv->int_ctrl |= PCI9118_INT_CTRL_TIMER;
1085 if (cmd->scan_begin_src == TRIG_EXT) {
1086 struct pci9118_dmabuf *dmabuf = &devpriv->dmabuf[0];
1088 devpriv->ai_cfg |= PCI9118_AI_CFG_AM;
1089 outl(devpriv->ai_cfg, dev->iobase + PCI9118_AI_CFG_REG);
1090 pci9118_timer_set_mode(dev, 0, I8254_MODE0);
1091 pci9118_timer_write(dev, 0, dmabuf->hw >> 1);
1092 devpriv->ai_cfg |= PCI9118_AI_CFG_START;
1096 if (cmd->scan_begin_src == TRIG_TIMER &&
1097 cmd->convert_src != TRIG_EXT) {
1098 if (!devpriv->usedma) {
1099 dev_err(dev->class_dev,
1100 "cmd->scan_begin_src=TRIG_TIMER works only with bus mastering!\n");
1104 /* double timed action */
1107 pci9118_calc_divisors(dev, s,
1108 &cmd->scan_begin_arg, &cmd->convert_arg,
1110 devpriv->ai_n_realscanlen,
1111 &devpriv->ai_divisor1,
1112 &devpriv->ai_divisor2,
1113 devpriv->ai_add_front);
1115 devpriv->ai_ctrl |= PCI9118_AI_CTRL_TMRTR;
1116 devpriv->ai_cfg |= PCI9118_AI_CFG_BM | PCI9118_AI_CFG_BS;
1117 if (cmd->convert_src == TRIG_NOW && !devpriv->softsshdelay)
1118 devpriv->ai_cfg |= PCI9118_AI_CFG_BSSH;
1119 outl(devpriv->ai_n_realscanlen,
1120 dev->iobase + PCI9118_AI_BURST_NUM_REG);
1123 if (cmd->scan_begin_src == TRIG_FOLLOW &&
1124 cmd->convert_src == TRIG_EXT) {
1125 /* external trigger conversion */
1128 devpriv->ai_ctrl |= PCI9118_AI_CTRL_EXTM;
1131 if (devpriv->ai_do == 0) {
1132 dev_err(dev->class_dev,
1133 "Unable to determine acqusition mode! BUG in (*do_cmdtest)?\n");
1137 if (devpriv->usedma)
1138 devpriv->ai_ctrl |= PCI9118_AI_CTRL_DMA;
1140 pci9118_start_pacer(dev, -1); /* stop pacer */
1142 /* set default config (disable burst and triggers) */
1143 devpriv->ai_cfg = PCI9118_AI_CFG_PDTRG | PCI9118_AI_CFG_PETRG;
1144 outl(devpriv->ai_cfg, dev->iobase + PCI9118_AI_CFG_REG);
1146 pci9118_ai_reset_fifo(dev);
1148 /* clear A/D and INT status registers */
1149 inl(dev->iobase + PCI9118_AI_STATUS_REG);
1150 inl(dev->iobase + PCI9118_INT_CTRL_REG);
1152 devpriv->ai_act_dmapos = 0;
1154 if (devpriv->usedma) {
1155 Compute_and_setup_dma(dev, s);
1157 outl(0x02000000 | AINT_WRITE_COMPL,
1158 devpriv->iobase_a + AMCC_OP_REG_INTCSR);
1160 pci9118_amcc_int_ena(dev, true);
1163 /* start async command now or wait for internal trigger */
1164 if (cmd->start_src == TRIG_NOW)
1165 pci9118_ai_cmd_start(dev);
1166 else if (cmd->start_src == TRIG_INT)
1167 s->async->inttrig = pci9118_ai_inttrig;
1169 /* enable external trigger for command start/stop */
1170 if (cmd->start_src == TRIG_EXT || cmd->stop_src == TRIG_EXT)
1171 pci9118_exttrg_enable(dev, true);
1176 static int pci9118_ai_cmdtest(struct comedi_device *dev,
1177 struct comedi_subdevice *s,
1178 struct comedi_cmd *cmd)
1180 struct pci9118_private *devpriv = dev->private;
1184 unsigned int divisor1 = 0, divisor2 = 0;
1186 /* Step 1 : check if triggers are trivially valid */
1188 err |= cfc_check_trigger_src(&cmd->start_src,
1189 TRIG_NOW | TRIG_EXT | TRIG_INT);
1191 flags = TRIG_FOLLOW;
1192 if (devpriv->master)
1193 flags |= TRIG_TIMER | TRIG_EXT;
1194 err |= cfc_check_trigger_src(&cmd->scan_begin_src, flags);
1196 flags = TRIG_TIMER | TRIG_EXT;
1197 if (devpriv->master)
1199 err |= cfc_check_trigger_src(&cmd->convert_src, flags);
1201 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
1202 err |= cfc_check_trigger_src(&cmd->stop_src,
1203 TRIG_COUNT | TRIG_NONE | TRIG_EXT);
1208 /* Step 2a : make sure trigger sources are unique */
1210 err |= cfc_check_trigger_is_unique(cmd->start_src);
1211 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
1212 err |= cfc_check_trigger_is_unique(cmd->convert_src);
1213 err |= cfc_check_trigger_is_unique(cmd->stop_src);
1215 /* Step 2b : and mutually compatible */
1217 if (cmd->start_src == TRIG_EXT && cmd->scan_begin_src == TRIG_EXT)
1220 if (cmd->start_src == TRIG_INT && cmd->scan_begin_src == TRIG_INT)
1223 if ((cmd->scan_begin_src & (TRIG_TIMER | TRIG_EXT)) &&
1224 (!(cmd->convert_src & (TRIG_TIMER | TRIG_NOW))))
1227 if ((cmd->scan_begin_src == TRIG_FOLLOW) &&
1228 (!(cmd->convert_src & (TRIG_TIMER | TRIG_EXT))))
1231 if (cmd->stop_src == TRIG_EXT && cmd->scan_begin_src == TRIG_EXT)
1237 /* Step 3: check if arguments are trivially valid */
1239 switch (cmd->start_src) {
1242 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
1245 /* start_arg is the internal trigger (any value) */
1249 if (cmd->scan_begin_src & (TRIG_FOLLOW | TRIG_EXT))
1250 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
1252 if ((cmd->scan_begin_src == TRIG_TIMER) &&
1253 (cmd->convert_src == TRIG_TIMER) && (cmd->scan_end_arg == 1)) {
1254 cmd->scan_begin_src = TRIG_FOLLOW;
1255 cmd->convert_arg = cmd->scan_begin_arg;
1256 cmd->scan_begin_arg = 0;
1259 if (cmd->scan_begin_src == TRIG_TIMER)
1260 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
1261 devpriv->ai_ns_min);
1263 if (cmd->scan_begin_src == TRIG_EXT)
1264 if (cmd->scan_begin_arg) {
1265 cmd->scan_begin_arg = 0;
1267 err |= cfc_check_trigger_arg_max(&cmd->scan_end_arg,
1271 if (cmd->convert_src & (TRIG_TIMER | TRIG_NOW))
1272 err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
1273 devpriv->ai_ns_min);
1275 if (cmd->convert_src == TRIG_EXT)
1276 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
1278 if (cmd->stop_src == TRIG_COUNT)
1279 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
1280 else /* TRIG_NONE */
1281 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
1283 err |= cfc_check_trigger_arg_min(&cmd->chanlist_len, 1);
1285 err |= cfc_check_trigger_arg_min(&cmd->scan_end_arg,
1288 if ((cmd->scan_end_arg % cmd->chanlist_len)) {
1290 cmd->chanlist_len * (cmd->scan_end_arg / cmd->chanlist_len);
1297 /* step 4: fix up any arguments */
1299 if (cmd->scan_begin_src == TRIG_TIMER) {
1300 arg = cmd->scan_begin_arg;
1301 i8253_cascade_ns_to_timer(I8254_OSC_BASE_4MHZ,
1302 &divisor1, &divisor2,
1304 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, arg);
1307 if (cmd->convert_src & (TRIG_TIMER | TRIG_NOW)) {
1308 arg = cmd->convert_arg;
1309 i8253_cascade_ns_to_timer(I8254_OSC_BASE_4MHZ,
1310 &divisor1, &divisor2,
1312 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, arg);
1314 if (cmd->scan_begin_src == TRIG_TIMER &&
1315 cmd->convert_src == TRIG_NOW) {
1316 if (cmd->convert_arg == 0) {
1317 arg = devpriv->ai_ns_min *
1318 (cmd->scan_end_arg + 2);
1320 arg = cmd->convert_arg * cmd->chanlist_len;
1322 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
1331 if (!check_channel_list(dev, s, cmd->chanlist_len,
1332 cmd->chanlist, 0, 0))
1333 return 5; /* incorrect channels list */
1338 static int pci9118_ai_eoc(struct comedi_device *dev,
1339 struct comedi_subdevice *s,
1340 struct comedi_insn *insn,
1341 unsigned long context)
1343 unsigned int status;
1345 status = inl(dev->iobase + PCI9118_AI_STATUS_REG);
1346 if (status & PCI9118_AI_STATUS_ADRDY)
1351 static void pci9118_ai_start_conv(struct comedi_device *dev)
1353 /* writing any value triggers an A/D conversion */
1354 outl(0, dev->iobase + PCI9118_SOFTTRG_REG);
1357 static int pci9118_ai_insn_read(struct comedi_device *dev,
1358 struct comedi_subdevice *s,
1359 struct comedi_insn *insn,
1362 struct pci9118_private *devpriv = dev->private;
1368 * Configure analog input based on the chanspec.
1369 * Acqusition is software controlled without interrupts.
1371 pci9118_set_chanlist(dev, s, 1, &insn->chanspec, 0, 0);
1373 /* set default config (disable burst and triggers) */
1374 devpriv->ai_cfg = PCI9118_AI_CFG_PDTRG | PCI9118_AI_CFG_PETRG;
1375 outl(devpriv->ai_cfg, dev->iobase + PCI9118_AI_CFG_REG);
1377 pci9118_ai_reset_fifo(dev);
1379 for (i = 0; i < insn->n; i++) {
1380 pci9118_ai_start_conv(dev);
1382 ret = comedi_timeout(dev, s, insn, pci9118_ai_eoc, 0);
1386 val = inl(dev->iobase + PCI9118_AI_FIFO_REG);
1387 if (s->maxdata == 0xffff)
1388 data[i] = (val & 0xffff) ^ 0x8000;
1390 data[i] = (val >> 4) & 0xfff;
1396 static int pci9118_ao_insn_write(struct comedi_device *dev,
1397 struct comedi_subdevice *s,
1398 struct comedi_insn *insn,
1401 unsigned int chan = CR_CHAN(insn->chanspec);
1402 unsigned int val = s->readback[chan];
1405 for (i = 0; i < insn->n; i++) {
1407 outl(val, dev->iobase + PCI9118_AO_REG(chan));
1409 s->readback[chan] = val;
1414 static int pci9118_di_insn_bits(struct comedi_device *dev,
1415 struct comedi_subdevice *s,
1416 struct comedi_insn *insn,
1420 * The digital inputs and outputs share the read register.
1421 * bits [7:4] are the digital outputs
1422 * bits [3:0] are the digital inputs
1424 data[1] = inl(dev->iobase + PCI9118_DIO_REG) & 0xf;
1429 static int pci9118_do_insn_bits(struct comedi_device *dev,
1430 struct comedi_subdevice *s,
1431 struct comedi_insn *insn,
1435 * The digital outputs are set with the same register that
1436 * the digital inputs and outputs are read from. But the
1437 * outputs are set with bits [3:0] so we can simply write
1438 * the s->state to set them.
1440 if (comedi_dio_update_state(s, data))
1441 outl(s->state, dev->iobase + PCI9118_DIO_REG);
1448 static void pci9118_reset(struct comedi_device *dev)
1450 /* reset analog input subsystem */
1451 outl(0, dev->iobase + PCI9118_INT_CTRL_REG);
1452 outl(0, dev->iobase + PCI9118_AI_CTRL_REG);
1453 outl(0, dev->iobase + PCI9118_AI_CFG_REG);
1454 pci9118_ai_reset_fifo(dev);
1456 /* clear any pending interrupts and status */
1457 inl(dev->iobase + PCI9118_INT_CTRL_REG);
1458 inl(dev->iobase + PCI9118_AI_STATUS_REG);
1460 /* reset and stop counters */
1461 pci9118_timer_set_mode(dev, 0, I8254_MODE0);
1462 pci9118_start_pacer(dev, 0);
1464 /* reset DMA and scan queue */
1465 outl(0, dev->iobase + PCI9118_AI_BURST_NUM_REG);
1466 outl(1, dev->iobase + PCI9118_AI_AUTOSCAN_MODE_REG);
1467 outl(2, dev->iobase + PCI9118_AI_AUTOSCAN_MODE_REG);
1469 /* reset analog outputs to 0V */
1470 outl(2047, dev->iobase + PCI9118_AO_REG(0));
1471 outl(2047, dev->iobase + PCI9118_AO_REG(1));
1474 static struct pci_dev *pci9118_find_pci(struct comedi_device *dev,
1475 struct comedi_devconfig *it)
1477 struct pci_dev *pcidev = NULL;
1478 int bus = it->options[0];
1479 int slot = it->options[1];
1481 for_each_pci_dev(pcidev) {
1482 if (pcidev->vendor != PCI_VENDOR_ID_AMCC)
1484 if (pcidev->device != 0x80d9)
1487 /* requested particular bus/slot */
1488 if (pcidev->bus->number != bus ||
1489 PCI_SLOT(pcidev->devfn) != slot)
1494 dev_err(dev->class_dev,
1495 "no supported board found! (req. bus/slot : %d/%d)\n",
1500 static void pci9118_alloc_dma(struct comedi_device *dev)
1502 struct pci9118_private *devpriv = dev->private;
1503 struct pci9118_dmabuf *dmabuf;
1507 for (i = 0; i < 2; i++) {
1508 dmabuf = &devpriv->dmabuf[i];
1509 for (order = 2; order >= 0; order--) {
1511 dma_alloc_coherent(dev->hw_dev, PAGE_SIZE << order,
1512 &dmabuf->hw, GFP_KERNEL);
1518 dmabuf->size = PAGE_SIZE << order;
1521 devpriv->master = 1;
1523 devpriv->dma_doublebuf = 1;
1527 static void pci9118_free_dma(struct comedi_device *dev)
1529 struct pci9118_private *devpriv = dev->private;
1530 struct pci9118_dmabuf *dmabuf;
1536 for (i = 0; i < 2; i++) {
1537 dmabuf = &devpriv->dmabuf[i];
1539 dma_free_coherent(dev->hw_dev, dmabuf->size,
1540 dmabuf->virt, dmabuf->hw);
1545 static int pci9118_common_attach(struct comedi_device *dev,
1546 int ext_mux, int softsshdelay)
1548 const struct pci9118_boardinfo *board = dev->board_ptr;
1549 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1550 struct pci9118_private *devpriv;
1551 struct comedi_subdevice *s;
1556 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
1560 ret = comedi_pci_enable(dev);
1563 pci_set_master(pcidev);
1565 devpriv->iobase_a = pci_resource_start(pcidev, 0);
1566 dev->iobase = pci_resource_start(pcidev, 2);
1571 ret = request_irq(pcidev->irq, pci9118_interrupt, IRQF_SHARED,
1572 dev->board_name, dev);
1574 dev->irq = pcidev->irq;
1576 pci9118_alloc_dma(dev);
1582 ext_mux = 256; /* max 256 channels! */
1583 if (softsshdelay > 0)
1586 devpriv->usemux = 1;
1588 devpriv->usemux = 0;
1591 if (softsshdelay < 0) {
1592 /* select sample&hold signal polarity */
1593 devpriv->softsshdelay = -softsshdelay;
1594 devpriv->softsshsample = 0x80;
1595 devpriv->softsshhold = 0x00;
1597 devpriv->softsshdelay = softsshdelay;
1598 devpriv->softsshsample = 0x00;
1599 devpriv->softsshhold = 0x80;
1602 pci_read_config_word(pcidev, PCI_COMMAND, &u16w);
1603 pci_write_config_word(pcidev, PCI_COMMAND, u16w | 64);
1604 /* Enable parity check for parity error */
1606 ret = comedi_alloc_subdevices(dev, 4);
1610 /* Analog Input subdevice */
1611 s = &dev->subdevices[0];
1612 s->type = COMEDI_SUBD_AI;
1613 s->subdev_flags = SDF_READABLE | SDF_COMMON | SDF_GROUND | SDF_DIFF;
1614 s->n_chan = (devpriv->usemux) ? ext_mux : 16;
1615 s->maxdata = board->ai_is_16bit ? 0xffff : 0x0fff;
1616 s->range_table = board->is_hg ? &pci9118hg_ai_range
1617 : &pci9118_ai_range;
1618 s->insn_read = pci9118_ai_insn_read;
1620 dev->read_subdev = s;
1621 s->subdev_flags |= SDF_CMD_READ;
1622 s->len_chanlist = PCI9118_CHANLEN;
1623 s->do_cmdtest = pci9118_ai_cmdtest;
1624 s->do_cmd = pci9118_ai_cmd;
1625 s->cancel = pci9118_ai_cancel;
1626 s->munge = pci9118_ai_munge;
1629 if (s->maxdata == 0xffff) {
1631 * 16-bit samples are from an ADS7805 A/D converter.
1632 * Minimum sampling rate is 10us.
1634 devpriv->ai_ns_min = 10000;
1637 * 12-bit samples are from an ADS7800 A/D converter.
1638 * Minimum sampling rate is 3us.
1640 devpriv->ai_ns_min = 3000;
1643 /* Analog Output subdevice */
1644 s = &dev->subdevices[1];
1645 s->type = COMEDI_SUBD_AO;
1646 s->subdev_flags = SDF_WRITABLE | SDF_GROUND | SDF_COMMON;
1648 s->maxdata = 0x0fff;
1649 s->range_table = &range_bipolar10;
1650 s->insn_write = pci9118_ao_insn_write;
1652 ret = comedi_alloc_subdev_readback(s);
1656 /* the analog outputs were reset to 0V, make the readback match */
1657 for (i = 0; i < s->n_chan; i++)
1658 s->readback[i] = 2047;
1660 /* Digital Input subdevice */
1661 s = &dev->subdevices[2];
1662 s->type = COMEDI_SUBD_DI;
1663 s->subdev_flags = SDF_READABLE;
1666 s->range_table = &range_digital;
1667 s->insn_bits = pci9118_di_insn_bits;
1669 /* Digital Output subdevice */
1670 s = &dev->subdevices[3];
1671 s->type = COMEDI_SUBD_DO;
1672 s->subdev_flags = SDF_WRITABLE;
1675 s->range_table = &range_digital;
1676 s->insn_bits = pci9118_do_insn_bits;
1678 /* get the current state of the digital outputs */
1679 s->state = inl(dev->iobase + PCI9118_DIO_REG) >> 4;
1684 static int pci9118_attach(struct comedi_device *dev,
1685 struct comedi_devconfig *it)
1687 struct pci_dev *pcidev;
1688 int ext_mux, softsshdelay;
1690 ext_mux = it->options[2];
1691 softsshdelay = it->options[4];
1693 pcidev = pci9118_find_pci(dev, it);
1696 comedi_set_hw_dev(dev, &pcidev->dev);
1698 return pci9118_common_attach(dev, ext_mux, softsshdelay);
1701 static int pci9118_auto_attach(struct comedi_device *dev,
1702 unsigned long context)
1704 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1705 const struct pci9118_boardinfo *board = NULL;
1707 if (context < ARRAY_SIZE(pci9118_boards))
1708 board = &pci9118_boards[context];
1711 dev->board_ptr = board;
1712 dev->board_name = board->name;
1715 * Need to 'get' the PCI device to match the 'put' in pci9118_detach().
1716 * (The 'put' also matches the implicit 'get' by pci9118_find_pci().)
1718 pci_dev_get(pcidev);
1719 /* no external mux, no sample-hold delay */
1720 return pci9118_common_attach(dev, 0, 0);
1723 static void pci9118_detach(struct comedi_device *dev)
1725 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1729 comedi_pci_detach(dev);
1730 pci9118_free_dma(dev);
1732 pci_dev_put(pcidev);
1735 static struct comedi_driver adl_pci9118_driver = {
1736 .driver_name = "adl_pci9118",
1737 .module = THIS_MODULE,
1738 .attach = pci9118_attach,
1739 .auto_attach = pci9118_auto_attach,
1740 .detach = pci9118_detach,
1741 .num_names = ARRAY_SIZE(pci9118_boards),
1742 .board_name = &pci9118_boards[0].name,
1743 .offset = sizeof(struct pci9118_boardinfo),
1746 static int adl_pci9118_pci_probe(struct pci_dev *dev,
1747 const struct pci_device_id *id)
1749 return comedi_pci_auto_config(dev, &adl_pci9118_driver,
1753 /* FIXME: All the supported board types have the same device ID! */
1754 static const struct pci_device_id adl_pci9118_pci_table[] = {
1755 { PCI_VDEVICE(AMCC, 0x80d9), BOARD_PCI9118DG },
1756 /* { PCI_VDEVICE(AMCC, 0x80d9), BOARD_PCI9118HG }, */
1757 /* { PCI_VDEVICE(AMCC, 0x80d9), BOARD_PCI9118HR }, */
1760 MODULE_DEVICE_TABLE(pci, adl_pci9118_pci_table);
1762 static struct pci_driver adl_pci9118_pci_driver = {
1763 .name = "adl_pci9118",
1764 .id_table = adl_pci9118_pci_table,
1765 .probe = adl_pci9118_pci_probe,
1766 .remove = comedi_pci_auto_unconfig,
1768 module_comedi_pci_driver(adl_pci9118_driver, adl_pci9118_pci_driver);
1770 MODULE_AUTHOR("Comedi http://www.comedi.org");
1771 MODULE_DESCRIPTION("Comedi low-level driver");
1772 MODULE_LICENSE("GPL");