2 * comedi/drivers/adv_pci_dio.c
4 * Author: Michal Dobes <dobes@tesnet.cz>
6 * Hardware driver for Advantech PCI DIO cards.
10 Description: Advantech PCI-1730, PCI-1733, PCI-1734, PCI-1735U,
11 PCI-1736UP, PCI-1739U, PCI-1750, PCI-1751, PCI-1752,
12 PCI-1753/E, PCI-1754, PCI-1756, PCI-1760, PCI-1762
13 Author: Michal Dobes <dobes@tesnet.cz>
14 Devices: [Advantech] PCI-1730 (adv_pci_dio), PCI-1733,
15 PCI-1734, PCI-1735U, PCI-1736UP, PCI-1739U, PCI-1750,
16 PCI-1751, PCI-1752, PCI-1753,
17 PCI-1753+PCI-1753E, PCI-1754, PCI-1756,
20 Updated: Mon, 09 Jan 2012 12:40:46 +0000
22 This driver supports now only insn interface for DI/DO/DIO.
24 Configuration options:
25 [0] - PCI bus of device (optional)
26 [1] - PCI slot of device (optional)
27 If bus/slot is not specified, the first available PCI
32 #include <linux/pci.h>
33 #include <linux/delay.h>
35 #include "../comedidev.h"
40 /* hardware types of the cards */
42 TYPE_PCI1730, TYPE_PCI1733, TYPE_PCI1734, TYPE_PCI1735, TYPE_PCI1736,
47 TYPE_PCI1753, TYPE_PCI1753E,
48 TYPE_PCI1754, TYPE_PCI1756,
53 /* which I/O instructions to use */
58 #define MAX_DI_SUBDEVS 2 /* max number of DI subdevices per card */
59 #define MAX_DO_SUBDEVS 2 /* max number of DO subdevices per card */
60 #define MAX_DIO_SUBDEVG 2 /* max number of DIO subdevices group per
62 #define MAX_8254_SUBDEVS 1 /* max number of 8254 counter subdevs per
64 /* (could be more than one 8254 per
67 #define SIZE_8254 4 /* 8254 IO space length */
68 #define SIZE_8255 4 /* 8255 IO space length */
70 #define PCIDIO_MAINREG 2 /* main I/O region for all Advantech cards? */
72 /* Register offset definitions */
73 /* Advantech PCI-1730/3/4 */
74 #define PCI1730_IDI 0 /* R: Isolated digital input 0-15 */
75 #define PCI1730_IDO 0 /* W: Isolated digital output 0-15 */
76 #define PCI1730_DI 2 /* R: Digital input 0-15 */
77 #define PCI1730_DO 2 /* W: Digital output 0-15 */
78 #define PCI1733_IDI 0 /* R: Isolated digital input 0-31 */
79 #define PCI1730_3_INT_EN 0x08 /* R/W: enable/disable interrupts */
80 #define PCI1730_3_INT_RF 0x0c /* R/W: set falling/raising edge for
82 #define PCI1730_3_INT_CLR 0x10 /* R/W: clear interrupts */
83 #define PCI1734_IDO 0 /* W: Isolated digital output 0-31 */
84 #define PCI173x_BOARDID 4 /* R: Board I/D switch for 1730/3/4 */
86 /* Advantech PCI-1735U */
87 #define PCI1735_DI 0 /* R: Digital input 0-31 */
88 #define PCI1735_DO 0 /* W: Digital output 0-31 */
89 #define PCI1735_C8254 4 /* R/W: 8254 counter */
90 #define PCI1735_BOARDID 8 /* R: Board I/D switch for 1735U */
92 /* Advantech PCI-1736UP */
93 #define PCI1736_IDI 0 /* R: Isolated digital input 0-15 */
94 #define PCI1736_IDO 0 /* W: Isolated digital output 0-15 */
95 #define PCI1736_3_INT_EN 0x08 /* R/W: enable/disable interrupts */
96 #define PCI1736_3_INT_RF 0x0c /* R/W: set falling/raising edge for
98 #define PCI1736_3_INT_CLR 0x10 /* R/W: clear interrupts */
99 #define PCI1736_BOARDID 4 /* R: Board I/D switch for 1736UP */
100 #define PCI1736_MAINREG 0 /* Normal register (2) doesn't work */
102 /* Advantech PCI-1739U */
103 #define PCI1739_DIO 0 /* R/W: begin of 8255 registers block */
104 #define PCI1739_ICR 32 /* W: Interrupt control register */
105 #define PCI1739_ISR 32 /* R: Interrupt status register */
106 #define PCI1739_BOARDID 8 /* R: Board I/D switch for 1739U */
108 /* Advantech PCI-1750 */
109 #define PCI1750_IDI 0 /* R: Isolated digital input 0-15 */
110 #define PCI1750_IDO 0 /* W: Isolated digital output 0-15 */
111 #define PCI1750_ICR 32 /* W: Interrupt control register */
112 #define PCI1750_ISR 32 /* R: Interrupt status register */
114 /* Advantech PCI-1751/3/3E */
115 #define PCI1751_DIO 0 /* R/W: begin of 8255 registers block */
116 #define PCI1751_CNT 24 /* R/W: begin of 8254 registers block */
117 #define PCI1751_ICR 32 /* W: Interrupt control register */
118 #define PCI1751_ISR 32 /* R: Interrupt status register */
119 #define PCI1753_DIO 0 /* R/W: begin of 8255 registers block */
120 #define PCI1753_ICR0 16 /* R/W: Interrupt control register group 0 */
121 #define PCI1753_ICR1 17 /* R/W: Interrupt control register group 1 */
122 #define PCI1753_ICR2 18 /* R/W: Interrupt control register group 2 */
123 #define PCI1753_ICR3 19 /* R/W: Interrupt control register group 3 */
124 #define PCI1753E_DIO 32 /* R/W: begin of 8255 registers block */
125 #define PCI1753E_ICR0 48 /* R/W: Interrupt control register group 0 */
126 #define PCI1753E_ICR1 49 /* R/W: Interrupt control register group 1 */
127 #define PCI1753E_ICR2 50 /* R/W: Interrupt control register group 2 */
128 #define PCI1753E_ICR3 51 /* R/W: Interrupt control register group 3 */
130 /* Advantech PCI-1752/4/6 */
131 #define PCI1752_IDO 0 /* R/W: Digital output 0-31 */
132 #define PCI1752_IDO2 4 /* R/W: Digital output 32-63 */
133 #define PCI1754_IDI 0 /* R: Digital input 0-31 */
134 #define PCI1754_IDI2 4 /* R: Digital input 32-64 */
135 #define PCI1756_IDI 0 /* R: Digital input 0-31 */
136 #define PCI1756_IDO 4 /* R/W: Digital output 0-31 */
137 #define PCI1754_6_ICR0 0x08 /* R/W: Interrupt control register group 0 */
138 #define PCI1754_6_ICR1 0x0a /* R/W: Interrupt control register group 1 */
139 #define PCI1754_ICR2 0x0c /* R/W: Interrupt control register group 2 */
140 #define PCI1754_ICR3 0x0e /* R/W: Interrupt control register group 3 */
141 #define PCI1752_6_CFC 0x12 /* R/W: set/read channel freeze function */
142 #define PCI175x_BOARDID 0x10 /* R: Board I/D switch for 1752/4/6 */
144 /* Advantech PCI-1762 registers */
145 #define PCI1762_RO 0 /* R/W: Relays status/output */
146 #define PCI1762_IDI 2 /* R: Isolated input status */
147 #define PCI1762_BOARDID 4 /* R: Board I/D switch */
148 #define PCI1762_ICR 6 /* W: Interrupt control register */
149 #define PCI1762_ISR 6 /* R: Interrupt status register */
151 /* Advantech PCI-1760 registers */
152 #define OMB0 0x0c /* W: Mailbox outgoing registers */
156 #define IMB0 0x1c /* R: Mailbox incoming registers */
160 #define INTCSR0 0x38 /* R/W: Interrupt control registers */
165 /* PCI-1760 mailbox commands */
166 #define CMD_ClearIMB2 0x00 /* Clear IMB2 status and return actual
167 * DI status in IMB3 */
168 #define CMD_SetRelaysOutput 0x01 /* Set relay output from OMB0 */
169 #define CMD_GetRelaysStatus 0x02 /* Get relay status to IMB0 */
170 #define CMD_ReadCurrentStatus 0x07 /* Read the current status of the
171 * register in OMB0, result in IMB0 */
172 #define CMD_ReadFirmwareVersion 0x0e /* Read the firmware ver., result in
174 #define CMD_ReadHardwareVersion 0x0f /* Read the hardware ver., result in
176 #define CMD_EnableIDIFilters 0x20 /* Enable IDI filters based on bits in
178 #define CMD_EnableIDIPatternMatch 0x21 /* Enable IDI pattern match based on
180 #define CMD_SetIDIPatternMatch 0x22 /* Enable IDI pattern match based on
182 #define CMD_EnableIDICounters 0x28 /* Enable IDI counters based on bits in
184 #define CMD_ResetIDICounters 0x29 /* Reset IDI counters based on bits in
185 * OMB0 to its reset values */
186 #define CMD_OverflowIDICounters 0x2a /* Enable IDI counters overflow
187 * interrupts based on bits in OMB0 */
188 #define CMD_MatchIntIDICounters 0x2b /* Enable IDI counters match value
189 * interrupts based on bits in OMB0 */
190 #define CMD_EdgeIDICounters 0x2c /* Set IDI up counters count edge (bit=0
191 * - rising, =1 - falling) */
192 #define CMD_GetIDICntCurValue 0x2f /* Read IDI{OMB0} up counter current
194 #define CMD_SetIDI0CntResetValue 0x40 /* Set IDI0 Counter Reset Value
196 #define CMD_SetIDI1CntResetValue 0x41 /* Set IDI1 Counter Reset Value
198 #define CMD_SetIDI2CntResetValue 0x42 /* Set IDI2 Counter Reset Value
200 #define CMD_SetIDI3CntResetValue 0x43 /* Set IDI3 Counter Reset Value
202 #define CMD_SetIDI4CntResetValue 0x44 /* Set IDI4 Counter Reset Value
204 #define CMD_SetIDI5CntResetValue 0x45 /* Set IDI5 Counter Reset Value
206 #define CMD_SetIDI6CntResetValue 0x46 /* Set IDI6 Counter Reset Value
208 #define CMD_SetIDI7CntResetValue 0x47 /* Set IDI7 Counter Reset Value
210 #define CMD_SetIDI0CntMatchValue 0x48 /* Set IDI0 Counter Match Value
212 #define CMD_SetIDI1CntMatchValue 0x49 /* Set IDI1 Counter Match Value
214 #define CMD_SetIDI2CntMatchValue 0x4a /* Set IDI2 Counter Match Value
216 #define CMD_SetIDI3CntMatchValue 0x4b /* Set IDI3 Counter Match Value
218 #define CMD_SetIDI4CntMatchValue 0x4c /* Set IDI4 Counter Match Value
220 #define CMD_SetIDI5CntMatchValue 0x4d /* Set IDI5 Counter Match Value
222 #define CMD_SetIDI6CntMatchValue 0x4e /* Set IDI6 Counter Match Value
224 #define CMD_SetIDI7CntMatchValue 0x4f /* Set IDI7 Counter Match Value
227 #define OMBCMD_RETRY 0x03 /* 3 times try request before error */
229 struct diosubd_data {
230 int chans; /* num of chans */
231 int addr; /* PCI address ofset */
232 int regs; /* number of registers to read or 8255
233 subdevices or 8254 chips */
234 unsigned int specflags; /* addon subdevice flags */
237 struct dio_boardtype {
238 const char *name; /* board name */
239 int vendor_id; /* vendor/device PCI ID */
241 int main_pci_region; /* main I/O PCI region */
242 enum hw_cards_id cardtype;
244 struct diosubd_data sdi[MAX_DI_SUBDEVS]; /* DI chans */
245 struct diosubd_data sdo[MAX_DO_SUBDEVS]; /* DO chans */
246 struct diosubd_data sdio[MAX_DIO_SUBDEVG]; /* DIO 8255 chans */
247 struct diosubd_data boardid; /* card supports board ID switch */
248 struct diosubd_data s8254[MAX_8254_SUBDEVS]; /* 8254 subdevices */
249 enum hw_io_access io_access;
252 static const struct dio_boardtype boardtypes[] = {
255 .vendor_id = PCI_VENDOR_ID_ADVANTECH,
257 .main_pci_region = PCIDIO_MAINREG,
258 .cardtype = TYPE_PCI1730,
260 .sdi[0] = { 16, PCI1730_DI, 2, 0, },
261 .sdi[1] = { 16, PCI1730_IDI, 2, 0, },
262 .sdo[0] = { 16, PCI1730_DO, 2, 0, },
263 .sdo[1] = { 16, PCI1730_IDO, 2, 0, },
264 .boardid = { 4, PCI173x_BOARDID, 1, SDF_INTERNAL, },
268 .vendor_id = PCI_VENDOR_ID_ADVANTECH,
270 .main_pci_region = PCIDIO_MAINREG,
271 .cardtype = TYPE_PCI1733,
273 .sdi[1] = { 32, PCI1733_IDI, 4, 0, },
274 .boardid = { 4, PCI173x_BOARDID, 1, SDF_INTERNAL, },
278 .vendor_id = PCI_VENDOR_ID_ADVANTECH,
280 .main_pci_region = PCIDIO_MAINREG,
281 .cardtype = TYPE_PCI1734,
283 .sdo[1] = { 32, PCI1734_IDO, 4, 0, },
284 .boardid = { 4, PCI173x_BOARDID, 1, SDF_INTERNAL, },
288 .vendor_id = PCI_VENDOR_ID_ADVANTECH,
290 .main_pci_region = PCIDIO_MAINREG,
291 .cardtype = TYPE_PCI1735,
293 .sdi[0] = { 32, PCI1735_DI, 4, 0, },
294 .sdo[0] = { 32, PCI1735_DO, 4, 0, },
295 .boardid = { 4, PCI1735_BOARDID, 1, SDF_INTERNAL, },
296 .s8254[0] = { 3, PCI1735_C8254, 1, 0, },
300 .vendor_id = PCI_VENDOR_ID_ADVANTECH,
302 .main_pci_region = PCI1736_MAINREG,
303 .cardtype = TYPE_PCI1736,
305 .sdi[1] = { 16, PCI1736_IDI, 2, 0, },
306 .sdo[1] = { 16, PCI1736_IDO, 2, 0, },
307 .boardid = { 4, PCI1736_BOARDID, 1, SDF_INTERNAL, },
311 .vendor_id = PCI_VENDOR_ID_ADVANTECH,
313 .main_pci_region = PCIDIO_MAINREG,
314 .cardtype = TYPE_PCI1739,
316 .sdio[0] = { 48, PCI1739_DIO, 2, 0, },
320 .vendor_id = PCI_VENDOR_ID_ADVANTECH,
322 .main_pci_region = PCIDIO_MAINREG,
323 .cardtype = TYPE_PCI1750,
325 .sdi[1] = { 16, PCI1750_IDI, 2, 0, },
326 .sdo[1] = { 16, PCI1750_IDO, 2, 0, },
330 .vendor_id = PCI_VENDOR_ID_ADVANTECH,
332 .main_pci_region = PCIDIO_MAINREG,
333 .cardtype = TYPE_PCI1751,
335 .sdio[0] = { 48, PCI1751_DIO, 2, 0, },
336 .s8254[0] = { 3, PCI1751_CNT, 1, 0, },
340 .vendor_id = PCI_VENDOR_ID_ADVANTECH,
342 .main_pci_region = PCIDIO_MAINREG,
343 .cardtype = TYPE_PCI1752,
345 .sdo[0] = { 32, PCI1752_IDO, 2, 0, },
346 .sdo[1] = { 32, PCI1752_IDO2, 2, 0, },
347 .boardid = { 4, PCI175x_BOARDID, 1, SDF_INTERNAL, },
351 .vendor_id = PCI_VENDOR_ID_ADVANTECH,
353 .main_pci_region = PCIDIO_MAINREG,
354 .cardtype = TYPE_PCI1753,
356 .sdio[0] = { 96, PCI1753_DIO, 4, 0, },
360 .vendor_id = PCI_VENDOR_ID_ADVANTECH,
362 .main_pci_region = PCIDIO_MAINREG,
363 .cardtype = TYPE_PCI1753E,
365 .sdio[0] = { 96, PCI1753_DIO, 4, 0, },
366 .sdio[1] = { 96, PCI1753E_DIO, 4, 0, },
370 .vendor_id = PCI_VENDOR_ID_ADVANTECH,
372 .main_pci_region = PCIDIO_MAINREG,
373 .cardtype = TYPE_PCI1754,
375 .sdi[0] = { 32, PCI1754_IDI, 2, 0, },
376 .sdi[1] = { 32, PCI1754_IDI2, 2, 0, },
377 .boardid = { 4, PCI175x_BOARDID, 1, SDF_INTERNAL, },
381 .vendor_id = PCI_VENDOR_ID_ADVANTECH,
383 .main_pci_region = PCIDIO_MAINREG,
384 .cardtype = TYPE_PCI1756,
386 .sdi[1] = { 32, PCI1756_IDI, 2, 0, },
387 .sdo[1] = { 32, PCI1756_IDO, 2, 0, },
388 .boardid = { 4, PCI175x_BOARDID, 1, SDF_INTERNAL, },
391 /* This card has its own 'attach' */
393 .vendor_id = PCI_VENDOR_ID_ADVANTECH,
395 .main_pci_region = 0,
396 .cardtype = TYPE_PCI1760,
401 .vendor_id = PCI_VENDOR_ID_ADVANTECH,
403 .main_pci_region = PCIDIO_MAINREG,
404 .cardtype = TYPE_PCI1762,
406 .sdi[1] = { 16, PCI1762_IDI, 1, 0, },
407 .sdo[1] = { 16, PCI1762_RO, 1, 0, },
408 .boardid = { 4, PCI1762_BOARDID, 1, SDF_INTERNAL, },
413 struct pci_dio_private {
414 char valid; /* card is usable */
415 char GlobalIrqEnabled; /* 1= any IRQ source is enabled */
416 /* PCI-1760 specific data */
417 unsigned char IDICntEnable; /* counter's counting enable status */
418 unsigned char IDICntOverEnable; /* counter's overflow interrupts enable
420 unsigned char IDICntMatchEnable; /* counter's match interrupts
422 unsigned char IDICntEdge; /* counter's count edge value
423 * (bit=0 - rising, =1 - falling) */
424 unsigned short CntResValue[8]; /* counters' reset value */
425 unsigned short CntMatchValue[8]; /* counters' match interrupt value */
426 unsigned char IDIFiltersEn; /* IDI's digital filters enable status */
427 unsigned char IDIPatMatchEn; /* IDI's pattern match enable status */
428 unsigned char IDIPatMatchValue; /* IDI's pattern match value */
429 unsigned short IDIFiltrLow[8]; /* IDI's filter value low signal */
430 unsigned short IDIFiltrHigh[8]; /* IDI's filter value high signal */
434 ==============================================================================
436 static int pci_dio_insn_bits_di_b(struct comedi_device *dev,
437 struct comedi_subdevice *s,
438 struct comedi_insn *insn, unsigned int *data)
440 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
444 for (i = 0; i < d->regs; i++)
445 data[1] |= inb(dev->iobase + d->addr + i) << (8 * i);
452 ==============================================================================
454 static int pci_dio_insn_bits_di_w(struct comedi_device *dev,
455 struct comedi_subdevice *s,
456 struct comedi_insn *insn, unsigned int *data)
458 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
462 for (i = 0; i < d->regs; i++)
463 data[1] |= inw(dev->iobase + d->addr + 2 * i) << (16 * i);
469 ==============================================================================
471 static int pci_dio_insn_bits_do_b(struct comedi_device *dev,
472 struct comedi_subdevice *s,
473 struct comedi_insn *insn, unsigned int *data)
475 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
479 s->state &= ~data[0];
480 s->state |= (data[0] & data[1]);
481 for (i = 0; i < d->regs; i++)
482 outb((s->state >> (8 * i)) & 0xff,
483 dev->iobase + d->addr + i);
491 ==============================================================================
493 static int pci_dio_insn_bits_do_w(struct comedi_device *dev,
494 struct comedi_subdevice *s,
495 struct comedi_insn *insn, unsigned int *data)
497 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
501 s->state &= ~data[0];
502 s->state |= (data[0] & data[1]);
503 for (i = 0; i < d->regs; i++)
504 outw((s->state >> (16 * i)) & 0xffff,
505 dev->iobase + d->addr + 2 * i);
513 ==============================================================================
515 static int pci_8254_insn_read(struct comedi_device *dev,
516 struct comedi_subdevice *s,
517 struct comedi_insn *insn, unsigned int *data)
519 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
520 unsigned int chan, chip, chipchan;
523 chan = CR_CHAN(insn->chanspec); /* channel on subdevice */
524 chip = chan / 3; /* chip on subdevice */
525 chipchan = chan - (3 * chip); /* channel on chip on subdevice */
526 spin_lock_irqsave(&s->spin_lock, flags);
527 data[0] = i8254_read(dev->iobase + d->addr + (SIZE_8254 * chip),
529 spin_unlock_irqrestore(&s->spin_lock, flags);
534 ==============================================================================
536 static int pci_8254_insn_write(struct comedi_device *dev,
537 struct comedi_subdevice *s,
538 struct comedi_insn *insn, unsigned int *data)
540 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
541 unsigned int chan, chip, chipchan;
544 chan = CR_CHAN(insn->chanspec); /* channel on subdevice */
545 chip = chan / 3; /* chip on subdevice */
546 chipchan = chan - (3 * chip); /* channel on chip on subdevice */
547 spin_lock_irqsave(&s->spin_lock, flags);
548 i8254_write(dev->iobase + d->addr + (SIZE_8254 * chip),
549 0, chipchan, data[0]);
550 spin_unlock_irqrestore(&s->spin_lock, flags);
555 ==============================================================================
557 static int pci_8254_insn_config(struct comedi_device *dev,
558 struct comedi_subdevice *s,
559 struct comedi_insn *insn, unsigned int *data)
561 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
562 unsigned int chan, chip, chipchan;
563 unsigned long iobase;
567 chan = CR_CHAN(insn->chanspec); /* channel on subdevice */
568 chip = chan / 3; /* chip on subdevice */
569 chipchan = chan - (3 * chip); /* channel on chip on subdevice */
570 iobase = dev->iobase + d->addr + (SIZE_8254 * chip);
571 spin_lock_irqsave(&s->spin_lock, flags);
573 case INSN_CONFIG_SET_COUNTER_MODE:
574 ret = i8254_set_mode(iobase, 0, chipchan, data[1]);
578 case INSN_CONFIG_8254_READ_STATUS:
579 data[1] = i8254_status(iobase, 0, chipchan);
585 spin_unlock_irqrestore(&s->spin_lock, flags);
586 return ret < 0 ? ret : insn->n;
590 ==============================================================================
592 static int pci1760_unchecked_mbxrequest(struct comedi_device *dev,
593 unsigned char *omb, unsigned char *imb,
596 int cnt, tout, ok = 0;
598 for (cnt = 0; cnt < repeats; cnt++) {
599 outb(omb[0], dev->iobase + OMB0);
600 outb(omb[1], dev->iobase + OMB1);
601 outb(omb[2], dev->iobase + OMB2);
602 outb(omb[3], dev->iobase + OMB3);
603 for (tout = 0; tout < 251; tout++) {
604 imb[2] = inb(dev->iobase + IMB2);
605 if (imb[2] == omb[2]) {
606 imb[0] = inb(dev->iobase + IMB0);
607 imb[1] = inb(dev->iobase + IMB1);
608 imb[3] = inb(dev->iobase + IMB3);
618 comedi_error(dev, "PCI-1760 mailbox request timeout!");
622 static int pci1760_clear_imb2(struct comedi_device *dev)
624 unsigned char omb[4] = { 0x0, 0x0, CMD_ClearIMB2, 0x0 };
625 unsigned char imb[4];
626 /* check if imb2 is already clear */
627 if (inb(dev->iobase + IMB2) == CMD_ClearIMB2)
629 return pci1760_unchecked_mbxrequest(dev, omb, imb, OMBCMD_RETRY);
632 static int pci1760_mbxrequest(struct comedi_device *dev,
633 unsigned char *omb, unsigned char *imb)
635 if (omb[2] == CMD_ClearIMB2) {
637 "bug! this function should not be used for CMD_ClearIMB2 command");
640 if (inb(dev->iobase + IMB2) == omb[2]) {
642 retval = pci1760_clear_imb2(dev);
646 return pci1760_unchecked_mbxrequest(dev, omb, imb, OMBCMD_RETRY);
650 ==============================================================================
652 static int pci1760_insn_bits_di(struct comedi_device *dev,
653 struct comedi_subdevice *s,
654 struct comedi_insn *insn, unsigned int *data)
656 data[1] = inb(dev->iobase + IMB3);
662 ==============================================================================
664 static int pci1760_insn_bits_do(struct comedi_device *dev,
665 struct comedi_subdevice *s,
666 struct comedi_insn *insn, unsigned int *data)
669 unsigned char omb[4] = {
675 unsigned char imb[4];
678 s->state &= ~data[0];
679 s->state |= (data[0] & data[1]);
681 ret = pci1760_mbxrequest(dev, omb, imb);
691 ==============================================================================
693 static int pci1760_insn_cnt_read(struct comedi_device *dev,
694 struct comedi_subdevice *s,
695 struct comedi_insn *insn, unsigned int *data)
698 unsigned char omb[4] = {
699 CR_CHAN(insn->chanspec) & 0x07,
701 CMD_GetIDICntCurValue,
704 unsigned char imb[4];
706 for (n = 0; n < insn->n; n++) {
707 ret = pci1760_mbxrequest(dev, omb, imb);
710 data[n] = (imb[1] << 8) + imb[0];
717 ==============================================================================
719 static int pci1760_insn_cnt_write(struct comedi_device *dev,
720 struct comedi_subdevice *s,
721 struct comedi_insn *insn, unsigned int *data)
723 struct pci_dio_private *devpriv = dev->private;
725 unsigned char chan = CR_CHAN(insn->chanspec) & 0x07;
726 unsigned char bitmask = 1 << chan;
727 unsigned char omb[4] = {
729 (data[0] >> 8) & 0xff,
730 CMD_SetIDI0CntResetValue + chan,
733 unsigned char imb[4];
735 /* Set reset value if different */
736 if (devpriv->CntResValue[chan] != (data[0] & 0xffff)) {
737 ret = pci1760_mbxrequest(dev, omb, imb);
740 devpriv->CntResValue[chan] = data[0] & 0xffff;
743 omb[0] = bitmask; /* reset counter to it reset value */
744 omb[2] = CMD_ResetIDICounters;
745 ret = pci1760_mbxrequest(dev, omb, imb);
749 /* start counter if it don't run */
750 if (!(bitmask & devpriv->IDICntEnable)) {
752 omb[2] = CMD_EnableIDICounters;
753 ret = pci1760_mbxrequest(dev, omb, imb);
756 devpriv->IDICntEnable |= bitmask;
762 ==============================================================================
764 static int pci1760_reset(struct comedi_device *dev)
766 struct pci_dio_private *devpriv = dev->private;
768 unsigned char omb[4] = { 0x00, 0x00, 0x00, 0x00 };
769 unsigned char imb[4];
771 outb(0, dev->iobase + INTCSR0); /* disable IRQ */
772 outb(0, dev->iobase + INTCSR1);
773 outb(0, dev->iobase + INTCSR2);
774 outb(0, dev->iobase + INTCSR3);
775 devpriv->GlobalIrqEnabled = 0;
778 omb[2] = CMD_SetRelaysOutput; /* reset relay outputs */
779 pci1760_mbxrequest(dev, omb, imb);
782 omb[2] = CMD_EnableIDICounters; /* disable IDI up counters */
783 pci1760_mbxrequest(dev, omb, imb);
784 devpriv->IDICntEnable = 0;
787 omb[2] = CMD_OverflowIDICounters; /* disable counters overflow
789 pci1760_mbxrequest(dev, omb, imb);
790 devpriv->IDICntOverEnable = 0;
793 omb[2] = CMD_MatchIntIDICounters; /* disable counters match value
795 pci1760_mbxrequest(dev, omb, imb);
796 devpriv->IDICntMatchEnable = 0;
800 for (i = 0; i < 8; i++) { /* set IDI up counters match value */
801 omb[2] = CMD_SetIDI0CntMatchValue + i;
802 pci1760_mbxrequest(dev, omb, imb);
803 devpriv->CntMatchValue[i] = 0x8000;
808 for (i = 0; i < 8; i++) { /* set IDI up counters reset value */
809 omb[2] = CMD_SetIDI0CntResetValue + i;
810 pci1760_mbxrequest(dev, omb, imb);
811 devpriv->CntResValue[i] = 0x0000;
815 omb[2] = CMD_ResetIDICounters; /* reset IDI up counters to reset
817 pci1760_mbxrequest(dev, omb, imb);
820 omb[2] = CMD_EdgeIDICounters; /* set IDI up counters count edge */
821 pci1760_mbxrequest(dev, omb, imb);
822 devpriv->IDICntEdge = 0x00;
825 omb[2] = CMD_EnableIDIFilters; /* disable all digital in filters */
826 pci1760_mbxrequest(dev, omb, imb);
827 devpriv->IDIFiltersEn = 0x00;
830 omb[2] = CMD_EnableIDIPatternMatch; /* disable pattern matching */
831 pci1760_mbxrequest(dev, omb, imb);
832 devpriv->IDIPatMatchEn = 0x00;
835 omb[2] = CMD_SetIDIPatternMatch; /* set pattern match value */
836 pci1760_mbxrequest(dev, omb, imb);
837 devpriv->IDIPatMatchValue = 0x00;
843 ==============================================================================
845 static int pci_dio_reset(struct comedi_device *dev)
847 const struct dio_boardtype *this_board = comedi_board(dev);
849 switch (this_board->cardtype) {
851 outb(0, dev->iobase + PCI1730_DO); /* clear outputs */
852 outb(0, dev->iobase + PCI1730_DO + 1);
853 outb(0, dev->iobase + PCI1730_IDO);
854 outb(0, dev->iobase + PCI1730_IDO + 1);
855 /* NO break there! */
857 /* disable interrupts */
858 outb(0, dev->iobase + PCI1730_3_INT_EN);
859 /* clear interrupts */
860 outb(0x0f, dev->iobase + PCI1730_3_INT_CLR);
861 /* set rising edge trigger */
862 outb(0, dev->iobase + PCI1730_3_INT_RF);
865 outb(0, dev->iobase + PCI1734_IDO); /* clear outputs */
866 outb(0, dev->iobase + PCI1734_IDO + 1);
867 outb(0, dev->iobase + PCI1734_IDO + 2);
868 outb(0, dev->iobase + PCI1734_IDO + 3);
871 outb(0, dev->iobase + PCI1735_DO); /* clear outputs */
872 outb(0, dev->iobase + PCI1735_DO + 1);
873 outb(0, dev->iobase + PCI1735_DO + 2);
874 outb(0, dev->iobase + PCI1735_DO + 3);
875 i8254_set_mode(dev->iobase + PCI1735_C8254, 0, 0, I8254_MODE0);
876 i8254_set_mode(dev->iobase + PCI1735_C8254, 0, 1, I8254_MODE0);
877 i8254_set_mode(dev->iobase + PCI1735_C8254, 0, 2, I8254_MODE0);
881 outb(0, dev->iobase + PCI1736_IDO);
882 outb(0, dev->iobase + PCI1736_IDO + 1);
883 /* disable interrupts */
884 outb(0, dev->iobase + PCI1736_3_INT_EN);
885 /* clear interrupts */
886 outb(0x0f, dev->iobase + PCI1736_3_INT_CLR);
887 /* set rising edge trigger */
888 outb(0, dev->iobase + PCI1736_3_INT_RF);
892 /* disable & clear interrupts */
893 outb(0x88, dev->iobase + PCI1739_ICR);
898 /* disable & clear interrupts */
899 outb(0x88, dev->iobase + PCI1750_ICR);
902 outw(0, dev->iobase + PCI1752_6_CFC); /* disable channel freeze
904 outw(0, dev->iobase + PCI1752_IDO); /* clear outputs */
905 outw(0, dev->iobase + PCI1752_IDO + 2);
906 outw(0, dev->iobase + PCI1752_IDO2);
907 outw(0, dev->iobase + PCI1752_IDO2 + 2);
910 outb(0x88, dev->iobase + PCI1753E_ICR0); /* disable & clear
912 outb(0x80, dev->iobase + PCI1753E_ICR1);
913 outb(0x80, dev->iobase + PCI1753E_ICR2);
914 outb(0x80, dev->iobase + PCI1753E_ICR3);
915 /* NO break there! */
917 outb(0x88, dev->iobase + PCI1753_ICR0); /* disable & clear
919 outb(0x80, dev->iobase + PCI1753_ICR1);
920 outb(0x80, dev->iobase + PCI1753_ICR2);
921 outb(0x80, dev->iobase + PCI1753_ICR3);
924 outw(0x08, dev->iobase + PCI1754_6_ICR0); /* disable and clear
926 outw(0x08, dev->iobase + PCI1754_6_ICR1);
927 outw(0x08, dev->iobase + PCI1754_ICR2);
928 outw(0x08, dev->iobase + PCI1754_ICR3);
931 outw(0, dev->iobase + PCI1752_6_CFC); /* disable channel freeze
933 outw(0x08, dev->iobase + PCI1754_6_ICR0); /* disable and clear
935 outw(0x08, dev->iobase + PCI1754_6_ICR1);
936 outw(0, dev->iobase + PCI1756_IDO); /* clear outputs */
937 outw(0, dev->iobase + PCI1756_IDO + 2);
943 outw(0x0101, dev->iobase + PCI1762_ICR); /* disable & clear
952 ==============================================================================
954 static int pci1760_attach(struct comedi_device *dev)
956 struct comedi_subdevice *s;
958 s = &dev->subdevices[0];
959 s->type = COMEDI_SUBD_DI;
960 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_COMMON;
964 s->range_table = &range_digital;
965 s->insn_bits = pci1760_insn_bits_di;
967 s = &dev->subdevices[1];
968 s->type = COMEDI_SUBD_DO;
969 s->subdev_flags = SDF_WRITABLE | SDF_GROUND | SDF_COMMON;
973 s->range_table = &range_digital;
975 s->insn_bits = pci1760_insn_bits_do;
977 s = &dev->subdevices[2];
978 s->type = COMEDI_SUBD_TIMER;
979 s->subdev_flags = SDF_WRITABLE | SDF_LSAMPL;
981 s->maxdata = 0xffffffff;
983 /* s->insn_config=pci1760_insn_pwm_cfg; */
985 s = &dev->subdevices[3];
986 s->type = COMEDI_SUBD_COUNTER;
987 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
991 s->insn_read = pci1760_insn_cnt_read;
992 s->insn_write = pci1760_insn_cnt_write;
993 /* s->insn_config=pci1760_insn_cnt_cfg; */
999 ==============================================================================
1001 static int pci_dio_add_di(struct comedi_device *dev,
1002 struct comedi_subdevice *s,
1003 const struct diosubd_data *d)
1005 const struct dio_boardtype *this_board = comedi_board(dev);
1007 s->type = COMEDI_SUBD_DI;
1008 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_COMMON | d->specflags;
1010 s->subdev_flags |= SDF_LSAMPL;
1011 s->n_chan = d->chans;
1013 s->len_chanlist = d->chans;
1014 s->range_table = &range_digital;
1015 switch (this_board->io_access) {
1017 s->insn_bits = pci_dio_insn_bits_di_b;
1020 s->insn_bits = pci_dio_insn_bits_di_w;
1023 s->private = (void *)d;
1029 ==============================================================================
1031 static int pci_dio_add_do(struct comedi_device *dev,
1032 struct comedi_subdevice *s,
1033 const struct diosubd_data *d)
1035 const struct dio_boardtype *this_board = comedi_board(dev);
1037 s->type = COMEDI_SUBD_DO;
1038 s->subdev_flags = SDF_WRITABLE | SDF_GROUND | SDF_COMMON;
1040 s->subdev_flags |= SDF_LSAMPL;
1041 s->n_chan = d->chans;
1043 s->len_chanlist = d->chans;
1044 s->range_table = &range_digital;
1046 switch (this_board->io_access) {
1048 s->insn_bits = pci_dio_insn_bits_do_b;
1051 s->insn_bits = pci_dio_insn_bits_do_w;
1054 s->private = (void *)d;
1060 ==============================================================================
1062 static int pci_dio_add_8254(struct comedi_device *dev,
1063 struct comedi_subdevice *s,
1064 const struct diosubd_data *d)
1066 s->type = COMEDI_SUBD_COUNTER;
1067 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
1068 s->n_chan = d->chans;
1070 s->len_chanlist = d->chans;
1071 s->insn_read = pci_8254_insn_read;
1072 s->insn_write = pci_8254_insn_write;
1073 s->insn_config = pci_8254_insn_config;
1074 s->private = (void *)d;
1079 static const void *pci_dio_find_boardinfo(struct comedi_device *dev,
1080 struct pci_dev *pcidev)
1082 const struct dio_boardtype *this_board;
1085 for (i = 0; i < ARRAY_SIZE(boardtypes); ++i) {
1086 this_board = &boardtypes[i];
1087 if (this_board->vendor_id == pcidev->vendor &&
1088 this_board->device_id == pcidev->device)
1094 static int pci_dio_auto_attach(struct comedi_device *dev,
1095 unsigned long context_unused)
1097 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1098 const struct dio_boardtype *this_board;
1099 struct pci_dio_private *devpriv;
1100 struct comedi_subdevice *s;
1101 int ret, subdev, i, j;
1103 this_board = pci_dio_find_boardinfo(dev, pcidev);
1106 dev->board_ptr = this_board;
1107 dev->board_name = this_board->name;
1109 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
1112 dev->private = devpriv;
1114 ret = comedi_pci_enable(pcidev, dev->board_name);
1117 dev->iobase = pci_resource_start(pcidev, this_board->main_pci_region);
1119 ret = comedi_alloc_subdevices(dev, this_board->nsubdevs);
1124 for (i = 0; i < MAX_DI_SUBDEVS; i++)
1125 if (this_board->sdi[i].chans) {
1126 s = &dev->subdevices[subdev];
1127 pci_dio_add_di(dev, s, &this_board->sdi[i]);
1131 for (i = 0; i < MAX_DO_SUBDEVS; i++)
1132 if (this_board->sdo[i].chans) {
1133 s = &dev->subdevices[subdev];
1134 pci_dio_add_do(dev, s, &this_board->sdo[i]);
1138 for (i = 0; i < MAX_DIO_SUBDEVG; i++)
1139 for (j = 0; j < this_board->sdio[i].regs; j++) {
1140 s = &dev->subdevices[subdev];
1141 subdev_8255_init(dev, s, NULL,
1143 this_board->sdio[i].addr +
1148 if (this_board->boardid.chans) {
1149 s = &dev->subdevices[subdev];
1150 s->type = COMEDI_SUBD_DI;
1151 pci_dio_add_di(dev, s, &this_board->boardid);
1155 for (i = 0; i < MAX_8254_SUBDEVS; i++)
1156 if (this_board->s8254[i].chans) {
1157 s = &dev->subdevices[subdev];
1158 pci_dio_add_8254(dev, s, &this_board->s8254[i]);
1162 if (this_board->cardtype == TYPE_PCI1760)
1163 pci1760_attach(dev);
1172 static void pci_dio_detach(struct comedi_device *dev)
1174 struct pci_dio_private *devpriv = dev->private;
1175 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1176 struct comedi_subdevice *s;
1183 if (dev->subdevices) {
1184 for (i = 0; i < dev->n_subdevices; i++) {
1185 s = &dev->subdevices[i];
1186 if (s->type == COMEDI_SUBD_DIO)
1187 subdev_8255_cleanup(dev, s);
1193 comedi_pci_disable(pcidev);
1197 static struct comedi_driver adv_pci_dio_driver = {
1198 .driver_name = "adv_pci_dio",
1199 .module = THIS_MODULE,
1200 .auto_attach = pci_dio_auto_attach,
1201 .detach = pci_dio_detach,
1204 static int adv_pci_dio_pci_probe(struct pci_dev *dev,
1205 const struct pci_device_id *ent)
1207 return comedi_pci_auto_config(dev, &adv_pci_dio_driver);
1210 static DEFINE_PCI_DEVICE_TABLE(adv_pci_dio_pci_table) = {
1211 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1730) },
1212 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1733) },
1213 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1734) },
1214 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1735) },
1215 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1736) },
1216 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1739) },
1217 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1750) },
1218 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1751) },
1219 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1752) },
1220 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1753) },
1221 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1754) },
1222 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1756) },
1223 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1760) },
1224 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1762) },
1227 MODULE_DEVICE_TABLE(pci, adv_pci_dio_pci_table);
1229 static struct pci_driver adv_pci_dio_pci_driver = {
1230 .name = "adv_pci_dio",
1231 .id_table = adv_pci_dio_pci_table,
1232 .probe = adv_pci_dio_pci_probe,
1233 .remove = comedi_pci_auto_unconfig,
1235 module_comedi_pci_driver(adv_pci_dio_driver, adv_pci_dio_pci_driver);
1237 MODULE_AUTHOR("Comedi http://www.comedi.org");
1238 MODULE_DESCRIPTION("Comedi low-level driver");
1239 MODULE_LICENSE("GPL");