2 comedi/drivers/amplc_dio200.c
3 Driver for Amplicon PC272E and PCI272 DIO boards.
4 (Support for other boards in Amplicon 200 series may be added at
5 a later date, e.g. PCI215.)
7 Copyright (C) 2005 MEV Ltd. <http://www.mev.co.uk/>
9 COMEDI - Linux Control and Measurement Device Interface
10 Copyright (C) 1998,2000 David A. Schleef <ds@schleef.org>
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 * Driver: amplc_dio200
29 * Description: Amplicon 200 Series Digital I/O
30 * Author: Ian Abbott <abbotti@mev.co.uk>
31 * Devices: [Amplicon] PC212E (pc212e), PC214E (pc214e), PC215E (pc215e),
32 * PCI215 (pci215), PCIe215 (pcie215), PC218E (pc218e), PCIe236 (pcie236),
33 * PC272E (pc272e), PCI272 (pci272), PCIe296 (pcie296)
34 * Updated: Wed, 24 Oct 2012 16:22:34 +0100
37 * Configuration options - PC212E, PC214E, PC215E, PC218E, PC272E:
38 * [0] - I/O port base address
39 * [1] - IRQ (optional, but commands won't work without it)
41 * Manual configuration of PCI(e) cards is not supported; they are configured
44 * Passing a zero for an option is the same as leaving it unspecified.
48 * PC212E PC214E PC215E/PCI215
49 * ------------- ------------- -------------
52 * 1 CTR-Y1 PPI-Y PPI-Y
53 * 2 CTR-Y2 CTR-Z1* CTR-Z1
54 * 3 CTR-Z1 INTERRUPT* CTR-Z2
58 * PCIe215 PC218E PCIe236
59 * ------------- ------------- -------------
61 * 0 PPI-X CTR-X1 PPI-X
62 * 1 UNUSED CTR-X2 UNUSED
63 * 2 PPI-Y CTR-Y1 UNUSED
64 * 3 UNUSED CTR-Y2 UNUSED
65 * 4 CTR-Z1 CTR-Z1 CTR-Z1
66 * 5 CTR-Z2 CTR-Z2 CTR-Z2
67 * 6 TIMER INTERRUPT TIMER
68 * 7 INTERRUPT INTERRUPT
70 * PC272E/PCI272 PCIe296
71 * ------------- -------------
82 * Each PPI is a 8255 chip providing 24 DIO channels. The DIO channels
83 * are configurable as inputs or outputs in four groups:
85 * Port A - channels 0 to 7
86 * Port B - channels 8 to 15
87 * Port CL - channels 16 to 19
88 * Port CH - channels 20 to 23
90 * Only mode 0 of the 8255 chips is supported.
92 * Each CTR is a 8254 chip providing 3 16-bit counter channels. Each
93 * channel is configured individually with INSN_CONFIG instructions. The
94 * specific type of configuration instruction is specified in data[0].
95 * Some configuration instructions expect an additional parameter in
96 * data[1]; others return a value in data[1]. The following configuration
97 * instructions are supported:
99 * INSN_CONFIG_SET_COUNTER_MODE. Sets the counter channel's mode and
100 * BCD/binary setting specified in data[1].
102 * INSN_CONFIG_8254_READ_STATUS. Reads the status register value for the
103 * counter channel into data[1].
105 * INSN_CONFIG_SET_CLOCK_SRC. Sets the counter channel's clock source as
106 * specified in data[1] (this is a hardware-specific value). Not
107 * supported on PC214E. For the other boards, valid clock sources are
110 * 0. CLK n, the counter channel's dedicated CLK input from the SK1
111 * connector. (N.B. for other values, the counter channel's CLKn
112 * pin on the SK1 connector is an output!)
113 * 1. Internal 10 MHz clock.
114 * 2. Internal 1 MHz clock.
115 * 3. Internal 100 kHz clock.
116 * 4. Internal 10 kHz clock.
117 * 5. Internal 1 kHz clock.
118 * 6. OUT n-1, the output of counter channel n-1 (see note 1 below).
119 * 7. Ext Clock, the counter chip's dedicated Ext Clock input from
120 * the SK1 connector. This pin is shared by all three counter
121 * channels on the chip.
123 * For the PCIe boards, clock sources in the range 0 to 31 are allowed
124 * and the following additional clock sources are defined:
126 * 8. HIGH logic level.
127 * 9. LOW logic level.
128 * 10. "Pattern present" signal.
129 * 11. Internal 20 MHz clock.
131 * INSN_CONFIG_GET_CLOCK_SRC. Returns the counter channel's current
132 * clock source in data[1]. For internal clock sources, data[2] is set
133 * to the period in ns.
135 * INSN_CONFIG_SET_GATE_SRC. Sets the counter channel's gate source as
136 * specified in data[2] (this is a hardware-specific value). Not
137 * supported on PC214E. For the other boards, valid gate sources are 0
140 * 0. VCC (internal +5V d.c.), i.e. gate permanently enabled.
141 * 1. GND (internal 0V d.c.), i.e. gate permanently disabled.
142 * 2. GAT n, the counter channel's dedicated GAT input from the SK1
143 * connector. (N.B. for other values, the counter channel's GATn
144 * pin on the SK1 connector is an output!)
145 * 3. /OUT n-2, the inverted output of counter channel n-2 (see note
152 * For the PCIe boards, gate sources in the range 0 to 31 are allowed;
153 * the following additional clock sources and clock sources 6 and 7 are
156 * 6. /GAT n, negated version of the counter channel's dedicated
157 * GAT input (negated version of gate source 2).
158 * 7. OUT n-2, the non-inverted output of counter channel n-2
159 * (negated version of gate source 3).
160 * 8. "Pattern present" signal, HIGH while pattern present.
161 * 9. "Pattern occurred" latched signal, latches HIGH when pattern
163 * 10. "Pattern gone away" latched signal, latches LOW when pattern
164 * goes away after it occurred.
165 * 11. Negated "pattern present" signal, LOW while pattern present
166 * (negated version of gate source 8).
167 * 12. Negated "pattern occurred" latched signal, latches LOW when
168 * pattern occurs (negated version of gate source 9).
169 * 13. Negated "pattern gone away" latched signal, latches LOW when
170 * pattern goes away after it occurred (negated version of gate
173 * INSN_CONFIG_GET_GATE_SRC. Returns the counter channel's current gate
176 * Clock and gate interconnection notes:
178 * 1. Clock source OUT n-1 is the output of the preceding channel on the
179 * same counter subdevice if n > 0, or the output of channel 2 on the
180 * preceding counter subdevice (see note 3) if n = 0.
182 * 2. Gate source /OUT n-2 is the inverted output of channel 0 on the
183 * same counter subdevice if n = 2, or the inverted output of channel n+1
184 * on the preceding counter subdevice (see note 3) if n < 2.
186 * 3. The counter subdevices are connected in a ring, so the highest
187 * counter subdevice precedes the lowest.
189 * The 'TIMER' subdevice is a free-running 32-bit timer subdevice.
191 * The 'INTERRUPT' subdevice pretends to be a digital input subdevice. The
192 * digital inputs come from the interrupt status register. The number of
193 * channels matches the number of interrupt sources. The PC214E does not
194 * have an interrupt status register; see notes on 'INTERRUPT SOURCES'
199 * PC212E PC214E PC215E/PCI215
200 * ------------- ------------- -------------
202 * 0 PPI-X-C0 JUMPER-J5 PPI-X-C0
203 * 1 PPI-X-C3 PPI-X-C3
204 * 2 CTR-Y1-OUT1 PPI-Y-C0
205 * 3 CTR-Y2-OUT1 PPI-Y-C3
206 * 4 CTR-Z1-OUT1 CTR-Z1-OUT1
207 * 5 CTR-Z2-OUT1 CTR-Z2-OUT1
209 * PCIe215 PC218E PCIe236
210 * ------------- ------------- -------------
212 * 0 PPI-X-C0 CTR-X1-OUT1 PPI-X-C0
213 * 1 PPI-X-C3 CTR-X2-OUT1 PPI-X-C3
214 * 2 PPI-Y-C0 CTR-Y1-OUT1 unused
215 * 3 PPI-Y-C3 CTR-Y2-OUT1 unused
216 * 4 CTR-Z1-OUT1 CTR-Z1-OUT1 CTR-Z1-OUT1
217 * 5 CTR-Z2-OUT1 CTR-Z2-OUT1 CTR-Z2-OUT1
219 * PC272E/PCI272 PCIe296
220 * ------------- -------------
222 * 0 PPI-X-C0 PPI-X1-C0
223 * 1 PPI-X-C3 PPI-X1-C3
224 * 2 PPI-Y-C0 PPI-Y1-C0
225 * 3 PPI-Y-C3 PPI-Y1-C3
226 * 4 PPI-Z-C0 CTR-Z1-OUT1
227 * 5 PPI-Z-C3 CTR-Z2-OUT1
229 * When an interrupt source is enabled in the interrupt source enable
230 * register, a rising edge on the source signal latches the corresponding
231 * bit to 1 in the interrupt status register.
233 * When the interrupt status register value as a whole (actually, just the
234 * 6 least significant bits) goes from zero to non-zero, the board will
235 * generate an interrupt. For level-triggered hardware interrupts (PCI
236 * card), the interrupt will remain asserted until the interrupt status
237 * register is cleared to zero. For edge-triggered hardware interrupts
238 * (ISA card), no further interrupts will occur until the interrupt status
239 * register is cleared to zero. To clear a bit to zero in the interrupt
240 * status register, the corresponding interrupt source must be disabled
241 * in the interrupt source enable register (there is no separate interrupt
244 * The PC214E does not have an interrupt source enable register or an
245 * interrupt status register; its 'INTERRUPT' subdevice has a single
246 * channel and its interrupt source is selected by the position of jumper
251 * The driver supports a read streaming acquisition command on the
252 * 'INTERRUPT' subdevice. The channel list selects the interrupt sources
253 * to be enabled. All channels will be sampled together (convert_src ==
254 * TRIG_NOW). The scan begins a short time after the hardware interrupt
255 * occurs, subject to interrupt latencies (scan_begin_src == TRIG_EXT,
256 * scan_begin_arg == 0). The value read from the interrupt status register
257 * is packed into a short value, one bit per requested channel, in the
258 * order they appear in the channel list.
261 #include <linux/interrupt.h>
262 #include <linux/slab.h>
264 #include "../comedidev.h"
266 #include "comedi_fc.h"
269 #define DIO200_DRIVER_NAME "amplc_dio200"
271 #define DO_ISA IS_ENABLED(CONFIG_COMEDI_AMPLC_DIO200_ISA)
272 #define DO_PCI IS_ENABLED(CONFIG_COMEDI_AMPLC_DIO200_PCI)
275 #define PCI_DEVICE_ID_AMPLICON_PCI272 0x000a
276 #define PCI_DEVICE_ID_AMPLICON_PCI215 0x000b
277 #define PCI_DEVICE_ID_AMPLICON_PCIE236 0x0011
278 #define PCI_DEVICE_ID_AMPLICON_PCIE215 0x0012
279 #define PCI_DEVICE_ID_AMPLICON_PCIE296 0x0014
281 /* 8255 control register bits */
282 #define CR_C_LO_IO 0x01
284 #define CR_B_MODE 0x04
285 #define CR_C_HI_IO 0x08
287 #define CR_A_MODE(a) ((a)<<5)
290 /* 200 series registers */
291 #define DIO200_IO_SIZE 0x20
292 #define DIO200_PCIE_IO_SIZE 0x4000
293 #define DIO200_XCLK_SCE 0x18 /* Group X clock selection register */
294 #define DIO200_YCLK_SCE 0x19 /* Group Y clock selection register */
295 #define DIO200_ZCLK_SCE 0x1a /* Group Z clock selection register */
296 #define DIO200_XGAT_SCE 0x1b /* Group X gate selection register */
297 #define DIO200_YGAT_SCE 0x1c /* Group Y gate selection register */
298 #define DIO200_ZGAT_SCE 0x1d /* Group Z gate selection register */
299 #define DIO200_INT_SCE 0x1e /* Interrupt enable/status register */
300 /* Extra registers for new PCIe boards */
301 #define DIO200_ENHANCE 0x20 /* 1 to enable enhanced features */
302 #define DIO200_VERSION 0x24 /* Hardware version register */
303 #define DIO200_TS_CONFIG 0x600 /* Timestamp timer config register */
304 #define DIO200_TS_COUNT 0x602 /* Timestamp timer count register */
307 * Functions for constructing value for DIO_200_?CLK_SCE and
308 * DIO_200_?GAT_SCE registers:
310 * 'which' is: 0 for CTR-X1, CTR-Y1, CTR-Z1; 1 for CTR-X2, CTR-Y2 or CTR-Z2.
311 * 'chan' is the channel: 0, 1 or 2.
312 * 'source' is the signal source: 0 to 7, or 0 to 31 for "enhanced" boards.
314 static unsigned char clk_gat_sce(unsigned int which, unsigned int chan,
317 return (which << 5) | (chan << 3) |
318 ((source & 030) << 3) | (source & 007);
321 static unsigned char clk_sce(unsigned int which, unsigned int chan,
324 return clk_gat_sce(which, chan, source);
327 static unsigned char gat_sce(unsigned int which, unsigned int chan,
330 return clk_gat_sce(which, chan, source);
334 * Periods of the internal clock sources in nanoseconds.
336 static const unsigned int clock_period[32] = {
337 [1] = 100, /* 10 MHz */
338 [2] = 1000, /* 1 MHz */
339 [3] = 10000, /* 100 kHz */
340 [4] = 100000, /* 10 kHz */
341 [5] = 1000000, /* 1 kHz */
342 [11] = 50, /* 20 MHz (enhanced boards) */
343 /* clock sources 12 and later reserved for enhanced boards */
347 * Timestamp timer configuration register (for new PCIe boards).
349 #define TS_CONFIG_RESET 0x100 /* Reset counter to zero. */
350 #define TS_CONFIG_CLK_SRC_MASK 0x0FF /* Clock source. */
351 #define TS_CONFIG_MAX_CLK_SRC 2 /* Maximum clock source value. */
354 * Periods of the timestamp timer clock sources in nanoseconds.
356 static const unsigned int ts_clock_period[TS_CONFIG_MAX_CLK_SRC + 1] = {
357 1, /* 1 nanosecond (but with 20 ns granularity). */
358 1000, /* 1 microsecond. */
359 1000000, /* 1 millisecond. */
365 enum dio200_regtype { no_regtype = 0, io_regtype, mmio_regtype };
366 struct dio200_region {
368 unsigned long iobase; /* I/O base address */
369 unsigned char __iomem *membase; /* mapped MMIO base address */
371 enum dio200_regtype regtype;
375 * Board descriptions.
378 enum dio200_bustype { isa_bustype, pci_bustype };
383 pc215e_model, pci215_model, pcie215_model,
386 pc272e_model, pci272_model,
390 enum dio200_layout_idx {
407 struct dio200_board {
409 unsigned short devid;
410 enum dio200_bustype bustype;
411 enum dio200_model model;
412 enum dio200_layout_idx layout;
413 unsigned char mainbar;
414 unsigned char mainshift;
415 unsigned int mainsize;
418 static const struct dio200_board dio200_boards[] = {
422 .bustype = isa_bustype,
423 .model = pc212e_model,
424 .layout = pc212_layout,
425 .mainsize = DIO200_IO_SIZE,
429 .bustype = isa_bustype,
430 .model = pc214e_model,
431 .layout = pc214_layout,
432 .mainsize = DIO200_IO_SIZE,
436 .bustype = isa_bustype,
437 .model = pc215e_model,
438 .layout = pc215_layout,
439 .mainsize = DIO200_IO_SIZE,
443 .bustype = isa_bustype,
444 .model = pc218e_model,
445 .layout = pc218_layout,
446 .mainsize = DIO200_IO_SIZE,
450 .bustype = isa_bustype,
451 .model = pc272e_model,
452 .layout = pc272_layout,
453 .mainsize = DIO200_IO_SIZE,
459 .devid = PCI_DEVICE_ID_AMPLICON_PCI215,
460 .bustype = pci_bustype,
461 .model = pci215_model,
462 .layout = pc215_layout,
464 .mainsize = DIO200_IO_SIZE,
468 .devid = PCI_DEVICE_ID_AMPLICON_PCI272,
469 .bustype = pci_bustype,
470 .model = pci272_model,
471 .layout = pc272_layout,
473 .mainsize = DIO200_IO_SIZE,
477 .devid = PCI_DEVICE_ID_AMPLICON_PCIE215,
478 .bustype = pci_bustype,
479 .model = pcie215_model,
480 .layout = pcie215_layout,
483 .mainsize = DIO200_PCIE_IO_SIZE,
487 .devid = PCI_DEVICE_ID_AMPLICON_PCIE236,
488 .bustype = pci_bustype,
489 .model = pcie236_model,
490 .layout = pcie236_layout,
493 .mainsize = DIO200_PCIE_IO_SIZE,
497 .devid = PCI_DEVICE_ID_AMPLICON_PCIE296,
498 .bustype = pci_bustype,
499 .model = pcie296_model,
500 .layout = pcie296_layout,
503 .mainsize = DIO200_PCIE_IO_SIZE,
509 * Layout descriptions - some ISA and PCI board descriptions share the same
513 enum dio200_sdtype { sd_none, sd_intr, sd_8255, sd_8254, sd_timer };
515 #define DIO200_MAX_SUBDEVS 8
516 #define DIO200_MAX_ISNS 6
518 struct dio200_layout {
519 unsigned short n_subdevs; /* number of subdevices */
520 unsigned char sdtype[DIO200_MAX_SUBDEVS]; /* enum dio200_sdtype */
521 unsigned char sdinfo[DIO200_MAX_SUBDEVS]; /* depends on sdtype */
522 char has_int_sce; /* has interrupt enable/status register */
523 char has_clk_gat_sce; /* has clock/gate selection registers */
524 char has_enhancements; /* has enhanced features */
527 static const struct dio200_layout dio200_layouts[] = {
531 .sdtype = {sd_8255, sd_8254, sd_8254, sd_8254,
534 .sdinfo = {0x00, 0x08, 0x0C, 0x10, 0x14,
537 .has_clk_gat_sce = 1,
541 .sdtype = {sd_8255, sd_8255, sd_8254,
543 .sdinfo = {0x00, 0x08, 0x10, 0x01},
545 .has_clk_gat_sce = 0,
550 .sdtype = {sd_8255, sd_8255, sd_8254,
553 .sdinfo = {0x00, 0x08, 0x10, 0x14, 0x3F},
555 .has_clk_gat_sce = 1,
560 .sdtype = {sd_8254, sd_8254, sd_8255, sd_8254,
563 .sdinfo = {0x00, 0x04, 0x08, 0x0C, 0x10,
567 .has_clk_gat_sce = 1,
572 .sdtype = {sd_8255, sd_8255, sd_8255,
574 .sdinfo = {0x00, 0x08, 0x10, 0x3F},
576 .has_clk_gat_sce = 0,
581 .sdtype = {sd_8255, sd_none, sd_8255, sd_none,
582 sd_8254, sd_8254, sd_timer, sd_intr},
583 .sdinfo = {0x00, 0x00, 0x08, 0x00,
584 0x10, 0x14, 0x00, 0x3F},
586 .has_clk_gat_sce = 1,
587 .has_enhancements = 1,
591 .sdtype = {sd_8255, sd_none, sd_none, sd_none,
592 sd_8254, sd_8254, sd_timer, sd_intr},
593 .sdinfo = {0x00, 0x00, 0x00, 0x00,
594 0x10, 0x14, 0x00, 0x3F},
596 .has_clk_gat_sce = 1,
597 .has_enhancements = 1,
601 .sdtype = {sd_8255, sd_8255, sd_8255, sd_8255,
602 sd_8254, sd_8254, sd_timer, sd_intr},
603 .sdinfo = {0x00, 0x04, 0x08, 0x0C,
604 0x10, 0x14, 0x00, 0x3F},
606 .has_clk_gat_sce = 1,
607 .has_enhancements = 1,
612 /* this structure is for data unique to this hardware driver. If
613 several hardware drivers keep similar information in this structure,
614 feel free to suggest moving the variable to the struct comedi_device struct.
616 struct dio200_private {
617 struct dio200_region io; /* Register region */
621 struct dio200_subdev_8254 {
622 unsigned int ofs; /* Counter base offset */
623 unsigned int clk_sce_ofs; /* CLK_SCE base address */
624 unsigned int gat_sce_ofs; /* GAT_SCE base address */
625 int which; /* Bit 5 of CLK_SCE or GAT_SCE */
626 unsigned int clock_src[3]; /* Current clock sources */
627 unsigned int gate_src[3]; /* Current gate sources */
631 struct dio200_subdev_8255 {
632 unsigned int ofs; /* DIO base offset */
635 struct dio200_subdev_intr {
639 unsigned int valid_isns;
640 unsigned int enabled_isns;
641 unsigned int stopcount;
645 static inline const struct dio200_layout *
646 dio200_board_layout(const struct dio200_board *board)
648 return &dio200_layouts[board->layout];
651 static inline const struct dio200_layout *
652 dio200_dev_layout(struct comedi_device *dev)
654 return dio200_board_layout(comedi_board(dev));
657 static inline bool is_pci_board(const struct dio200_board *board)
659 return DO_PCI && board->bustype == pci_bustype;
662 static inline bool is_isa_board(const struct dio200_board *board)
664 return DO_ISA && board->bustype == isa_bustype;
668 * Read 8-bit register.
670 static unsigned char dio200_read8(struct comedi_device *dev,
673 const struct dio200_board *thisboard = comedi_board(dev);
674 struct dio200_private *devpriv = dev->private;
676 offset <<= thisboard->mainshift;
677 if (devpriv->io.regtype == io_regtype)
678 return inb(devpriv->io.u.iobase + offset);
680 return readb(devpriv->io.u.membase + offset);
684 * Write 8-bit register.
686 static void dio200_write8(struct comedi_device *dev, unsigned int offset,
689 const struct dio200_board *thisboard = comedi_board(dev);
690 struct dio200_private *devpriv = dev->private;
692 offset <<= thisboard->mainshift;
693 if (devpriv->io.regtype == io_regtype)
694 outb(val, devpriv->io.u.iobase + offset);
696 writeb(val, devpriv->io.u.membase + offset);
700 * Read 32-bit register.
702 static unsigned int dio200_read32(struct comedi_device *dev,
705 const struct dio200_board *thisboard = comedi_board(dev);
706 struct dio200_private *devpriv = dev->private;
708 offset <<= thisboard->mainshift;
709 if (devpriv->io.regtype == io_regtype)
710 return inl(devpriv->io.u.iobase + offset);
712 return readl(devpriv->io.u.membase + offset);
716 * Write 32-bit register.
718 static void dio200_write32(struct comedi_device *dev, unsigned int offset,
721 const struct dio200_board *thisboard = comedi_board(dev);
722 struct dio200_private *devpriv = dev->private;
724 offset <<= thisboard->mainshift;
725 if (devpriv->io.regtype == io_regtype)
726 outl(val, devpriv->io.u.iobase + offset);
728 writel(val, devpriv->io.u.membase + offset);
732 * This function looks for a board matching the supplied PCI device.
734 static const struct dio200_board *
735 dio200_find_pci_board(struct pci_dev *pci_dev)
739 for (i = 0; i < ARRAY_SIZE(dio200_boards); i++)
740 if (is_pci_board(&dio200_boards[i]) &&
741 pci_dev->device == dio200_boards[i].devid)
742 return &dio200_boards[i];
747 * This function checks and requests an I/O region, reporting an error
748 * if there is a conflict.
751 dio200_request_region(struct comedi_device *dev,
752 unsigned long from, unsigned long extent)
754 if (!from || !request_region(from, extent, DIO200_DRIVER_NAME)) {
755 dev_err(dev->class_dev, "I/O port conflict (%#lx,%lu)!\n",
763 * 'insn_bits' function for an 'INTERRUPT' subdevice.
766 dio200_subdev_intr_insn_bits(struct comedi_device *dev,
767 struct comedi_subdevice *s,
768 struct comedi_insn *insn, unsigned int *data)
770 const struct dio200_layout *layout = dio200_dev_layout(dev);
771 struct dio200_subdev_intr *subpriv = s->private;
773 if (layout->has_int_sce) {
774 /* Just read the interrupt status register. */
775 data[1] = dio200_read8(dev, subpriv->ofs) & subpriv->valid_isns;
777 /* No interrupt status register. */
785 * Called to stop acquisition for an 'INTERRUPT' subdevice.
787 static void dio200_stop_intr(struct comedi_device *dev,
788 struct comedi_subdevice *s)
790 const struct dio200_layout *layout = dio200_dev_layout(dev);
791 struct dio200_subdev_intr *subpriv = s->private;
794 subpriv->enabled_isns = 0;
795 if (layout->has_int_sce)
796 dio200_write8(dev, subpriv->ofs, 0);
800 * Called to start acquisition for an 'INTERRUPT' subdevice.
802 static int dio200_start_intr(struct comedi_device *dev,
803 struct comedi_subdevice *s)
807 const struct dio200_layout *layout = dio200_dev_layout(dev);
808 struct dio200_subdev_intr *subpriv = s->private;
809 struct comedi_cmd *cmd = &s->async->cmd;
812 if (!subpriv->continuous && subpriv->stopcount == 0) {
813 /* An empty acquisition! */
814 s->async->events |= COMEDI_CB_EOA;
818 /* Determine interrupt sources to enable. */
821 for (n = 0; n < cmd->chanlist_len; n++)
822 isn_bits |= (1U << CR_CHAN(cmd->chanlist[n]));
824 isn_bits &= subpriv->valid_isns;
825 /* Enable interrupt sources. */
826 subpriv->enabled_isns = isn_bits;
827 if (layout->has_int_sce)
828 dio200_write8(dev, subpriv->ofs, isn_bits);
835 * Internal trigger function to start acquisition for an 'INTERRUPT' subdevice.
838 dio200_inttrig_start_intr(struct comedi_device *dev, struct comedi_subdevice *s,
839 unsigned int trignum)
841 struct dio200_subdev_intr *subpriv;
848 subpriv = s->private;
850 spin_lock_irqsave(&subpriv->spinlock, flags);
851 s->async->inttrig = NULL;
853 event = dio200_start_intr(dev, s);
855 spin_unlock_irqrestore(&subpriv->spinlock, flags);
858 comedi_event(dev, s);
864 * This is called from the interrupt service routine to handle a read
865 * scan on an 'INTERRUPT' subdevice.
867 static int dio200_handle_read_intr(struct comedi_device *dev,
868 struct comedi_subdevice *s)
870 const struct dio200_layout *layout = dio200_dev_layout(dev);
871 struct dio200_subdev_intr *subpriv = s->private;
874 unsigned cur_enabled;
875 unsigned int oldevents;
880 spin_lock_irqsave(&subpriv->spinlock, flags);
881 oldevents = s->async->events;
882 if (layout->has_int_sce) {
884 * Collect interrupt sources that have triggered and disable
885 * them temporarily. Loop around until no extra interrupt
886 * sources have triggered, at which point, the valid part of
887 * the interrupt status register will read zero, clearing the
888 * cause of the interrupt.
890 * Mask off interrupt sources already seen to avoid infinite
891 * loop in case of misconfiguration.
893 cur_enabled = subpriv->enabled_isns;
894 while ((intstat = (dio200_read8(dev, subpriv->ofs) &
895 subpriv->valid_isns & ~triggered)) != 0) {
896 triggered |= intstat;
897 cur_enabled &= ~triggered;
898 dio200_write8(dev, subpriv->ofs, cur_enabled);
902 * No interrupt status register. Assume the single interrupt
903 * source has triggered.
905 triggered = subpriv->enabled_isns;
910 * Some interrupt sources have triggered and have been
911 * temporarily disabled to clear the cause of the interrupt.
913 * Reenable them NOW to minimize the time they are disabled.
915 cur_enabled = subpriv->enabled_isns;
916 if (layout->has_int_sce)
917 dio200_write8(dev, subpriv->ofs, cur_enabled);
919 if (subpriv->active) {
921 * The command is still active.
923 * Ignore interrupt sources that the command isn't
924 * interested in (just in case there's a race
927 if (triggered & subpriv->enabled_isns) {
928 /* Collect scan data. */
930 unsigned int n, ch, len;
933 len = s->async->cmd.chanlist_len;
934 for (n = 0; n < len; n++) {
935 ch = CR_CHAN(s->async->cmd.chanlist[n]);
936 if (triggered & (1U << ch))
939 /* Write the scan to the buffer. */
940 if (comedi_buf_put(s->async, val)) {
941 s->async->events |= (COMEDI_CB_BLOCK |
944 /* Error! Stop acquisition. */
945 dio200_stop_intr(dev, s);
946 s->async->events |= COMEDI_CB_ERROR
947 | COMEDI_CB_OVERFLOW;
948 comedi_error(dev, "buffer overflow");
951 /* Check for end of acquisition. */
952 if (!subpriv->continuous) {
953 /* stop_src == TRIG_COUNT */
954 if (subpriv->stopcount > 0) {
955 subpriv->stopcount--;
956 if (subpriv->stopcount == 0) {
959 dio200_stop_intr(dev,
967 spin_unlock_irqrestore(&subpriv->spinlock, flags);
969 if (oldevents != s->async->events)
970 comedi_event(dev, s);
972 return (triggered != 0);
976 * 'cancel' function for an 'INTERRUPT' subdevice.
978 static int dio200_subdev_intr_cancel(struct comedi_device *dev,
979 struct comedi_subdevice *s)
981 struct dio200_subdev_intr *subpriv = s->private;
984 spin_lock_irqsave(&subpriv->spinlock, flags);
986 dio200_stop_intr(dev, s);
988 spin_unlock_irqrestore(&subpriv->spinlock, flags);
994 * 'do_cmdtest' function for an 'INTERRUPT' subdevice.
997 dio200_subdev_intr_cmdtest(struct comedi_device *dev,
998 struct comedi_subdevice *s, struct comedi_cmd *cmd)
1002 /* Step 1 : check if triggers are trivially valid */
1004 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_INT);
1005 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
1006 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
1007 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
1008 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
1013 /* Step 2a : make sure trigger sources are unique */
1015 err |= cfc_check_trigger_is_unique(cmd->start_src);
1016 err |= cfc_check_trigger_is_unique(cmd->stop_src);
1018 /* Step 2b : and mutually compatible */
1023 /* Step 3: check if arguments are trivially valid */
1025 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
1026 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
1027 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
1028 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
1030 switch (cmd->stop_src) {
1032 /* any count allowed */
1035 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
1044 /* step 4: fix up any arguments */
1046 /* if (err) return 4; */
1052 * 'do_cmd' function for an 'INTERRUPT' subdevice.
1054 static int dio200_subdev_intr_cmd(struct comedi_device *dev,
1055 struct comedi_subdevice *s)
1057 struct comedi_cmd *cmd = &s->async->cmd;
1058 struct dio200_subdev_intr *subpriv = s->private;
1059 unsigned long flags;
1062 spin_lock_irqsave(&subpriv->spinlock, flags);
1063 subpriv->active = 1;
1065 /* Set up end of acquisition. */
1066 switch (cmd->stop_src) {
1068 subpriv->continuous = 0;
1069 subpriv->stopcount = cmd->stop_arg;
1073 subpriv->continuous = 1;
1074 subpriv->stopcount = 0;
1078 /* Set up start of acquisition. */
1079 switch (cmd->start_src) {
1081 s->async->inttrig = dio200_inttrig_start_intr;
1085 event = dio200_start_intr(dev, s);
1088 spin_unlock_irqrestore(&subpriv->spinlock, flags);
1091 comedi_event(dev, s);
1097 * This function initializes an 'INTERRUPT' subdevice.
1100 dio200_subdev_intr_init(struct comedi_device *dev, struct comedi_subdevice *s,
1101 unsigned int offset, unsigned valid_isns)
1103 const struct dio200_layout *layout = dio200_dev_layout(dev);
1104 struct dio200_subdev_intr *subpriv;
1106 subpriv = kzalloc(sizeof(*subpriv), GFP_KERNEL);
1108 dev_err(dev->class_dev, "error! out of memory!\n");
1111 subpriv->ofs = offset;
1112 subpriv->valid_isns = valid_isns;
1113 spin_lock_init(&subpriv->spinlock);
1115 if (layout->has_int_sce)
1116 /* Disable interrupt sources. */
1117 dio200_write8(dev, subpriv->ofs, 0);
1119 s->private = subpriv;
1120 s->type = COMEDI_SUBD_DI;
1121 s->subdev_flags = SDF_READABLE | SDF_CMD_READ;
1122 if (layout->has_int_sce) {
1123 s->n_chan = DIO200_MAX_ISNS;
1124 s->len_chanlist = DIO200_MAX_ISNS;
1126 /* No interrupt source register. Support single channel. */
1128 s->len_chanlist = 1;
1130 s->range_table = &range_digital;
1132 s->insn_bits = dio200_subdev_intr_insn_bits;
1133 s->do_cmdtest = dio200_subdev_intr_cmdtest;
1134 s->do_cmd = dio200_subdev_intr_cmd;
1135 s->cancel = dio200_subdev_intr_cancel;
1141 * This function cleans up an 'INTERRUPT' subdevice.
1144 dio200_subdev_intr_cleanup(struct comedi_device *dev,
1145 struct comedi_subdevice *s)
1147 struct dio200_subdev_intr *subpriv = s->private;
1152 * Interrupt service routine.
1154 static irqreturn_t dio200_interrupt(int irq, void *d)
1156 struct comedi_device *dev = d;
1157 struct dio200_private *devpriv = dev->private;
1158 struct comedi_subdevice *s;
1164 if (devpriv->intr_sd >= 0) {
1165 s = &dev->subdevices[devpriv->intr_sd];
1166 handled = dio200_handle_read_intr(dev, s);
1171 return IRQ_RETVAL(handled);
1175 * Read an '8254' counter subdevice channel.
1178 dio200_subdev_8254_read_chan(struct comedi_device *dev,
1179 struct comedi_subdevice *s, unsigned int chan)
1181 struct dio200_subdev_8254 *subpriv = s->private;
1186 dio200_write8(dev, subpriv->ofs + i8254_control_reg, val);
1188 val = dio200_read8(dev, subpriv->ofs + chan);
1189 val += dio200_read8(dev, subpriv->ofs + chan) << 8;
1194 * Write an '8254' subdevice channel.
1197 dio200_subdev_8254_write_chan(struct comedi_device *dev,
1198 struct comedi_subdevice *s, unsigned int chan,
1201 struct dio200_subdev_8254 *subpriv = s->private;
1203 /* write lsb, msb */
1204 dio200_write8(dev, subpriv->ofs + chan, count & 0xff);
1205 dio200_write8(dev, subpriv->ofs + chan, (count >> 8) & 0xff);
1209 * Set mode of an '8254' subdevice channel.
1212 dio200_subdev_8254_set_mode(struct comedi_device *dev,
1213 struct comedi_subdevice *s, unsigned int chan,
1216 struct dio200_subdev_8254 *subpriv = s->private;
1220 byte |= 0x30; /* access order: lsb, msb */
1221 byte |= (mode & 0xf); /* counter mode and BCD|binary */
1222 dio200_write8(dev, subpriv->ofs + i8254_control_reg, byte);
1226 * Read status byte of an '8254' counter subdevice channel.
1229 dio200_subdev_8254_status(struct comedi_device *dev,
1230 struct comedi_subdevice *s, unsigned int chan)
1232 struct dio200_subdev_8254 *subpriv = s->private;
1235 dio200_write8(dev, subpriv->ofs + i8254_control_reg,
1236 0xe0 | (2 << chan));
1238 return dio200_read8(dev, subpriv->ofs + chan);
1242 * Handle 'insn_read' for an '8254' counter subdevice.
1245 dio200_subdev_8254_read(struct comedi_device *dev, struct comedi_subdevice *s,
1246 struct comedi_insn *insn, unsigned int *data)
1248 struct dio200_subdev_8254 *subpriv = s->private;
1249 int chan = CR_CHAN(insn->chanspec);
1251 unsigned long flags;
1253 for (n = 0; n < insn->n; n++) {
1254 spin_lock_irqsave(&subpriv->spinlock, flags);
1255 data[n] = dio200_subdev_8254_read_chan(dev, s, chan);
1256 spin_unlock_irqrestore(&subpriv->spinlock, flags);
1262 * Handle 'insn_write' for an '8254' counter subdevice.
1265 dio200_subdev_8254_write(struct comedi_device *dev, struct comedi_subdevice *s,
1266 struct comedi_insn *insn, unsigned int *data)
1268 struct dio200_subdev_8254 *subpriv = s->private;
1269 int chan = CR_CHAN(insn->chanspec);
1271 unsigned long flags;
1273 for (n = 0; n < insn->n; n++) {
1274 spin_lock_irqsave(&subpriv->spinlock, flags);
1275 dio200_subdev_8254_write_chan(dev, s, chan, data[n]);
1276 spin_unlock_irqrestore(&subpriv->spinlock, flags);
1282 * Set gate source for an '8254' counter subdevice channel.
1285 dio200_subdev_8254_set_gate_src(struct comedi_device *dev,
1286 struct comedi_subdevice *s,
1287 unsigned int counter_number,
1288 unsigned int gate_src)
1290 const struct dio200_layout *layout = dio200_dev_layout(dev);
1291 struct dio200_subdev_8254 *subpriv = s->private;
1294 if (!layout->has_clk_gat_sce)
1296 if (counter_number > 2)
1298 if (gate_src > (layout->has_enhancements ? 31 : 7))
1301 subpriv->gate_src[counter_number] = gate_src;
1302 byte = gat_sce(subpriv->which, counter_number, gate_src);
1303 dio200_write8(dev, subpriv->gat_sce_ofs, byte);
1309 * Get gate source for an '8254' counter subdevice channel.
1312 dio200_subdev_8254_get_gate_src(struct comedi_device *dev,
1313 struct comedi_subdevice *s,
1314 unsigned int counter_number)
1316 const struct dio200_layout *layout = dio200_dev_layout(dev);
1317 struct dio200_subdev_8254 *subpriv = s->private;
1319 if (!layout->has_clk_gat_sce)
1321 if (counter_number > 2)
1324 return subpriv->gate_src[counter_number];
1328 * Set clock source for an '8254' counter subdevice channel.
1331 dio200_subdev_8254_set_clock_src(struct comedi_device *dev,
1332 struct comedi_subdevice *s,
1333 unsigned int counter_number,
1334 unsigned int clock_src)
1336 const struct dio200_layout *layout = dio200_dev_layout(dev);
1337 struct dio200_subdev_8254 *subpriv = s->private;
1340 if (!layout->has_clk_gat_sce)
1342 if (counter_number > 2)
1344 if (clock_src > (layout->has_enhancements ? 31 : 7))
1347 subpriv->clock_src[counter_number] = clock_src;
1348 byte = clk_sce(subpriv->which, counter_number, clock_src);
1349 dio200_write8(dev, subpriv->clk_sce_ofs, byte);
1355 * Get clock source for an '8254' counter subdevice channel.
1358 dio200_subdev_8254_get_clock_src(struct comedi_device *dev,
1359 struct comedi_subdevice *s,
1360 unsigned int counter_number,
1361 unsigned int *period_ns)
1363 const struct dio200_layout *layout = dio200_dev_layout(dev);
1364 struct dio200_subdev_8254 *subpriv = s->private;
1367 if (!layout->has_clk_gat_sce)
1369 if (counter_number > 2)
1372 clock_src = subpriv->clock_src[counter_number];
1373 *period_ns = clock_period[clock_src];
1378 * Handle 'insn_config' for an '8254' counter subdevice.
1381 dio200_subdev_8254_config(struct comedi_device *dev, struct comedi_subdevice *s,
1382 struct comedi_insn *insn, unsigned int *data)
1384 struct dio200_subdev_8254 *subpriv = s->private;
1386 int chan = CR_CHAN(insn->chanspec);
1387 unsigned long flags;
1389 spin_lock_irqsave(&subpriv->spinlock, flags);
1391 case INSN_CONFIG_SET_COUNTER_MODE:
1392 if (data[1] > (I8254_MODE5 | I8254_BINARY))
1395 dio200_subdev_8254_set_mode(dev, s, chan, data[1]);
1397 case INSN_CONFIG_8254_READ_STATUS:
1398 data[1] = dio200_subdev_8254_status(dev, s, chan);
1400 case INSN_CONFIG_SET_GATE_SRC:
1401 ret = dio200_subdev_8254_set_gate_src(dev, s, chan, data[2]);
1405 case INSN_CONFIG_GET_GATE_SRC:
1406 ret = dio200_subdev_8254_get_gate_src(dev, s, chan);
1413 case INSN_CONFIG_SET_CLOCK_SRC:
1414 ret = dio200_subdev_8254_set_clock_src(dev, s, chan, data[1]);
1418 case INSN_CONFIG_GET_CLOCK_SRC:
1419 ret = dio200_subdev_8254_get_clock_src(dev, s, chan, &data[2]);
1430 spin_unlock_irqrestore(&subpriv->spinlock, flags);
1431 return ret < 0 ? ret : insn->n;
1435 * This function initializes an '8254' counter subdevice.
1438 dio200_subdev_8254_init(struct comedi_device *dev, struct comedi_subdevice *s,
1439 unsigned int offset)
1441 const struct dio200_layout *layout = dio200_dev_layout(dev);
1442 struct dio200_subdev_8254 *subpriv;
1445 subpriv = kzalloc(sizeof(*subpriv), GFP_KERNEL);
1447 dev_err(dev->class_dev, "error! out of memory!\n");
1451 s->private = subpriv;
1452 s->type = COMEDI_SUBD_COUNTER;
1453 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
1455 s->maxdata = 0xFFFF;
1456 s->insn_read = dio200_subdev_8254_read;
1457 s->insn_write = dio200_subdev_8254_write;
1458 s->insn_config = dio200_subdev_8254_config;
1460 spin_lock_init(&subpriv->spinlock);
1461 subpriv->ofs = offset;
1462 if (layout->has_clk_gat_sce) {
1463 /* Derive CLK_SCE and GAT_SCE register offsets from
1465 subpriv->clk_sce_ofs = DIO200_XCLK_SCE + (offset >> 3);
1466 subpriv->gat_sce_ofs = DIO200_XGAT_SCE + (offset >> 3);
1467 subpriv->which = (offset >> 2) & 1;
1470 /* Initialize channels. */
1471 for (chan = 0; chan < 3; chan++) {
1472 dio200_subdev_8254_set_mode(dev, s, chan,
1473 I8254_MODE0 | I8254_BINARY);
1474 if (layout->has_clk_gat_sce) {
1475 /* Gate source 0 is VCC (logic 1). */
1476 dio200_subdev_8254_set_gate_src(dev, s, chan, 0);
1477 /* Clock source 0 is the dedicated clock input. */
1478 dio200_subdev_8254_set_clock_src(dev, s, chan, 0);
1486 * This function cleans up an '8254' counter subdevice.
1489 dio200_subdev_8254_cleanup(struct comedi_device *dev,
1490 struct comedi_subdevice *s)
1492 struct dio200_subdev_intr *subpriv = s->private;
1497 * This function sets I/O directions for an '8255' DIO subdevice.
1499 static void dio200_subdev_8255_set_dir(struct comedi_device *dev,
1500 struct comedi_subdevice *s)
1502 struct dio200_subdev_8255 *subpriv = s->private;
1506 /* 1 in io_bits indicates output, 1 in config indicates input */
1507 if (!(s->io_bits & 0x0000ff))
1509 if (!(s->io_bits & 0x00ff00))
1511 if (!(s->io_bits & 0x0f0000))
1512 config |= CR_C_LO_IO;
1513 if (!(s->io_bits & 0xf00000))
1514 config |= CR_C_HI_IO;
1515 dio200_write8(dev, subpriv->ofs + 3, config);
1519 * Handle 'insn_bits' for an '8255' DIO subdevice.
1521 static int dio200_subdev_8255_bits(struct comedi_device *dev,
1522 struct comedi_subdevice *s,
1523 struct comedi_insn *insn, unsigned int *data)
1525 struct dio200_subdev_8255 *subpriv = s->private;
1528 s->state &= ~data[0];
1529 s->state |= (data[0] & data[1]);
1531 dio200_write8(dev, subpriv->ofs, s->state & 0xff);
1532 if (data[0] & 0xff00)
1533 dio200_write8(dev, subpriv->ofs + 1,
1534 (s->state >> 8) & 0xff);
1535 if (data[0] & 0xff0000)
1536 dio200_write8(dev, subpriv->ofs + 2,
1537 (s->state >> 16) & 0xff);
1539 data[1] = dio200_read8(dev, subpriv->ofs);
1540 data[1] |= dio200_read8(dev, subpriv->ofs + 1) << 8;
1541 data[1] |= dio200_read8(dev, subpriv->ofs + 2) << 16;
1546 * Handle 'insn_config' for an '8255' DIO subdevice.
1548 static int dio200_subdev_8255_config(struct comedi_device *dev,
1549 struct comedi_subdevice *s,
1550 struct comedi_insn *insn,
1556 mask = 1 << CR_CHAN(insn->chanspec);
1557 if (mask & 0x0000ff)
1559 else if (mask & 0x00ff00)
1561 else if (mask & 0x0f0000)
1566 case INSN_CONFIG_DIO_INPUT:
1567 s->io_bits &= ~bits;
1569 case INSN_CONFIG_DIO_OUTPUT:
1572 case INSN_CONFIG_DIO_QUERY:
1573 data[1] = (s->io_bits & bits) ? COMEDI_OUTPUT : COMEDI_INPUT;
1579 dio200_subdev_8255_set_dir(dev, s);
1584 * This function initializes an '8255' DIO subdevice.
1586 * offset is the offset to the 8255 chip.
1588 static int dio200_subdev_8255_init(struct comedi_device *dev,
1589 struct comedi_subdevice *s,
1590 unsigned int offset)
1592 struct dio200_subdev_8255 *subpriv;
1594 subpriv = kzalloc(sizeof(*subpriv), GFP_KERNEL);
1597 subpriv->ofs = offset;
1598 s->private = subpriv;
1599 s->type = COMEDI_SUBD_DIO;
1600 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1602 s->range_table = &range_digital;
1604 s->insn_bits = dio200_subdev_8255_bits;
1605 s->insn_config = dio200_subdev_8255_config;
1608 dio200_subdev_8255_set_dir(dev, s);
1613 * This function cleans up an '8255' DIO subdevice.
1615 static void dio200_subdev_8255_cleanup(struct comedi_device *dev,
1616 struct comedi_subdevice *s)
1618 struct dio200_subdev_8255 *subpriv = s->private;
1624 * Handle 'insn_read' for a timer subdevice.
1626 static int dio200_subdev_timer_read(struct comedi_device *dev,
1627 struct comedi_subdevice *s,
1628 struct comedi_insn *insn,
1633 for (n = 0; n < insn->n; n++)
1634 data[n] = dio200_read32(dev, DIO200_TS_COUNT);
1639 * Reset timer subdevice.
1641 static void dio200_subdev_timer_reset(struct comedi_device *dev,
1642 struct comedi_subdevice *s)
1646 clock = dio200_read32(dev, DIO200_TS_CONFIG) & TS_CONFIG_CLK_SRC_MASK;
1647 dio200_write32(dev, DIO200_TS_CONFIG, clock | TS_CONFIG_RESET);
1648 dio200_write32(dev, DIO200_TS_CONFIG, clock);
1652 * Get timer subdevice clock source and period.
1654 static void dio200_subdev_timer_get_clock_src(struct comedi_device *dev,
1655 struct comedi_subdevice *s,
1657 unsigned int *period)
1661 clk = dio200_read32(dev, DIO200_TS_CONFIG) & TS_CONFIG_CLK_SRC_MASK;
1663 *period = (clk < ARRAY_SIZE(ts_clock_period)) ?
1664 ts_clock_period[clk] : 0;
1668 * Set timer subdevice clock source.
1670 static int dio200_subdev_timer_set_clock_src(struct comedi_device *dev,
1671 struct comedi_subdevice *s,
1674 if (src > TS_CONFIG_MAX_CLK_SRC)
1676 dio200_write32(dev, DIO200_TS_CONFIG, src);
1681 * Handle 'insn_config' for a timer subdevice.
1683 static int dio200_subdev_timer_config(struct comedi_device *dev,
1684 struct comedi_subdevice *s,
1685 struct comedi_insn *insn,
1691 case INSN_CONFIG_RESET:
1692 dio200_subdev_timer_reset(dev, s);
1694 case INSN_CONFIG_SET_CLOCK_SRC:
1695 ret = dio200_subdev_timer_set_clock_src(dev, s, data[1]);
1699 case INSN_CONFIG_GET_CLOCK_SRC:
1700 dio200_subdev_timer_get_clock_src(dev, s, &data[1], &data[2]);
1706 return ret < 0 ? ret : insn->n;
1710 * This function initializes a timer subdevice.
1712 * Uses the timestamp timer registers. There is only one timestamp timer.
1714 static int dio200_subdev_timer_init(struct comedi_device *dev,
1715 struct comedi_subdevice *s)
1717 s->type = COMEDI_SUBD_TIMER;
1718 s->subdev_flags = SDF_READABLE | SDF_LSAMPL;
1720 s->maxdata = 0xFFFFFFFF;
1721 s->insn_read = dio200_subdev_timer_read;
1722 s->insn_config = dio200_subdev_timer_config;
1727 * This function cleans up a timer subdevice.
1729 static void dio200_subdev_timer_cleanup(struct comedi_device *dev,
1730 struct comedi_subdevice *s)
1732 /* Nothing to do. */
1736 * This function does some special set-up for the PCIe boards
1737 * PCIe215, PCIe236, PCIe296.
1739 static int dio200_pcie_board_setup(struct comedi_device *dev)
1741 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1742 void __iomem *brbase;
1743 resource_size_t brlen;
1746 * The board uses Altera Cyclone IV with PCI-Express hard IP.
1747 * The FPGA configuration has the PCI-Express Avalon-MM Bridge
1748 * Control registers in PCI BAR 0, offset 0, and the length of
1749 * these registers is 0x4000.
1751 * We need to write 0x80 to the "Avalon-MM to PCI-Express Interrupt
1752 * Enable" register at offset 0x50 to allow generation of PCIe
1753 * interrupts when RXmlrq_i is asserted in the SOPC Builder system.
1755 brlen = pci_resource_len(pcidev, 0);
1756 if (brlen < 0x4000 ||
1757 !(pci_resource_flags(pcidev, 0) & IORESOURCE_MEM)) {
1758 dev_err(dev->class_dev, "error! bad PCI region!\n");
1761 brbase = ioremap_nocache(pci_resource_start(pcidev, 0), brlen);
1763 dev_err(dev->class_dev, "error! failed to map registers!\n");
1766 writel(0x80, brbase + 0x50);
1768 /* Enable "enhanced" features of board. */
1769 dio200_write8(dev, DIO200_ENHANCE, 1);
1773 static void dio200_report_attach(struct comedi_device *dev, unsigned int irq)
1775 const struct dio200_board *thisboard = comedi_board(dev);
1776 struct dio200_private *devpriv = dev->private;
1777 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1781 if (is_isa_board(thisboard))
1782 tmplen = scnprintf(tmpbuf, sizeof(tmpbuf),
1783 "(base %#lx) ", devpriv->io.u.iobase);
1784 else if (is_pci_board(thisboard))
1785 tmplen = scnprintf(tmpbuf, sizeof(tmpbuf),
1786 "(pci %s) ", pci_name(pcidev));
1790 tmplen += scnprintf(&tmpbuf[tmplen], sizeof(tmpbuf) - tmplen,
1792 (dev->irq ? "" : " UNAVAILABLE"));
1794 tmplen += scnprintf(&tmpbuf[tmplen], sizeof(tmpbuf) - tmplen,
1796 dev_info(dev->class_dev, "%s %sattached\n", dev->board_name, tmpbuf);
1799 static int dio200_common_attach(struct comedi_device *dev, unsigned int irq,
1800 unsigned long req_irq_flags)
1802 const struct dio200_board *thisboard = comedi_board(dev);
1803 struct dio200_private *devpriv = dev->private;
1804 const struct dio200_layout *layout = dio200_board_layout(thisboard);
1805 struct comedi_subdevice *s;
1810 devpriv->intr_sd = -1;
1811 dev->board_name = thisboard->name;
1813 ret = comedi_alloc_subdevices(dev, layout->n_subdevs);
1817 for (n = 0; n < dev->n_subdevices; n++) {
1818 s = &dev->subdevices[n];
1819 switch (layout->sdtype[n]) {
1821 /* counter subdevice (8254) */
1822 ret = dio200_subdev_8254_init(dev, s,
1828 /* digital i/o subdevice (8255) */
1829 ret = dio200_subdev_8255_init(dev, s,
1835 /* 'INTERRUPT' subdevice */
1837 ret = dio200_subdev_intr_init(dev, s,
1843 devpriv->intr_sd = n;
1845 s->type = COMEDI_SUBD_UNUSED;
1849 /* Only on PCIe boards. */
1851 ret = dio200_subdev_timer_init(dev, s);
1855 s->type = COMEDI_SUBD_UNUSED;
1859 s->type = COMEDI_SUBD_UNUSED;
1863 sdx = devpriv->intr_sd;
1864 if (sdx >= 0 && sdx < dev->n_subdevices)
1865 dev->read_subdev = &dev->subdevices[sdx];
1867 if (request_irq(irq, dio200_interrupt, req_irq_flags,
1868 DIO200_DRIVER_NAME, dev) >= 0) {
1871 dev_warn(dev->class_dev,
1872 "warning! irq %u unavailable!\n", irq);
1875 dio200_report_attach(dev, irq);
1880 * Attach is called by the Comedi core to configure the driver
1881 * for a particular board. If you specified a board_name array
1882 * in the driver structure, dev->board_ptr contains that
1885 static int dio200_attach(struct comedi_device *dev, struct comedi_devconfig *it)
1887 const struct dio200_board *thisboard = comedi_board(dev);
1888 struct dio200_private *devpriv;
1891 dev_info(dev->class_dev, DIO200_DRIVER_NAME ": attach\n");
1893 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
1896 dev->private = devpriv;
1898 /* Process options and reserve resources according to bus type. */
1899 if (is_isa_board(thisboard)) {
1900 unsigned long iobase;
1903 iobase = it->options[0];
1904 irq = it->options[1];
1905 ret = dio200_request_region(dev, iobase, thisboard->mainsize);
1908 devpriv->io.u.iobase = iobase;
1909 devpriv->io.regtype = io_regtype;
1910 return dio200_common_attach(dev, irq, 0);
1911 } else if (is_pci_board(thisboard)) {
1912 dev_err(dev->class_dev,
1913 "Manual configuration of PCI board '%s' is not supported\n",
1917 dev_err(dev->class_dev, DIO200_DRIVER_NAME
1918 ": BUG! cannot determine board type!\n");
1924 * The auto_attach hook is called at PCI probe time via
1925 * comedi_pci_auto_config(). dev->board_ptr is NULL on entry.
1926 * There should be a board entry matching the supplied PCI device.
1928 static int dio200_auto_attach(struct comedi_device *dev,
1929 unsigned long context_unused)
1931 struct pci_dev *pci_dev = comedi_to_pci_dev(dev);
1932 const struct dio200_board *thisboard;
1933 struct dio200_private *devpriv;
1934 resource_size_t base, len;
1941 dev_info(dev->class_dev, DIO200_DRIVER_NAME ": attach pci %s\n",
1944 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
1947 dev->private = devpriv;
1949 dev->board_ptr = dio200_find_pci_board(pci_dev);
1950 if (dev->board_ptr == NULL) {
1951 dev_err(dev->class_dev, "BUG! cannot determine board type!\n");
1954 thisboard = comedi_board(dev);
1955 ret = comedi_pci_enable(pci_dev, DIO200_DRIVER_NAME);
1957 dev_err(dev->class_dev,
1958 "error! cannot enable PCI device and request regions!\n");
1961 bar = thisboard->mainbar;
1962 base = pci_resource_start(pci_dev, bar);
1963 len = pci_resource_len(pci_dev, bar);
1964 if (len < thisboard->mainsize) {
1965 dev_err(dev->class_dev, "error! PCI region size too small!\n");
1968 if ((pci_resource_flags(pci_dev, bar) & IORESOURCE_MEM) != 0) {
1969 devpriv->io.u.membase = ioremap_nocache(base, len);
1970 if (!devpriv->io.u.membase) {
1971 dev_err(dev->class_dev,
1972 "error! cannot remap registers\n");
1975 devpriv->io.regtype = mmio_regtype;
1977 devpriv->io.u.iobase = (unsigned long)base;
1978 devpriv->io.regtype = io_regtype;
1980 switch (thisboard->model) {
1984 ret = dio200_pcie_board_setup(dev);
1991 return dio200_common_attach(dev, pci_dev->irq, IRQF_SHARED);
1994 static void dio200_detach(struct comedi_device *dev)
1996 const struct dio200_board *thisboard = comedi_board(dev);
1997 struct dio200_private *devpriv = dev->private;
1998 const struct dio200_layout *layout;
2001 if (!thisboard || !devpriv)
2004 free_irq(dev->irq, dev);
2005 if (dev->subdevices) {
2006 layout = dio200_board_layout(thisboard);
2007 for (n = 0; n < dev->n_subdevices; n++) {
2008 struct comedi_subdevice *s = &dev->subdevices[n];
2009 switch (layout->sdtype[n]) {
2011 dio200_subdev_8254_cleanup(dev, s);
2014 dio200_subdev_8255_cleanup(dev, s);
2017 dio200_subdev_intr_cleanup(dev, s);
2020 /* Only on PCIe boards. */
2022 dio200_subdev_timer_cleanup(dev, s);
2029 if (is_isa_board(thisboard)) {
2030 if (devpriv->io.regtype == io_regtype)
2031 release_region(devpriv->io.u.iobase,
2032 thisboard->mainsize);
2033 } else if (is_pci_board(thisboard)) {
2034 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2036 if (devpriv->io.regtype != no_regtype) {
2037 if (devpriv->io.regtype == mmio_regtype)
2038 iounmap(devpriv->io.u.membase);
2039 comedi_pci_disable(pcidev);
2046 * The struct comedi_driver structure tells the Comedi core module
2047 * which functions to call to configure/deconfigure (attach/detach)
2048 * the board, and also about the kernel module that contains
2051 static struct comedi_driver amplc_dio200_driver = {
2052 .driver_name = DIO200_DRIVER_NAME,
2053 .module = THIS_MODULE,
2054 .attach = dio200_attach,
2055 .auto_attach = dio200_auto_attach,
2056 .detach = dio200_detach,
2057 .board_name = &dio200_boards[0].name,
2058 .offset = sizeof(struct dio200_board),
2059 .num_names = ARRAY_SIZE(dio200_boards),
2063 static DEFINE_PCI_DEVICE_TABLE(dio200_pci_table) = {
2064 { PCI_DEVICE(PCI_VENDOR_ID_AMPLICON, PCI_DEVICE_ID_AMPLICON_PCI215) },
2065 { PCI_DEVICE(PCI_VENDOR_ID_AMPLICON, PCI_DEVICE_ID_AMPLICON_PCI272) },
2066 { PCI_DEVICE(PCI_VENDOR_ID_AMPLICON, PCI_DEVICE_ID_AMPLICON_PCIE236) },
2067 { PCI_DEVICE(PCI_VENDOR_ID_AMPLICON, PCI_DEVICE_ID_AMPLICON_PCIE215) },
2068 { PCI_DEVICE(PCI_VENDOR_ID_AMPLICON, PCI_DEVICE_ID_AMPLICON_PCIE296) },
2072 MODULE_DEVICE_TABLE(pci, dio200_pci_table);
2074 static int amplc_dio200_pci_probe(struct pci_dev *dev,
2075 const struct pci_device_id
2078 return comedi_pci_auto_config(dev, &lc_dio200_driver);
2081 static struct pci_driver amplc_dio200_pci_driver = {
2082 .name = DIO200_DRIVER_NAME,
2083 .id_table = dio200_pci_table,
2084 .probe = &lc_dio200_pci_probe,
2085 .remove = comedi_pci_auto_unconfig,
2087 module_comedi_pci_driver(amplc_dio200_driver, amplc_dio200_pci_driver);
2089 module_comedi_driver(amplc_dio200_driver);
2092 MODULE_AUTHOR("Comedi http://www.comedi.org");
2093 MODULE_DESCRIPTION("Comedi low-level driver");
2094 MODULE_LICENSE("GPL");