2 * comedi/drivers/amplc_dio200_common.c
4 * Common support code for "amplc_dio200" and "amplc_dio200_pci".
6 * Copyright (C) 2005-2013 MEV Ltd. <http://www.mev.co.uk/>
8 * COMEDI - Linux Control and Measurement Device Interface
9 * Copyright (C) 1998,2000 David A. Schleef <ds@schleef.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
22 #include <linux/module.h>
23 #include <linux/interrupt.h>
25 #include "../comedidev.h"
27 #include "amplc_dio200.h"
28 #include "comedi_8254.h"
29 #include "8255.h" /* only for register defines */
31 /* 200 series registers */
32 #define DIO200_IO_SIZE 0x20
33 #define DIO200_PCIE_IO_SIZE 0x4000
34 #define DIO200_CLK_SCE(x) (0x18 + (x)) /* Group X/Y/Z clock sel reg */
35 #define DIO200_GAT_SCE(x) (0x1b + (x)) /* Group X/Y/Z gate sel reg */
36 #define DIO200_INT_SCE 0x1e /* Interrupt enable/status register */
37 /* Extra registers for new PCIe boards */
38 #define DIO200_ENHANCE 0x20 /* 1 to enable enhanced features */
39 #define DIO200_VERSION 0x24 /* Hardware version register */
40 #define DIO200_TS_CONFIG 0x600 /* Timestamp timer config register */
41 #define DIO200_TS_COUNT 0x602 /* Timestamp timer count register */
44 * Functions for constructing value for DIO_200_?CLK_SCE and
45 * DIO_200_?GAT_SCE registers:
47 * 'which' is: 0 for CTR-X1, CTR-Y1, CTR-Z1; 1 for CTR-X2, CTR-Y2 or CTR-Z2.
48 * 'chan' is the channel: 0, 1 or 2.
49 * 'source' is the signal source: 0 to 7, or 0 to 31 for "enhanced" boards.
51 static unsigned char clk_gat_sce(unsigned int which, unsigned int chan,
54 return (which << 5) | (chan << 3) |
55 ((source & 030) << 3) | (source & 007);
58 static unsigned char clk_sce(unsigned int which, unsigned int chan,
61 return clk_gat_sce(which, chan, source);
64 static unsigned char gat_sce(unsigned int which, unsigned int chan,
67 return clk_gat_sce(which, chan, source);
71 * Periods of the internal clock sources in nanoseconds.
73 static const unsigned int clock_period[32] = {
74 [1] = 100, /* 10 MHz */
75 [2] = 1000, /* 1 MHz */
76 [3] = 10000, /* 100 kHz */
77 [4] = 100000, /* 10 kHz */
78 [5] = 1000000, /* 1 kHz */
79 [11] = 50, /* 20 MHz (enhanced boards) */
80 /* clock sources 12 and later reserved for enhanced boards */
84 * Timestamp timer configuration register (for new PCIe boards).
86 #define TS_CONFIG_RESET 0x100 /* Reset counter to zero. */
87 #define TS_CONFIG_CLK_SRC_MASK 0x0FF /* Clock source. */
88 #define TS_CONFIG_MAX_CLK_SRC 2 /* Maximum clock source value. */
91 * Periods of the timestamp timer clock sources in nanoseconds.
93 static const unsigned int ts_clock_period[TS_CONFIG_MAX_CLK_SRC + 1] = {
94 1, /* 1 nanosecond (but with 20 ns granularity). */
95 1000, /* 1 microsecond. */
96 1000000, /* 1 millisecond. */
99 struct dio200_subdev_8255 {
100 unsigned int ofs; /* DIO base offset */
103 struct dio200_subdev_intr {
106 unsigned int valid_isns;
107 unsigned int enabled_isns;
111 static unsigned char dio200_read8(struct comedi_device *dev,
114 const struct dio200_board *board = dev->board_ptr;
120 return readb(dev->mmio + offset);
121 return inb(dev->iobase + offset);
124 static void dio200_write8(struct comedi_device *dev,
125 unsigned int offset, unsigned char val)
127 const struct dio200_board *board = dev->board_ptr;
133 writeb(val, dev->mmio + offset);
135 outb(val, dev->iobase + offset);
138 static unsigned int dio200_read32(struct comedi_device *dev,
141 const struct dio200_board *board = dev->board_ptr;
147 return readl(dev->mmio + offset);
148 return inl(dev->iobase + offset);
151 static void dio200_write32(struct comedi_device *dev,
152 unsigned int offset, unsigned int val)
154 const struct dio200_board *board = dev->board_ptr;
160 writel(val, dev->mmio + offset);
162 outl(val, dev->iobase + offset);
165 static unsigned int dio200_subdev_8254_offset(struct comedi_device *dev,
166 struct comedi_subdevice *s)
168 const struct dio200_board *board = dev->board_ptr;
169 struct comedi_8254 *i8254 = s->private;
172 /* get the offset that was passed to comedi_8254_*_init() */
174 offset = i8254->mmio - dev->mmio;
176 offset = i8254->iobase - dev->iobase;
178 /* remove the shift that was added for PCIe boards */
182 /* this offset now works for the dio200_{read,write} helpers */
186 static int dio200_subdev_intr_insn_bits(struct comedi_device *dev,
187 struct comedi_subdevice *s,
188 struct comedi_insn *insn,
191 const struct dio200_board *board = dev->board_ptr;
192 struct dio200_subdev_intr *subpriv = s->private;
194 if (board->has_int_sce) {
195 /* Just read the interrupt status register. */
196 data[1] = dio200_read8(dev, subpriv->ofs) & subpriv->valid_isns;
198 /* No interrupt status register. */
205 static void dio200_stop_intr(struct comedi_device *dev,
206 struct comedi_subdevice *s)
208 const struct dio200_board *board = dev->board_ptr;
209 struct dio200_subdev_intr *subpriv = s->private;
211 subpriv->active = false;
212 subpriv->enabled_isns = 0;
213 if (board->has_int_sce)
214 dio200_write8(dev, subpriv->ofs, 0);
217 static void dio200_start_intr(struct comedi_device *dev,
218 struct comedi_subdevice *s)
220 const struct dio200_board *board = dev->board_ptr;
221 struct dio200_subdev_intr *subpriv = s->private;
222 struct comedi_cmd *cmd = &s->async->cmd;
226 /* Determine interrupt sources to enable. */
229 for (n = 0; n < cmd->chanlist_len; n++)
230 isn_bits |= (1U << CR_CHAN(cmd->chanlist[n]));
232 isn_bits &= subpriv->valid_isns;
233 /* Enable interrupt sources. */
234 subpriv->enabled_isns = isn_bits;
235 if (board->has_int_sce)
236 dio200_write8(dev, subpriv->ofs, isn_bits);
239 static int dio200_inttrig_start_intr(struct comedi_device *dev,
240 struct comedi_subdevice *s,
241 unsigned int trig_num)
243 struct dio200_subdev_intr *subpriv = s->private;
244 struct comedi_cmd *cmd = &s->async->cmd;
247 if (trig_num != cmd->start_arg)
250 spin_lock_irqsave(&subpriv->spinlock, flags);
251 s->async->inttrig = NULL;
253 dio200_start_intr(dev, s);
255 spin_unlock_irqrestore(&subpriv->spinlock, flags);
260 static void dio200_read_scan_intr(struct comedi_device *dev,
261 struct comedi_subdevice *s,
262 unsigned int triggered)
264 struct comedi_cmd *cmd = &s->async->cmd;
269 for (n = 0; n < cmd->chanlist_len; n++) {
270 ch = CR_CHAN(cmd->chanlist[n]);
271 if (triggered & (1U << ch))
275 comedi_buf_write_samples(s, &val, 1);
277 if (cmd->stop_src == TRIG_COUNT &&
278 s->async->scans_done >= cmd->stop_arg)
279 s->async->events |= COMEDI_CB_EOA;
282 static int dio200_handle_read_intr(struct comedi_device *dev,
283 struct comedi_subdevice *s)
285 const struct dio200_board *board = dev->board_ptr;
286 struct dio200_subdev_intr *subpriv = s->private;
289 unsigned cur_enabled;
294 spin_lock_irqsave(&subpriv->spinlock, flags);
295 if (board->has_int_sce) {
297 * Collect interrupt sources that have triggered and disable
298 * them temporarily. Loop around until no extra interrupt
299 * sources have triggered, at which point, the valid part of
300 * the interrupt status register will read zero, clearing the
301 * cause of the interrupt.
303 * Mask off interrupt sources already seen to avoid infinite
304 * loop in case of misconfiguration.
306 cur_enabled = subpriv->enabled_isns;
307 while ((intstat = (dio200_read8(dev, subpriv->ofs) &
308 subpriv->valid_isns & ~triggered)) != 0) {
309 triggered |= intstat;
310 cur_enabled &= ~triggered;
311 dio200_write8(dev, subpriv->ofs, cur_enabled);
315 * No interrupt status register. Assume the single interrupt
316 * source has triggered.
318 triggered = subpriv->enabled_isns;
323 * Some interrupt sources have triggered and have been
324 * temporarily disabled to clear the cause of the interrupt.
326 * Reenable them NOW to minimize the time they are disabled.
328 cur_enabled = subpriv->enabled_isns;
329 if (board->has_int_sce)
330 dio200_write8(dev, subpriv->ofs, cur_enabled);
332 if (subpriv->active) {
334 * The command is still active.
336 * Ignore interrupt sources that the command isn't
337 * interested in (just in case there's a race
340 if (triggered & subpriv->enabled_isns) {
341 /* Collect scan data. */
342 dio200_read_scan_intr(dev, s, triggered);
346 spin_unlock_irqrestore(&subpriv->spinlock, flags);
348 comedi_handle_events(dev, s);
350 return (triggered != 0);
353 static int dio200_subdev_intr_cancel(struct comedi_device *dev,
354 struct comedi_subdevice *s)
356 struct dio200_subdev_intr *subpriv = s->private;
359 spin_lock_irqsave(&subpriv->spinlock, flags);
361 dio200_stop_intr(dev, s);
363 spin_unlock_irqrestore(&subpriv->spinlock, flags);
368 static int dio200_subdev_intr_cmdtest(struct comedi_device *dev,
369 struct comedi_subdevice *s,
370 struct comedi_cmd *cmd)
374 /* Step 1 : check if triggers are trivially valid */
376 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_INT);
377 err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
378 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
379 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
380 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
385 /* Step 2a : make sure trigger sources are unique */
387 err |= comedi_check_trigger_is_unique(cmd->start_src);
388 err |= comedi_check_trigger_is_unique(cmd->stop_src);
390 /* Step 2b : and mutually compatible */
395 /* Step 3: check if arguments are trivially valid */
397 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
398 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
399 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
400 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
403 if (cmd->stop_src == TRIG_COUNT)
404 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
406 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
411 /* step 4: fix up any arguments */
413 /* if (err) return 4; */
418 static int dio200_subdev_intr_cmd(struct comedi_device *dev,
419 struct comedi_subdevice *s)
421 struct comedi_cmd *cmd = &s->async->cmd;
422 struct dio200_subdev_intr *subpriv = s->private;
425 spin_lock_irqsave(&subpriv->spinlock, flags);
427 subpriv->active = true;
429 if (cmd->start_src == TRIG_INT)
430 s->async->inttrig = dio200_inttrig_start_intr;
432 dio200_start_intr(dev, s);
434 spin_unlock_irqrestore(&subpriv->spinlock, flags);
439 static int dio200_subdev_intr_init(struct comedi_device *dev,
440 struct comedi_subdevice *s,
444 const struct dio200_board *board = dev->board_ptr;
445 struct dio200_subdev_intr *subpriv;
447 subpriv = comedi_alloc_spriv(s, sizeof(*subpriv));
451 subpriv->ofs = offset;
452 subpriv->valid_isns = valid_isns;
453 spin_lock_init(&subpriv->spinlock);
455 if (board->has_int_sce)
456 /* Disable interrupt sources. */
457 dio200_write8(dev, subpriv->ofs, 0);
459 s->type = COMEDI_SUBD_DI;
460 s->subdev_flags = SDF_READABLE | SDF_CMD_READ | SDF_PACKED;
461 if (board->has_int_sce) {
462 s->n_chan = DIO200_MAX_ISNS;
463 s->len_chanlist = DIO200_MAX_ISNS;
465 /* No interrupt source register. Support single channel. */
469 s->range_table = &range_digital;
471 s->insn_bits = dio200_subdev_intr_insn_bits;
472 s->do_cmdtest = dio200_subdev_intr_cmdtest;
473 s->do_cmd = dio200_subdev_intr_cmd;
474 s->cancel = dio200_subdev_intr_cancel;
479 static irqreturn_t dio200_interrupt(int irq, void *d)
481 struct comedi_device *dev = d;
482 struct comedi_subdevice *s = dev->read_subdev;
488 handled = dio200_handle_read_intr(dev, s);
490 return IRQ_RETVAL(handled);
493 static void dio200_subdev_8254_set_gate_src(struct comedi_device *dev,
494 struct comedi_subdevice *s,
498 unsigned int offset = dio200_subdev_8254_offset(dev, s);
500 dio200_write8(dev, DIO200_GAT_SCE(offset >> 3),
501 gat_sce((offset >> 2) & 1, chan, src));
504 static void dio200_subdev_8254_set_clock_src(struct comedi_device *dev,
505 struct comedi_subdevice *s,
509 unsigned int offset = dio200_subdev_8254_offset(dev, s);
511 dio200_write8(dev, DIO200_CLK_SCE(offset >> 3),
512 clk_sce((offset >> 2) & 1, chan, src));
515 static int dio200_subdev_8254_config(struct comedi_device *dev,
516 struct comedi_subdevice *s,
517 struct comedi_insn *insn,
520 const struct dio200_board *board = dev->board_ptr;
521 struct comedi_8254 *i8254 = s->private;
522 unsigned int chan = CR_CHAN(insn->chanspec);
523 unsigned int max_src = board->is_pcie ? 31 : 7;
526 if (!board->has_clk_gat_sce)
530 case INSN_CONFIG_SET_GATE_SRC:
535 dio200_subdev_8254_set_gate_src(dev, s, chan, src);
536 i8254->gate_src[chan] = src;
538 case INSN_CONFIG_GET_GATE_SRC:
539 data[2] = i8254->gate_src[chan];
541 case INSN_CONFIG_SET_CLOCK_SRC:
546 dio200_subdev_8254_set_clock_src(dev, s, chan, src);
547 i8254->clock_src[chan] = src;
549 case INSN_CONFIG_GET_CLOCK_SRC:
550 data[1] = i8254->clock_src[chan];
551 data[2] = clock_period[i8254->clock_src[chan]];
560 static int dio200_subdev_8254_init(struct comedi_device *dev,
561 struct comedi_subdevice *s,
564 const struct dio200_board *board = dev->board_ptr;
565 struct comedi_8254 *i8254;
566 unsigned int regshift;
570 * PCIe boards need the offset shifted in order to get the
571 * correct base address of the timer.
573 if (board->is_pcie) {
581 i8254 = comedi_8254_mm_init(dev->mmio + offset,
582 0, I8254_IO8, regshift);
584 i8254 = comedi_8254_init(dev->iobase + offset,
585 0, I8254_IO8, regshift);
590 comedi_8254_subdevice_init(s, i8254);
592 i8254->insn_config = dio200_subdev_8254_config;
595 * There could be multiple timers so this driver does not
596 * use dev->pacer to save the i8254 pointer. Instead,
597 * comedi_8254_subdevice_init() saved the i8254 pointer in
598 * s->private. Mark the subdevice as having private data
599 * to be automatically freed when the device is detached.
601 comedi_set_spriv_auto_free(s);
603 /* Initialize channels. */
604 if (board->has_clk_gat_sce) {
605 for (chan = 0; chan < 3; chan++) {
606 /* Gate source 0 is VCC (logic 1). */
607 dio200_subdev_8254_set_gate_src(dev, s, chan, 0);
608 /* Clock source 0 is the dedicated clock input. */
609 dio200_subdev_8254_set_clock_src(dev, s, chan, 0);
616 static void dio200_subdev_8255_set_dir(struct comedi_device *dev,
617 struct comedi_subdevice *s)
619 struct dio200_subdev_8255 *subpriv = s->private;
622 config = I8255_CTRL_CW;
623 /* 1 in io_bits indicates output, 1 in config indicates input */
624 if (!(s->io_bits & 0x0000ff))
625 config |= I8255_CTRL_A_IO;
626 if (!(s->io_bits & 0x00ff00))
627 config |= I8255_CTRL_B_IO;
628 if (!(s->io_bits & 0x0f0000))
629 config |= I8255_CTRL_C_LO_IO;
630 if (!(s->io_bits & 0xf00000))
631 config |= I8255_CTRL_C_HI_IO;
632 dio200_write8(dev, subpriv->ofs + I8255_CTRL_REG, config);
635 static int dio200_subdev_8255_bits(struct comedi_device *dev,
636 struct comedi_subdevice *s,
637 struct comedi_insn *insn,
640 struct dio200_subdev_8255 *subpriv = s->private;
644 mask = comedi_dio_update_state(s, data);
647 dio200_write8(dev, subpriv->ofs + I8255_DATA_A_REG,
651 dio200_write8(dev, subpriv->ofs + I8255_DATA_B_REG,
652 (s->state >> 8) & 0xff);
654 if (mask & 0xff0000) {
655 dio200_write8(dev, subpriv->ofs + I8255_DATA_C_REG,
656 (s->state >> 16) & 0xff);
660 val = dio200_read8(dev, subpriv->ofs + I8255_DATA_A_REG);
661 val |= dio200_read8(dev, subpriv->ofs + I8255_DATA_B_REG) << 8;
662 val |= dio200_read8(dev, subpriv->ofs + I8255_DATA_C_REG) << 16;
669 static int dio200_subdev_8255_config(struct comedi_device *dev,
670 struct comedi_subdevice *s,
671 struct comedi_insn *insn,
674 unsigned int chan = CR_CHAN(insn->chanspec);
687 ret = comedi_dio_insn_config(dev, s, insn, data, mask);
691 dio200_subdev_8255_set_dir(dev, s);
696 static int dio200_subdev_8255_init(struct comedi_device *dev,
697 struct comedi_subdevice *s,
700 struct dio200_subdev_8255 *subpriv;
702 subpriv = comedi_alloc_spriv(s, sizeof(*subpriv));
706 subpriv->ofs = offset;
708 s->type = COMEDI_SUBD_DIO;
709 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
711 s->range_table = &range_digital;
713 s->insn_bits = dio200_subdev_8255_bits;
714 s->insn_config = dio200_subdev_8255_config;
715 dio200_subdev_8255_set_dir(dev, s);
719 static int dio200_subdev_timer_read(struct comedi_device *dev,
720 struct comedi_subdevice *s,
721 struct comedi_insn *insn,
726 for (n = 0; n < insn->n; n++)
727 data[n] = dio200_read32(dev, DIO200_TS_COUNT);
731 static void dio200_subdev_timer_reset(struct comedi_device *dev,
732 struct comedi_subdevice *s)
736 clock = dio200_read32(dev, DIO200_TS_CONFIG) & TS_CONFIG_CLK_SRC_MASK;
737 dio200_write32(dev, DIO200_TS_CONFIG, clock | TS_CONFIG_RESET);
738 dio200_write32(dev, DIO200_TS_CONFIG, clock);
741 static void dio200_subdev_timer_get_clock_src(struct comedi_device *dev,
742 struct comedi_subdevice *s,
744 unsigned int *period)
748 clk = dio200_read32(dev, DIO200_TS_CONFIG) & TS_CONFIG_CLK_SRC_MASK;
750 *period = (clk < ARRAY_SIZE(ts_clock_period)) ?
751 ts_clock_period[clk] : 0;
754 static int dio200_subdev_timer_set_clock_src(struct comedi_device *dev,
755 struct comedi_subdevice *s,
758 if (src > TS_CONFIG_MAX_CLK_SRC)
760 dio200_write32(dev, DIO200_TS_CONFIG, src);
764 static int dio200_subdev_timer_config(struct comedi_device *dev,
765 struct comedi_subdevice *s,
766 struct comedi_insn *insn,
772 case INSN_CONFIG_RESET:
773 dio200_subdev_timer_reset(dev, s);
775 case INSN_CONFIG_SET_CLOCK_SRC:
776 ret = dio200_subdev_timer_set_clock_src(dev, s, data[1]);
780 case INSN_CONFIG_GET_CLOCK_SRC:
781 dio200_subdev_timer_get_clock_src(dev, s, &data[1], &data[2]);
787 return ret < 0 ? ret : insn->n;
790 void amplc_dio200_set_enhance(struct comedi_device *dev, unsigned char val)
792 dio200_write8(dev, DIO200_ENHANCE, val);
794 EXPORT_SYMBOL_GPL(amplc_dio200_set_enhance);
796 int amplc_dio200_common_attach(struct comedi_device *dev, unsigned int irq,
797 unsigned long req_irq_flags)
799 const struct dio200_board *board = dev->board_ptr;
800 struct comedi_subdevice *s;
804 ret = comedi_alloc_subdevices(dev, board->n_subdevs);
808 for (n = 0; n < dev->n_subdevices; n++) {
809 s = &dev->subdevices[n];
810 switch (board->sdtype[n]) {
812 /* counter subdevice (8254) */
813 ret = dio200_subdev_8254_init(dev, s,
819 /* digital i/o subdevice (8255) */
820 ret = dio200_subdev_8255_init(dev, s,
826 /* 'INTERRUPT' subdevice */
827 if (irq && !dev->read_subdev) {
828 ret = dio200_subdev_intr_init(dev, s,
833 dev->read_subdev = s;
835 s->type = COMEDI_SUBD_UNUSED;
839 s->type = COMEDI_SUBD_TIMER;
840 s->subdev_flags = SDF_READABLE | SDF_LSAMPL;
842 s->maxdata = 0xffffffff;
843 s->insn_read = dio200_subdev_timer_read;
844 s->insn_config = dio200_subdev_timer_config;
847 s->type = COMEDI_SUBD_UNUSED;
852 if (irq && dev->read_subdev) {
853 if (request_irq(irq, dio200_interrupt, req_irq_flags,
854 dev->board_name, dev) >= 0) {
857 dev_warn(dev->class_dev,
858 "warning! irq %u unavailable!\n", irq);
864 EXPORT_SYMBOL_GPL(amplc_dio200_common_attach);
866 static int __init amplc_dio200_common_init(void)
870 module_init(amplc_dio200_common_init);
872 static void __exit amplc_dio200_common_exit(void)
875 module_exit(amplc_dio200_common_exit);
877 MODULE_AUTHOR("Comedi http://www.comedi.org");
878 MODULE_DESCRIPTION("Comedi helper for amplc_dio200 and amplc_dio200_pci");
879 MODULE_LICENSE("GPL");