2 comedi/drivers/amplc_dio200_common.c
4 Common support code for "amplc_dio200" and "amplc_dio200_pci".
6 Copyright (C) 2005-2013 MEV Ltd. <http://www.mev.co.uk/>
8 COMEDI - Linux Control and Measurement Device Interface
9 Copyright (C) 1998,2000 David A. Schleef <ds@schleef.org>
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 #include <linux/interrupt.h>
28 #include <linux/slab.h>
30 #include "../comedidev.h"
32 #include "amplc_dio200.h"
33 #include "comedi_fc.h"
36 /* 8255 control register bits */
37 #define CR_C_LO_IO 0x01
39 #define CR_B_MODE 0x04
40 #define CR_C_HI_IO 0x08
42 #define CR_A_MODE(a) ((a)<<5)
45 /* 200 series registers */
46 #define DIO200_IO_SIZE 0x20
47 #define DIO200_PCIE_IO_SIZE 0x4000
48 #define DIO200_XCLK_SCE 0x18 /* Group X clock selection register */
49 #define DIO200_YCLK_SCE 0x19 /* Group Y clock selection register */
50 #define DIO200_ZCLK_SCE 0x1a /* Group Z clock selection register */
51 #define DIO200_XGAT_SCE 0x1b /* Group X gate selection register */
52 #define DIO200_YGAT_SCE 0x1c /* Group Y gate selection register */
53 #define DIO200_ZGAT_SCE 0x1d /* Group Z gate selection register */
54 #define DIO200_INT_SCE 0x1e /* Interrupt enable/status register */
55 /* Extra registers for new PCIe boards */
56 #define DIO200_ENHANCE 0x20 /* 1 to enable enhanced features */
57 #define DIO200_VERSION 0x24 /* Hardware version register */
58 #define DIO200_TS_CONFIG 0x600 /* Timestamp timer config register */
59 #define DIO200_TS_COUNT 0x602 /* Timestamp timer count register */
62 * Functions for constructing value for DIO_200_?CLK_SCE and
63 * DIO_200_?GAT_SCE registers:
65 * 'which' is: 0 for CTR-X1, CTR-Y1, CTR-Z1; 1 for CTR-X2, CTR-Y2 or CTR-Z2.
66 * 'chan' is the channel: 0, 1 or 2.
67 * 'source' is the signal source: 0 to 7, or 0 to 31 for "enhanced" boards.
69 static unsigned char clk_gat_sce(unsigned int which, unsigned int chan,
72 return (which << 5) | (chan << 3) |
73 ((source & 030) << 3) | (source & 007);
76 static unsigned char clk_sce(unsigned int which, unsigned int chan,
79 return clk_gat_sce(which, chan, source);
82 static unsigned char gat_sce(unsigned int which, unsigned int chan,
85 return clk_gat_sce(which, chan, source);
89 * Periods of the internal clock sources in nanoseconds.
91 static const unsigned int clock_period[32] = {
92 [1] = 100, /* 10 MHz */
93 [2] = 1000, /* 1 MHz */
94 [3] = 10000, /* 100 kHz */
95 [4] = 100000, /* 10 kHz */
96 [5] = 1000000, /* 1 kHz */
97 [11] = 50, /* 20 MHz (enhanced boards) */
98 /* clock sources 12 and later reserved for enhanced boards */
102 * Timestamp timer configuration register (for new PCIe boards).
104 #define TS_CONFIG_RESET 0x100 /* Reset counter to zero. */
105 #define TS_CONFIG_CLK_SRC_MASK 0x0FF /* Clock source. */
106 #define TS_CONFIG_MAX_CLK_SRC 2 /* Maximum clock source value. */
109 * Periods of the timestamp timer clock sources in nanoseconds.
111 static const unsigned int ts_clock_period[TS_CONFIG_MAX_CLK_SRC + 1] = {
112 1, /* 1 nanosecond (but with 20 ns granularity). */
113 1000, /* 1 microsecond. */
114 1000000, /* 1 millisecond. */
117 struct dio200_subdev_8254 {
118 unsigned int ofs; /* Counter base offset */
119 unsigned int clk_sce_ofs; /* CLK_SCE base address */
120 unsigned int gat_sce_ofs; /* GAT_SCE base address */
121 int which; /* Bit 5 of CLK_SCE or GAT_SCE */
122 unsigned int clock_src[3]; /* Current clock sources */
123 unsigned int gate_src[3]; /* Current gate sources */
127 struct dio200_subdev_8255 {
128 unsigned int ofs; /* DIO base offset */
131 struct dio200_subdev_intr {
134 unsigned int valid_isns;
135 unsigned int enabled_isns;
136 unsigned int stopcount;
141 static inline const struct dio200_layout *
142 dio200_board_layout(const struct dio200_board *board)
144 return &board->layout;
147 static inline const struct dio200_layout *
148 dio200_dev_layout(struct comedi_device *dev)
150 return dio200_board_layout(comedi_board(dev));
154 * Read 8-bit register.
156 static unsigned char dio200_read8(struct comedi_device *dev,
159 const struct dio200_board *thisboard = comedi_board(dev);
160 struct dio200_private *devpriv = dev->private;
162 offset <<= thisboard->mainshift;
163 if (devpriv->io.regtype == io_regtype)
164 return inb(devpriv->io.u.iobase + offset);
166 return readb(devpriv->io.u.membase + offset);
170 * Write 8-bit register.
172 static void dio200_write8(struct comedi_device *dev, unsigned int offset,
175 const struct dio200_board *thisboard = comedi_board(dev);
176 struct dio200_private *devpriv = dev->private;
178 offset <<= thisboard->mainshift;
179 if (devpriv->io.regtype == io_regtype)
180 outb(val, devpriv->io.u.iobase + offset);
182 writeb(val, devpriv->io.u.membase + offset);
186 * Read 32-bit register.
188 static unsigned int dio200_read32(struct comedi_device *dev,
191 const struct dio200_board *thisboard = comedi_board(dev);
192 struct dio200_private *devpriv = dev->private;
194 offset <<= thisboard->mainshift;
195 if (devpriv->io.regtype == io_regtype)
196 return inl(devpriv->io.u.iobase + offset);
198 return readl(devpriv->io.u.membase + offset);
202 * Write 32-bit register.
204 static void dio200_write32(struct comedi_device *dev, unsigned int offset,
207 const struct dio200_board *thisboard = comedi_board(dev);
208 struct dio200_private *devpriv = dev->private;
210 offset <<= thisboard->mainshift;
211 if (devpriv->io.regtype == io_regtype)
212 outl(val, devpriv->io.u.iobase + offset);
214 writel(val, devpriv->io.u.membase + offset);
218 * 'insn_bits' function for an 'INTERRUPT' subdevice.
221 dio200_subdev_intr_insn_bits(struct comedi_device *dev,
222 struct comedi_subdevice *s,
223 struct comedi_insn *insn, unsigned int *data)
225 const struct dio200_layout *layout = dio200_dev_layout(dev);
226 struct dio200_subdev_intr *subpriv = s->private;
228 if (layout->has_int_sce) {
229 /* Just read the interrupt status register. */
230 data[1] = dio200_read8(dev, subpriv->ofs) & subpriv->valid_isns;
232 /* No interrupt status register. */
240 * Called to stop acquisition for an 'INTERRUPT' subdevice.
242 static void dio200_stop_intr(struct comedi_device *dev,
243 struct comedi_subdevice *s)
245 const struct dio200_layout *layout = dio200_dev_layout(dev);
246 struct dio200_subdev_intr *subpriv = s->private;
248 subpriv->active = false;
249 subpriv->enabled_isns = 0;
250 if (layout->has_int_sce)
251 dio200_write8(dev, subpriv->ofs, 0);
255 * Called to start acquisition for an 'INTERRUPT' subdevice.
257 static int dio200_start_intr(struct comedi_device *dev,
258 struct comedi_subdevice *s)
262 const struct dio200_layout *layout = dio200_dev_layout(dev);
263 struct dio200_subdev_intr *subpriv = s->private;
264 struct comedi_cmd *cmd = &s->async->cmd;
267 if (!subpriv->continuous && subpriv->stopcount == 0) {
268 /* An empty acquisition! */
269 s->async->events |= COMEDI_CB_EOA;
270 subpriv->active = false;
273 /* Determine interrupt sources to enable. */
276 for (n = 0; n < cmd->chanlist_len; n++)
277 isn_bits |= (1U << CR_CHAN(cmd->chanlist[n]));
279 isn_bits &= subpriv->valid_isns;
280 /* Enable interrupt sources. */
281 subpriv->enabled_isns = isn_bits;
282 if (layout->has_int_sce)
283 dio200_write8(dev, subpriv->ofs, isn_bits);
290 * Internal trigger function to start acquisition for an 'INTERRUPT' subdevice.
293 dio200_inttrig_start_intr(struct comedi_device *dev, struct comedi_subdevice *s,
294 unsigned int trignum)
296 struct dio200_subdev_intr *subpriv;
303 subpriv = s->private;
305 spin_lock_irqsave(&subpriv->spinlock, flags);
306 s->async->inttrig = NULL;
308 event = dio200_start_intr(dev, s);
310 spin_unlock_irqrestore(&subpriv->spinlock, flags);
313 comedi_event(dev, s);
318 static void dio200_read_scan_intr(struct comedi_device *dev,
319 struct comedi_subdevice *s,
320 unsigned int triggered)
322 struct dio200_subdev_intr *subpriv = s->private;
324 unsigned int n, ch, len;
327 len = s->async->cmd.chanlist_len;
328 for (n = 0; n < len; n++) {
329 ch = CR_CHAN(s->async->cmd.chanlist[n]);
330 if (triggered & (1U << ch))
333 /* Write the scan to the buffer. */
334 if (comedi_buf_put(s->async, val)) {
335 s->async->events |= (COMEDI_CB_BLOCK | COMEDI_CB_EOS);
337 /* Error! Stop acquisition. */
338 dio200_stop_intr(dev, s);
339 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW;
340 comedi_error(dev, "buffer overflow");
343 /* Check for end of acquisition. */
344 if (!subpriv->continuous) {
345 /* stop_src == TRIG_COUNT */
346 if (subpriv->stopcount > 0) {
347 subpriv->stopcount--;
348 if (subpriv->stopcount == 0) {
349 s->async->events |= COMEDI_CB_EOA;
350 dio200_stop_intr(dev, s);
357 * This is called from the interrupt service routine to handle a read
358 * scan on an 'INTERRUPT' subdevice.
360 static int dio200_handle_read_intr(struct comedi_device *dev,
361 struct comedi_subdevice *s)
363 const struct dio200_layout *layout = dio200_dev_layout(dev);
364 struct dio200_subdev_intr *subpriv = s->private;
367 unsigned cur_enabled;
368 unsigned int oldevents;
373 spin_lock_irqsave(&subpriv->spinlock, flags);
374 oldevents = s->async->events;
375 if (layout->has_int_sce) {
377 * Collect interrupt sources that have triggered and disable
378 * them temporarily. Loop around until no extra interrupt
379 * sources have triggered, at which point, the valid part of
380 * the interrupt status register will read zero, clearing the
381 * cause of the interrupt.
383 * Mask off interrupt sources already seen to avoid infinite
384 * loop in case of misconfiguration.
386 cur_enabled = subpriv->enabled_isns;
387 while ((intstat = (dio200_read8(dev, subpriv->ofs) &
388 subpriv->valid_isns & ~triggered)) != 0) {
389 triggered |= intstat;
390 cur_enabled &= ~triggered;
391 dio200_write8(dev, subpriv->ofs, cur_enabled);
395 * No interrupt status register. Assume the single interrupt
396 * source has triggered.
398 triggered = subpriv->enabled_isns;
403 * Some interrupt sources have triggered and have been
404 * temporarily disabled to clear the cause of the interrupt.
406 * Reenable them NOW to minimize the time they are disabled.
408 cur_enabled = subpriv->enabled_isns;
409 if (layout->has_int_sce)
410 dio200_write8(dev, subpriv->ofs, cur_enabled);
412 if (subpriv->active) {
414 * The command is still active.
416 * Ignore interrupt sources that the command isn't
417 * interested in (just in case there's a race
420 if (triggered & subpriv->enabled_isns)
421 /* Collect scan data. */
422 dio200_read_scan_intr(dev, s, triggered);
425 spin_unlock_irqrestore(&subpriv->spinlock, flags);
427 if (oldevents != s->async->events)
428 comedi_event(dev, s);
430 return (triggered != 0);
434 * 'cancel' function for an 'INTERRUPT' subdevice.
436 static int dio200_subdev_intr_cancel(struct comedi_device *dev,
437 struct comedi_subdevice *s)
439 struct dio200_subdev_intr *subpriv = s->private;
442 spin_lock_irqsave(&subpriv->spinlock, flags);
444 dio200_stop_intr(dev, s);
446 spin_unlock_irqrestore(&subpriv->spinlock, flags);
452 * 'do_cmdtest' function for an 'INTERRUPT' subdevice.
455 dio200_subdev_intr_cmdtest(struct comedi_device *dev,
456 struct comedi_subdevice *s, struct comedi_cmd *cmd)
460 /* Step 1 : check if triggers are trivially valid */
462 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_INT);
463 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
464 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
465 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
466 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
471 /* Step 2a : make sure trigger sources are unique */
473 err |= cfc_check_trigger_is_unique(cmd->start_src);
474 err |= cfc_check_trigger_is_unique(cmd->stop_src);
476 /* Step 2b : and mutually compatible */
481 /* Step 3: check if arguments are trivially valid */
483 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
484 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
485 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
486 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
488 switch (cmd->stop_src) {
490 /* any count allowed */
493 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
502 /* step 4: fix up any arguments */
504 /* if (err) return 4; */
510 * 'do_cmd' function for an 'INTERRUPT' subdevice.
512 static int dio200_subdev_intr_cmd(struct comedi_device *dev,
513 struct comedi_subdevice *s)
515 struct comedi_cmd *cmd = &s->async->cmd;
516 struct dio200_subdev_intr *subpriv = s->private;
520 spin_lock_irqsave(&subpriv->spinlock, flags);
523 /* Set up end of acquisition. */
524 switch (cmd->stop_src) {
526 subpriv->continuous = false;
527 subpriv->stopcount = cmd->stop_arg;
531 subpriv->continuous = true;
532 subpriv->stopcount = 0;
536 /* Set up start of acquisition. */
537 switch (cmd->start_src) {
539 s->async->inttrig = dio200_inttrig_start_intr;
543 event = dio200_start_intr(dev, s);
546 spin_unlock_irqrestore(&subpriv->spinlock, flags);
549 comedi_event(dev, s);
555 * This function initializes an 'INTERRUPT' subdevice.
558 dio200_subdev_intr_init(struct comedi_device *dev, struct comedi_subdevice *s,
559 unsigned int offset, unsigned valid_isns)
561 const struct dio200_layout *layout = dio200_dev_layout(dev);
562 struct dio200_subdev_intr *subpriv;
564 subpriv = kzalloc(sizeof(*subpriv), GFP_KERNEL);
568 subpriv->ofs = offset;
569 subpriv->valid_isns = valid_isns;
570 spin_lock_init(&subpriv->spinlock);
572 if (layout->has_int_sce)
573 /* Disable interrupt sources. */
574 dio200_write8(dev, subpriv->ofs, 0);
576 s->private = subpriv;
577 s->type = COMEDI_SUBD_DI;
578 s->subdev_flags = SDF_READABLE | SDF_CMD_READ;
579 if (layout->has_int_sce) {
580 s->n_chan = DIO200_MAX_ISNS;
581 s->len_chanlist = DIO200_MAX_ISNS;
583 /* No interrupt source register. Support single channel. */
587 s->range_table = &range_digital;
589 s->insn_bits = dio200_subdev_intr_insn_bits;
590 s->do_cmdtest = dio200_subdev_intr_cmdtest;
591 s->do_cmd = dio200_subdev_intr_cmd;
592 s->cancel = dio200_subdev_intr_cancel;
598 * Interrupt service routine.
600 static irqreturn_t dio200_interrupt(int irq, void *d)
602 struct comedi_device *dev = d;
603 struct dio200_private *devpriv = dev->private;
604 struct comedi_subdevice *s;
610 if (devpriv->intr_sd >= 0) {
611 s = &dev->subdevices[devpriv->intr_sd];
612 handled = dio200_handle_read_intr(dev, s);
617 return IRQ_RETVAL(handled);
621 * Read an '8254' counter subdevice channel.
624 dio200_subdev_8254_read_chan(struct comedi_device *dev,
625 struct comedi_subdevice *s, unsigned int chan)
627 struct dio200_subdev_8254 *subpriv = s->private;
632 dio200_write8(dev, subpriv->ofs + i8254_control_reg, val);
634 val = dio200_read8(dev, subpriv->ofs + chan);
635 val += dio200_read8(dev, subpriv->ofs + chan) << 8;
640 * Write an '8254' subdevice channel.
643 dio200_subdev_8254_write_chan(struct comedi_device *dev,
644 struct comedi_subdevice *s, unsigned int chan,
647 struct dio200_subdev_8254 *subpriv = s->private;
650 dio200_write8(dev, subpriv->ofs + chan, count & 0xff);
651 dio200_write8(dev, subpriv->ofs + chan, (count >> 8) & 0xff);
655 * Set mode of an '8254' subdevice channel.
658 dio200_subdev_8254_set_mode(struct comedi_device *dev,
659 struct comedi_subdevice *s, unsigned int chan,
662 struct dio200_subdev_8254 *subpriv = s->private;
666 byte |= 0x30; /* access order: lsb, msb */
667 byte |= (mode & 0xf); /* counter mode and BCD|binary */
668 dio200_write8(dev, subpriv->ofs + i8254_control_reg, byte);
672 * Read status byte of an '8254' counter subdevice channel.
675 dio200_subdev_8254_status(struct comedi_device *dev,
676 struct comedi_subdevice *s, unsigned int chan)
678 struct dio200_subdev_8254 *subpriv = s->private;
681 dio200_write8(dev, subpriv->ofs + i8254_control_reg,
684 return dio200_read8(dev, subpriv->ofs + chan);
688 * Handle 'insn_read' for an '8254' counter subdevice.
691 dio200_subdev_8254_read(struct comedi_device *dev, struct comedi_subdevice *s,
692 struct comedi_insn *insn, unsigned int *data)
694 struct dio200_subdev_8254 *subpriv = s->private;
695 int chan = CR_CHAN(insn->chanspec);
699 for (n = 0; n < insn->n; n++) {
700 spin_lock_irqsave(&subpriv->spinlock, flags);
701 data[n] = dio200_subdev_8254_read_chan(dev, s, chan);
702 spin_unlock_irqrestore(&subpriv->spinlock, flags);
708 * Handle 'insn_write' for an '8254' counter subdevice.
711 dio200_subdev_8254_write(struct comedi_device *dev, struct comedi_subdevice *s,
712 struct comedi_insn *insn, unsigned int *data)
714 struct dio200_subdev_8254 *subpriv = s->private;
715 int chan = CR_CHAN(insn->chanspec);
719 for (n = 0; n < insn->n; n++) {
720 spin_lock_irqsave(&subpriv->spinlock, flags);
721 dio200_subdev_8254_write_chan(dev, s, chan, data[n]);
722 spin_unlock_irqrestore(&subpriv->spinlock, flags);
728 * Set gate source for an '8254' counter subdevice channel.
731 dio200_subdev_8254_set_gate_src(struct comedi_device *dev,
732 struct comedi_subdevice *s,
733 unsigned int counter_number,
734 unsigned int gate_src)
736 const struct dio200_layout *layout = dio200_dev_layout(dev);
737 struct dio200_subdev_8254 *subpriv = s->private;
740 if (!layout->has_clk_gat_sce)
742 if (counter_number > 2)
744 if (gate_src > (layout->has_enhancements ? 31 : 7))
747 subpriv->gate_src[counter_number] = gate_src;
748 byte = gat_sce(subpriv->which, counter_number, gate_src);
749 dio200_write8(dev, subpriv->gat_sce_ofs, byte);
755 * Get gate source for an '8254' counter subdevice channel.
758 dio200_subdev_8254_get_gate_src(struct comedi_device *dev,
759 struct comedi_subdevice *s,
760 unsigned int counter_number)
762 const struct dio200_layout *layout = dio200_dev_layout(dev);
763 struct dio200_subdev_8254 *subpriv = s->private;
765 if (!layout->has_clk_gat_sce)
767 if (counter_number > 2)
770 return subpriv->gate_src[counter_number];
774 * Set clock source for an '8254' counter subdevice channel.
777 dio200_subdev_8254_set_clock_src(struct comedi_device *dev,
778 struct comedi_subdevice *s,
779 unsigned int counter_number,
780 unsigned int clock_src)
782 const struct dio200_layout *layout = dio200_dev_layout(dev);
783 struct dio200_subdev_8254 *subpriv = s->private;
786 if (!layout->has_clk_gat_sce)
788 if (counter_number > 2)
790 if (clock_src > (layout->has_enhancements ? 31 : 7))
793 subpriv->clock_src[counter_number] = clock_src;
794 byte = clk_sce(subpriv->which, counter_number, clock_src);
795 dio200_write8(dev, subpriv->clk_sce_ofs, byte);
801 * Get clock source for an '8254' counter subdevice channel.
804 dio200_subdev_8254_get_clock_src(struct comedi_device *dev,
805 struct comedi_subdevice *s,
806 unsigned int counter_number,
807 unsigned int *period_ns)
809 const struct dio200_layout *layout = dio200_dev_layout(dev);
810 struct dio200_subdev_8254 *subpriv = s->private;
813 if (!layout->has_clk_gat_sce)
815 if (counter_number > 2)
818 clock_src = subpriv->clock_src[counter_number];
819 *period_ns = clock_period[clock_src];
824 * Handle 'insn_config' for an '8254' counter subdevice.
827 dio200_subdev_8254_config(struct comedi_device *dev, struct comedi_subdevice *s,
828 struct comedi_insn *insn, unsigned int *data)
830 struct dio200_subdev_8254 *subpriv = s->private;
832 int chan = CR_CHAN(insn->chanspec);
835 spin_lock_irqsave(&subpriv->spinlock, flags);
837 case INSN_CONFIG_SET_COUNTER_MODE:
838 if (data[1] > (I8254_MODE5 | I8254_BINARY))
841 dio200_subdev_8254_set_mode(dev, s, chan, data[1]);
843 case INSN_CONFIG_8254_READ_STATUS:
844 data[1] = dio200_subdev_8254_status(dev, s, chan);
846 case INSN_CONFIG_SET_GATE_SRC:
847 ret = dio200_subdev_8254_set_gate_src(dev, s, chan, data[2]);
851 case INSN_CONFIG_GET_GATE_SRC:
852 ret = dio200_subdev_8254_get_gate_src(dev, s, chan);
859 case INSN_CONFIG_SET_CLOCK_SRC:
860 ret = dio200_subdev_8254_set_clock_src(dev, s, chan, data[1]);
864 case INSN_CONFIG_GET_CLOCK_SRC:
865 ret = dio200_subdev_8254_get_clock_src(dev, s, chan, &data[2]);
876 spin_unlock_irqrestore(&subpriv->spinlock, flags);
877 return ret < 0 ? ret : insn->n;
881 * This function initializes an '8254' counter subdevice.
884 dio200_subdev_8254_init(struct comedi_device *dev, struct comedi_subdevice *s,
887 const struct dio200_layout *layout = dio200_dev_layout(dev);
888 struct dio200_subdev_8254 *subpriv;
891 subpriv = kzalloc(sizeof(*subpriv), GFP_KERNEL);
895 s->private = subpriv;
896 s->type = COMEDI_SUBD_COUNTER;
897 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
900 s->insn_read = dio200_subdev_8254_read;
901 s->insn_write = dio200_subdev_8254_write;
902 s->insn_config = dio200_subdev_8254_config;
904 spin_lock_init(&subpriv->spinlock);
905 subpriv->ofs = offset;
906 if (layout->has_clk_gat_sce) {
907 /* Derive CLK_SCE and GAT_SCE register offsets from
909 subpriv->clk_sce_ofs = DIO200_XCLK_SCE + (offset >> 3);
910 subpriv->gat_sce_ofs = DIO200_XGAT_SCE + (offset >> 3);
911 subpriv->which = (offset >> 2) & 1;
914 /* Initialize channels. */
915 for (chan = 0; chan < 3; chan++) {
916 dio200_subdev_8254_set_mode(dev, s, chan,
917 I8254_MODE0 | I8254_BINARY);
918 if (layout->has_clk_gat_sce) {
919 /* Gate source 0 is VCC (logic 1). */
920 dio200_subdev_8254_set_gate_src(dev, s, chan, 0);
921 /* Clock source 0 is the dedicated clock input. */
922 dio200_subdev_8254_set_clock_src(dev, s, chan, 0);
930 * This function sets I/O directions for an '8255' DIO subdevice.
932 static void dio200_subdev_8255_set_dir(struct comedi_device *dev,
933 struct comedi_subdevice *s)
935 struct dio200_subdev_8255 *subpriv = s->private;
939 /* 1 in io_bits indicates output, 1 in config indicates input */
940 if (!(s->io_bits & 0x0000ff))
942 if (!(s->io_bits & 0x00ff00))
944 if (!(s->io_bits & 0x0f0000))
945 config |= CR_C_LO_IO;
946 if (!(s->io_bits & 0xf00000))
947 config |= CR_C_HI_IO;
948 dio200_write8(dev, subpriv->ofs + 3, config);
952 * Handle 'insn_bits' for an '8255' DIO subdevice.
954 static int dio200_subdev_8255_bits(struct comedi_device *dev,
955 struct comedi_subdevice *s,
956 struct comedi_insn *insn, unsigned int *data)
958 struct dio200_subdev_8255 *subpriv = s->private;
961 s->state &= ~data[0];
962 s->state |= (data[0] & data[1]);
964 dio200_write8(dev, subpriv->ofs, s->state & 0xff);
965 if (data[0] & 0xff00)
966 dio200_write8(dev, subpriv->ofs + 1,
967 (s->state >> 8) & 0xff);
968 if (data[0] & 0xff0000)
969 dio200_write8(dev, subpriv->ofs + 2,
970 (s->state >> 16) & 0xff);
972 data[1] = dio200_read8(dev, subpriv->ofs);
973 data[1] |= dio200_read8(dev, subpriv->ofs + 1) << 8;
974 data[1] |= dio200_read8(dev, subpriv->ofs + 2) << 16;
979 * Handle 'insn_config' for an '8255' DIO subdevice.
981 static int dio200_subdev_8255_config(struct comedi_device *dev,
982 struct comedi_subdevice *s,
983 struct comedi_insn *insn,
989 mask = 1 << CR_CHAN(insn->chanspec);
992 else if (mask & 0x00ff00)
994 else if (mask & 0x0f0000)
999 case INSN_CONFIG_DIO_INPUT:
1000 s->io_bits &= ~bits;
1002 case INSN_CONFIG_DIO_OUTPUT:
1005 case INSN_CONFIG_DIO_QUERY:
1006 data[1] = (s->io_bits & bits) ? COMEDI_OUTPUT : COMEDI_INPUT;
1012 dio200_subdev_8255_set_dir(dev, s);
1017 * This function initializes an '8255' DIO subdevice.
1019 * offset is the offset to the 8255 chip.
1021 static int dio200_subdev_8255_init(struct comedi_device *dev,
1022 struct comedi_subdevice *s,
1023 unsigned int offset)
1025 struct dio200_subdev_8255 *subpriv;
1027 subpriv = kzalloc(sizeof(*subpriv), GFP_KERNEL);
1030 subpriv->ofs = offset;
1031 s->private = subpriv;
1032 s->type = COMEDI_SUBD_DIO;
1033 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1035 s->range_table = &range_digital;
1037 s->insn_bits = dio200_subdev_8255_bits;
1038 s->insn_config = dio200_subdev_8255_config;
1041 dio200_subdev_8255_set_dir(dev, s);
1046 * Handle 'insn_read' for a timer subdevice.
1048 static int dio200_subdev_timer_read(struct comedi_device *dev,
1049 struct comedi_subdevice *s,
1050 struct comedi_insn *insn,
1055 for (n = 0; n < insn->n; n++)
1056 data[n] = dio200_read32(dev, DIO200_TS_COUNT);
1061 * Reset timer subdevice.
1063 static void dio200_subdev_timer_reset(struct comedi_device *dev,
1064 struct comedi_subdevice *s)
1068 clock = dio200_read32(dev, DIO200_TS_CONFIG) & TS_CONFIG_CLK_SRC_MASK;
1069 dio200_write32(dev, DIO200_TS_CONFIG, clock | TS_CONFIG_RESET);
1070 dio200_write32(dev, DIO200_TS_CONFIG, clock);
1074 * Get timer subdevice clock source and period.
1076 static void dio200_subdev_timer_get_clock_src(struct comedi_device *dev,
1077 struct comedi_subdevice *s,
1079 unsigned int *period)
1083 clk = dio200_read32(dev, DIO200_TS_CONFIG) & TS_CONFIG_CLK_SRC_MASK;
1085 *period = (clk < ARRAY_SIZE(ts_clock_period)) ?
1086 ts_clock_period[clk] : 0;
1090 * Set timer subdevice clock source.
1092 static int dio200_subdev_timer_set_clock_src(struct comedi_device *dev,
1093 struct comedi_subdevice *s,
1096 if (src > TS_CONFIG_MAX_CLK_SRC)
1098 dio200_write32(dev, DIO200_TS_CONFIG, src);
1103 * Handle 'insn_config' for a timer subdevice.
1105 static int dio200_subdev_timer_config(struct comedi_device *dev,
1106 struct comedi_subdevice *s,
1107 struct comedi_insn *insn,
1113 case INSN_CONFIG_RESET:
1114 dio200_subdev_timer_reset(dev, s);
1116 case INSN_CONFIG_SET_CLOCK_SRC:
1117 ret = dio200_subdev_timer_set_clock_src(dev, s, data[1]);
1121 case INSN_CONFIG_GET_CLOCK_SRC:
1122 dio200_subdev_timer_get_clock_src(dev, s, &data[1], &data[2]);
1128 return ret < 0 ? ret : insn->n;
1132 * This function initializes a timer subdevice.
1134 * Uses the timestamp timer registers. There is only one timestamp timer.
1136 static int dio200_subdev_timer_init(struct comedi_device *dev,
1137 struct comedi_subdevice *s)
1139 s->type = COMEDI_SUBD_TIMER;
1140 s->subdev_flags = SDF_READABLE | SDF_LSAMPL;
1142 s->maxdata = 0xFFFFFFFF;
1143 s->insn_read = dio200_subdev_timer_read;
1144 s->insn_config = dio200_subdev_timer_config;
1148 void amplc_dio200_set_enhance(struct comedi_device *dev, unsigned char val)
1150 dio200_write8(dev, DIO200_ENHANCE, val);
1152 EXPORT_SYMBOL_GPL(amplc_dio200_set_enhance);
1154 int amplc_dio200_common_attach(struct comedi_device *dev, unsigned int irq,
1155 unsigned long req_irq_flags)
1157 const struct dio200_board *thisboard = comedi_board(dev);
1158 struct dio200_private *devpriv = dev->private;
1159 const struct dio200_layout *layout = dio200_board_layout(thisboard);
1160 struct comedi_subdevice *s;
1165 devpriv->intr_sd = -1;
1167 ret = comedi_alloc_subdevices(dev, layout->n_subdevs);
1171 for (n = 0; n < dev->n_subdevices; n++) {
1172 s = &dev->subdevices[n];
1173 switch (layout->sdtype[n]) {
1175 /* counter subdevice (8254) */
1176 ret = dio200_subdev_8254_init(dev, s,
1182 /* digital i/o subdevice (8255) */
1183 ret = dio200_subdev_8255_init(dev, s,
1189 /* 'INTERRUPT' subdevice */
1191 ret = dio200_subdev_intr_init(dev, s,
1197 devpriv->intr_sd = n;
1199 s->type = COMEDI_SUBD_UNUSED;
1203 ret = dio200_subdev_timer_init(dev, s);
1208 s->type = COMEDI_SUBD_UNUSED;
1212 sdx = devpriv->intr_sd;
1213 if (sdx >= 0 && sdx < dev->n_subdevices)
1214 dev->read_subdev = &dev->subdevices[sdx];
1216 if (request_irq(irq, dio200_interrupt, req_irq_flags,
1217 dev->board_name, dev) >= 0) {
1220 dev_warn(dev->class_dev,
1221 "warning! irq %u unavailable!\n", irq);
1224 dev_info(dev->class_dev, "attached\n");
1227 EXPORT_SYMBOL_GPL(amplc_dio200_common_attach);
1229 void amplc_dio200_common_detach(struct comedi_device *dev)
1231 const struct dio200_board *thisboard = comedi_board(dev);
1232 struct dio200_private *devpriv = dev->private;
1233 const struct dio200_layout *layout;
1236 if (!thisboard || !devpriv)
1239 free_irq(dev->irq, dev);
1240 if (dev->subdevices) {
1241 layout = dio200_board_layout(thisboard);
1242 for (n = 0; n < dev->n_subdevices; n++) {
1243 switch (layout->sdtype[n]) {
1247 comedi_spriv_free(dev, n);
1256 EXPORT_SYMBOL_GPL(amplc_dio200_common_detach);
1258 static int __init amplc_dio200_common_init(void)
1262 module_init(amplc_dio200_common_init);
1264 static void __exit amplc_dio200_common_exit(void)
1267 module_exit(amplc_dio200_common_exit);
1269 MODULE_AUTHOR("Comedi http://www.comedi.org");
1270 MODULE_DESCRIPTION("Comedi helper for amplc_dio200 and amplc_dio200_pci");
1271 MODULE_LICENSE("GPL");