drivers/staging/comedi/drivers/cb_pcidas64.c

   1 /*
   2     comedi/drivers/cb_pcidas64.c
   3     This is a driver for the ComputerBoards/MeasurementComputing PCI-DAS
   4     64xx, 60xx, and 4020 cards.
   5
   6     Author:  Frank Mori Hess <fmhess@users.sourceforge.net>
   7     Copyright (C) 2001, 2002 Frank Mori Hess
   8
   9     Thanks also go to the following people:
  10
  11     Steve Rosenbluth, for providing the source code for
  12     his pci-das6402 driver, and source code for working QNX pci-6402
  13     drivers by Greg Laird and Mariusz Bogacz.  None of the code was
  14     used directly here, but it was useful as an additional source of
  15     documentation on how to program the boards.
  16
  17     John Sims, for much testing and feedback on pcidas-4020 support.
  18
  19     COMEDI - Linux Control and Measurement Device Interface
  20     Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
  21
  22     This program is free software; you can redistribute it and/or modify
  23     it under the terms of the GNU General Public License as published by
  24     the Free Software Foundation; either version 2 of the License, or
  25     (at your option) any later version.
  26
  27     This program is distributed in the hope that it will be useful,
  28     but WITHOUT ANY WARRANTY; without even the implied warranty of
  29     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  30     GNU General Public License for more details.
  31 */
  32
  33 /*
  34  * Driver: cb_pcidas64
  35  * Description: MeasurementComputing PCI-DAS64xx, 60XX, and 4020 series
  36  *   with the PLX 9080 PCI controller
  37  * Author: Frank Mori Hess <fmhess@users.sourceforge.net>
  38  * Status: works
  39  * Updated: Fri, 02 Nov 2012 18:58:55 +0000
  40  * Devices: [Measurement Computing] PCI-DAS6402/16 (cb_pcidas64),
  41  *   PCI-DAS6402/12, PCI-DAS64/M1/16, PCI-DAS64/M2/16,
  42  *   PCI-DAS64/M3/16, PCI-DAS6402/16/JR, PCI-DAS64/M1/16/JR,
  43  *   PCI-DAS64/M2/16/JR, PCI-DAS64/M3/16/JR, PCI-DAS64/M1/14,
  44  *   PCI-DAS64/M2/14, PCI-DAS64/M3/14, PCI-DAS6013, PCI-DAS6014,
  45  *   PCI-DAS6023, PCI-DAS6025, PCI-DAS6030,
  46  *   PCI-DAS6031, PCI-DAS6032, PCI-DAS6033, PCI-DAS6034,
  47  *   PCI-DAS6035, PCI-DAS6036, PCI-DAS6040, PCI-DAS6052,
  48  *   PCI-DAS6070, PCI-DAS6071, PCI-DAS4020/12
  49  *
  50  * Configuration options:
  51  *   None.
  52  *
  53  * Manual attachment of PCI cards with the comedi_config utility is not
  54  * supported by this driver; they are attached automatically.
  55  *
  56  * These boards may be autocalibrated with the comedi_calibrate utility.
  57  *
  58  * To select the bnc trigger input on the 4020 (instead of the dio input),
  59  * specify a nonzero channel in the chanspec.  If you wish to use an external
  60  * master clock on the 4020, you may do so by setting the scan_begin_src
  61  * to TRIG_OTHER, and using an INSN_CONFIG_TIMER_1 configuration insn
  62  * to configure the divisor to use for the external clock.
  63  *
  64  * Some devices are not identified because the PCI device IDs are not yet
  65  * known. If you have such a board, please let the maintainers know.
  66  */
  67
  68 /*
  69
  70 TODO:
  71         make it return error if user attempts an ai command that uses the
  72         external queue, and an ao command simultaneously user counter subdevice
  73         there are a number of boards this driver will support when they are
  74         fully released, but does not yet since the pci device id numbers
  75         are not yet available.
  76
  77         support prescaled 100khz clock for slow pacing (not available on 6000
  78         series?)
  79
  80         make ao fifo size adjustable like ai fifo
  81 */
  82
  83 #include <linux/module.h>
  84 #include <linux/delay.h>
  85 #include <linux/interrupt.h>
  86
  87 #include "../comedi_pci.h"
  88
  89 #include "8255.h"
  90 #include "plx9080.h"
  91 #include "comedi_fc.h"
  92
  93 #define TIMER_BASE 25           /*  40MHz master clock */
  94 /* 100kHz 'prescaled' clock for slow acquisition,
  95  * maybe I'll support this someday */
  96 #define PRESCALED_TIMER_BASE    10000
  97 #define DMA_BUFFER_SIZE 0x1000
  98
  99 /* maximum value that can be loaded into board's 24-bit counters*/
 100 static const int max_counter_value = 0xffffff;
 101
 102 /* PCI-DAS64xxx base addresses */
 103
 104 /* devpriv->main_iobase registers */
 105 enum write_only_registers {
 106         INTR_ENABLE_REG = 0x0,  /*  interrupt enable register */
 107         HW_CONFIG_REG = 0x2,    /*  hardware config register */
 108         DAQ_SYNC_REG = 0xc,
 109         DAQ_ATRIG_LOW_4020_REG = 0xc,
 110         ADC_CONTROL0_REG = 0x10,        /*  adc control register 0 */
 111         ADC_CONTROL1_REG = 0x12,        /*  adc control register 1 */
 112         CALIBRATION_REG = 0x14,
 113         /*  lower 16 bits of adc sample interval counter */
 114         ADC_SAMPLE_INTERVAL_LOWER_REG = 0x16,
 115         /*  upper 8 bits of adc sample interval counter */
 116         ADC_SAMPLE_INTERVAL_UPPER_REG = 0x18,
 117         /*  lower 16 bits of delay interval counter */
 118         ADC_DELAY_INTERVAL_LOWER_REG = 0x1a,
 119         /*  upper 8 bits of delay interval counter */
 120         ADC_DELAY_INTERVAL_UPPER_REG = 0x1c,
 121         /*  lower 16 bits of hardware conversion/scan counter */
 122         ADC_COUNT_LOWER_REG = 0x1e,
 123         /*  upper 8 bits of hardware conversion/scan counter */
 124         ADC_COUNT_UPPER_REG = 0x20,
 125         ADC_START_REG = 0x22,   /*  software trigger to start acquisition */
 126         ADC_CONVERT_REG = 0x24, /*  initiates single conversion */
 127         ADC_QUEUE_CLEAR_REG = 0x26,     /*  clears adc queue */
 128         ADC_QUEUE_LOAD_REG = 0x28,      /*  loads adc queue */
 129         ADC_BUFFER_CLEAR_REG = 0x2a,
 130         /*  high channel for internal queue, use adc_chan_bits() inline above */
 131         ADC_QUEUE_HIGH_REG = 0x2c,
 132         DAC_CONTROL0_REG = 0x50,        /*  dac control register 0 */
 133         DAC_CONTROL1_REG = 0x52,        /*  dac control register 0 */
 134         /*  lower 16 bits of dac sample interval counter */
 135         DAC_SAMPLE_INTERVAL_LOWER_REG = 0x54,
 136         /*  upper 8 bits of dac sample interval counter */
 137         DAC_SAMPLE_INTERVAL_UPPER_REG = 0x56,
 138         DAC_SELECT_REG = 0x60,
 139         DAC_START_REG = 0x64,
 140         DAC_BUFFER_CLEAR_REG = 0x66,    /*  clear dac buffer */
 141 };
 142
 143 static inline unsigned int dac_convert_reg(unsigned int channel)
 144 {
 145         return 0x70 + (2 * (channel & 0x1));
 146 }
 147
 148 static inline unsigned int dac_lsb_4020_reg(unsigned int channel)
 149 {
 150         return 0x70 + (4 * (channel & 0x1));
 151 }
 152
 153 static inline unsigned int dac_msb_4020_reg(unsigned int channel)
 154 {
 155         return 0x72 + (4 * (channel & 0x1));
 156 }
 157
 158 enum read_only_registers {
 159         /*  hardware status register,
 160          *  reading this apparently clears pending interrupts as well */
 161         HW_STATUS_REG = 0x0,
 162         PIPE1_READ_REG = 0x4,
 163         ADC_READ_PNTR_REG = 0x8,
 164         LOWER_XFER_REG = 0x10,
 165         ADC_WRITE_PNTR_REG = 0xc,
 166         PREPOST_REG = 0x14,
 167 };
 168
 169 enum read_write_registers {
 170         I8255_4020_REG = 0x48,  /*  8255 offset, for 4020 only */
 171         /*  external channel/gain queue, uses same bits as ADC_QUEUE_LOAD_REG */
 172         ADC_QUEUE_FIFO_REG = 0x100,
 173         ADC_FIFO_REG = 0x200,   /* adc data fifo */
 174         /* dac data fifo, has weird interactions with external channel queue */
 175         DAC_FIFO_REG = 0x300,
 176 };
 177
 178 /* dev->mmio registers */
 179 enum dio_counter_registers {
 180         DIO_8255_OFFSET = 0x0,
 181         DO_REG = 0x20,
 182         DI_REG = 0x28,
 183         DIO_DIRECTION_60XX_REG = 0x40,
 184         DIO_DATA_60XX_REG = 0x48,
 185 };
 186
 187 /* bit definitions for write-only registers */
 188
 189 enum intr_enable_contents {
 190         ADC_INTR_SRC_MASK = 0x3,        /*  adc interrupt source mask */
 191         ADC_INTR_QFULL_BITS = 0x0,      /*  interrupt fifo quarter full */
 192         ADC_INTR_EOC_BITS = 0x1,        /*  interrupt end of conversion */
 193         ADC_INTR_EOSCAN_BITS = 0x2,     /*  interrupt end of scan */
 194         ADC_INTR_EOSEQ_BITS = 0x3,      /*  interrupt end of sequence mask */
 195         EN_ADC_INTR_SRC_BIT = 0x4,      /*  enable adc interrupt source */
 196         EN_ADC_DONE_INTR_BIT = 0x8,     /*  enable adc acquisition done intr */
 197         DAC_INTR_SRC_MASK = 0x30,
 198         DAC_INTR_QEMPTY_BITS = 0x0,
 199         DAC_INTR_HIGH_CHAN_BITS = 0x10,
 200         EN_DAC_INTR_SRC_BIT = 0x40,     /*  enable dac interrupt source */
 201         EN_DAC_DONE_INTR_BIT = 0x80,
 202         EN_ADC_ACTIVE_INTR_BIT = 0x200, /*  enable adc active interrupt */
 203         EN_ADC_STOP_INTR_BIT = 0x400,   /*  enable adc stop trigger interrupt */
 204         EN_DAC_ACTIVE_INTR_BIT = 0x800, /*  enable dac active interrupt */
 205         EN_DAC_UNDERRUN_BIT = 0x4000,   /*  enable dac underrun status bit */
 206         EN_ADC_OVERRUN_BIT = 0x8000,    /*  enable adc overrun status bit */
 207 };
 208
 209 enum hw_config_contents {
 210         MASTER_CLOCK_4020_MASK = 0x3,   /*  master clock source mask for 4020 */
 211         INTERNAL_CLOCK_4020_BITS = 0x1, /*  use 40 MHz internal master clock */
 212         BNC_CLOCK_4020_BITS = 0x2,      /*  use BNC input for master clock */
 213         EXT_CLOCK_4020_BITS = 0x3,      /*  use dio input for master clock */
 214         EXT_QUEUE_BIT = 0x200,          /*  use external channel/gain queue */
 215         /*  use 225 nanosec strobe when loading dac instead of 50 nanosec */
 216         SLOW_DAC_BIT = 0x400,
 217         /*  bit with unknown function yet given as default value in pci-das64
 218          *  manual */
 219         HW_CONFIG_DUMMY_BITS = 0x2000,
 220         /*  bit selects channels 1/0 for analog input/output, otherwise 0/1 */
 221         DMA_CH_SELECT_BIT = 0x8000,
 222         FIFO_SIZE_REG = 0x4,            /*  allows adjustment of fifo sizes */
 223         DAC_FIFO_SIZE_MASK = 0xff00,    /*  bits that set dac fifo size */
 224         DAC_FIFO_BITS = 0xf800,         /*  8k sample ao fifo */
 225 };
 226 #define DAC_FIFO_SIZE 0x2000
 227
 228 enum daq_atrig_low_4020_contents {
 229         /*  use trig/ext clk bnc input for analog gate signal */
 230         EXT_AGATE_BNC_BIT = 0x8000,
 231         /*  use trig/ext clk bnc input for external stop trigger signal */
 232         EXT_STOP_TRIG_BNC_BIT = 0x4000,
 233         /*  use trig/ext clk bnc input for external start trigger signal */
 234         EXT_START_TRIG_BNC_BIT = 0x2000,
 235 };
 236
 237 static inline uint16_t analog_trig_low_threshold_bits(uint16_t threshold)
 238 {
 239         return threshold & 0xfff;
 240 }
 241
 242 enum adc_control0_contents {
 243         ADC_GATE_SRC_MASK = 0x3,        /*  bits that select gate */
 244         ADC_SOFT_GATE_BITS = 0x1,       /*  software gate */
 245         ADC_EXT_GATE_BITS = 0x2,        /*  external digital gate */
 246         ADC_ANALOG_GATE_BITS = 0x3,     /*  analog level gate */
 247         ADC_GATE_LEVEL_BIT = 0x4,       /*  level-sensitive gate (for digital) */
 248         ADC_GATE_POLARITY_BIT = 0x8,    /*  gate active low */
 249         ADC_START_TRIG_SOFT_BITS = 0x10,
 250         ADC_START_TRIG_EXT_BITS = 0x20,
 251         ADC_START_TRIG_ANALOG_BITS = 0x30,
 252         ADC_START_TRIG_MASK = 0x30,
 253         ADC_START_TRIG_FALLING_BIT = 0x40,      /*  trig 1 uses falling edge */
 254         /*  external pacing uses falling edge */
 255         ADC_EXT_CONV_FALLING_BIT = 0x800,
 256         /*  enable hardware scan counter */
 257         ADC_SAMPLE_COUNTER_EN_BIT = 0x1000,
 258         ADC_DMA_DISABLE_BIT = 0x4000,   /*  disables dma */
 259         ADC_ENABLE_BIT = 0x8000,        /*  master adc enable */
 260 };
 261
 262 enum adc_control1_contents {
 263         /*  should be set for boards with > 16 channels */
 264         ADC_QUEUE_CONFIG_BIT = 0x1,
 265         CONVERT_POLARITY_BIT = 0x10,
 266         EOC_POLARITY_BIT = 0x20,
 267         ADC_SW_GATE_BIT = 0x40, /*  software gate of adc */
 268         ADC_DITHER_BIT = 0x200, /*  turn on extra noise for dithering */
 269         RETRIGGER_BIT = 0x800,
 270         ADC_LO_CHANNEL_4020_MASK = 0x300,
 271         ADC_HI_CHANNEL_4020_MASK = 0xc00,
 272         TWO_CHANNEL_4020_BITS = 0x1000, /*  two channel mode for 4020 */
 273         FOUR_CHANNEL_4020_BITS = 0x2000, /*  four channel mode for 4020 */
 274         CHANNEL_MODE_4020_MASK = 0x3000,
 275         ADC_MODE_MASK = 0xf000,
 276 };
 277
 278 static inline uint16_t adc_lo_chan_4020_bits(unsigned int channel)
 279 {
 280         return (channel & 0x3) << 8;
 281 };
 282
 283 static inline uint16_t adc_hi_chan_4020_bits(unsigned int channel)
 284 {
 285         return (channel & 0x3) << 10;
 286 };
 287
 288 static inline uint16_t adc_mode_bits(unsigned int mode)
 289 {
 290         return (mode & 0xf) << 12;
 291 };
 292
 293 enum calibration_contents {
 294         SELECT_8800_BIT = 0x1,
 295         SELECT_8402_64XX_BIT = 0x2,
 296         SELECT_1590_60XX_BIT = 0x2,
 297         CAL_EN_64XX_BIT = 0x40, /*  calibration enable for 64xx series */
 298         SERIAL_DATA_IN_BIT = 0x80,
 299         SERIAL_CLOCK_BIT = 0x100,
 300         CAL_EN_60XX_BIT = 0x200, /*  calibration enable for 60xx series */
 301         CAL_GAIN_BIT = 0x800,
 302 };
 303
 304 /* calibration sources for 6025 are:
 305  *  0 : ground
 306  *  1 : 10V
 307  *  2 : 5V
 308  *  3 : 0.5V
 309  *  4 : 0.05V
 310  *  5 : ground
 311  *  6 : dac channel 0
 312  *  7 : dac channel 1
 313  */
 314
 315 static inline uint16_t adc_src_bits(unsigned int source)
 316 {
 317         return (source & 0xf) << 3;
 318 };
 319
 320 static inline uint16_t adc_convert_chan_4020_bits(unsigned int channel)
 321 {
 322         return (channel & 0x3) << 8;
 323 };
 324
 325 enum adc_queue_load_contents {
 326         UNIP_BIT = 0x800,       /*  unipolar/bipolar bit */
 327         ADC_SE_DIFF_BIT = 0x1000,       /*  single-ended/ differential bit */
 328         /*  non-referenced single-ended (common-mode input) */
 329         ADC_COMMON_BIT = 0x2000,
 330         QUEUE_EOSEQ_BIT = 0x4000,       /*  queue end of sequence */
 331         QUEUE_EOSCAN_BIT = 0x8000,      /*  queue end of scan */
 332 };
 333
 334 static inline uint16_t adc_chan_bits(unsigned int channel)
 335 {
 336         return channel & 0x3f;
 337 };
 338
 339 enum dac_control0_contents {
 340         DAC_ENABLE_BIT = 0x8000,        /*  dac controller enable bit */
 341         DAC_CYCLIC_STOP_BIT = 0x4000,
 342         DAC_WAVEFORM_MODE_BIT = 0x100,
 343         DAC_EXT_UPDATE_FALLING_BIT = 0x80,
 344         DAC_EXT_UPDATE_ENABLE_BIT = 0x40,
 345         WAVEFORM_TRIG_MASK = 0x30,
 346         WAVEFORM_TRIG_DISABLED_BITS = 0x0,
 347         WAVEFORM_TRIG_SOFT_BITS = 0x10,
 348         WAVEFORM_TRIG_EXT_BITS = 0x20,
 349         WAVEFORM_TRIG_ADC1_BITS = 0x30,
 350         WAVEFORM_TRIG_FALLING_BIT = 0x8,
 351         WAVEFORM_GATE_LEVEL_BIT = 0x4,
 352         WAVEFORM_GATE_ENABLE_BIT = 0x2,
 353         WAVEFORM_GATE_SELECT_BIT = 0x1,
 354 };
 355
 356 enum dac_control1_contents {
 357         DAC_WRITE_POLARITY_BIT = 0x800, /* board-dependent setting */
 358         DAC1_EXT_REF_BIT = 0x200,
 359         DAC0_EXT_REF_BIT = 0x100,
 360         DAC_OUTPUT_ENABLE_BIT = 0x80,   /*  dac output enable bit */
 361         DAC_UPDATE_POLARITY_BIT = 0x40, /* board-dependent setting */
 362         DAC_SW_GATE_BIT = 0x20,
 363         DAC1_UNIPOLAR_BIT = 0x8,
 364         DAC0_UNIPOLAR_BIT = 0x2,
 365 };
 366
 367 /* bit definitions for read-only registers */
 368 enum hw_status_contents {
 369         DAC_UNDERRUN_BIT = 0x1,
 370         ADC_OVERRUN_BIT = 0x2,
 371         DAC_ACTIVE_BIT = 0x4,
 372         ADC_ACTIVE_BIT = 0x8,
 373         DAC_INTR_PENDING_BIT = 0x10,
 374         ADC_INTR_PENDING_BIT = 0x20,
 375         DAC_DONE_BIT = 0x40,
 376         ADC_DONE_BIT = 0x80,
 377         EXT_INTR_PENDING_BIT = 0x100,
 378         ADC_STOP_BIT = 0x200,
 379 };
 380
 381 static inline uint16_t pipe_full_bits(uint16_t hw_status_bits)
 382 {
 383         return (hw_status_bits >> 10) & 0x3;
 384 };
 385
 386 static inline unsigned int dma_chain_flag_bits(uint16_t prepost_bits)
 387 {
 388         return (prepost_bits >> 6) & 0x3;
 389 }
 390
 391 static inline unsigned int adc_upper_read_ptr_code(uint16_t prepost_bits)
 392 {
 393         return (prepost_bits >> 12) & 0x3;
 394 }
 395
 396 static inline unsigned int adc_upper_write_ptr_code(uint16_t prepost_bits)
 397 {
 398         return (prepost_bits >> 14) & 0x3;
 399 }
 400
 401 /* I2C addresses for 4020 */
 402 enum i2c_addresses {
 403         RANGE_CAL_I2C_ADDR = 0x20,
 404         CALDAC0_I2C_ADDR = 0xc,
 405         CALDAC1_I2C_ADDR = 0xd,
 406 };
 407
 408 enum range_cal_i2c_contents {
 409         /*  bits that set what source the adc converter measures */
 410         ADC_SRC_4020_MASK = 0x70,
 411         /*  make bnc trig/ext clock threshold 0V instead of 2.5V */
 412         BNC_TRIG_THRESHOLD_0V_BIT = 0x80,
 413 };
 414
 415 static inline uint8_t adc_src_4020_bits(unsigned int source)
 416 {
 417         return (source << 4) & ADC_SRC_4020_MASK;
 418 };
 419
 420 static inline uint8_t attenuate_bit(unsigned int channel)
 421 {
 422         /*  attenuate channel (+-5V input range) */
 423         return 1 << (channel & 0x3);
 424 };
 425
 426 /* analog input ranges for 64xx boards */
 427 static const struct comedi_lrange ai_ranges_64xx = {
 428         8, {
 429                 BIP_RANGE(10),
 430                 BIP_RANGE(5),
 431                 BIP_RANGE(2.5),
 432                 BIP_RANGE(1.25),
 433                 UNI_RANGE(10),
 434                 UNI_RANGE(5),
 435                 UNI_RANGE(2.5),
 436                 UNI_RANGE(1.25)
 437         }
 438 };
 439
 440 static const uint8_t ai_range_code_64xx[8] = {
 441         0x0, 0x1, 0x2, 0x3,     /* bipolar 10, 5, 2,5, 1.25 */
 442         0x8, 0x9, 0xa, 0xb      /* unipolar 10, 5, 2.5, 1.25 */
 443 };
 444
 445 /* analog input ranges for 64-Mx boards */
 446 static const struct comedi_lrange ai_ranges_64_mx = {
 447         7, {
 448                 BIP_RANGE(5),
 449                 BIP_RANGE(2.5),
 450                 BIP_RANGE(1.25),
 451                 BIP_RANGE(0.625),
 452                 UNI_RANGE(5),
 453                 UNI_RANGE(2.5),
 454                 UNI_RANGE(1.25)
 455         }
 456 };
 457
 458 static const uint8_t ai_range_code_64_mx[7] = {
 459         0x0, 0x1, 0x2, 0x3,     /* bipolar 5, 2.5, 1.25, 0.625 */
 460         0x9, 0xa, 0xb           /* unipolar 5, 2.5, 1.25 */
 461 };
 462
 463 /* analog input ranges for 60xx boards */
 464 static const struct comedi_lrange ai_ranges_60xx = {
 465         4, {
 466                 BIP_RANGE(10),
 467                 BIP_RANGE(5),
 468                 BIP_RANGE(0.5),
 469                 BIP_RANGE(0.05)
 470         }
 471 };
 472
 473 static const uint8_t ai_range_code_60xx[4] = {
 474         0x0, 0x1, 0x4, 0x7      /* bipolar 10, 5, 0.5, 0.05 */
 475 };
 476
 477 /* analog input ranges for 6030, etc boards */
 478 static const struct comedi_lrange ai_ranges_6030 = {
 479         14, {
 480                 BIP_RANGE(10),
 481                 BIP_RANGE(5),
 482                 BIP_RANGE(2),
 483                 BIP_RANGE(1),
 484                 BIP_RANGE(0.5),
 485                 BIP_RANGE(0.2),
 486                 BIP_RANGE(0.1),
 487                 UNI_RANGE(10),
 488                 UNI_RANGE(5),
 489                 UNI_RANGE(2),
 490                 UNI_RANGE(1),
 491                 UNI_RANGE(0.5),
 492                 UNI_RANGE(0.2),
 493                 UNI_RANGE(0.1)
 494         }
 495 };
 496
 497 static const uint8_t ai_range_code_6030[14] = {
 498         0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, /* bip 10, 5, 2, 1, 0.5, 0.2, 0.1 */
 499         0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf  /* uni 10, 5, 2, 1, 0.5, 0.2, 0.1 */
 500 };
 501
 502 /* analog input ranges for 6052, etc boards */
 503 static const struct comedi_lrange ai_ranges_6052 = {
 504         15, {
 505                 BIP_RANGE(10),
 506                 BIP_RANGE(5),
 507                 BIP_RANGE(2.5),
 508                 BIP_RANGE(1),
 509                 BIP_RANGE(0.5),
 510                 BIP_RANGE(0.25),
 511                 BIP_RANGE(0.1),
 512                 BIP_RANGE(0.05),
 513                 UNI_RANGE(10),
 514                 UNI_RANGE(5),
 515                 UNI_RANGE(2),
 516                 UNI_RANGE(1),
 517                 UNI_RANGE(0.5),
 518                 UNI_RANGE(0.2),
 519                 UNI_RANGE(0.1)
 520         }
 521 };
 522
 523 static const uint8_t ai_range_code_6052[15] = {
 524         0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, /* bipolar 10 ... 0.05 */
 525         0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf       /* unipolar 10 ... 0.1 */
 526 };
 527
 528 /* analog input ranges for 4020 board */
 529 static const struct comedi_lrange ai_ranges_4020 = {
 530         2, {
 531                 BIP_RANGE(5),
 532                 BIP_RANGE(1)
 533         }
 534 };
 535
 536 /* analog output ranges */
 537 static const struct comedi_lrange ao_ranges_64xx = {
 538         4, {
 539                 BIP_RANGE(5),
 540                 BIP_RANGE(10),
 541                 UNI_RANGE(5),
 542                 UNI_RANGE(10)
 543         }
 544 };
 545
 546 static const int ao_range_code_64xx[] = {
 547         0x0,
 548         0x1,
 549         0x2,
 550         0x3,
 551 };
 552
 553 static const int ao_range_code_60xx[] = {
 554         0x0,
 555 };
 556
 557 static const struct comedi_lrange ao_ranges_6030 = {
 558         2, {
 559                 BIP_RANGE(10),
 560                 UNI_RANGE(10)
 561         }
 562 };
 563
 564 static const int ao_range_code_6030[] = {
 565         0x0,
 566         0x2,
 567 };
 568
 569 static const struct comedi_lrange ao_ranges_4020 = {
 570         2, {
 571                 BIP_RANGE(5),
 572                 BIP_RANGE(10)
 573         }
 574 };
 575
 576 static const int ao_range_code_4020[] = {
 577         0x1,
 578         0x0,
 579 };
 580
 581 enum register_layout {
 582         LAYOUT_60XX,
 583         LAYOUT_64XX,
 584         LAYOUT_4020,
 585 };
 586
 587 struct hw_fifo_info {
 588         unsigned int num_segments;
 589         unsigned int max_segment_length;
 590         unsigned int sample_packing_ratio;
 591         uint16_t fifo_size_reg_mask;
 592 };
 593
 594 enum pcidas64_boardid {
 595         BOARD_PCIDAS6402_16,
 596         BOARD_PCIDAS6402_12,
 597         BOARD_PCIDAS64_M1_16,
 598         BOARD_PCIDAS64_M2_16,
 599         BOARD_PCIDAS64_M3_16,
 600         BOARD_PCIDAS6013,
 601         BOARD_PCIDAS6014,
 602         BOARD_PCIDAS6023,
 603         BOARD_PCIDAS6025,
 604         BOARD_PCIDAS6030,
 605         BOARD_PCIDAS6031,
 606         BOARD_PCIDAS6032,
 607         BOARD_PCIDAS6033,
 608         BOARD_PCIDAS6034,
 609         BOARD_PCIDAS6035,
 610         BOARD_PCIDAS6036,
 611         BOARD_PCIDAS6040,
 612         BOARD_PCIDAS6052,
 613         BOARD_PCIDAS6070,
 614         BOARD_PCIDAS6071,
 615         BOARD_PCIDAS4020_12,
 616         BOARD_PCIDAS6402_16_JR,
 617         BOARD_PCIDAS64_M1_16_JR,
 618         BOARD_PCIDAS64_M2_16_JR,
 619         BOARD_PCIDAS64_M3_16_JR,
 620         BOARD_PCIDAS64_M1_14,
 621         BOARD_PCIDAS64_M2_14,
 622         BOARD_PCIDAS64_M3_14,
 623 };
 624
 625 struct pcidas64_board {
 626         const char *name;
 627         int ai_se_chans;        /*  number of ai inputs in single-ended mode */
 628         int ai_bits;            /*  analog input resolution */
 629         int ai_speed;           /*  fastest conversion period in ns */
 630         const struct comedi_lrange *ai_range_table;
 631         const uint8_t *ai_range_code;
 632         int ao_nchan;           /*  number of analog out channels */
 633         int ao_bits;            /*  analog output resolution */
 634         int ao_scan_speed;      /*  analog output scan speed */
 635         const struct comedi_lrange *ao_range_table;
 636         const int *ao_range_code;
 637         const struct hw_fifo_info *const ai_fifo;
 638         /*  different board families have slightly different registers */
 639         enum register_layout layout;
 640         unsigned has_8255:1;
 641 };
 642
 643 static const struct hw_fifo_info ai_fifo_4020 = {
 644         .num_segments = 2,
 645         .max_segment_length = 0x8000,
 646         .sample_packing_ratio = 2,
 647         .fifo_size_reg_mask = 0x7f,
 648 };
 649
 650 static const struct hw_fifo_info ai_fifo_64xx = {
 651         .num_segments = 4,
 652         .max_segment_length = 0x800,
 653         .sample_packing_ratio = 1,
 654         .fifo_size_reg_mask = 0x3f,
 655 };
 656
 657 static const struct hw_fifo_info ai_fifo_60xx = {
 658         .num_segments = 4,
 659         .max_segment_length = 0x800,
 660         .sample_packing_ratio = 1,
 661         .fifo_size_reg_mask = 0x7f,
 662 };
 663
 664 /* maximum number of dma transfers we will chain together into a ring
 665  * (and the maximum number of dma buffers we maintain) */
 666 #define MAX_AI_DMA_RING_COUNT (0x80000 / DMA_BUFFER_SIZE)
 667 #define MIN_AI_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
 668 #define AO_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
 669 static inline unsigned int ai_dma_ring_count(const struct pcidas64_board *board)
 670 {
 671         if (board->layout == LAYOUT_4020)
 672                 return MAX_AI_DMA_RING_COUNT;
 673
 674         return MIN_AI_DMA_RING_COUNT;
 675 }
 676
 677 static const int bytes_in_sample = 2;
 678
 679 static const struct pcidas64_board pcidas64_boards[] = {
 680         [BOARD_PCIDAS6402_16] = {
 681                 .name           = "pci-das6402/16",
 682                 .ai_se_chans    = 64,
 683                 .ai_bits        = 16,
 684                 .ai_speed       = 5000,
 685                 .ao_nchan       = 2,
 686                 .ao_bits        = 16,
 687                 .ao_scan_speed  = 10000,
 688                 .layout         = LAYOUT_64XX,
 689                 .ai_range_table = &ai_ranges_64xx,
 690                 .ai_range_code  = ai_range_code_64xx,
 691                 .ao_range_table = &ao_ranges_64xx,
 692                 .ao_range_code  = ao_range_code_64xx,
 693                 .ai_fifo        = &ai_fifo_64xx,
 694                 .has_8255       = 1,
 695         },
 696         [BOARD_PCIDAS6402_12] = {
 697                 .name           = "pci-das6402/12",     /*  XXX check */
 698                 .ai_se_chans    = 64,
 699                 .ai_bits        = 12,
 700                 .ai_speed       = 5000,
 701                 .ao_nchan       = 2,
 702                 .ao_bits        = 12,
 703                 .ao_scan_speed  = 10000,
 704                 .layout         = LAYOUT_64XX,
 705                 .ai_range_table = &ai_ranges_64xx,
 706                 .ai_range_code  = ai_range_code_64xx,
 707                 .ao_range_table = &ao_ranges_64xx,
 708                 .ao_range_code  = ao_range_code_64xx,
 709                 .ai_fifo        = &ai_fifo_64xx,
 710                 .has_8255       = 1,
 711         },
 712         [BOARD_PCIDAS64_M1_16] = {
 713                 .name           = "pci-das64/m1/16",
 714                 .ai_se_chans    = 64,
 715                 .ai_bits        = 16,
 716                 .ai_speed       = 1000,
 717                 .ao_nchan       = 2,
 718                 .ao_bits        = 16,
 719                 .ao_scan_speed  = 10000,
 720                 .layout         = LAYOUT_64XX,
 721                 .ai_range_table = &ai_ranges_64_mx,
 722                 .ai_range_code  = ai_range_code_64_mx,
 723                 .ao_range_table = &ao_ranges_64xx,
 724                 .ao_range_code  = ao_range_code_64xx,
 725                 .ai_fifo        = &ai_fifo_64xx,
 726                 .has_8255       = 1,
 727         },
 728         [BOARD_PCIDAS64_M2_16] = {
 729                 .name = "pci-das64/m2/16",
 730                 .ai_se_chans    = 64,
 731                 .ai_bits        = 16,
 732                 .ai_speed       = 500,
 733                 .ao_nchan       = 2,
 734                 .ao_bits        = 16,
 735                 .ao_scan_speed  = 10000,
 736                 .layout         = LAYOUT_64XX,
 737                 .ai_range_table = &ai_ranges_64_mx,
 738                 .ai_range_code  = ai_range_code_64_mx,
 739                 .ao_range_table = &ao_ranges_64xx,
 740                 .ao_range_code  = ao_range_code_64xx,
 741                 .ai_fifo        = &ai_fifo_64xx,
 742                 .has_8255       = 1,
 743         },
 744         [BOARD_PCIDAS64_M3_16] = {
 745                 .name           = "pci-das64/m3/16",
 746                 .ai_se_chans    = 64,
 747                 .ai_bits        = 16,
 748                 .ai_speed       = 333,
 749                 .ao_nchan       = 2,
 750                 .ao_bits        = 16,
 751                 .ao_scan_speed  = 10000,
 752                 .layout         = LAYOUT_64XX,
 753                 .ai_range_table = &ai_ranges_64_mx,
 754                 .ai_range_code  = ai_range_code_64_mx,
 755                 .ao_range_table = &ao_ranges_64xx,
 756                 .ao_range_code  = ao_range_code_64xx,
 757                 .ai_fifo        = &ai_fifo_64xx,
 758                 .has_8255       = 1,
 759         },
 760         [BOARD_PCIDAS6013] = {
 761                 .name           = "pci-das6013",
 762                 .ai_se_chans    = 16,
 763                 .ai_bits        = 16,
 764                 .ai_speed       = 5000,
 765                 .ao_nchan       = 0,
 766                 .ao_bits        = 16,
 767                 .layout         = LAYOUT_60XX,
 768                 .ai_range_table = &ai_ranges_60xx,
 769                 .ai_range_code  = ai_range_code_60xx,
 770                 .ao_range_table = &range_bipolar10,
 771                 .ao_range_code  = ao_range_code_60xx,
 772                 .ai_fifo        = &ai_fifo_60xx,
 773                 .has_8255       = 0,
 774         },
 775         [BOARD_PCIDAS6014] = {
 776                 .name           = "pci-das6014",
 777                 .ai_se_chans    = 16,
 778                 .ai_bits        = 16,
 779                 .ai_speed       = 5000,
 780                 .ao_nchan       = 2,
 781                 .ao_bits        = 16,
 782                 .ao_scan_speed  = 100000,
 783                 .layout         = LAYOUT_60XX,
 784                 .ai_range_table = &ai_ranges_60xx,
 785                 .ai_range_code  = ai_range_code_60xx,
 786                 .ao_range_table = &range_bipolar10,
 787                 .ao_range_code  = ao_range_code_60xx,
 788                 .ai_fifo        = &ai_fifo_60xx,
 789                 .has_8255       = 0,
 790         },
 791         [BOARD_PCIDAS6023] = {
 792                 .name           = "pci-das6023",
 793                 .ai_se_chans    = 16,
 794                 .ai_bits        = 12,
 795                 .ai_speed       = 5000,
 796                 .ao_nchan       = 0,
 797                 .ao_scan_speed  = 100000,
 798                 .layout         = LAYOUT_60XX,
 799                 .ai_range_table = &ai_ranges_60xx,
 800                 .ai_range_code  = ai_range_code_60xx,
 801                 .ao_range_table = &range_bipolar10,
 802                 .ao_range_code  = ao_range_code_60xx,
 803                 .ai_fifo        = &ai_fifo_60xx,
 804                 .has_8255       = 1,
 805         },
 806         [BOARD_PCIDAS6025] = {
 807                 .name           = "pci-das6025",
 808                 .ai_se_chans    = 16,
 809                 .ai_bits        = 12,
 810                 .ai_speed       = 5000,
 811                 .ao_nchan       = 2,
 812                 .ao_bits        = 12,
 813                 .ao_scan_speed  = 100000,
 814                 .layout         = LAYOUT_60XX,
 815                 .ai_range_table = &ai_ranges_60xx,
 816                 .ai_range_code  = ai_range_code_60xx,
 817                 .ao_range_table = &range_bipolar10,
 818                 .ao_range_code  = ao_range_code_60xx,
 819                 .ai_fifo        = &ai_fifo_60xx,
 820                 .has_8255       = 1,
 821         },
 822         [BOARD_PCIDAS6030] = {
 823                 .name           = "pci-das6030",
 824                 .ai_se_chans    = 16,
 825                 .ai_bits        = 16,
 826                 .ai_speed       = 10000,
 827                 .ao_nchan       = 2,
 828                 .ao_bits        = 16,
 829                 .ao_scan_speed  = 10000,
 830                 .layout         = LAYOUT_60XX,
 831                 .ai_range_table = &ai_ranges_6030,
 832                 .ai_range_code  = ai_range_code_6030,
 833                 .ao_range_table = &ao_ranges_6030,
 834                 .ao_range_code  = ao_range_code_6030,
 835                 .ai_fifo        = &ai_fifo_60xx,
 836                 .has_8255       = 0,
 837         },
 838         [BOARD_PCIDAS6031] = {
 839                 .name           = "pci-das6031",
 840                 .ai_se_chans    = 64,
 841                 .ai_bits        = 16,
 842                 .ai_speed       = 10000,
 843                 .ao_nchan       = 2,
 844                 .ao_bits        = 16,
 845                 .ao_scan_speed  = 10000,
 846                 .layout         = LAYOUT_60XX,
 847                 .ai_range_table = &ai_ranges_6030,
 848                 .ai_range_code  = ai_range_code_6030,
 849                 .ao_range_table = &ao_ranges_6030,
 850                 .ao_range_code  = ao_range_code_6030,
 851                 .ai_fifo        = &ai_fifo_60xx,
 852                 .has_8255       = 0,
 853         },
 854         [BOARD_PCIDAS6032] = {
 855                 .name           = "pci-das6032",
 856                 .ai_se_chans    = 16,
 857                 .ai_bits        = 16,
 858                 .ai_speed       = 10000,
 859                 .ao_nchan       = 0,
 860                 .layout         = LAYOUT_60XX,
 861                 .ai_range_table = &ai_ranges_6030,
 862                 .ai_range_code  = ai_range_code_6030,
 863                 .ai_fifo        = &ai_fifo_60xx,
 864                 .has_8255       = 0,
 865         },
 866         [BOARD_PCIDAS6033] = {
 867                 .name           = "pci-das6033",
 868                 .ai_se_chans    = 64,
 869                 .ai_bits        = 16,
 870                 .ai_speed       = 10000,
 871                 .ao_nchan       = 0,
 872                 .layout         = LAYOUT_60XX,
 873                 .ai_range_table = &ai_ranges_6030,
 874                 .ai_range_code  = ai_range_code_6030,
 875                 .ai_fifo        = &ai_fifo_60xx,
 876                 .has_8255       = 0,
 877         },
 878         [BOARD_PCIDAS6034] = {
 879                 .name           = "pci-das6034",
 880                 .ai_se_chans    = 16,
 881                 .ai_bits        = 16,
 882                 .ai_speed       = 5000,
 883                 .ao_nchan       = 0,
 884                 .ao_scan_speed  = 0,
 885                 .layout         = LAYOUT_60XX,
 886                 .ai_range_table = &ai_ranges_60xx,
 887                 .ai_range_code  = ai_range_code_60xx,
 888                 .ai_fifo        = &ai_fifo_60xx,
 889                 .has_8255       = 0,
 890         },
 891         [BOARD_PCIDAS6035] = {
 892                 .name           = "pci-das6035",
 893                 .ai_se_chans    = 16,
 894                 .ai_bits        = 16,
 895                 .ai_speed       = 5000,
 896                 .ao_nchan       = 2,
 897                 .ao_bits        = 12,
 898                 .ao_scan_speed  = 100000,
 899                 .layout         = LAYOUT_60XX,
 900                 .ai_range_table = &ai_ranges_60xx,
 901                 .ai_range_code  = ai_range_code_60xx,
 902                 .ao_range_table = &range_bipolar10,
 903                 .ao_range_code  = ao_range_code_60xx,
 904                 .ai_fifo        = &ai_fifo_60xx,
 905                 .has_8255       = 0,
 906         },
 907         [BOARD_PCIDAS6036] = {
 908                 .name           = "pci-das6036",
 909                 .ai_se_chans    = 16,
 910                 .ai_bits        = 16,
 911                 .ai_speed       = 5000,
 912                 .ao_nchan       = 2,
 913                 .ao_bits        = 16,
 914                 .ao_scan_speed  = 100000,
 915                 .layout         = LAYOUT_60XX,
 916                 .ai_range_table = &ai_ranges_60xx,
 917                 .ai_range_code  = ai_range_code_60xx,
 918                 .ao_range_table = &range_bipolar10,
 919                 .ao_range_code  = ao_range_code_60xx,
 920                 .ai_fifo        = &ai_fifo_60xx,
 921                 .has_8255       = 0,
 922         },
 923         [BOARD_PCIDAS6040] = {
 924                 .name           = "pci-das6040",
 925                 .ai_se_chans    = 16,
 926                 .ai_bits        = 12,
 927                 .ai_speed       = 2000,
 928                 .ao_nchan       = 2,
 929                 .ao_bits        = 12,
 930                 .ao_scan_speed  = 1000,
 931                 .layout         = LAYOUT_60XX,
 932                 .ai_range_table = &ai_ranges_6052,
 933                 .ai_range_code  = ai_range_code_6052,
 934                 .ao_range_table = &ao_ranges_6030,
 935                 .ao_range_code  = ao_range_code_6030,
 936                 .ai_fifo        = &ai_fifo_60xx,
 937                 .has_8255       = 0,
 938         },
 939         [BOARD_PCIDAS6052] = {
 940                 .name           = "pci-das6052",
 941                 .ai_se_chans    = 16,
 942                 .ai_bits        = 16,
 943                 .ai_speed       = 3333,
 944                 .ao_nchan       = 2,
 945                 .ao_bits        = 16,
 946                 .ao_scan_speed  = 3333,
 947                 .layout         = LAYOUT_60XX,
 948                 .ai_range_table = &ai_ranges_6052,
 949                 .ai_range_code  = ai_range_code_6052,
 950                 .ao_range_table = &ao_ranges_6030,
 951                 .ao_range_code  = ao_range_code_6030,
 952                 .ai_fifo        = &ai_fifo_60xx,
 953                 .has_8255       = 0,
 954         },
 955         [BOARD_PCIDAS6070] = {
 956                 .name           = "pci-das6070",
 957                 .ai_se_chans    = 16,
 958                 .ai_bits        = 12,
 959                 .ai_speed       = 800,
 960                 .ao_nchan       = 2,
 961                 .ao_bits        = 12,
 962                 .ao_scan_speed  = 1000,
 963                 .layout         = LAYOUT_60XX,
 964                 .ai_range_table = &ai_ranges_6052,
 965                 .ai_range_code  = ai_range_code_6052,
 966                 .ao_range_table = &ao_ranges_6030,
 967                 .ao_range_code  = ao_range_code_6030,
 968                 .ai_fifo        = &ai_fifo_60xx,
 969                 .has_8255       = 0,
 970         },
 971         [BOARD_PCIDAS6071] = {
 972                 .name           = "pci-das6071",
 973                 .ai_se_chans    = 64,
 974                 .ai_bits        = 12,
 975                 .ai_speed       = 800,
 976                 .ao_nchan       = 2,
 977                 .ao_bits        = 12,
 978                 .ao_scan_speed  = 1000,
 979                 .layout         = LAYOUT_60XX,
 980                 .ai_range_table = &ai_ranges_6052,
 981                 .ai_range_code  = ai_range_code_6052,
 982                 .ao_range_table = &ao_ranges_6030,
 983                 .ao_range_code  = ao_range_code_6030,
 984                 .ai_fifo        = &ai_fifo_60xx,
 985                 .has_8255       = 0,
 986         },
 987         [BOARD_PCIDAS4020_12] = {
 988                 .name           = "pci-das4020/12",
 989                 .ai_se_chans    = 4,
 990                 .ai_bits        = 12,
 991                 .ai_speed       = 50,
 992                 .ao_bits        = 12,
 993                 .ao_nchan       = 2,
 994                 .ao_scan_speed  = 0,    /*  no hardware pacing on ao */
 995                 .layout         = LAYOUT_4020,
 996                 .ai_range_table = &ai_ranges_4020,
 997                 .ao_range_table = &ao_ranges_4020,
 998                 .ao_range_code  = ao_range_code_4020,
 999                 .ai_fifo        = &ai_fifo_4020,
1000                 .has_8255       = 1,
1001         },
1002 #if 0
1003         /*
1004          * The device id for these boards is unknown
1005          */
1006
1007         [BOARD_PCIDAS6402_16_JR] = {
1008                 .name           = "pci-das6402/16/jr",
1009                 .ai_se_chans    = 64,
1010                 .ai_bits        = 16,
1011                 .ai_speed       = 5000,
1012                 .ao_nchan       = 0,
1013                 .ao_scan_speed  = 10000,
1014                 .layout         = LAYOUT_64XX,
1015                 .ai_range_table = &ai_ranges_64xx,
1016                 .ai_range_code  = ai_range_code_64xx,
1017                 .ai_fifo        = ai_fifo_64xx,
1018                 .has_8255       = 1,
1019         },
1020         [BOARD_PCIDAS64_M1_16_JR] = {
1021                 .name           = "pci-das64/m1/16/jr",
1022                 .ai_se_chans    = 64,
1023                 .ai_bits        = 16,
1024                 .ai_speed       = 1000,
1025                 .ao_nchan       = 0,
1026                 .ao_scan_speed  = 10000,
1027                 .layout         = LAYOUT_64XX,
1028                 .ai_range_table = &ai_ranges_64_mx,
1029                 .ai_range_code  = ai_range_code_64_mx,
1030                 .ai_fifo        = ai_fifo_64xx,
1031                 .has_8255       = 1,
1032         },
1033         [BOARD_PCIDAS64_M2_16_JR] = {
1034                 .name = "pci-das64/m2/16/jr",
1035                 .ai_se_chans    = 64,
1036                 .ai_bits        = 16,
1037                 .ai_speed       = 500,
1038                 .ao_nchan       = 0,
1039                 .ao_scan_speed  = 10000,
1040                 .layout         = LAYOUT_64XX,
1041                 .ai_range_table = &ai_ranges_64_mx,
1042                 .ai_range_code  = ai_range_code_64_mx,
1043                 .ai_fifo        = ai_fifo_64xx,
1044                 .has_8255       = 1,
1045         },
1046         [BOARD_PCIDAS64_M3_16_JR] = {
1047                 .name           = "pci-das64/m3/16/jr",
1048                 .ai_se_chans    = 64,
1049                 .ai_bits        = 16,
1050                 .ai_speed       = 333,
1051                 .ao_nchan       = 0,
1052                 .ao_scan_speed  = 10000,
1053                 .layout         = LAYOUT_64XX,
1054                 .ai_range_table = &ai_ranges_64_mx,
1055                 .ai_range_code  = ai_range_code_64_mx,
1056                 .ai_fifo        = ai_fifo_64xx,
1057                 .has_8255       = 1,
1058         },
1059         [BOARD_PCIDAS64_M1_14] = {
1060                 .name           = "pci-das64/m1/14",
1061                 .ai_se_chans    = 64,
1062                 .ai_bits        = 14,
1063                 .ai_speed       = 1000,
1064                 .ao_nchan       = 2,
1065                 .ao_scan_speed  = 10000,
1066                 .layout         = LAYOUT_64XX,
1067                 .ai_range_table = &ai_ranges_64_mx,
1068                 .ai_range_code  = ai_range_code_64_mx,
1069                 .ai_fifo        = ai_fifo_64xx,
1070                 .has_8255       = 1,
1071         },
1072         [BOARD_PCIDAS64_M2_14] = {
1073                 .name           = "pci-das64/m2/14",
1074                 .ai_se_chans    = 64,
1075                 .ai_bits        = 14,
1076                 .ai_speed       = 500,
1077                 .ao_nchan       = 2,
1078                 .ao_scan_speed  = 10000,
1079                 .layout         = LAYOUT_64XX,
1080                 .ai_range_table = &ai_ranges_64_mx,
1081                 .ai_range_code  = ai_range_code_64_mx,
1082                 .ai_fifo        = ai_fifo_64xx,
1083                 .has_8255       = 1,
1084         },
1085         [BOARD_PCIDAS64_M3_14] = {
1086                 .name           = "pci-das64/m3/14",
1087                 .ai_se_chans    = 64,
1088                 .ai_bits        = 14,
1089                 .ai_speed       = 333,
1090                 .ao_nchan       = 2,
1091                 .ao_scan_speed  = 10000,
1092                 .layout         = LAYOUT_64XX,
1093                 .ai_range_table = &ai_ranges_64_mx,
1094                 .ai_range_code  = ai_range_code_64_mx,
1095                 .ai_fifo        = ai_fifo_64xx,
1096                 .has_8255       = 1,
1097         },
1098 #endif
1099 };
1100
1101 static inline unsigned short se_diff_bit_6xxx(struct comedi_device *dev,
1102                                               int use_differential)
1103 {
1104         const struct pcidas64_board *thisboard = dev->board_ptr;
1105
1106         if ((thisboard->layout == LAYOUT_64XX && !use_differential) ||
1107             (thisboard->layout == LAYOUT_60XX && use_differential))
1108                 return ADC_SE_DIFF_BIT;
1109
1110         return 0;
1111 }
1112
1113 struct ext_clock_info {
1114         /*  master clock divisor to use for scans with external master clock */
1115         unsigned int divisor;
1116         /*  chanspec for master clock input when used as scan begin src */
1117         unsigned int chanspec;
1118 };
1119
1120 /* this structure is for data unique to this hardware driver. */
1121 struct pcidas64_private {
1122         /*  base addresses (physical) */
1123         resource_size_t main_phys_iobase;
1124         resource_size_t dio_counter_phys_iobase;
1125         /*  base addresses (ioremapped) */
1126         void __iomem *plx9080_iobase;
1127         void __iomem *main_iobase;
1128         /*  local address (used by dma controller) */
1129         uint32_t local0_iobase;
1130         uint32_t local1_iobase;
1131         /*  dma buffers for analog input */
1132         uint16_t *ai_buffer[MAX_AI_DMA_RING_COUNT];
1133         /*  physical addresses of ai dma buffers */
1134         dma_addr_t ai_buffer_bus_addr[MAX_AI_DMA_RING_COUNT];
1135         /*  array of ai dma descriptors read by plx9080,
1136          *  allocated to get proper alignment */
1137         struct plx_dma_desc *ai_dma_desc;
1138         /*  physical address of ai dma descriptor array */
1139         dma_addr_t ai_dma_desc_bus_addr;
1140         /*  index of the ai dma descriptor/buffer
1141          *  that is currently being used */
1142         unsigned int ai_dma_index;
1143         /*  dma buffers for analog output */
1144         uint16_t *ao_buffer[AO_DMA_RING_COUNT];
1145         /*  physical addresses of ao dma buffers */
1146         dma_addr_t ao_buffer_bus_addr[AO_DMA_RING_COUNT];
1147         struct plx_dma_desc *ao_dma_desc;
1148         dma_addr_t ao_dma_desc_bus_addr;
1149         /*  keeps track of buffer where the next ao sample should go */
1150         unsigned int ao_dma_index;
1151         unsigned int hw_revision;       /*  stc chip hardware revision number */
1152         /*  last bits sent to INTR_ENABLE_REG register */
1153         unsigned int intr_enable_bits;
1154         /*  last bits sent to ADC_CONTROL1_REG register */
1155         uint16_t adc_control1_bits;
1156         /*  last bits sent to FIFO_SIZE_REG register */
1157         uint16_t fifo_size_bits;
1158         /*  last bits sent to HW_CONFIG_REG register */
1159         uint16_t hw_config_bits;
1160         uint16_t dac_control1_bits;
1161         /*  last bits written to plx9080 control register */
1162         uint32_t plx_control_bits;
1163         /*  last bits written to plx interrupt control and status register */
1164         uint32_t plx_intcsr_bits;
1165         /*  index of calibration source readable through ai ch0 */
1166         int calibration_source;
1167         /*  bits written to i2c calibration/range register */
1168         uint8_t i2c_cal_range_bits;
1169         /*  configure digital triggers to trigger on falling edge */
1170         unsigned int ext_trig_falling;
1171         short ai_cmd_running;
1172         unsigned int ai_fifo_segment_length;
1173         struct ext_clock_info ext_clock;
1174         unsigned short ao_bounce_buffer[DAC_FIFO_SIZE];
1175 };
1176
1177 static unsigned int ai_range_bits_6xxx(const struct comedi_device *dev,
1178                                        unsigned int range_index)
1179 {
1180         const struct pcidas64_board *thisboard = dev->board_ptr;
1181
1182         return thisboard->ai_range_code[range_index] << 8;
1183 }
1184
1185 static unsigned int hw_revision(const struct comedi_device *dev,
1186                                 uint16_t hw_status_bits)
1187 {
1188         const struct pcidas64_board *thisboard = dev->board_ptr;
1189
1190         if (thisboard->layout == LAYOUT_4020)
1191                 return (hw_status_bits >> 13) & 0x7;
1192
1193         return (hw_status_bits >> 12) & 0xf;
1194 }
1195
1196 static void set_dac_range_bits(struct comedi_device *dev,
1197                                uint16_t *bits, unsigned int channel,
1198                                unsigned int range)
1199 {
1200         const struct pcidas64_board *thisboard = dev->board_ptr;
1201         unsigned int code = thisboard->ao_range_code[range];
1202
1203         if (channel > 1)
1204                 dev_err(dev->class_dev, "bug! bad channel?\n");
1205         if (code & ~0x3)
1206                 dev_err(dev->class_dev, "bug! bad range code?\n");
1207
1208         *bits &= ~(0x3 << (2 * channel));
1209         *bits |= code << (2 * channel);
1210 };
1211
1212 static inline int ao_cmd_is_supported(const struct pcidas64_board *board)
1213 {
1214         return board->ao_nchan && board->layout != LAYOUT_4020;
1215 }
1216
1217 static void abort_dma(struct comedi_device *dev, unsigned int channel)
1218 {
1219         struct pcidas64_private *devpriv = dev->private;
1220         unsigned long flags;
1221
1222         /*  spinlock for plx dma control/status reg */
1223         spin_lock_irqsave(&dev->spinlock, flags);
1224
1225         plx9080_abort_dma(devpriv->plx9080_iobase, channel);
1226
1227         spin_unlock_irqrestore(&dev->spinlock, flags);
1228 }
1229
1230 static void disable_plx_interrupts(struct comedi_device *dev)
1231 {
1232         struct pcidas64_private *devpriv = dev->private;
1233
1234         devpriv->plx_intcsr_bits = 0;
1235         writel(devpriv->plx_intcsr_bits,
1236                devpriv->plx9080_iobase + PLX_INTRCS_REG);
1237 }
1238
1239 static void disable_ai_interrupts(struct comedi_device *dev)
1240 {
1241         struct pcidas64_private *devpriv = dev->private;
1242         unsigned long flags;
1243
1244         spin_lock_irqsave(&dev->spinlock, flags);
1245         devpriv->intr_enable_bits &=
1246                 ~EN_ADC_INTR_SRC_BIT & ~EN_ADC_DONE_INTR_BIT &
1247                 ~EN_ADC_ACTIVE_INTR_BIT & ~EN_ADC_STOP_INTR_BIT &
1248                 ~EN_ADC_OVERRUN_BIT & ~ADC_INTR_SRC_MASK;
1249         writew(devpriv->intr_enable_bits,
1250                devpriv->main_iobase + INTR_ENABLE_REG);
1251         spin_unlock_irqrestore(&dev->spinlock, flags);
1252 }
1253
1254 static void enable_ai_interrupts(struct comedi_device *dev,
1255                                  const struct comedi_cmd *cmd)
1256 {
1257         const struct pcidas64_board *thisboard = dev->board_ptr;
1258         struct pcidas64_private *devpriv = dev->private;
1259         uint32_t bits;
1260         unsigned long flags;
1261
1262         bits = EN_ADC_OVERRUN_BIT | EN_ADC_DONE_INTR_BIT |
1263                EN_ADC_ACTIVE_INTR_BIT | EN_ADC_STOP_INTR_BIT;
1264         /*  Use pio transfer and interrupt on end of conversion
1265          *  if CMDF_WAKE_EOS flag is set. */
1266         if (cmd->flags & CMDF_WAKE_EOS) {
1267                 /*  4020 doesn't support pio transfers except for fifo dregs */
1268                 if (thisboard->layout != LAYOUT_4020)
1269                         bits |= ADC_INTR_EOSCAN_BITS | EN_ADC_INTR_SRC_BIT;
1270         }
1271         spin_lock_irqsave(&dev->spinlock, flags);
1272         devpriv->intr_enable_bits |= bits;
1273         writew(devpriv->intr_enable_bits,
1274                devpriv->main_iobase + INTR_ENABLE_REG);
1275         spin_unlock_irqrestore(&dev->spinlock, flags);
1276 }
1277
1278 /* initialize plx9080 chip */
1279 static void init_plx9080(struct comedi_device *dev)
1280 {
1281         const struct pcidas64_board *thisboard = dev->board_ptr;
1282         struct pcidas64_private *devpriv = dev->private;
1283         uint32_t bits;
1284         void __iomem *plx_iobase = devpriv->plx9080_iobase;
1285
1286         devpriv->plx_control_bits =
1287                 readl(devpriv->plx9080_iobase + PLX_CONTROL_REG);
1288
1289 #ifdef __BIG_ENDIAN
1290         bits = BIGEND_DMA0 | BIGEND_DMA1;
1291 #else
1292         bits = 0;
1293 #endif
1294         writel(bits, devpriv->plx9080_iobase + PLX_BIGEND_REG);
1295
1296         disable_plx_interrupts(dev);
1297
1298         abort_dma(dev, 0);
1299         abort_dma(dev, 1);
1300
1301         /*  configure dma0 mode */
1302         bits = 0;
1303         /*  enable ready input, not sure if this is necessary */
1304         bits |= PLX_DMA_EN_READYIN_BIT;
1305         /*  enable bterm, not sure if this is necessary */
1306         bits |= PLX_EN_BTERM_BIT;
1307         /*  enable dma chaining */
1308         bits |= PLX_EN_CHAIN_BIT;
1309         /*  enable interrupt on dma done
1310          *  (probably don't need this, since chain never finishes) */
1311         bits |= PLX_EN_DMA_DONE_INTR_BIT;
1312         /*  don't increment local address during transfers
1313          *  (we are transferring from a fixed fifo register) */
1314         bits |= PLX_LOCAL_ADDR_CONST_BIT;
1315         /*  route dma interrupt to pci bus */
1316         bits |= PLX_DMA_INTR_PCI_BIT;
1317         /*  enable demand mode */
1318         bits |= PLX_DEMAND_MODE_BIT;
1319         /*  enable local burst mode */
1320         bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
1321         /*  4020 uses 32 bit dma */
1322         if (thisboard->layout == LAYOUT_4020)
1323                 bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
1324         else            /*  localspace0 bus is 16 bits wide */
1325                 bits |= PLX_LOCAL_BUS_16_WIDE_BITS;
1326         writel(bits, plx_iobase + PLX_DMA1_MODE_REG);
1327         if (ao_cmd_is_supported(thisboard))
1328                 writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
1329
1330         /*  enable interrupts on plx 9080 */
1331         devpriv->plx_intcsr_bits |=
1332             ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
1333             ICS_DMA0_E | ICS_DMA1_E;
1334         writel(devpriv->plx_intcsr_bits,
1335                devpriv->plx9080_iobase + PLX_INTRCS_REG);
1336 }
1337
1338 static void disable_ai_pacing(struct comedi_device *dev)
1339 {
1340         struct pcidas64_private *devpriv = dev->private;
1341         unsigned long flags;
1342
1343         disable_ai_interrupts(dev);
1344
1345         spin_lock_irqsave(&dev->spinlock, flags);
1346         devpriv->adc_control1_bits &= ~ADC_SW_GATE_BIT;
1347         writew(devpriv->adc_control1_bits,
1348                devpriv->main_iobase + ADC_CONTROL1_REG);
1349         spin_unlock_irqrestore(&dev->spinlock, flags);
1350
1351         /* disable pacing, triggering, etc */
1352         writew(ADC_DMA_DISABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT,
1353                devpriv->main_iobase + ADC_CONTROL0_REG);
1354 }
1355
1356 static int set_ai_fifo_segment_length(struct comedi_device *dev,
1357                                       unsigned int num_entries)
1358 {
1359         const struct pcidas64_board *thisboard = dev->board_ptr;
1360         struct pcidas64_private *devpriv = dev->private;
1361         static const int increment_size = 0x100;
1362         const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1363         unsigned int num_increments;
1364         uint16_t bits;
1365
1366         if (num_entries < increment_size)
1367                 num_entries = increment_size;
1368         if (num_entries > fifo->max_segment_length)
1369                 num_entries = fifo->max_segment_length;
1370
1371         /*  1 == 256 entries, 2 == 512 entries, etc */
1372         num_increments = (num_entries + increment_size / 2) / increment_size;
1373
1374         bits = (~(num_increments - 1)) & fifo->fifo_size_reg_mask;
1375         devpriv->fifo_size_bits &= ~fifo->fifo_size_reg_mask;
1376         devpriv->fifo_size_bits |= bits;
1377         writew(devpriv->fifo_size_bits,
1378                devpriv->main_iobase + FIFO_SIZE_REG);
1379
1380         devpriv->ai_fifo_segment_length = num_increments * increment_size;
1381
1382         return devpriv->ai_fifo_segment_length;
1383 }
1384
1385 /* adjusts the size of hardware fifo (which determines block size for dma xfers) */
1386 static int set_ai_fifo_size(struct comedi_device *dev, unsigned int num_samples)
1387 {
1388         const struct pcidas64_board *thisboard = dev->board_ptr;
1389         unsigned int num_fifo_entries;
1390         int retval;
1391         const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1392
1393         num_fifo_entries = num_samples / fifo->sample_packing_ratio;
1394
1395         retval = set_ai_fifo_segment_length(dev,
1396                                             num_fifo_entries /
1397                                             fifo->num_segments);
1398         if (retval < 0)
1399                 return retval;
1400
1401         num_samples = retval * fifo->num_segments * fifo->sample_packing_ratio;
1402
1403         return num_samples;
1404 }
1405
1406 /* query length of fifo */
1407 static unsigned int ai_fifo_size(struct comedi_device *dev)
1408 {
1409         const struct pcidas64_board *thisboard = dev->board_ptr;
1410         struct pcidas64_private *devpriv = dev->private;
1411
1412         return devpriv->ai_fifo_segment_length *
1413                thisboard->ai_fifo->num_segments *
1414                thisboard->ai_fifo->sample_packing_ratio;
1415 }
1416
1417 static void init_stc_registers(struct comedi_device *dev)
1418 {
1419         const struct pcidas64_board *thisboard = dev->board_ptr;
1420         struct pcidas64_private *devpriv = dev->private;
1421         uint16_t bits;
1422         unsigned long flags;
1423
1424         spin_lock_irqsave(&dev->spinlock, flags);
1425
1426         /*  bit should be set for 6025,
1427          *  although docs say boards with <= 16 chans should be cleared XXX */
1428         if (1)
1429                 devpriv->adc_control1_bits |= ADC_QUEUE_CONFIG_BIT;
1430         writew(devpriv->adc_control1_bits,
1431                devpriv->main_iobase + ADC_CONTROL1_REG);
1432
1433         /*  6402/16 manual says this register must be initialized to 0xff? */
1434         writew(0xff, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1435
1436         bits = SLOW_DAC_BIT | DMA_CH_SELECT_BIT;
1437         if (thisboard->layout == LAYOUT_4020)
1438                 bits |= INTERNAL_CLOCK_4020_BITS;
1439         devpriv->hw_config_bits |= bits;
1440         writew(devpriv->hw_config_bits,
1441                devpriv->main_iobase + HW_CONFIG_REG);
1442
1443         writew(0, devpriv->main_iobase + DAQ_SYNC_REG);
1444         writew(0, devpriv->main_iobase + CALIBRATION_REG);
1445
1446         spin_unlock_irqrestore(&dev->spinlock, flags);
1447
1448         /*  set fifos to maximum size */
1449         devpriv->fifo_size_bits |= DAC_FIFO_BITS;
1450         set_ai_fifo_segment_length(dev,
1451                                    thisboard->ai_fifo->max_segment_length);
1452
1453         devpriv->dac_control1_bits = DAC_OUTPUT_ENABLE_BIT;
1454         devpriv->intr_enable_bits =
1455                 /* EN_DAC_INTR_SRC_BIT | DAC_INTR_QEMPTY_BITS | */
1456                 EN_DAC_DONE_INTR_BIT | EN_DAC_UNDERRUN_BIT;
1457         writew(devpriv->intr_enable_bits,
1458                devpriv->main_iobase + INTR_ENABLE_REG);
1459
1460         disable_ai_pacing(dev);
1461 };
1462
1463 static int alloc_and_init_dma_members(struct comedi_device *dev)
1464 {
1465         const struct pcidas64_board *thisboard = dev->board_ptr;
1466         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1467         struct pcidas64_private *devpriv = dev->private;
1468         int i;
1469
1470         /*  allocate pci dma buffers */
1471         for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
1472                 devpriv->ai_buffer[i] =
1473                         pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
1474                                              &devpriv->ai_buffer_bus_addr[i]);
1475                 if (!devpriv->ai_buffer[i])
1476                         return -ENOMEM;
1477         }
1478         for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1479                 if (ao_cmd_is_supported(thisboard)) {
1480                         devpriv->ao_buffer[i] =
1481                                 pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
1482                                                      &devpriv->
1483                                                       ao_buffer_bus_addr[i]);
1484                         if (!devpriv->ao_buffer[i])
1485                                 return -ENOMEM;
1486                 }
1487         }
1488         /*  allocate dma descriptors */
1489         devpriv->ai_dma_desc =
1490                 pci_alloc_consistent(pcidev, sizeof(struct plx_dma_desc) *
1491                                      ai_dma_ring_count(thisboard),
1492                                      &devpriv->ai_dma_desc_bus_addr);
1493         if (!devpriv->ai_dma_desc)
1494                 return -ENOMEM;
1495
1496         if (ao_cmd_is_supported(thisboard)) {
1497                 devpriv->ao_dma_desc =
1498                         pci_alloc_consistent(pcidev,
1499                                              sizeof(struct plx_dma_desc) *
1500                                              AO_DMA_RING_COUNT,
1501                                              &devpriv->ao_dma_desc_bus_addr);
1502                 if (!devpriv->ao_dma_desc)
1503                         return -ENOMEM;
1504         }
1505         /*  initialize dma descriptors */
1506         for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
1507                 devpriv->ai_dma_desc[i].pci_start_addr =
1508                         cpu_to_le32(devpriv->ai_buffer_bus_addr[i]);
1509                 if (thisboard->layout == LAYOUT_4020)
1510                         devpriv->ai_dma_desc[i].local_start_addr =
1511                                 cpu_to_le32(devpriv->local1_iobase +
1512                                             ADC_FIFO_REG);
1513                 else
1514                         devpriv->ai_dma_desc[i].local_start_addr =
1515                                 cpu_to_le32(devpriv->local0_iobase +
1516                                             ADC_FIFO_REG);
1517                 devpriv->ai_dma_desc[i].transfer_size = cpu_to_le32(0);
1518                 devpriv->ai_dma_desc[i].next =
1519                         cpu_to_le32((devpriv->ai_dma_desc_bus_addr +
1520                                      ((i + 1) % ai_dma_ring_count(thisboard)) *
1521                                      sizeof(devpriv->ai_dma_desc[0])) |
1522                                     PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
1523                                     PLX_XFER_LOCAL_TO_PCI);
1524         }
1525         if (ao_cmd_is_supported(thisboard)) {
1526                 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1527                         devpriv->ao_dma_desc[i].pci_start_addr =
1528                                 cpu_to_le32(devpriv->ao_buffer_bus_addr[i]);
1529                         devpriv->ao_dma_desc[i].local_start_addr =
1530                                 cpu_to_le32(devpriv->local0_iobase +
1531                                             DAC_FIFO_REG);
1532                         devpriv->ao_dma_desc[i].transfer_size = cpu_to_le32(0);
1533                         devpriv->ao_dma_desc[i].next =
1534                                 cpu_to_le32((devpriv->ao_dma_desc_bus_addr +
1535                                              ((i + 1) % (AO_DMA_RING_COUNT)) *
1536                                              sizeof(devpriv->ao_dma_desc[0])) |
1537                                             PLX_DESC_IN_PCI_BIT |
1538                                             PLX_INTR_TERM_COUNT);
1539                 }
1540         }
1541         return 0;
1542 }
1543
1544 static void cb_pcidas64_free_dma(struct comedi_device *dev)
1545 {
1546         const struct pcidas64_board *thisboard = dev->board_ptr;
1547         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1548         struct pcidas64_private *devpriv = dev->private;
1549         int i;
1550
1551         if (!devpriv)
1552                 return;
1553
1554         /* free pci dma buffers */
1555         for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
1556                 if (devpriv->ai_buffer[i])
1557                         pci_free_consistent(pcidev,
1558                                             DMA_BUFFER_SIZE,
1559                                             devpriv->ai_buffer[i],
1560                                             devpriv->ai_buffer_bus_addr[i]);
1561         }
1562         for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1563                 if (devpriv->ao_buffer[i])
1564                         pci_free_consistent(pcidev,
1565                                             DMA_BUFFER_SIZE,
1566                                             devpriv->ao_buffer[i],
1567                                             devpriv->ao_buffer_bus_addr[i]);
1568         }
1569         /* free dma descriptors */
1570         if (devpriv->ai_dma_desc)
1571                 pci_free_consistent(pcidev,
1572                                     sizeof(struct plx_dma_desc) *
1573                                     ai_dma_ring_count(thisboard),
1574                                     devpriv->ai_dma_desc,
1575                                     devpriv->ai_dma_desc_bus_addr);
1576         if (devpriv->ao_dma_desc)
1577                 pci_free_consistent(pcidev,
1578                                     sizeof(struct plx_dma_desc) *
1579                                     AO_DMA_RING_COUNT,
1580                                     devpriv->ao_dma_desc,
1581                                     devpriv->ao_dma_desc_bus_addr);
1582 }
1583
1584 static inline void warn_external_queue(struct comedi_device *dev)
1585 {
1586         dev_err(dev->class_dev,
1587                 "AO command and AI external channel queue cannot be used simultaneously\n");
1588         dev_err(dev->class_dev,
1589                 "Use internal AI channel queue (channels must be consecutive and use same range/aref)\n");
1590 }
1591
1592 /* Their i2c requires a huge delay on setting clock or data high for some reason */
1593 static const int i2c_high_udelay = 1000;
1594 static const int i2c_low_udelay = 10;
1595
1596 /* set i2c data line high or low */
1597 static void i2c_set_sda(struct comedi_device *dev, int state)
1598 {
1599         struct pcidas64_private *devpriv = dev->private;
1600         static const int data_bit = CTL_EE_W;
1601         void __iomem *plx_control_addr = devpriv->plx9080_iobase +
1602                                          PLX_CONTROL_REG;
1603
1604         if (state) {
1605                 /*  set data line high */
1606                 devpriv->plx_control_bits &= ~data_bit;
1607                 writel(devpriv->plx_control_bits, plx_control_addr);
1608                 udelay(i2c_high_udelay);
1609         } else {                /*  set data line low */
1610
1611                 devpriv->plx_control_bits |= data_bit;
1612                 writel(devpriv->plx_control_bits, plx_control_addr);
1613                 udelay(i2c_low_udelay);
1614         }
1615 }
1616
1617 /* set i2c clock line high or low */
1618 static void i2c_set_scl(struct comedi_device *dev, int state)
1619 {
1620         struct pcidas64_private *devpriv = dev->private;
1621         static const int clock_bit = CTL_USERO;
1622         void __iomem *plx_control_addr = devpriv->plx9080_iobase +
1623                                          PLX_CONTROL_REG;
1624
1625         if (state) {
1626                 /*  set clock line high */
1627                 devpriv->plx_control_bits &= ~clock_bit;
1628                 writel(devpriv->plx_control_bits, plx_control_addr);
1629                 udelay(i2c_high_udelay);
1630         } else {                /*  set clock line low */
1631
1632                 devpriv->plx_control_bits |= clock_bit;
1633                 writel(devpriv->plx_control_bits, plx_control_addr);
1634                 udelay(i2c_low_udelay);
1635         }
1636 }
1637
1638 static void i2c_write_byte(struct comedi_device *dev, uint8_t byte)
1639 {
1640         uint8_t bit;
1641         unsigned int num_bits = 8;
1642
1643         for (bit = 1 << (num_bits - 1); bit; bit >>= 1) {
1644                 i2c_set_scl(dev, 0);
1645                 if ((byte & bit))
1646                         i2c_set_sda(dev, 1);
1647                 else
1648                         i2c_set_sda(dev, 0);
1649                 i2c_set_scl(dev, 1);
1650         }
1651 }
1652
1653 /* we can't really read the lines, so fake it */
1654 static int i2c_read_ack(struct comedi_device *dev)
1655 {
1656         i2c_set_scl(dev, 0);
1657         i2c_set_sda(dev, 1);
1658         i2c_set_scl(dev, 1);
1659
1660         return 0;               /*  return fake acknowledge bit */
1661 }
1662
1663 /* send start bit */
1664 static void i2c_start(struct comedi_device *dev)
1665 {
1666         i2c_set_scl(dev, 1);
1667         i2c_set_sda(dev, 1);
1668         i2c_set_sda(dev, 0);
1669 }
1670
1671 /* send stop bit */
1672 static void i2c_stop(struct comedi_device *dev)
1673 {
1674         i2c_set_scl(dev, 0);
1675         i2c_set_sda(dev, 0);
1676         i2c_set_scl(dev, 1);
1677         i2c_set_sda(dev, 1);
1678 }
1679
1680 static void i2c_write(struct comedi_device *dev, unsigned int address,
1681                       const uint8_t *data, unsigned int length)
1682 {
1683         struct pcidas64_private *devpriv = dev->private;
1684         unsigned int i;
1685         uint8_t bitstream;
1686         static const int read_bit = 0x1;
1687
1688         /* XXX need mutex to prevent simultaneous attempts to access
1689          * eeprom and i2c bus */
1690
1691         /*  make sure we dont send anything to eeprom */
1692         devpriv->plx_control_bits &= ~CTL_EE_CS;
1693
1694         i2c_stop(dev);
1695         i2c_start(dev);
1696
1697         /*  send address and write bit */
1698         bitstream = (address << 1) & ~read_bit;
1699         i2c_write_byte(dev, bitstream);
1700
1701         /*  get acknowledge */
1702         if (i2c_read_ack(dev) != 0) {
1703                 dev_err(dev->class_dev, "failed: no acknowledge\n");
1704                 i2c_stop(dev);
1705                 return;
1706         }
1707         /*  write data bytes */
1708         for (i = 0; i < length; i++) {
1709                 i2c_write_byte(dev, data[i]);
1710                 if (i2c_read_ack(dev) != 0) {
1711                         dev_err(dev->class_dev, "failed: no acknowledge\n");
1712                         i2c_stop(dev);
1713                         return;
1714                 }
1715         }
1716         i2c_stop(dev);
1717 }
1718
1719 static int cb_pcidas64_ai_eoc(struct comedi_device *dev,
1720                               struct comedi_subdevice *s,
1721                               struct comedi_insn *insn,
1722                               unsigned long context)
1723 {
1724         const struct pcidas64_board *thisboard = dev->board_ptr;
1725         struct pcidas64_private *devpriv = dev->private;
1726         unsigned int status;
1727
1728         status = readw(devpriv->main_iobase + HW_STATUS_REG);
1729         if (thisboard->layout == LAYOUT_4020) {
1730                 status = readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG);
1731                 if (status)
1732                         return 0;
1733         } else {
1734                 if (pipe_full_bits(status))
1735                         return 0;
1736         }
1737         return -EBUSY;
1738 }
1739
1740 static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1741                     struct comedi_insn *insn, unsigned int *data)
1742 {
1743         const struct pcidas64_board *thisboard = dev->board_ptr;
1744         struct pcidas64_private *devpriv = dev->private;
1745         unsigned int bits = 0, n;
1746         unsigned int channel, range, aref;
1747         unsigned long flags;
1748         int ret;
1749
1750         channel = CR_CHAN(insn->chanspec);
1751         range = CR_RANGE(insn->chanspec);
1752         aref = CR_AREF(insn->chanspec);
1753
1754         /*  disable card's analog input interrupt sources and pacing */
1755         /*  4020 generates dac done interrupts even though they are disabled */
1756         disable_ai_pacing(dev);
1757
1758         spin_lock_irqsave(&dev->spinlock, flags);
1759         if (insn->chanspec & CR_ALT_FILTER)
1760                 devpriv->adc_control1_bits |= ADC_DITHER_BIT;
1761         else
1762                 devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
1763         writew(devpriv->adc_control1_bits,
1764                devpriv->main_iobase + ADC_CONTROL1_REG);
1765         spin_unlock_irqrestore(&dev->spinlock, flags);
1766
1767         if (thisboard->layout != LAYOUT_4020) {
1768                 /*  use internal queue */
1769                 devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
1770                 writew(devpriv->hw_config_bits,
1771                        devpriv->main_iobase + HW_CONFIG_REG);
1772
1773                 /*  ALT_SOURCE is internal calibration reference */
1774                 if (insn->chanspec & CR_ALT_SOURCE) {
1775                         unsigned int cal_en_bit;
1776
1777                         if (thisboard->layout == LAYOUT_60XX)
1778                                 cal_en_bit = CAL_EN_60XX_BIT;
1779                         else
1780                                 cal_en_bit = CAL_EN_64XX_BIT;
1781                         /*  select internal reference source to connect
1782                          *  to channel 0 */
1783                         writew(cal_en_bit |
1784                                adc_src_bits(devpriv->calibration_source),
1785                                devpriv->main_iobase + CALIBRATION_REG);
1786                 } else {
1787                         /*  make sure internal calibration source
1788                          *  is turned off */
1789                         writew(0, devpriv->main_iobase + CALIBRATION_REG);
1790                 }
1791                 /*  load internal queue */
1792                 bits = 0;
1793                 /*  set gain */
1794                 bits |= ai_range_bits_6xxx(dev, CR_RANGE(insn->chanspec));
1795                 /*  set single-ended / differential */
1796                 bits |= se_diff_bit_6xxx(dev, aref == AREF_DIFF);
1797                 if (aref == AREF_COMMON)
1798                         bits |= ADC_COMMON_BIT;
1799                 bits |= adc_chan_bits(channel);
1800                 /*  set stop channel */
1801                 writew(adc_chan_bits(channel),
1802                        devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
1803                 /*  set start channel, and rest of settings */
1804                 writew(bits, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
1805         } else {
1806                 uint8_t old_cal_range_bits = devpriv->i2c_cal_range_bits;
1807
1808                 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
1809                 if (insn->chanspec & CR_ALT_SOURCE) {
1810                         devpriv->i2c_cal_range_bits |=
1811                                 adc_src_4020_bits(devpriv->calibration_source);
1812                 } else {        /* select BNC inputs */
1813                         devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
1814                 }
1815                 /*  select range */
1816                 if (range == 0)
1817                         devpriv->i2c_cal_range_bits |= attenuate_bit(channel);
1818                 else
1819                         devpriv->i2c_cal_range_bits &= ~attenuate_bit(channel);
1820                 /*  update calibration/range i2c register only if necessary,
1821                  *  as it is very slow */
1822                 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
1823                         uint8_t i2c_data = devpriv->i2c_cal_range_bits;
1824
1825                         i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
1826                                   sizeof(i2c_data));
1827                 }
1828
1829                 /* 4020 manual asks that sample interval register to be set
1830                  * before writing to convert register.
1831                  * Using somewhat arbitrary setting of 4 master clock ticks
1832                  * = 0.1 usec */
1833                 writew(0, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1834                 writew(2, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
1835         }
1836
1837         for (n = 0; n < insn->n; n++) {
1838                 /*  clear adc buffer (inside loop for 4020 sake) */
1839                 writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
1840
1841                 /* trigger conversion, bits sent only matter for 4020 */
1842                 writew(adc_convert_chan_4020_bits(CR_CHAN(insn->chanspec)),
1843                        devpriv->main_iobase + ADC_CONVERT_REG);
1844
1845                 /*  wait for data */
1846                 ret = comedi_timeout(dev, s, insn, cb_pcidas64_ai_eoc, 0);
1847                 if (ret)
1848                         return ret;
1849
1850                 if (thisboard->layout == LAYOUT_4020)
1851                         data[n] = readl(dev->mmio + ADC_FIFO_REG) & 0xffff;
1852                 else
1853                         data[n] = readw(devpriv->main_iobase + PIPE1_READ_REG);
1854         }
1855
1856         return n;
1857 }
1858
1859 static int ai_config_calibration_source(struct comedi_device *dev,
1860                                         unsigned int *data)
1861 {
1862         const struct pcidas64_board *thisboard = dev->board_ptr;
1863         struct pcidas64_private *devpriv = dev->private;
1864         unsigned int source = data[1];
1865         int num_calibration_sources;
1866
1867         if (thisboard->layout == LAYOUT_60XX)
1868                 num_calibration_sources = 16;
1869         else
1870                 num_calibration_sources = 8;
1871         if (source >= num_calibration_sources) {
1872                 dev_dbg(dev->class_dev, "invalid calibration source: %i\n",
1873                         source);
1874                 return -EINVAL;
1875         }
1876
1877         devpriv->calibration_source = source;
1878
1879         return 2;
1880 }
1881
1882 static int ai_config_block_size(struct comedi_device *dev, unsigned int *data)
1883 {
1884         const struct pcidas64_board *thisboard = dev->board_ptr;
1885         int fifo_size;
1886         const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1887         unsigned int block_size, requested_block_size;
1888         int retval;
1889
1890         requested_block_size = data[1];
1891
1892         if (requested_block_size) {
1893                 fifo_size = requested_block_size * fifo->num_segments /
1894                             bytes_in_sample;
1895
1896                 retval = set_ai_fifo_size(dev, fifo_size);
1897                 if (retval < 0)
1898                         return retval;
1899         }
1900
1901         block_size = ai_fifo_size(dev) / fifo->num_segments * bytes_in_sample;
1902
1903         data[1] = block_size;
1904
1905         return 2;
1906 }
1907
1908 static int ai_config_master_clock_4020(struct comedi_device *dev,
1909                                        unsigned int *data)
1910 {
1911         struct pcidas64_private *devpriv = dev->private;
1912         unsigned int divisor = data[4];
1913         int retval = 0;
1914
1915         if (divisor < 2) {
1916                 divisor = 2;
1917                 retval = -EAGAIN;
1918         }
1919
1920         switch (data[1]) {
1921         case COMEDI_EV_SCAN_BEGIN:
1922                 devpriv->ext_clock.divisor = divisor;
1923                 devpriv->ext_clock.chanspec = data[2];
1924                 break;
1925         default:
1926                 return -EINVAL;
1927         }
1928
1929         data[4] = divisor;
1930
1931         return retval ? retval : 5;
1932 }
1933
1934 /* XXX could add support for 60xx series */
1935 static int ai_config_master_clock(struct comedi_device *dev, unsigned int *data)
1936 {
1937         const struct pcidas64_board *thisboard = dev->board_ptr;
1938
1939         switch (thisboard->layout) {
1940         case LAYOUT_4020:
1941                 return ai_config_master_clock_4020(dev, data);
1942         default:
1943                 return -EINVAL;
1944         }
1945
1946         return -EINVAL;
1947 }
1948
1949 static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s,
1950                           struct comedi_insn *insn, unsigned int *data)
1951 {
1952         int id = data[0];
1953
1954         switch (id) {
1955         case INSN_CONFIG_ALT_SOURCE:
1956                 return ai_config_calibration_source(dev, data);
1957         case INSN_CONFIG_BLOCK_SIZE:
1958                 return ai_config_block_size(dev, data);
1959         case INSN_CONFIG_TIMER_1:
1960                 return ai_config_master_clock(dev, data);
1961         default:
1962                 return -EINVAL;
1963         }
1964         return -EINVAL;
1965 }
1966
1967 /* Gets nearest achievable timing given master clock speed, does not
1968  * take into account possible minimum/maximum divisor values.  Used
1969  * by other timing checking functions. */
1970 static unsigned int get_divisor(unsigned int ns, unsigned int flags)
1971 {
1972         unsigned int divisor;
1973
1974         switch (flags & CMDF_ROUND_MASK) {
1975         case CMDF_ROUND_UP:
1976                 divisor = (ns + TIMER_BASE - 1) / TIMER_BASE;
1977                 break;
1978         case CMDF_ROUND_DOWN:
1979                 divisor = ns / TIMER_BASE;
1980                 break;
1981         case CMDF_ROUND_NEAREST:
1982         default:
1983                 divisor = (ns + TIMER_BASE / 2) / TIMER_BASE;
1984                 break;
1985         }
1986         return divisor;
1987 }
1988
1989 /* utility function that rounds desired timing to an achievable time, and
1990  * sets cmd members appropriately.
1991  * adc paces conversions from master clock by dividing by (x + 3) where x is 24 bit number
1992  */
1993 static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd)
1994 {
1995         const struct pcidas64_board *thisboard = dev->board_ptr;
1996         unsigned long long convert_divisor = 0;
1997         unsigned int scan_divisor;
1998         static const int min_convert_divisor = 3;
1999         static const int max_convert_divisor =
2000                 max_counter_value + min_convert_divisor;
2001         static const int min_scan_divisor_4020 = 2;
2002         unsigned long long max_scan_divisor, min_scan_divisor;
2003
2004         if (cmd->convert_src == TRIG_TIMER) {
2005                 if (thisboard->layout == LAYOUT_4020) {
2006                         cmd->convert_arg = 0;
2007                 } else {
2008                         convert_divisor = get_divisor(cmd->convert_arg,
2009                                                       cmd->flags);
2010                         if (convert_divisor > max_convert_divisor)
2011                                 convert_divisor = max_convert_divisor;
2012                         if (convert_divisor < min_convert_divisor)
2013                                 convert_divisor = min_convert_divisor;
2014                         cmd->convert_arg = convert_divisor * TIMER_BASE;
2015                 }
2016         } else if (cmd->convert_src == TRIG_NOW) {
2017                 cmd->convert_arg = 0;
2018         }
2019
2020         if (cmd->scan_begin_src == TRIG_TIMER) {
2021                 scan_divisor = get_divisor(cmd->scan_begin_arg, cmd->flags);
2022                 if (cmd->convert_src == TRIG_TIMER) {
2023                         min_scan_divisor = convert_divisor * cmd->chanlist_len;
2024                         max_scan_divisor =
2025                                 (convert_divisor * cmd->chanlist_len - 1) +
2026                                 max_counter_value;
2027                 } else {
2028                         min_scan_divisor = min_scan_divisor_4020;
2029                         max_scan_divisor = max_counter_value + min_scan_divisor;
2030                 }
2031                 if (scan_divisor > max_scan_divisor)
2032                         scan_divisor = max_scan_divisor;
2033                 if (scan_divisor < min_scan_divisor)
2034                         scan_divisor = min_scan_divisor;
2035                 cmd->scan_begin_arg = scan_divisor * TIMER_BASE;
2036         }
2037 }
2038
2039 static int cb_pcidas64_ai_check_chanlist(struct comedi_device *dev,
2040                                          struct comedi_subdevice *s,
2041                                          struct comedi_cmd *cmd)
2042 {
2043         const struct pcidas64_board *board = dev->board_ptr;
2044         unsigned int aref0 = CR_AREF(cmd->chanlist[0]);
2045         int i;
2046
2047         for (i = 1; i < cmd->chanlist_len; i++) {
2048                 unsigned int aref = CR_AREF(cmd->chanlist[i]);
2049
2050                 if (aref != aref0) {
2051                         dev_dbg(dev->class_dev,
2052                                 "all elements in chanlist must use the same analog reference\n");
2053                         return -EINVAL;
2054                 }
2055         }
2056
2057         if (board->layout == LAYOUT_4020) {
2058                 unsigned int chan0 = CR_CHAN(cmd->chanlist[0]);
2059
2060                 for (i = 1; i < cmd->chanlist_len; i++) {
2061                         unsigned int chan = CR_CHAN(cmd->chanlist[i]);
2062
2063                         if (chan != (chan0 + i)) {
2064                                 dev_dbg(dev->class_dev,
2065                                         "chanlist must use consecutive channels\n");
2066                                 return -EINVAL;
2067                         }
2068                 }
2069                 if (cmd->chanlist_len == 3) {
2070                         dev_dbg(dev->class_dev,
2071                                 "chanlist cannot be 3 channels long, use 1, 2, or 4 channels\n");
2072                         return -EINVAL;
2073                 }
2074         }
2075
2076         return 0;
2077 }
2078
2079 static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2080                       struct comedi_cmd *cmd)
2081 {
2082         const struct pcidas64_board *thisboard = dev->board_ptr;
2083         int err = 0;
2084         unsigned int tmp_arg, tmp_arg2;
2085         unsigned int triggers;
2086
2087         /* Step 1 : check if triggers are trivially valid */
2088
2089         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
2090
2091         triggers = TRIG_TIMER;
2092         if (thisboard->layout == LAYOUT_4020)
2093                 triggers |= TRIG_OTHER;
2094         else
2095                 triggers |= TRIG_FOLLOW;
2096         err |= cfc_check_trigger_src(&cmd->scan_begin_src, triggers);
2097
2098         triggers = TRIG_TIMER;
2099         if (thisboard->layout == LAYOUT_4020)
2100                 triggers |= TRIG_NOW;
2101         else
2102                 triggers |= TRIG_EXT;
2103         err |= cfc_check_trigger_src(&cmd->convert_src, triggers);
2104         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2105         err |= cfc_check_trigger_src(&cmd->stop_src,
2106                                      TRIG_COUNT | TRIG_EXT | TRIG_NONE);
2107
2108         if (err)
2109                 return 1;
2110
2111         /* Step 2a : make sure trigger sources are unique */
2112
2113         err |= cfc_check_trigger_is_unique(cmd->start_src);
2114         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2115         err |= cfc_check_trigger_is_unique(cmd->convert_src);
2116         err |= cfc_check_trigger_is_unique(cmd->stop_src);
2117
2118         /* Step 2b : and mutually compatible */
2119
2120         if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
2121                 err |= -EINVAL;
2122
2123         if (err)
2124                 return 2;
2125
2126         /* Step 3: check if arguments are trivially valid */
2127
2128         switch (cmd->start_src) {
2129         case TRIG_NOW:
2130                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
2131                 break;
2132         case TRIG_EXT:
2133                 /*
2134                  * start_arg is the CR_CHAN | CR_INVERT of the
2135                  * external trigger.
2136                  */
2137                 break;
2138         }
2139
2140         if (cmd->convert_src == TRIG_TIMER) {
2141                 if (thisboard->layout == LAYOUT_4020) {
2142                         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2143                 } else {
2144                         err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
2145                                                          thisboard->ai_speed);
2146                         /* if scans are timed faster than conversion rate allows */
2147                         if (cmd->scan_begin_src == TRIG_TIMER)
2148                                 err |= cfc_check_trigger_arg_min(
2149                                                 &cmd->scan_begin_arg,
2150                                                 cmd->convert_arg *
2151                                                 cmd->chanlist_len);
2152                 }
2153         }
2154
2155         err |= cfc_check_trigger_arg_min(&cmd->chanlist_len, 1);
2156         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
2157
2158         switch (cmd->stop_src) {
2159         case TRIG_EXT:
2160                 break;
2161         case TRIG_COUNT:
2162                 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
2163                 break;
2164         case TRIG_NONE:
2165                 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
2166                 break;
2167         default:
2168                 break;
2169         }
2170
2171         if (err)
2172                 return 3;
2173
2174         /* step 4: fix up any arguments */
2175
2176         if (cmd->convert_src == TRIG_TIMER) {
2177                 tmp_arg = cmd->convert_arg;
2178                 tmp_arg2 = cmd->scan_begin_arg;
2179                 check_adc_timing(dev, cmd);
2180                 if (tmp_arg != cmd->convert_arg)
2181                         err++;
2182                 if (tmp_arg2 != cmd->scan_begin_arg)
2183                         err++;
2184         }
2185
2186         if (err)
2187                 return 4;
2188
2189         /* Step 5: check channel list if it exists */
2190         if (cmd->chanlist && cmd->chanlist_len > 0)
2191                 err |= cb_pcidas64_ai_check_chanlist(dev, s, cmd);
2192
2193         if (err)
2194                 return 5;
2195
2196         return 0;
2197 }
2198
2199 static int use_hw_sample_counter(struct comedi_cmd *cmd)
2200 {
2201 /* disable for now until I work out a race */
2202         return 0;
2203
2204         if (cmd->stop_src == TRIG_COUNT && cmd->stop_arg <= max_counter_value)
2205                 return 1;
2206
2207         return 0;
2208 }
2209
2210 static void setup_sample_counters(struct comedi_device *dev,
2211                                   struct comedi_cmd *cmd)
2212 {
2213         struct pcidas64_private *devpriv = dev->private;
2214
2215         /*  load hardware conversion counter */
2216         if (use_hw_sample_counter(cmd)) {
2217                 writew(cmd->stop_arg & 0xffff,
2218                        devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2219                 writew((cmd->stop_arg >> 16) & 0xff,
2220                        devpriv->main_iobase + ADC_COUNT_UPPER_REG);
2221         } else {
2222                 writew(1, devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2223         }
2224 }
2225
2226 static inline unsigned int dma_transfer_size(struct comedi_device *dev)
2227 {
2228         const struct pcidas64_board *thisboard = dev->board_ptr;
2229         struct pcidas64_private *devpriv = dev->private;
2230         unsigned int num_samples;
2231
2232         num_samples = devpriv->ai_fifo_segment_length *
2233                       thisboard->ai_fifo->sample_packing_ratio;
2234         if (num_samples > DMA_BUFFER_SIZE / sizeof(uint16_t))
2235                 num_samples = DMA_BUFFER_SIZE / sizeof(uint16_t);
2236
2237         return num_samples;
2238 }
2239
2240 static uint32_t ai_convert_counter_6xxx(const struct comedi_device *dev,
2241                                         const struct comedi_cmd *cmd)
2242 {
2243         /*  supposed to load counter with desired divisor minus 3 */
2244         return cmd->convert_arg / TIMER_BASE - 3;
2245 }
2246
2247 static uint32_t ai_scan_counter_6xxx(struct comedi_device *dev,
2248                                      struct comedi_cmd *cmd)
2249 {
2250         uint32_t count;
2251
2252         /*  figure out how long we need to delay at end of scan */
2253         switch (cmd->scan_begin_src) {
2254         case TRIG_TIMER:
2255                 count = (cmd->scan_begin_arg -
2256                          (cmd->convert_arg * (cmd->chanlist_len - 1))) /
2257                         TIMER_BASE;
2258                 break;
2259         case TRIG_FOLLOW:
2260                 count = cmd->convert_arg / TIMER_BASE;
2261                 break;
2262         default:
2263                 return 0;
2264         }
2265         return count - 3;
2266 }
2267
2268 static uint32_t ai_convert_counter_4020(struct comedi_device *dev,
2269                                         struct comedi_cmd *cmd)
2270 {
2271         struct pcidas64_private *devpriv = dev->private;
2272         unsigned int divisor;
2273
2274         switch (cmd->scan_begin_src) {
2275         case TRIG_TIMER:
2276                 divisor = cmd->scan_begin_arg / TIMER_BASE;
2277                 break;
2278         case TRIG_OTHER:
2279                 divisor = devpriv->ext_clock.divisor;
2280                 break;
2281         default:                /*  should never happen */
2282                 dev_err(dev->class_dev, "bug! failed to set ai pacing!\n");
2283                 divisor = 1000;
2284                 break;
2285         }
2286
2287         /*  supposed to load counter with desired divisor minus 2 for 4020 */
2288         return divisor - 2;
2289 }
2290
2291 static void select_master_clock_4020(struct comedi_device *dev,
2292                                      const struct comedi_cmd *cmd)
2293 {
2294         struct pcidas64_private *devpriv = dev->private;
2295
2296         /*  select internal/external master clock */
2297         devpriv->hw_config_bits &= ~MASTER_CLOCK_4020_MASK;
2298         if (cmd->scan_begin_src == TRIG_OTHER) {
2299                 int chanspec = devpriv->ext_clock.chanspec;
2300
2301                 if (CR_CHAN(chanspec))
2302                         devpriv->hw_config_bits |= BNC_CLOCK_4020_BITS;
2303                 else
2304                         devpriv->hw_config_bits |= EXT_CLOCK_4020_BITS;
2305         } else {
2306                 devpriv->hw_config_bits |= INTERNAL_CLOCK_4020_BITS;
2307         }
2308         writew(devpriv->hw_config_bits,
2309                devpriv->main_iobase + HW_CONFIG_REG);
2310 }
2311
2312 static void select_master_clock(struct comedi_device *dev,
2313                                 const struct comedi_cmd *cmd)
2314 {
2315         const struct pcidas64_board *thisboard = dev->board_ptr;
2316
2317         switch (thisboard->layout) {
2318         case LAYOUT_4020:
2319                 select_master_clock_4020(dev, cmd);
2320                 break;
2321         default:
2322                 break;
2323         }
2324 }
2325
2326 static inline void dma_start_sync(struct comedi_device *dev,
2327                                   unsigned int channel)
2328 {
2329         struct pcidas64_private *devpriv = dev->private;
2330         unsigned long flags;
2331
2332         /*  spinlock for plx dma control/status reg */
2333         spin_lock_irqsave(&dev->spinlock, flags);
2334         if (channel)
2335                 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2336                        PLX_CLEAR_DMA_INTR_BIT,
2337                        devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2338         else
2339                 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2340                        PLX_CLEAR_DMA_INTR_BIT,
2341                        devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2342         spin_unlock_irqrestore(&dev->spinlock, flags);
2343 }
2344
2345 static void set_ai_pacing(struct comedi_device *dev, struct comedi_cmd *cmd)
2346 {
2347         const struct pcidas64_board *thisboard = dev->board_ptr;
2348         struct pcidas64_private *devpriv = dev->private;
2349         uint32_t convert_counter = 0, scan_counter = 0;
2350
2351         check_adc_timing(dev, cmd);
2352
2353         select_master_clock(dev, cmd);
2354
2355         if (thisboard->layout == LAYOUT_4020) {
2356                 convert_counter = ai_convert_counter_4020(dev, cmd);
2357         } else {
2358                 convert_counter = ai_convert_counter_6xxx(dev, cmd);
2359                 scan_counter = ai_scan_counter_6xxx(dev, cmd);
2360         }
2361
2362         /*  load lower 16 bits of convert interval */
2363         writew(convert_counter & 0xffff,
2364                devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
2365         /*  load upper 8 bits of convert interval */
2366         writew((convert_counter >> 16) & 0xff,
2367                devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
2368         /*  load lower 16 bits of scan delay */
2369         writew(scan_counter & 0xffff,
2370                devpriv->main_iobase + ADC_DELAY_INTERVAL_LOWER_REG);
2371         /*  load upper 8 bits of scan delay */
2372         writew((scan_counter >> 16) & 0xff,
2373                devpriv->main_iobase + ADC_DELAY_INTERVAL_UPPER_REG);
2374 }
2375
2376 static int use_internal_queue_6xxx(const struct comedi_cmd *cmd)
2377 {
2378         int i;
2379
2380         for (i = 0; i + 1 < cmd->chanlist_len; i++) {
2381                 if (CR_CHAN(cmd->chanlist[i + 1]) !=
2382                     CR_CHAN(cmd->chanlist[i]) + 1)
2383                         return 0;
2384                 if (CR_RANGE(cmd->chanlist[i + 1]) !=
2385                     CR_RANGE(cmd->chanlist[i]))
2386                         return 0;
2387                 if (CR_AREF(cmd->chanlist[i + 1]) != CR_AREF(cmd->chanlist[i]))
2388                         return 0;
2389         }
2390         return 1;
2391 }
2392
2393 static int setup_channel_queue(struct comedi_device *dev,
2394                                const struct comedi_cmd *cmd)
2395 {
2396         const struct pcidas64_board *thisboard = dev->board_ptr;
2397         struct pcidas64_private *devpriv = dev->private;
2398         unsigned short bits;
2399         int i;
2400
2401         if (thisboard->layout != LAYOUT_4020) {
2402                 if (use_internal_queue_6xxx(cmd)) {
2403                         devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
2404                         writew(devpriv->hw_config_bits,
2405                                devpriv->main_iobase + HW_CONFIG_REG);
2406                         bits = 0;
2407                         /*  set channel */
2408                         bits |= adc_chan_bits(CR_CHAN(cmd->chanlist[0]));
2409                         /*  set gain */
2410                         bits |= ai_range_bits_6xxx(dev,
2411                                                    CR_RANGE(cmd->chanlist[0]));
2412                         /*  set single-ended / differential */
2413                         bits |= se_diff_bit_6xxx(dev,
2414                                                  CR_AREF(cmd->chanlist[0]) ==
2415                                                  AREF_DIFF);
2416                         if (CR_AREF(cmd->chanlist[0]) == AREF_COMMON)
2417                                 bits |= ADC_COMMON_BIT;
2418                         /*  set stop channel */
2419                         writew(adc_chan_bits
2420                                (CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1])),
2421                                devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
2422                         /*  set start channel, and rest of settings */
2423                         writew(bits,
2424                                devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2425                 } else {
2426                         /*  use external queue */
2427                         if (dev->write_subdev && dev->write_subdev->busy) {
2428                                 warn_external_queue(dev);
2429                                 return -EBUSY;
2430                         }
2431                         devpriv->hw_config_bits |= EXT_QUEUE_BIT;
2432                         writew(devpriv->hw_config_bits,
2433                                devpriv->main_iobase + HW_CONFIG_REG);
2434                         /*  clear DAC buffer to prevent weird interactions */
2435                         writew(0,
2436                                devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
2437                         /*  clear queue pointer */
2438                         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2439                         /*  load external queue */
2440                         for (i = 0; i < cmd->chanlist_len; i++) {
2441                                 bits = 0;
2442                                 /*  set channel */
2443                                 bits |= adc_chan_bits(CR_CHAN(cmd->
2444                                                               chanlist[i]));
2445                                 /*  set gain */
2446                                 bits |= ai_range_bits_6xxx(dev,
2447                                                            CR_RANGE(cmd->
2448                                                                     chanlist
2449                                                                     [i]));
2450                                 /*  set single-ended / differential */
2451                                 bits |= se_diff_bit_6xxx(dev,
2452                                                          CR_AREF(cmd->
2453                                                                  chanlist[i]) ==
2454                                                          AREF_DIFF);
2455                                 if (CR_AREF(cmd->chanlist[i]) == AREF_COMMON)
2456                                         bits |= ADC_COMMON_BIT;
2457                                 /*  mark end of queue */
2458                                 if (i == cmd->chanlist_len - 1)
2459                                         bits |= QUEUE_EOSCAN_BIT |
2460                                                 QUEUE_EOSEQ_BIT;
2461                                 writew(bits,
2462                                        devpriv->main_iobase +
2463                                        ADC_QUEUE_FIFO_REG);
2464                         }
2465                         /* doing a queue clear is not specified in board docs,
2466                          * but required for reliable operation */
2467                         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2468                         /*  prime queue holding register */
2469                         writew(0, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2470                 }
2471         } else {
2472                 unsigned short old_cal_range_bits = devpriv->i2c_cal_range_bits;
2473
2474                 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
2475                 /* select BNC inputs */
2476                 devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
2477                 /*  select ranges */
2478                 for (i = 0; i < cmd->chanlist_len; i++) {
2479                         unsigned int channel = CR_CHAN(cmd->chanlist[i]);
2480                         unsigned int range = CR_RANGE(cmd->chanlist[i]);
2481
2482                         if (range == 0)
2483                                 devpriv->i2c_cal_range_bits |=
2484                                         attenuate_bit(channel);
2485                         else
2486                                 devpriv->i2c_cal_range_bits &=
2487                                         ~attenuate_bit(channel);
2488                 }
2489                 /*  update calibration/range i2c register only if necessary,
2490                  *  as it is very slow */
2491                 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
2492                         uint8_t i2c_data = devpriv->i2c_cal_range_bits;
2493
2494                         i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
2495                                   sizeof(i2c_data));
2496                 }
2497         }
2498         return 0;
2499 }
2500
2501 static inline void load_first_dma_descriptor(struct comedi_device *dev,
2502                                              unsigned int dma_channel,
2503                                              unsigned int descriptor_bits)
2504 {
2505         struct pcidas64_private *devpriv = dev->private;
2506
2507         /* The transfer size, pci address, and local address registers
2508          * are supposedly unused during chained dma,
2509          * but I have found that left over values from last operation
2510          * occasionally cause problems with transfer of first dma
2511          * block.  Initializing them to zero seems to fix the problem. */
2512         if (dma_channel) {
2513                 writel(0,
2514                        devpriv->plx9080_iobase + PLX_DMA1_TRANSFER_SIZE_REG);
2515                 writel(0, devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG);
2516                 writel(0,
2517                        devpriv->plx9080_iobase + PLX_DMA1_LOCAL_ADDRESS_REG);
2518                 writel(descriptor_bits,
2519                        devpriv->plx9080_iobase + PLX_DMA1_DESCRIPTOR_REG);
2520         } else {
2521                 writel(0,
2522                        devpriv->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG);
2523                 writel(0, devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
2524                 writel(0,
2525                        devpriv->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG);
2526                 writel(descriptor_bits,
2527                        devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
2528         }
2529 }
2530
2531 static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2532 {
2533         const struct pcidas64_board *thisboard = dev->board_ptr;
2534         struct pcidas64_private *devpriv = dev->private;
2535         struct comedi_async *async = s->async;
2536         struct comedi_cmd *cmd = &async->cmd;
2537         uint32_t bits;
2538         unsigned int i;
2539         unsigned long flags;
2540         int retval;
2541
2542         disable_ai_pacing(dev);
2543         abort_dma(dev, 1);
2544
2545         retval = setup_channel_queue(dev, cmd);
2546         if (retval < 0)
2547                 return retval;
2548
2549         /*  make sure internal calibration source is turned off */
2550         writew(0, devpriv->main_iobase + CALIBRATION_REG);
2551
2552         set_ai_pacing(dev, cmd);
2553
2554         setup_sample_counters(dev, cmd);
2555
2556         enable_ai_interrupts(dev, cmd);
2557
2558         spin_lock_irqsave(&dev->spinlock, flags);
2559         /* set mode, allow conversions through software gate */
2560         devpriv->adc_control1_bits |= ADC_SW_GATE_BIT;
2561         devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
2562         if (thisboard->layout != LAYOUT_4020) {
2563                 devpriv->adc_control1_bits &= ~ADC_MODE_MASK;
2564                 if (cmd->convert_src == TRIG_EXT)
2565                         /*  good old mode 13 */
2566                         devpriv->adc_control1_bits |= adc_mode_bits(13);
2567                 else
2568                         /*  mode 8.  What else could you need? */
2569                         devpriv->adc_control1_bits |= adc_mode_bits(8);
2570         } else {
2571                 devpriv->adc_control1_bits &= ~CHANNEL_MODE_4020_MASK;
2572                 if (cmd->chanlist_len == 4)
2573                         devpriv->adc_control1_bits |= FOUR_CHANNEL_4020_BITS;
2574                 else if (cmd->chanlist_len == 2)
2575                         devpriv->adc_control1_bits |= TWO_CHANNEL_4020_BITS;
2576                 devpriv->adc_control1_bits &= ~ADC_LO_CHANNEL_4020_MASK;
2577                 devpriv->adc_control1_bits |=
2578                         adc_lo_chan_4020_bits(CR_CHAN(cmd->chanlist[0]));
2579                 devpriv->adc_control1_bits &= ~ADC_HI_CHANNEL_4020_MASK;
2580                 devpriv->adc_control1_bits |=
2581                         adc_hi_chan_4020_bits(CR_CHAN(cmd->chanlist
2582                                                       [cmd->chanlist_len - 1]));
2583         }
2584         writew(devpriv->adc_control1_bits,
2585                devpriv->main_iobase + ADC_CONTROL1_REG);
2586         spin_unlock_irqrestore(&dev->spinlock, flags);
2587
2588         /*  clear adc buffer */
2589         writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
2590
2591         if ((cmd->flags & CMDF_WAKE_EOS) == 0 ||
2592             thisboard->layout == LAYOUT_4020) {
2593                 devpriv->ai_dma_index = 0;
2594
2595                 /*  set dma transfer size */
2596                 for (i = 0; i < ai_dma_ring_count(thisboard); i++)
2597                         devpriv->ai_dma_desc[i].transfer_size =
2598                                 cpu_to_le32(dma_transfer_size(dev) *
2599                                             sizeof(uint16_t));
2600
2601                 /*  give location of first dma descriptor */
2602                 load_first_dma_descriptor(dev, 1,
2603                                           devpriv->ai_dma_desc_bus_addr |
2604                                           PLX_DESC_IN_PCI_BIT |
2605                                           PLX_INTR_TERM_COUNT |
2606                                           PLX_XFER_LOCAL_TO_PCI);
2607
2608                 dma_start_sync(dev, 1);
2609         }
2610
2611         if (thisboard->layout == LAYOUT_4020) {
2612                 /* set source for external triggers */
2613                 bits = 0;
2614                 if (cmd->start_src == TRIG_EXT && CR_CHAN(cmd->start_arg))
2615                         bits |= EXT_START_TRIG_BNC_BIT;
2616                 if (cmd->stop_src == TRIG_EXT && CR_CHAN(cmd->stop_arg))
2617                         bits |= EXT_STOP_TRIG_BNC_BIT;
2618                 writew(bits, devpriv->main_iobase + DAQ_ATRIG_LOW_4020_REG);
2619         }
2620
2621         spin_lock_irqsave(&dev->spinlock, flags);
2622
2623         /* enable pacing, triggering, etc */
2624         bits = ADC_ENABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT;
2625         if (cmd->flags & CMDF_WAKE_EOS)
2626                 bits |= ADC_DMA_DISABLE_BIT;
2627         /*  set start trigger */
2628         if (cmd->start_src == TRIG_EXT) {
2629                 bits |= ADC_START_TRIG_EXT_BITS;
2630                 if (cmd->start_arg & CR_INVERT)
2631                         bits |= ADC_START_TRIG_FALLING_BIT;
2632         } else if (cmd->start_src == TRIG_NOW) {
2633                 bits |= ADC_START_TRIG_SOFT_BITS;
2634         }
2635         if (use_hw_sample_counter(cmd))
2636                 bits |= ADC_SAMPLE_COUNTER_EN_BIT;
2637         writew(bits, devpriv->main_iobase + ADC_CONTROL0_REG);
2638
2639         devpriv->ai_cmd_running = 1;
2640
2641         spin_unlock_irqrestore(&dev->spinlock, flags);
2642
2643         /*  start acquisition */
2644         if (cmd->start_src == TRIG_NOW)
2645                 writew(0, devpriv->main_iobase + ADC_START_REG);
2646
2647         return 0;
2648 }
2649
2650 /* read num_samples from 16 bit wide ai fifo */
2651 static void pio_drain_ai_fifo_16(struct comedi_device *dev)
2652 {
2653         struct pcidas64_private *devpriv = dev->private;
2654         struct comedi_subdevice *s = dev->read_subdev;
2655         unsigned int i;
2656         uint16_t prepost_bits;
2657         int read_segment, read_index, write_segment, write_index;
2658         int num_samples;
2659
2660         do {
2661                 /*  get least significant 15 bits */
2662                 read_index = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) &
2663                              0x7fff;
2664                 write_index = readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) &
2665                               0x7fff;
2666                 /* Get most significant bits (grey code).
2667                  * Different boards use different code so use a scheme
2668                  * that doesn't depend on encoding.  This read must
2669                  * occur after reading least significant 15 bits to avoid race
2670                  * with fifo switching to next segment. */
2671                 prepost_bits = readw(devpriv->main_iobase + PREPOST_REG);
2672
2673                 /* if read and write pointers are not on the same fifo segment,
2674                  * read to the end of the read segment */
2675                 read_segment = adc_upper_read_ptr_code(prepost_bits);
2676                 write_segment = adc_upper_write_ptr_code(prepost_bits);
2677
2678                 if (read_segment != write_segment)
2679                         num_samples =
2680                                 devpriv->ai_fifo_segment_length - read_index;
2681                 else
2682                         num_samples = write_index - read_index;
2683                 if (num_samples < 0) {
2684                         dev_err(dev->class_dev,
2685                                 "cb_pcidas64: bug! num_samples < 0\n");
2686                         break;
2687                 }
2688
2689                 num_samples = comedi_nsamples_left(s, num_samples);
2690                 if (num_samples == 0)
2691                         break;
2692
2693                 for (i = 0; i < num_samples; i++) {
2694                         unsigned short val;
2695
2696                         val = readw(devpriv->main_iobase + ADC_FIFO_REG);
2697                         comedi_buf_write_samples(s, &val, 1);
2698                 }
2699
2700         } while (read_segment != write_segment);
2701 }
2702
2703 /* Read from 32 bit wide ai fifo of 4020 - deal with insane grey coding of
2704  * pointers.  The pci-4020 hardware only supports dma transfers (it only
2705  * supports the use of pio for draining the last remaining points from the
2706  * fifo when a data acquisition operation has completed).
2707  */
2708 static void pio_drain_ai_fifo_32(struct comedi_device *dev)
2709 {
2710         struct pcidas64_private *devpriv = dev->private;
2711         struct comedi_subdevice *s = dev->read_subdev;
2712         unsigned int nsamples;
2713         unsigned int i;
2714         uint32_t fifo_data;
2715         int write_code =
2716                 readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff;
2717         int read_code =
2718                 readw(devpriv->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2719
2720         nsamples = comedi_nsamples_left(s, 100000);
2721         for (i = 0; read_code != write_code && i < nsamples;) {
2722                 unsigned short val;
2723
2724                 fifo_data = readl(dev->mmio + ADC_FIFO_REG);
2725                 val = fifo_data & 0xffff;
2726                 comedi_buf_write_samples(s, &val, 1);
2727                 i++;
2728                 if (i < nsamples) {
2729                         val = (fifo_data >> 16) & 0xffff;
2730                         comedi_buf_write_samples(s, &val, 1);
2731                         i++;
2732                 }
2733                 read_code = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) &
2734                             0x7fff;
2735         }
2736 }
2737
2738 /* empty fifo */
2739 static void pio_drain_ai_fifo(struct comedi_device *dev)
2740 {
2741         const struct pcidas64_board *thisboard = dev->board_ptr;
2742
2743         if (thisboard->layout == LAYOUT_4020)
2744                 pio_drain_ai_fifo_32(dev);
2745         else
2746                 pio_drain_ai_fifo_16(dev);
2747 }
2748
2749 static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
2750 {
2751         const struct pcidas64_board *thisboard = dev->board_ptr;
2752         struct pcidas64_private *devpriv = dev->private;
2753         struct comedi_subdevice *s = dev->read_subdev;
2754         uint32_t next_transfer_addr;
2755         int j;
2756         int num_samples = 0;
2757         void __iomem *pci_addr_reg;
2758
2759         if (channel)
2760                 pci_addr_reg =
2761                     devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
2762         else
2763                 pci_addr_reg =
2764                     devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
2765
2766         /*  loop until we have read all the full buffers */
2767         for (j = 0, next_transfer_addr = readl(pci_addr_reg);
2768              (next_transfer_addr <
2769               devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] ||
2770               next_transfer_addr >=
2771               devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] +
2772               DMA_BUFFER_SIZE) && j < ai_dma_ring_count(thisboard); j++) {
2773                 /*  transfer data from dma buffer to comedi buffer */
2774                 num_samples = comedi_nsamples_left(s, dma_transfer_size(dev));
2775                 comedi_buf_write_samples(s,
2776                                 devpriv->ai_buffer[devpriv->ai_dma_index],
2777                                 num_samples);
2778                 devpriv->ai_dma_index = (devpriv->ai_dma_index + 1) %
2779                                         ai_dma_ring_count(thisboard);
2780         }
2781         /* XXX check for dma ring buffer overrun
2782          * (use end-of-chain bit to mark last unused buffer) */
2783 }
2784
2785 static void handle_ai_interrupt(struct comedi_device *dev,
2786                                 unsigned short status,
2787                                 unsigned int plx_status)
2788 {
2789         const struct pcidas64_board *thisboard = dev->board_ptr;
2790         struct pcidas64_private *devpriv = dev->private;
2791         struct comedi_subdevice *s = dev->read_subdev;
2792         struct comedi_async *async = s->async;
2793         struct comedi_cmd *cmd = &async->cmd;
2794         uint8_t dma1_status;
2795         unsigned long flags;
2796
2797         /*  check for fifo overrun */
2798         if (status & ADC_OVERRUN_BIT) {
2799                 dev_err(dev->class_dev, "fifo overrun\n");
2800                 async->events |= COMEDI_CB_ERROR;
2801         }
2802         /*  spin lock makes sure no one else changes plx dma control reg */
2803         spin_lock_irqsave(&dev->spinlock, flags);
2804         dma1_status = readb(devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2805         if (plx_status & ICS_DMA1_A) {  /*  dma chan 1 interrupt */
2806                 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
2807                        devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2808
2809                 if (dma1_status & PLX_DMA_EN_BIT)
2810                         drain_dma_buffers(dev, 1);
2811         }
2812         spin_unlock_irqrestore(&dev->spinlock, flags);
2813
2814         /*  drain fifo with pio */
2815         if ((status & ADC_DONE_BIT) ||
2816             ((cmd->flags & CMDF_WAKE_EOS) &&
2817              (status & ADC_INTR_PENDING_BIT) &&
2818              (thisboard->layout != LAYOUT_4020))) {
2819                 spin_lock_irqsave(&dev->spinlock, flags);
2820                 if (devpriv->ai_cmd_running) {
2821                         spin_unlock_irqrestore(&dev->spinlock, flags);
2822                         pio_drain_ai_fifo(dev);
2823                 } else {
2824                         spin_unlock_irqrestore(&dev->spinlock, flags);
2825                 }
2826         }
2827         /*  if we are have all the data, then quit */
2828         if ((cmd->stop_src == TRIG_COUNT &&
2829              async->scans_done >= cmd->stop_arg) ||
2830             (cmd->stop_src == TRIG_EXT && (status & ADC_STOP_BIT)))
2831                 async->events |= COMEDI_CB_EOA;
2832
2833         comedi_handle_events(dev, s);
2834 }
2835
2836 static inline unsigned int prev_ao_dma_index(struct comedi_device *dev)
2837 {
2838         struct pcidas64_private *devpriv = dev->private;
2839         unsigned int buffer_index;
2840
2841         if (devpriv->ao_dma_index == 0)
2842                 buffer_index = AO_DMA_RING_COUNT - 1;
2843         else
2844                 buffer_index = devpriv->ao_dma_index - 1;
2845         return buffer_index;
2846 }
2847
2848 static int last_ao_dma_load_completed(struct comedi_device *dev)
2849 {
2850         struct pcidas64_private *devpriv = dev->private;
2851         unsigned int buffer_index;
2852         unsigned int transfer_address;
2853         unsigned short dma_status;
2854
2855         buffer_index = prev_ao_dma_index(dev);
2856         dma_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2857         if ((dma_status & PLX_DMA_DONE_BIT) == 0)
2858                 return 0;
2859
2860         transfer_address =
2861                 readl(devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
2862         if (transfer_address != devpriv->ao_buffer_bus_addr[buffer_index])
2863                 return 0;
2864
2865         return 1;
2866 }
2867
2868 static inline int ao_dma_needs_restart(struct comedi_device *dev,
2869                                        unsigned short dma_status)
2870 {
2871         if ((dma_status & PLX_DMA_DONE_BIT) == 0 ||
2872             (dma_status & PLX_DMA_EN_BIT) == 0)
2873                 return 0;
2874         if (last_ao_dma_load_completed(dev))
2875                 return 0;
2876
2877         return 1;
2878 }
2879
2880 static void restart_ao_dma(struct comedi_device *dev)
2881 {
2882         struct pcidas64_private *devpriv = dev->private;
2883         unsigned int dma_desc_bits;
2884
2885         dma_desc_bits =
2886                 readl(devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
2887         dma_desc_bits &= ~PLX_END_OF_CHAIN_BIT;
2888         load_first_dma_descriptor(dev, 0, dma_desc_bits);
2889
2890         dma_start_sync(dev, 0);
2891 }
2892
2893 static unsigned int cb_pcidas64_ao_fill_buffer(struct comedi_device *dev,
2894                                                struct comedi_subdevice *s,
2895                                                unsigned short *dest,
2896                                                unsigned int max_bytes)
2897 {
2898         unsigned int nsamples = comedi_bytes_to_samples(s, max_bytes);
2899         unsigned int actual_bytes;
2900
2901         nsamples = comedi_nsamples_left(s, nsamples);
2902         actual_bytes = comedi_buf_read_samples(s, dest, nsamples);
2903
2904         return comedi_bytes_to_samples(s, actual_bytes);
2905 }
2906
2907 static unsigned int load_ao_dma_buffer(struct comedi_device *dev,
2908                                        const struct comedi_cmd *cmd)
2909 {
2910         struct pcidas64_private *devpriv = dev->private;
2911         struct comedi_subdevice *s = dev->write_subdev;
2912         unsigned int buffer_index = devpriv->ao_dma_index;
2913         unsigned int prev_buffer_index = prev_ao_dma_index(dev);
2914         unsigned int nsamples;
2915         unsigned int nbytes;
2916         unsigned int next_bits;
2917
2918         nsamples = cb_pcidas64_ao_fill_buffer(dev, s,
2919                                               devpriv->ao_buffer[buffer_index],
2920                                               DMA_BUFFER_SIZE);
2921         if (nsamples == 0)
2922                 return 0;
2923
2924         nbytes = comedi_samples_to_bytes(s, nsamples);
2925         devpriv->ao_dma_desc[buffer_index].transfer_size = cpu_to_le32(nbytes);
2926         /* set end of chain bit so we catch underruns */
2927         next_bits = le32_to_cpu(devpriv->ao_dma_desc[buffer_index].next);
2928         next_bits |= PLX_END_OF_CHAIN_BIT;
2929         devpriv->ao_dma_desc[buffer_index].next = cpu_to_le32(next_bits);
2930         /* clear end of chain bit on previous buffer now that we have set it
2931          * for the last buffer */
2932         next_bits = le32_to_cpu(devpriv->ao_dma_desc[prev_buffer_index].next);
2933         next_bits &= ~PLX_END_OF_CHAIN_BIT;
2934         devpriv->ao_dma_desc[prev_buffer_index].next = cpu_to_le32(next_bits);
2935
2936         devpriv->ao_dma_index = (buffer_index + 1) % AO_DMA_RING_COUNT;
2937
2938         return nbytes;
2939 }
2940
2941 static void load_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
2942 {
2943         struct pcidas64_private *devpriv = dev->private;
2944         unsigned int num_bytes;
2945         unsigned int next_transfer_addr;
2946         void __iomem *pci_addr_reg =
2947                 devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
2948         unsigned int buffer_index;
2949
2950         do {
2951                 buffer_index = devpriv->ao_dma_index;
2952                 /* don't overwrite data that hasn't been transferred yet */
2953                 next_transfer_addr = readl(pci_addr_reg);
2954                 if (next_transfer_addr >=
2955                     devpriv->ao_buffer_bus_addr[buffer_index] &&
2956                     next_transfer_addr <
2957                     devpriv->ao_buffer_bus_addr[buffer_index] +
2958                     DMA_BUFFER_SIZE)
2959                         return;
2960                 num_bytes = load_ao_dma_buffer(dev, cmd);
2961         } while (num_bytes >= DMA_BUFFER_SIZE);
2962 }
2963
2964 static void handle_ao_interrupt(struct comedi_device *dev,
2965                                 unsigned short status, unsigned int plx_status)
2966 {
2967         struct pcidas64_private *devpriv = dev->private;
2968         struct comedi_subdevice *s = dev->write_subdev;
2969         struct comedi_async *async;
2970         struct comedi_cmd *cmd;
2971         uint8_t dma0_status;
2972         unsigned long flags;
2973
2974         /* board might not support ao, in which case write_subdev is NULL */
2975         if (!s)
2976                 return;
2977         async = s->async;
2978         cmd = &async->cmd;
2979
2980         /*  spin lock makes sure no one else changes plx dma control reg */
2981         spin_lock_irqsave(&dev->spinlock, flags);
2982         dma0_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2983         if (plx_status & ICS_DMA0_A) {  /*  dma chan 0 interrupt */
2984                 if ((dma0_status & PLX_DMA_EN_BIT) &&
2985                     !(dma0_status & PLX_DMA_DONE_BIT))
2986                         writeb(PLX_DMA_EN_BIT | PLX_CLEAR_DMA_INTR_BIT,
2987                                devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2988                 else
2989                         writeb(PLX_CLEAR_DMA_INTR_BIT,
2990                                devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2991                 spin_unlock_irqrestore(&dev->spinlock, flags);
2992                 if (dma0_status & PLX_DMA_EN_BIT) {
2993                         load_ao_dma(dev, cmd);
2994                         /* try to recover from dma end-of-chain event */
2995                         if (ao_dma_needs_restart(dev, dma0_status))
2996                                 restart_ao_dma(dev);
2997                 }
2998         } else {
2999                 spin_unlock_irqrestore(&dev->spinlock, flags);
3000         }
3001
3002         if ((status & DAC_DONE_BIT)) {
3003                 if ((cmd->stop_src == TRIG_COUNT &&
3004                      async->scans_done >= cmd->stop_arg) ||
3005                     last_ao_dma_load_completed(dev))
3006                         async->events |= COMEDI_CB_EOA;
3007                 else
3008                         async->events |= COMEDI_CB_ERROR;
3009         }
3010         comedi_handle_events(dev, s);
3011 }
3012
3013 static irqreturn_t handle_interrupt(int irq, void *d)
3014 {
3015         struct comedi_device *dev = d;
3016         struct pcidas64_private *devpriv = dev->private;
3017         unsigned short status;
3018         uint32_t plx_status;
3019         uint32_t plx_bits;
3020
3021         plx_status = readl(devpriv->plx9080_iobase + PLX_INTRCS_REG);
3022         status = readw(devpriv->main_iobase + HW_STATUS_REG);
3023
3024         /* an interrupt before all the postconfig stuff gets done could
3025          * cause a NULL dereference if we continue through the
3026          * interrupt handler */
3027         if (!dev->attached)
3028                 return IRQ_HANDLED;
3029
3030         handle_ai_interrupt(dev, status, plx_status);
3031         handle_ao_interrupt(dev, status, plx_status);
3032
3033         /*  clear possible plx9080 interrupt sources */
3034         if (plx_status & ICS_LDIA) {    /*  clear local doorbell interrupt */
3035                 plx_bits = readl(devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
3036                 writel(plx_bits, devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
3037         }
3038
3039         return IRQ_HANDLED;
3040 }
3041
3042 static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3043 {
3044         struct pcidas64_private *devpriv = dev->private;
3045         unsigned long flags;
3046
3047         spin_lock_irqsave(&dev->spinlock, flags);
3048         if (devpriv->ai_cmd_running == 0) {
3049                 spin_unlock_irqrestore(&dev->spinlock, flags);
3050                 return 0;
3051         }
3052         devpriv->ai_cmd_running = 0;
3053         spin_unlock_irqrestore(&dev->spinlock, flags);
3054
3055         disable_ai_pacing(dev);
3056
3057         abort_dma(dev, 1);
3058
3059         return 0;
3060 }
3061
3062 static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
3063                     struct comedi_insn *insn, unsigned int *data)
3064 {
3065         const struct pcidas64_board *thisboard = dev->board_ptr;
3066         struct pcidas64_private *devpriv = dev->private;
3067         int chan = CR_CHAN(insn->chanspec);
3068         int range = CR_RANGE(insn->chanspec);
3069
3070         /*  do some initializing */
3071         writew(0, devpriv->main_iobase + DAC_CONTROL0_REG);
3072
3073         /*  set range */
3074         set_dac_range_bits(dev, &devpriv->dac_control1_bits, chan, range);
3075         writew(devpriv->dac_control1_bits,
3076                devpriv->main_iobase + DAC_CONTROL1_REG);
3077
3078         /*  write to channel */
3079         if (thisboard->layout == LAYOUT_4020) {
3080                 writew(data[0] & 0xff,
3081                        devpriv->main_iobase + dac_lsb_4020_reg(chan));
3082                 writew((data[0] >> 8) & 0xf,
3083                        devpriv->main_iobase + dac_msb_4020_reg(chan));
3084         } else {
3085                 writew(data[0], devpriv->main_iobase + dac_convert_reg(chan));
3086         }
3087
3088         /*  remember output value */
3089         s->readback[chan] = data[0];
3090
3091         return 1;
3092 }
3093
3094 static void set_dac_control0_reg(struct comedi_device *dev,
3095                                  const struct comedi_cmd *cmd)
3096 {
3097         struct pcidas64_private *devpriv = dev->private;
3098         unsigned int bits = DAC_ENABLE_BIT | WAVEFORM_GATE_LEVEL_BIT |
3099                             WAVEFORM_GATE_ENABLE_BIT | WAVEFORM_GATE_SELECT_BIT;
3100
3101         if (cmd->start_src == TRIG_EXT) {
3102                 bits |= WAVEFORM_TRIG_EXT_BITS;
3103                 if (cmd->start_arg & CR_INVERT)
3104                         bits |= WAVEFORM_TRIG_FALLING_BIT;
3105         } else {
3106                 bits |= WAVEFORM_TRIG_SOFT_BITS;
3107         }
3108         if (cmd->scan_begin_src == TRIG_EXT) {
3109                 bits |= DAC_EXT_UPDATE_ENABLE_BIT;
3110                 if (cmd->scan_begin_arg & CR_INVERT)
3111                         bits |= DAC_EXT_UPDATE_FALLING_BIT;
3112         }
3113         writew(bits, devpriv->main_iobase + DAC_CONTROL0_REG);
3114 }
3115
3116 static void set_dac_control1_reg(struct comedi_device *dev,
3117                                  const struct comedi_cmd *cmd)
3118 {
3119         struct pcidas64_private *devpriv = dev->private;
3120         int i;
3121
3122         for (i = 0; i < cmd->chanlist_len; i++) {
3123                 int channel, range;
3124
3125                 channel = CR_CHAN(cmd->chanlist[i]);
3126                 range = CR_RANGE(cmd->chanlist[i]);
3127                 set_dac_range_bits(dev, &devpriv->dac_control1_bits, channel,
3128                                    range);
3129         }
3130         devpriv->dac_control1_bits |= DAC_SW_GATE_BIT;
3131         writew(devpriv->dac_control1_bits,
3132                devpriv->main_iobase + DAC_CONTROL1_REG);
3133 }
3134
3135 static void set_dac_select_reg(struct comedi_device *dev,
3136                                const struct comedi_cmd *cmd)
3137 {
3138         struct pcidas64_private *devpriv = dev->private;
3139         uint16_t bits;
3140         unsigned int first_channel, last_channel;
3141
3142         first_channel = CR_CHAN(cmd->chanlist[0]);
3143         last_channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
3144         if (last_channel < first_channel)
3145                 dev_err(dev->class_dev,
3146                         "bug! last ao channel < first ao channel\n");
3147
3148         bits = (first_channel & 0x7) | (last_channel & 0x7) << 3;
3149
3150         writew(bits, devpriv->main_iobase + DAC_SELECT_REG);
3151 }
3152
3153 static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags)
3154 {
3155         return get_divisor(ns, flags) - 2;
3156 }
3157
3158 static void set_dac_interval_regs(struct comedi_device *dev,
3159                                   const struct comedi_cmd *cmd)
3160 {
3161         struct pcidas64_private *devpriv = dev->private;
3162         unsigned int divisor;
3163
3164         if (cmd->scan_begin_src != TRIG_TIMER)
3165                 return;
3166
3167         divisor = get_ao_divisor(cmd->scan_begin_arg, cmd->flags);
3168         if (divisor > max_counter_value) {
3169                 dev_err(dev->class_dev, "bug! ao divisor too big\n");
3170                 divisor = max_counter_value;
3171         }
3172         writew(divisor & 0xffff,
3173                devpriv->main_iobase + DAC_SAMPLE_INTERVAL_LOWER_REG);
3174         writew((divisor >> 16) & 0xff,
3175                devpriv->main_iobase + DAC_SAMPLE_INTERVAL_UPPER_REG);
3176 }
3177
3178 static int prep_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3179 {
3180         struct pcidas64_private *devpriv = dev->private;
3181         struct comedi_subdevice *s = dev->write_subdev;
3182         unsigned int nsamples;
3183         unsigned int nbytes;
3184         int i;
3185
3186         /* clear queue pointer too, since external queue has
3187          * weird interactions with ao fifo */
3188         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
3189         writew(0, devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
3190
3191         nsamples = cb_pcidas64_ao_fill_buffer(dev, s,
3192                                               devpriv->ao_bounce_buffer,
3193                                               DAC_FIFO_SIZE);
3194         if (nsamples == 0)
3195                 return -1;
3196
3197         for (i = 0; i < nsamples; i++) {
3198                 writew(devpriv->ao_bounce_buffer[i],
3199                        devpriv->main_iobase + DAC_FIFO_REG);
3200         }
3201
3202         if (cmd->stop_src == TRIG_COUNT &&
3203             s->async->scans_done >= cmd->stop_arg)
3204                 return 0;
3205
3206         nbytes = load_ao_dma_buffer(dev, cmd);
3207         if (nbytes == 0)
3208                 return -1;
3209         load_ao_dma(dev, cmd);
3210
3211         dma_start_sync(dev, 0);
3212
3213         return 0;
3214 }
3215
3216 static inline int external_ai_queue_in_use(struct comedi_device *dev,
3217                                            struct comedi_subdevice *s,
3218                                            struct comedi_cmd *cmd)
3219 {
3220         const struct pcidas64_board *thisboard = dev->board_ptr;
3221
3222         if (s->busy)
3223                 return 0;
3224         if (thisboard->layout == LAYOUT_4020)
3225                 return 0;
3226         else if (use_internal_queue_6xxx(cmd))
3227                 return 0;
3228         return 1;
3229 }
3230
3231 static int ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3232                       unsigned int trig_num)
3233 {
3234         struct pcidas64_private *devpriv = dev->private;
3235         struct comedi_cmd *cmd = &s->async->cmd;
3236         int retval;
3237
3238         if (trig_num != cmd->start_arg)
3239                 return -EINVAL;
3240
3241         retval = prep_ao_dma(dev, cmd);
3242         if (retval < 0)
3243                 return -EPIPE;
3244
3245         set_dac_control0_reg(dev, cmd);
3246
3247         if (cmd->start_src == TRIG_INT)
3248                 writew(0, devpriv->main_iobase + DAC_START_REG);
3249
3250         s->async->inttrig = NULL;
3251
3252         return 0;
3253 }
3254
3255 static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3256 {
3257         struct pcidas64_private *devpriv = dev->private;
3258         struct comedi_cmd *cmd = &s->async->cmd;
3259
3260         if (external_ai_queue_in_use(dev, s, cmd)) {
3261                 warn_external_queue(dev);
3262                 return -EBUSY;
3263         }
3264         /* disable analog output system during setup */
3265         writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3266
3267         devpriv->ao_dma_index = 0;
3268
3269         set_dac_select_reg(dev, cmd);
3270         set_dac_interval_regs(dev, cmd);
3271         load_first_dma_descriptor(dev, 0, devpriv->ao_dma_desc_bus_addr |
3272                                   PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT);
3273
3274         set_dac_control1_reg(dev, cmd);
3275         s->async->inttrig = ao_inttrig;
3276
3277         return 0;
3278 }
3279
3280 static int cb_pcidas64_ao_check_chanlist(struct comedi_device *dev,
3281                                          struct comedi_subdevice *s,
3282                                          struct comedi_cmd *cmd)
3283 {
3284         unsigned int chan0 = CR_CHAN(cmd->chanlist[0]);
3285         int i;
3286
3287         for (i = 1; i < cmd->chanlist_len; i++) {
3288                 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3289
3290                 if (chan != (chan0 + i)) {
3291                         dev_dbg(dev->class_dev,
3292                                 "chanlist must use consecutive channels\n");
3293                         return -EINVAL;
3294                 }
3295         }
3296
3297         return 0;
3298 }
3299
3300 static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3301                       struct comedi_cmd *cmd)
3302 {
3303         const struct pcidas64_board *thisboard = dev->board_ptr;
3304         int err = 0;
3305         unsigned int tmp_arg;
3306
3307         /* Step 1 : check if triggers are trivially valid */
3308
3309         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3310         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
3311                                      TRIG_TIMER | TRIG_EXT);
3312         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3313         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3314         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3315
3316         if (err)
3317                 return 1;
3318
3319         /* Step 2a : make sure trigger sources are unique */
3320
3321         err |= cfc_check_trigger_is_unique(cmd->start_src);
3322         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
3323
3324         /* Step 2b : and mutually compatible */
3325
3326         if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
3327                 err |= -EINVAL;
3328         if (cmd->stop_src != TRIG_COUNT &&
3329             cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
3330                 err |= -EINVAL;
3331
3332         if (err)
3333                 return 2;
3334
3335         /* Step 3: check if arguments are trivially valid */
3336
3337         err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3338
3339         if (cmd->scan_begin_src == TRIG_TIMER) {
3340                 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
3341                                                  thisboard->ao_scan_speed);
3342                 if (get_ao_divisor(cmd->scan_begin_arg, cmd->flags) >
3343                     max_counter_value) {
3344                         cmd->scan_begin_arg = (max_counter_value + 2) *
3345                                               TIMER_BASE;
3346                         err |= -EINVAL;
3347                 }
3348         }
3349
3350         err |= cfc_check_trigger_arg_min(&cmd->chanlist_len, 1);
3351         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3352
3353         if (err)
3354                 return 3;
3355
3356         /* step 4: fix up any arguments */
3357
3358         if (cmd->scan_begin_src == TRIG_TIMER) {
3359                 tmp_arg = cmd->scan_begin_arg;
3360                 cmd->scan_begin_arg = get_divisor(cmd->scan_begin_arg,
3361                                                   cmd->flags) * TIMER_BASE;
3362                 if (tmp_arg != cmd->scan_begin_arg)
3363                         err++;
3364         }
3365
3366         if (err)
3367                 return 4;
3368
3369         /* Step 5: check channel list if it exists */
3370         if (cmd->chanlist && cmd->chanlist_len > 0)
3371                 err |= cb_pcidas64_ao_check_chanlist(dev, s, cmd);
3372
3373         if (err)
3374                 return 5;
3375
3376         return 0;
3377 }
3378
3379 static int ao_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3380 {
3381         struct pcidas64_private *devpriv = dev->private;
3382
3383         writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3384         abort_dma(dev, 0);
3385         return 0;
3386 }
3387
3388 static int dio_callback_4020(struct comedi_device *dev,
3389                              int dir, int port, int data, unsigned long iobase)
3390 {
3391         struct pcidas64_private *devpriv = dev->private;
3392
3393         if (dir) {
3394                 writew(data, devpriv->main_iobase + iobase + 2 * port);
3395                 return 0;
3396         }
3397         return readw(devpriv->main_iobase + iobase + 2 * port);
3398 }
3399
3400 static int di_rbits(struct comedi_device *dev, struct comedi_subdevice *s,
3401                     struct comedi_insn *insn, unsigned int *data)
3402 {
3403         unsigned int bits;
3404
3405         bits = readb(dev->mmio + DI_REG);
3406         bits &= 0xf;
3407         data[1] = bits;
3408         data[0] = 0;
3409
3410         return insn->n;
3411 }
3412
3413 static int do_wbits(struct comedi_device *dev,
3414                     struct comedi_subdevice *s,
3415                     struct comedi_insn *insn,
3416                     unsigned int *data)
3417 {
3418         if (comedi_dio_update_state(s, data))
3419                 writeb(s->state, dev->mmio + DO_REG);
3420
3421         data[1] = s->state;
3422
3423         return insn->n;
3424 }
3425
3426 static int dio_60xx_config_insn(struct comedi_device *dev,
3427                                 struct comedi_subdevice *s,
3428                                 struct comedi_insn *insn,
3429                                 unsigned int *data)
3430 {
3431         int ret;
3432
3433         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3434         if (ret)
3435                 return ret;
3436
3437         writeb(s->io_bits, dev->mmio + DIO_DIRECTION_60XX_REG);
3438
3439         return insn->n;
3440 }
3441
3442 static int dio_60xx_wbits(struct comedi_device *dev,
3443                           struct comedi_subdevice *s,
3444                           struct comedi_insn *insn,
3445                           unsigned int *data)
3446 {
3447         if (comedi_dio_update_state(s, data))
3448                 writeb(s->state, dev->mmio + DIO_DATA_60XX_REG);
3449
3450         data[1] = readb(dev->mmio + DIO_DATA_60XX_REG);
3451
3452         return insn->n;
3453 }
3454
3455 /* pci-6025 8800 caldac:
3456  * address 0 == dac channel 0 offset
3457  * address 1 == dac channel 0 gain
3458  * address 2 == dac channel 1 offset
3459  * address 3 == dac channel 1 gain
3460  * address 4 == fine adc offset
3461  * address 5 == coarse adc offset
3462  * address 6 == coarse adc gain
3463  * address 7 == fine adc gain
3464  */
3465 /* pci-6402/16 uses all 8 channels for dac:
3466  * address 0 == dac channel 0 fine gain
3467  * address 1 == dac channel 0 coarse gain
3468  * address 2 == dac channel 0 coarse offset
3469  * address 3 == dac channel 1 coarse offset
3470  * address 4 == dac channel 1 fine gain
3471  * address 5 == dac channel 1 coarse gain
3472  * address 6 == dac channel 0 fine offset
3473  * address 7 == dac channel 1 fine offset
3474 */
3475
3476 static int caldac_8800_write(struct comedi_device *dev, unsigned int address,
3477                              uint8_t value)
3478 {
3479         struct pcidas64_private *devpriv = dev->private;
3480         static const int num_caldac_channels = 8;
3481         static const int bitstream_length = 11;
3482         unsigned int bitstream = ((address & 0x7) << 8) | value;
3483         unsigned int bit, register_bits;
3484         static const int caldac_8800_udelay = 1;
3485
3486         if (address >= num_caldac_channels) {
3487                 dev_err(dev->class_dev, "illegal caldac channel\n");
3488                 return -1;
3489         }
3490         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3491                 register_bits = 0;
3492                 if (bitstream & bit)
3493                         register_bits |= SERIAL_DATA_IN_BIT;
3494                 udelay(caldac_8800_udelay);
3495                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3496                 register_bits |= SERIAL_CLOCK_BIT;
3497                 udelay(caldac_8800_udelay);
3498                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3499         }
3500         udelay(caldac_8800_udelay);
3501         writew(SELECT_8800_BIT, devpriv->main_iobase + CALIBRATION_REG);
3502         udelay(caldac_8800_udelay);
3503         writew(0, devpriv->main_iobase + CALIBRATION_REG);
3504         udelay(caldac_8800_udelay);
3505         return 0;
3506 }
3507
3508 /* 4020 caldacs */
3509 static int caldac_i2c_write(struct comedi_device *dev,
3510                             unsigned int caldac_channel, unsigned int value)
3511 {
3512         uint8_t serial_bytes[3];
3513         uint8_t i2c_addr;
3514         enum pointer_bits {
3515                 /*  manual has gain and offset bits switched */
3516                 OFFSET_0_2 = 0x1,
3517                 GAIN_0_2 = 0x2,
3518                 OFFSET_1_3 = 0x4,
3519                 GAIN_1_3 = 0x8,
3520         };
3521         enum data_bits {
3522                 NOT_CLEAR_REGISTERS = 0x20,
3523         };
3524
3525         switch (caldac_channel) {
3526         case 0:         /*  chan 0 offset */
3527                 i2c_addr = CALDAC0_I2C_ADDR;
3528                 serial_bytes[0] = OFFSET_0_2;
3529                 break;
3530         case 1:         /*  chan 1 offset */
3531                 i2c_addr = CALDAC0_I2C_ADDR;
3532                 serial_bytes[0] = OFFSET_1_3;
3533                 break;
3534         case 2:         /*  chan 2 offset */
3535                 i2c_addr = CALDAC1_I2C_ADDR;
3536                 serial_bytes[0] = OFFSET_0_2;
3537                 break;
3538         case 3:         /*  chan 3 offset */
3539                 i2c_addr = CALDAC1_I2C_ADDR;
3540                 serial_bytes[0] = OFFSET_1_3;
3541                 break;
3542         case 4:         /*  chan 0 gain */
3543                 i2c_addr = CALDAC0_I2C_ADDR;
3544                 serial_bytes[0] = GAIN_0_2;
3545                 break;
3546         case 5:         /*  chan 1 gain */
3547                 i2c_addr = CALDAC0_I2C_ADDR;
3548                 serial_bytes[0] = GAIN_1_3;
3549                 break;
3550         case 6:         /*  chan 2 gain */
3551                 i2c_addr = CALDAC1_I2C_ADDR;
3552                 serial_bytes[0] = GAIN_0_2;
3553                 break;
3554         case 7:         /*  chan 3 gain */
3555                 i2c_addr = CALDAC1_I2C_ADDR;
3556                 serial_bytes[0] = GAIN_1_3;
3557                 break;
3558         default:
3559                 dev_err(dev->class_dev, "invalid caldac channel\n");
3560                 return -1;
3561         }
3562         serial_bytes[1] = NOT_CLEAR_REGISTERS | ((value >> 8) & 0xf);
3563         serial_bytes[2] = value & 0xff;
3564         i2c_write(dev, i2c_addr, serial_bytes, 3);
3565         return 0;
3566 }
3567
3568 static void caldac_write(struct comedi_device *dev, unsigned int channel,
3569                          unsigned int value)
3570 {
3571         const struct pcidas64_board *thisboard = dev->board_ptr;
3572
3573         switch (thisboard->layout) {
3574         case LAYOUT_60XX:
3575         case LAYOUT_64XX:
3576                 caldac_8800_write(dev, channel, value);
3577                 break;
3578         case LAYOUT_4020:
3579                 caldac_i2c_write(dev, channel, value);
3580                 break;
3581         default:
3582                 break;
3583         }
3584 }
3585
3586 static int cb_pcidas64_calib_insn_write(struct comedi_device *dev,
3587                                         struct comedi_subdevice *s,
3588                                         struct comedi_insn *insn,
3589                                         unsigned int *data)
3590 {
3591         unsigned int chan = CR_CHAN(insn->chanspec);
3592
3593         /*
3594          * Programming the calib device is slow. Only write the
3595          * last data value if the value has changed.
3596          */
3597         if (insn->n) {
3598                 unsigned int val = data[insn->n - 1];
3599
3600                 if (s->readback[chan] != val) {
3601                         caldac_write(dev, chan, val);
3602                         s->readback[chan] = val;
3603                 }
3604         }
3605
3606         return insn->n;
3607 }
3608
3609 static void ad8402_write(struct comedi_device *dev, unsigned int channel,
3610                          unsigned int value)
3611 {
3612         struct pcidas64_private *devpriv = dev->private;
3613         static const int bitstream_length = 10;
3614         unsigned int bit, register_bits;
3615         unsigned int bitstream = ((channel & 0x3) << 8) | (value & 0xff);
3616         static const int ad8402_udelay = 1;
3617
3618         register_bits = SELECT_8402_64XX_BIT;
3619         udelay(ad8402_udelay);
3620         writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3621
3622         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3623                 if (bitstream & bit)
3624                         register_bits |= SERIAL_DATA_IN_BIT;
3625                 else
3626                         register_bits &= ~SERIAL_DATA_IN_BIT;
3627                 udelay(ad8402_udelay);
3628                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3629                 udelay(ad8402_udelay);
3630                 writew(register_bits | SERIAL_CLOCK_BIT,
3631                        devpriv->main_iobase + CALIBRATION_REG);
3632         }
3633
3634         udelay(ad8402_udelay);
3635         writew(0, devpriv->main_iobase + CALIBRATION_REG);
3636 }
3637
3638 /* for pci-das6402/16, channel 0 is analog input gain and channel 1 is offset */
3639 static int cb_pcidas64_ad8402_insn_write(struct comedi_device *dev,
3640                                          struct comedi_subdevice *s,
3641                                          struct comedi_insn *insn,
3642                                          unsigned int *data)
3643 {
3644         unsigned int chan = CR_CHAN(insn->chanspec);
3645
3646         /*
3647          * Programming the calib device is slow. Only write the
3648          * last data value if the value has changed.
3649          */
3650         if (insn->n) {
3651                 unsigned int val = data[insn->n - 1];
3652
3653                 if (s->readback[chan] != val) {
3654                         ad8402_write(dev, chan, val);
3655                         s->readback[chan] = val;
3656                 }
3657         }
3658
3659         return insn->n;
3660 }
3661
3662 static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address)
3663 {
3664         struct pcidas64_private *devpriv = dev->private;
3665         static const int bitstream_length = 11;
3666         static const int read_command = 0x6;
3667         unsigned int bitstream = (read_command << 8) | address;
3668         unsigned int bit;
3669         void __iomem * const plx_control_addr =
3670                 devpriv->plx9080_iobase + PLX_CONTROL_REG;
3671         uint16_t value;
3672         static const int value_length = 16;
3673         static const int eeprom_udelay = 1;
3674
3675         udelay(eeprom_udelay);
3676         devpriv->plx_control_bits &= ~CTL_EE_CLK & ~CTL_EE_CS;
3677         /*  make sure we don't send anything to the i2c bus on 4020 */
3678         devpriv->plx_control_bits |= CTL_USERO;
3679         writel(devpriv->plx_control_bits, plx_control_addr);
3680         /*  activate serial eeprom */
3681         udelay(eeprom_udelay);
3682         devpriv->plx_control_bits |= CTL_EE_CS;
3683         writel(devpriv->plx_control_bits, plx_control_addr);
3684
3685         /*  write read command and desired memory address */
3686         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3687                 /*  set bit to be written */
3688                 udelay(eeprom_udelay);
3689                 if (bitstream & bit)
3690                         devpriv->plx_control_bits |= CTL_EE_W;
3691                 else
3692                         devpriv->plx_control_bits &= ~CTL_EE_W;
3693                 writel(devpriv->plx_control_bits, plx_control_addr);
3694                 /*  clock in bit */
3695                 udelay(eeprom_udelay);
3696                 devpriv->plx_control_bits |= CTL_EE_CLK;
3697                 writel(devpriv->plx_control_bits, plx_control_addr);
3698                 udelay(eeprom_udelay);
3699                 devpriv->plx_control_bits &= ~CTL_EE_CLK;
3700                 writel(devpriv->plx_control_bits, plx_control_addr);
3701         }
3702         /*  read back value from eeprom memory location */
3703         value = 0;
3704         for (bit = 1 << (value_length - 1); bit; bit >>= 1) {
3705                 /*  clock out bit */
3706                 udelay(eeprom_udelay);
3707                 devpriv->plx_control_bits |= CTL_EE_CLK;
3708                 writel(devpriv->plx_control_bits, plx_control_addr);
3709                 udelay(eeprom_udelay);
3710                 devpriv->plx_control_bits &= ~CTL_EE_CLK;
3711                 writel(devpriv->plx_control_bits, plx_control_addr);
3712                 udelay(eeprom_udelay);
3713                 if (readl(plx_control_addr) & CTL_EE_R)
3714                         value |= bit;
3715         }
3716
3717         /*  deactivate eeprom serial input */
3718         udelay(eeprom_udelay);
3719         devpriv->plx_control_bits &= ~CTL_EE_CS;
3720         writel(devpriv->plx_control_bits, plx_control_addr);
3721
3722         return value;
3723 }
3724
3725 static int eeprom_read_insn(struct comedi_device *dev,
3726                             struct comedi_subdevice *s,
3727                             struct comedi_insn *insn, unsigned int *data)
3728 {
3729         data[0] = read_eeprom(dev, CR_CHAN(insn->chanspec));
3730
3731         return 1;
3732 }
3733
3734 /* Allocate and initialize the subdevice structures.
3735  */
3736 static int setup_subdevices(struct comedi_device *dev)
3737 {
3738         const struct pcidas64_board *thisboard = dev->board_ptr;
3739         struct pcidas64_private *devpriv = dev->private;
3740         struct comedi_subdevice *s;
3741         int i;
3742         int ret;
3743
3744         ret = comedi_alloc_subdevices(dev, 10);
3745         if (ret)
3746                 return ret;
3747
3748         s = &dev->subdevices[0];
3749         /* analog input subdevice */
3750         dev->read_subdev = s;
3751         s->type = COMEDI_SUBD_AI;
3752         s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DITHER | SDF_CMD_READ;
3753         if (thisboard->layout == LAYOUT_60XX)
3754                 s->subdev_flags |= SDF_COMMON | SDF_DIFF;
3755         else if (thisboard->layout == LAYOUT_64XX)
3756                 s->subdev_flags |= SDF_DIFF;
3757         /* XXX Number of inputs in differential mode is ignored */
3758         s->n_chan = thisboard->ai_se_chans;
3759         s->len_chanlist = 0x2000;
3760         s->maxdata = (1 << thisboard->ai_bits) - 1;
3761         s->range_table = thisboard->ai_range_table;
3762         s->insn_read = ai_rinsn;
3763         s->insn_config = ai_config_insn;
3764         s->do_cmd = ai_cmd;
3765         s->do_cmdtest = ai_cmdtest;
3766         s->cancel = ai_cancel;
3767         if (thisboard->layout == LAYOUT_4020) {
3768                 uint8_t data;
3769                 /*  set adc to read from inputs
3770                  *  (not internal calibration sources) */
3771                 devpriv->i2c_cal_range_bits = adc_src_4020_bits(4);
3772                 /*  set channels to +-5 volt input ranges */
3773                 for (i = 0; i < s->n_chan; i++)
3774                         devpriv->i2c_cal_range_bits |= attenuate_bit(i);
3775                 data = devpriv->i2c_cal_range_bits;
3776                 i2c_write(dev, RANGE_CAL_I2C_ADDR, &data, sizeof(data));
3777         }
3778
3779         /* analog output subdevice */
3780         s = &dev->subdevices[1];
3781         if (thisboard->ao_nchan) {
3782                 s->type = COMEDI_SUBD_AO;
3783                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE |
3784                                   SDF_GROUND | SDF_CMD_WRITE;
3785                 s->n_chan = thisboard->ao_nchan;
3786                 s->maxdata = (1 << thisboard->ao_bits) - 1;
3787                 s->range_table = thisboard->ao_range_table;
3788                 s->insn_write = ao_winsn;
3789
3790                 ret = comedi_alloc_subdev_readback(s);
3791                 if (ret)
3792                         return ret;
3793
3794                 if (ao_cmd_is_supported(thisboard)) {
3795                         dev->write_subdev = s;
3796                         s->do_cmdtest = ao_cmdtest;
3797                         s->do_cmd = ao_cmd;
3798                         s->len_chanlist = thisboard->ao_nchan;
3799                         s->cancel = ao_cancel;
3800                 }
3801         } else {
3802                 s->type = COMEDI_SUBD_UNUSED;
3803         }
3804
3805         /*  digital input */
3806         s = &dev->subdevices[2];
3807         if (thisboard->layout == LAYOUT_64XX) {
3808                 s->type = COMEDI_SUBD_DI;
3809                 s->subdev_flags = SDF_READABLE;
3810                 s->n_chan = 4;
3811                 s->maxdata = 1;
3812                 s->range_table = &range_digital;
3813                 s->insn_bits = di_rbits;
3814         } else {
3815                 s->type = COMEDI_SUBD_UNUSED;
3816         }
3817
3818         /*  digital output */
3819         if (thisboard->layout == LAYOUT_64XX) {
3820                 s = &dev->subdevices[3];
3821                 s->type = COMEDI_SUBD_DO;
3822                 s->subdev_flags = SDF_WRITABLE;
3823                 s->n_chan = 4;
3824                 s->maxdata = 1;
3825                 s->range_table = &range_digital;
3826                 s->insn_bits = do_wbits;
3827         } else {
3828                 s->type = COMEDI_SUBD_UNUSED;
3829         }
3830
3831         /* 8255 */
3832         s = &dev->subdevices[4];
3833         if (thisboard->has_8255) {
3834                 if (thisboard->layout == LAYOUT_4020) {
3835                         ret = subdev_8255_init(dev, s, dio_callback_4020,
3836                                                I8255_4020_REG);
3837                 } else {
3838                         ret = subdev_8255_mm_init(dev, s, NULL,
3839                                                   DIO_8255_OFFSET);
3840                 }
3841                 if (ret)
3842                         return ret;
3843         } else {
3844                 s->type = COMEDI_SUBD_UNUSED;
3845         }
3846
3847         /*  8 channel dio for 60xx */
3848         s = &dev->subdevices[5];
3849         if (thisboard->layout == LAYOUT_60XX) {
3850                 s->type = COMEDI_SUBD_DIO;
3851                 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
3852                 s->n_chan = 8;
3853                 s->maxdata = 1;
3854                 s->range_table = &range_digital;
3855                 s->insn_config = dio_60xx_config_insn;
3856                 s->insn_bits = dio_60xx_wbits;
3857         } else {
3858                 s->type = COMEDI_SUBD_UNUSED;
3859         }
3860
3861         /*  caldac */
3862         s = &dev->subdevices[6];
3863         s->type = COMEDI_SUBD_CALIB;
3864         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3865         s->n_chan = 8;
3866         if (thisboard->layout == LAYOUT_4020)
3867                 s->maxdata = 0xfff;
3868         else
3869                 s->maxdata = 0xff;
3870         s->insn_write = cb_pcidas64_calib_insn_write;
3871
3872         ret = comedi_alloc_subdev_readback(s);
3873         if (ret)
3874                 return ret;
3875
3876         for (i = 0; i < s->n_chan; i++) {
3877                 caldac_write(dev, i, s->maxdata / 2);
3878                 s->readback[i] = s->maxdata / 2;
3879         }
3880
3881         /*  2 channel ad8402 potentiometer */
3882         s = &dev->subdevices[7];
3883         if (thisboard->layout == LAYOUT_64XX) {
3884                 s->type = COMEDI_SUBD_CALIB;
3885                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3886                 s->n_chan = 2;
3887                 s->maxdata = 0xff;
3888                 s->insn_write = cb_pcidas64_ad8402_insn_write;
3889
3890                 ret = comedi_alloc_subdev_readback(s);
3891                 if (ret)
3892                         return ret;
3893
3894                 for (i = 0; i < s->n_chan; i++) {
3895                         ad8402_write(dev, i, s->maxdata / 2);
3896                         s->readback[i] = s->maxdata / 2;
3897                 }
3898         } else {
3899                 s->type = COMEDI_SUBD_UNUSED;
3900         }
3901
3902         /* serial EEPROM, if present */
3903         s = &dev->subdevices[8];
3904         if (readl(devpriv->plx9080_iobase + PLX_CONTROL_REG) & CTL_EECHK) {
3905                 s->type = COMEDI_SUBD_MEMORY;
3906                 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
3907                 s->n_chan = 128;
3908                 s->maxdata = 0xffff;
3909                 s->insn_read = eeprom_read_insn;
3910         } else {
3911                 s->type = COMEDI_SUBD_UNUSED;
3912         }
3913
3914         /*  user counter subd XXX */
3915         s = &dev->subdevices[9];
3916         s->type = COMEDI_SUBD_UNUSED;
3917
3918         return 0;
3919 }
3920
3921 static int auto_attach(struct comedi_device *dev,
3922                        unsigned long context)
3923 {
3924         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
3925         const struct pcidas64_board *thisboard = NULL;
3926         struct pcidas64_private *devpriv;
3927         uint32_t local_range, local_decode;
3928         int retval;
3929
3930         if (context < ARRAY_SIZE(pcidas64_boards))
3931                 thisboard = &pcidas64_boards[context];
3932         if (!thisboard)
3933                 return -ENODEV;
3934         dev->board_ptr = thisboard;
3935
3936         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
3937         if (!devpriv)
3938                 return -ENOMEM;
3939
3940         retval = comedi_pci_enable(dev);
3941         if (retval)
3942                 return retval;
3943         pci_set_master(pcidev);
3944
3945         /* Initialize dev->board_name */
3946         dev->board_name = thisboard->name;
3947
3948         devpriv->main_phys_iobase = pci_resource_start(pcidev, 2);
3949         devpriv->dio_counter_phys_iobase = pci_resource_start(pcidev, 3);
3950
3951         devpriv->plx9080_iobase = pci_ioremap_bar(pcidev, 0);
3952         devpriv->main_iobase = pci_ioremap_bar(pcidev, 2);
3953         dev->mmio = pci_ioremap_bar(pcidev, 3);
3954
3955         if (!devpriv->plx9080_iobase || !devpriv->main_iobase || !dev->mmio) {
3956                 dev_warn(dev->class_dev, "failed to remap io memory\n");
3957                 return -ENOMEM;
3958         }
3959
3960         /*  figure out what local addresses are */
3961         local_range = readl(devpriv->plx9080_iobase + PLX_LAS0RNG_REG) &
3962                       LRNG_MEM_MASK;
3963         local_decode = readl(devpriv->plx9080_iobase + PLX_LAS0MAP_REG) &
3964                        local_range & LMAP_MEM_MASK;
3965         devpriv->local0_iobase = ((uint32_t)devpriv->main_phys_iobase &
3966                                   ~local_range) | local_decode;
3967         local_range = readl(devpriv->plx9080_iobase + PLX_LAS1RNG_REG) &
3968                       LRNG_MEM_MASK;
3969         local_decode = readl(devpriv->plx9080_iobase + PLX_LAS1MAP_REG) &
3970                        local_range & LMAP_MEM_MASK;
3971         devpriv->local1_iobase = ((uint32_t)devpriv->dio_counter_phys_iobase &
3972                                   ~local_range) | local_decode;
3973
3974         retval = alloc_and_init_dma_members(dev);
3975         if (retval < 0)
3976                 return retval;
3977
3978         devpriv->hw_revision =
3979                 hw_revision(dev, readw(devpriv->main_iobase + HW_STATUS_REG));
3980         dev_dbg(dev->class_dev, "stc hardware revision %i\n",
3981                 devpriv->hw_revision);
3982         init_plx9080(dev);
3983         init_stc_registers(dev);
3984
3985         retval = request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
3986                              dev->board_name, dev);
3987         if (retval) {
3988                 dev_dbg(dev->class_dev, "unable to allocate irq %u\n",
3989                         pcidev->irq);
3990                 return retval;
3991         }
3992         dev->irq = pcidev->irq;
3993         dev_dbg(dev->class_dev, "irq %u\n", dev->irq);
3994
3995         retval = setup_subdevices(dev);
3996         if (retval < 0)
3997                 return retval;
3998
3999         return 0;
4000 }
4001
4002 static void detach(struct comedi_device *dev)
4003 {
4004         struct pcidas64_private *devpriv = dev->private;
4005
4006         if (dev->irq)
4007                 free_irq(dev->irq, dev);
4008         if (devpriv) {
4009                 if (devpriv->plx9080_iobase) {
4010                         disable_plx_interrupts(dev);
4011                         iounmap(devpriv->plx9080_iobase);
4012                 }
4013                 if (devpriv->main_iobase)
4014                         iounmap(devpriv->main_iobase);
4015                 if (dev->mmio)
4016                         iounmap(dev->mmio);
4017         }
4018         comedi_pci_disable(dev);
4019         cb_pcidas64_free_dma(dev);
4020 }
4021
4022 static struct comedi_driver cb_pcidas64_driver = {
4023         .driver_name    = "cb_pcidas64",
4024         .module         = THIS_MODULE,
4025         .auto_attach    = auto_attach,
4026         .detach         = detach,
4027 };
4028
4029 static int cb_pcidas64_pci_probe(struct pci_dev *dev,
4030                                  const struct pci_device_id *id)
4031 {
4032         return comedi_pci_auto_config(dev, &cb_pcidas64_driver,
4033                                       id->driver_data);
4034 }
4035
4036 static const struct pci_device_id cb_pcidas64_pci_table[] = {
4037         { PCI_VDEVICE(CB, 0x001d), BOARD_PCIDAS6402_16 },
4038         { PCI_VDEVICE(CB, 0x001e), BOARD_PCIDAS6402_12 },
4039         { PCI_VDEVICE(CB, 0x0035), BOARD_PCIDAS64_M1_16 },
4040         { PCI_VDEVICE(CB, 0x0036), BOARD_PCIDAS64_M2_16 },
4041         { PCI_VDEVICE(CB, 0x0037), BOARD_PCIDAS64_M3_16 },
4042         { PCI_VDEVICE(CB, 0x0052), BOARD_PCIDAS4020_12 },
4043         { PCI_VDEVICE(CB, 0x005d), BOARD_PCIDAS6023 },
4044         { PCI_VDEVICE(CB, 0x005e), BOARD_PCIDAS6025 },
4045         { PCI_VDEVICE(CB, 0x005f), BOARD_PCIDAS6030 },
4046         { PCI_VDEVICE(CB, 0x0060), BOARD_PCIDAS6031 },
4047         { PCI_VDEVICE(CB, 0x0061), BOARD_PCIDAS6032 },
4048         { PCI_VDEVICE(CB, 0x0062), BOARD_PCIDAS6033 },
4049         { PCI_VDEVICE(CB, 0x0063), BOARD_PCIDAS6034 },
4050         { PCI_VDEVICE(CB, 0x0064), BOARD_PCIDAS6035 },
4051         { PCI_VDEVICE(CB, 0x0065), BOARD_PCIDAS6040 },
4052         { PCI_VDEVICE(CB, 0x0066), BOARD_PCIDAS6052 },
4053         { PCI_VDEVICE(CB, 0x0067), BOARD_PCIDAS6070 },
4054         { PCI_VDEVICE(CB, 0x0068), BOARD_PCIDAS6071 },
4055         { PCI_VDEVICE(CB, 0x006f), BOARD_PCIDAS6036 },
4056         { PCI_VDEVICE(CB, 0x0078), BOARD_PCIDAS6013 },
4057         { PCI_VDEVICE(CB, 0x0079), BOARD_PCIDAS6014 },
4058         { 0 }
4059 };
4060 MODULE_DEVICE_TABLE(pci, cb_pcidas64_pci_table);
4061
4062 static struct pci_driver cb_pcidas64_pci_driver = {
4063         .name           = "cb_pcidas64",
4064         .id_table       = cb_pcidas64_pci_table,
4065         .probe          = cb_pcidas64_pci_probe,
4066         .remove         = comedi_pci_auto_unconfig,
4067 };
4068 module_comedi_pci_driver(cb_pcidas64_driver, cb_pcidas64_pci_driver);
4069
4070 MODULE_AUTHOR("Comedi http://www.comedi.org");
4071 MODULE_DESCRIPTION("Comedi low-level driver");
4072 MODULE_LICENSE("GPL");