2 comedi/drivers/cb_pcidas64.c
3 This is a driver for the ComputerBoards/MeasurementComputing PCI-DAS
4 64xx, 60xx, and 4020 cards.
6 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
7 Copyright (C) 2001, 2002 Frank Mori Hess
9 Thanks also go to the following people:
11 Steve Rosenbluth, for providing the source code for
12 his pci-das6402 driver, and source code for working QNX pci-6402
13 drivers by Greg Laird and Mariusz Bogacz. None of the code was
14 used directly here, but it was useful as an additional source of
15 documentation on how to program the boards.
17 John Sims, for much testing and feedback on pcidas-4020 support.
19 COMEDI - Linux Control and Measurement Device Interface
20 Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
22 This program is free software; you can redistribute it and/or modify
23 it under the terms of the GNU General Public License as published by
24 the Free Software Foundation; either version 2 of the License, or
25 (at your option) any later version.
27 This program is distributed in the hope that it will be useful,
28 but WITHOUT ANY WARRANTY; without even the implied warranty of
29 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 GNU General Public License for more details.
32 You should have received a copy of the GNU General Public License
33 along with this program; if not, write to the Free Software
34 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
36 ************************************************************************/
40 * Description: MeasurementComputing PCI-DAS64xx, 60XX, and 4020 series
41 * with the PLX 9080 PCI controller
42 * Author: Frank Mori Hess <fmhess@users.sourceforge.net>
44 * Updated: Fri, 02 Nov 2012 18:58:55 +0000
45 * Devices: [Measurement Computing] PCI-DAS6402/16 (cb_pcidas64),
46 * PCI-DAS6402/12, PCI-DAS64/M1/16, PCI-DAS64/M2/16,
47 * PCI-DAS64/M3/16, PCI-DAS6402/16/JR, PCI-DAS64/M1/16/JR,
48 * PCI-DAS64/M2/16/JR, PCI-DAS64/M3/16/JR, PCI-DAS64/M1/14,
49 * PCI-DAS64/M2/14, PCI-DAS64/M3/14, PCI-DAS6013, PCI-DAS6014,
50 * PCI-DAS6023, PCI-DAS6025, PCI-DAS6030,
51 * PCI-DAS6031, PCI-DAS6032, PCI-DAS6033, PCI-DAS6034,
52 * PCI-DAS6035, PCI-DAS6036, PCI-DAS6040, PCI-DAS6052,
53 * PCI-DAS6070, PCI-DAS6071, PCI-DAS4020/12
55 * Configuration options:
58 * Manual attachment of PCI cards with the comedi_config utility is not
59 * supported by this driver; they are attached automatically.
61 * These boards may be autocalibrated with the comedi_calibrate utility.
63 * To select the bnc trigger input on the 4020 (instead of the dio input),
64 * specify a nonzero channel in the chanspec. If you wish to use an external
65 * master clock on the 4020, you may do so by setting the scan_begin_src
66 * to TRIG_OTHER, and using an INSN_CONFIG_TIMER_1 configuration insn
67 * to configure the divisor to use for the external clock.
69 * Some devices are not identified because the PCI device IDs are not yet
70 * known. If you have such a board, please let the maintainers know.
76 make it return error if user attempts an ai command that uses the
77 external queue, and an ao command simultaneously user counter subdevice
78 there are a number of boards this driver will support when they are
79 fully released, but does not yet since the pci device id numbers
80 are not yet available.
82 support prescaled 100khz clock for slow pacing (not available on 6000
85 make ao fifo size adjustable like ai fifo
88 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
90 #include <linux/pci.h>
91 #include <linux/delay.h>
92 #include <linux/interrupt.h>
94 #include "../comedidev.h"
99 #include "comedi_fc.h"
101 #undef PCIDAS64_DEBUG /* disable debugging code */
102 /* #define PCIDAS64_DEBUG enable debugging code */
104 #ifdef PCIDAS64_DEBUG
105 #define DEBUG_PRINT(format, args...) pr_debug(format, ## args)
107 #define DEBUG_PRINT(format, args...) no_printk(format, ## args)
110 #define TIMER_BASE 25 /* 40MHz master clock */
111 /* 100kHz 'prescaled' clock for slow acquisition,
112 * maybe I'll support this someday */
113 #define PRESCALED_TIMER_BASE 10000
114 #define DMA_BUFFER_SIZE 0x1000
116 /* maximum value that can be loaded into board's 24-bit counters*/
117 static const int max_counter_value = 0xffffff;
119 /* PCI-DAS64xxx base addresses */
121 /* devpriv->main_iobase registers */
122 enum write_only_registers {
123 INTR_ENABLE_REG = 0x0, /* interrupt enable register */
124 HW_CONFIG_REG = 0x2, /* hardware config register */
126 DAQ_ATRIG_LOW_4020_REG = 0xc,
127 ADC_CONTROL0_REG = 0x10, /* adc control register 0 */
128 ADC_CONTROL1_REG = 0x12, /* adc control register 1 */
129 CALIBRATION_REG = 0x14,
130 /* lower 16 bits of adc sample interval counter */
131 ADC_SAMPLE_INTERVAL_LOWER_REG = 0x16,
132 /* upper 8 bits of adc sample interval counter */
133 ADC_SAMPLE_INTERVAL_UPPER_REG = 0x18,
134 /* lower 16 bits of delay interval counter */
135 ADC_DELAY_INTERVAL_LOWER_REG = 0x1a,
136 /* upper 8 bits of delay interval counter */
137 ADC_DELAY_INTERVAL_UPPER_REG = 0x1c,
138 /* lower 16 bits of hardware conversion/scan counter */
139 ADC_COUNT_LOWER_REG = 0x1e,
140 /* upper 8 bits of hardware conversion/scan counter */
141 ADC_COUNT_UPPER_REG = 0x20,
142 ADC_START_REG = 0x22, /* software trigger to start acquisition */
143 ADC_CONVERT_REG = 0x24, /* initiates single conversion */
144 ADC_QUEUE_CLEAR_REG = 0x26, /* clears adc queue */
145 ADC_QUEUE_LOAD_REG = 0x28, /* loads adc queue */
146 ADC_BUFFER_CLEAR_REG = 0x2a,
147 /* high channel for internal queue, use adc_chan_bits() inline above */
148 ADC_QUEUE_HIGH_REG = 0x2c,
149 DAC_CONTROL0_REG = 0x50, /* dac control register 0 */
150 DAC_CONTROL1_REG = 0x52, /* dac control register 0 */
151 /* lower 16 bits of dac sample interval counter */
152 DAC_SAMPLE_INTERVAL_LOWER_REG = 0x54,
153 /* upper 8 bits of dac sample interval counter */
154 DAC_SAMPLE_INTERVAL_UPPER_REG = 0x56,
155 DAC_SELECT_REG = 0x60,
156 DAC_START_REG = 0x64,
157 DAC_BUFFER_CLEAR_REG = 0x66, /* clear dac buffer */
160 static inline unsigned int dac_convert_reg(unsigned int channel)
162 return 0x70 + (2 * (channel & 0x1));
165 static inline unsigned int dac_lsb_4020_reg(unsigned int channel)
167 return 0x70 + (4 * (channel & 0x1));
170 static inline unsigned int dac_msb_4020_reg(unsigned int channel)
172 return 0x72 + (4 * (channel & 0x1));
175 enum read_only_registers {
176 /* hardware status register,
177 * reading this apparently clears pending interrupts as well */
179 PIPE1_READ_REG = 0x4,
180 ADC_READ_PNTR_REG = 0x8,
181 LOWER_XFER_REG = 0x10,
182 ADC_WRITE_PNTR_REG = 0xc,
186 enum read_write_registers {
187 I8255_4020_REG = 0x48, /* 8255 offset, for 4020 only */
188 /* external channel/gain queue, uses same bits as ADC_QUEUE_LOAD_REG */
189 ADC_QUEUE_FIFO_REG = 0x100,
190 ADC_FIFO_REG = 0x200, /* adc data fifo */
191 /* dac data fifo, has weird interactions with external channel queue */
192 DAC_FIFO_REG = 0x300,
195 /* devpriv->dio_counter_iobase registers */
196 enum dio_counter_registers {
197 DIO_8255_OFFSET = 0x0,
200 DIO_DIRECTION_60XX_REG = 0x40,
201 DIO_DATA_60XX_REG = 0x48,
204 /* bit definitions for write-only registers */
206 enum intr_enable_contents {
207 ADC_INTR_SRC_MASK = 0x3, /* adc interrupt source mask */
208 ADC_INTR_QFULL_BITS = 0x0, /* interrupt fifo quarter full */
209 ADC_INTR_EOC_BITS = 0x1, /* interrupt end of conversion */
210 ADC_INTR_EOSCAN_BITS = 0x2, /* interrupt end of scan */
211 ADC_INTR_EOSEQ_BITS = 0x3, /* interrupt end of sequence mask */
212 EN_ADC_INTR_SRC_BIT = 0x4, /* enable adc interrupt source */
213 EN_ADC_DONE_INTR_BIT = 0x8, /* enable adc acquisition done intr */
214 DAC_INTR_SRC_MASK = 0x30,
215 DAC_INTR_QEMPTY_BITS = 0x0,
216 DAC_INTR_HIGH_CHAN_BITS = 0x10,
217 EN_DAC_INTR_SRC_BIT = 0x40, /* enable dac interrupt source */
218 EN_DAC_DONE_INTR_BIT = 0x80,
219 EN_ADC_ACTIVE_INTR_BIT = 0x200, /* enable adc active interrupt */
220 EN_ADC_STOP_INTR_BIT = 0x400, /* enable adc stop trigger interrupt */
221 EN_DAC_ACTIVE_INTR_BIT = 0x800, /* enable dac active interrupt */
222 EN_DAC_UNDERRUN_BIT = 0x4000, /* enable dac underrun status bit */
223 EN_ADC_OVERRUN_BIT = 0x8000, /* enable adc overrun status bit */
226 enum hw_config_contents {
227 MASTER_CLOCK_4020_MASK = 0x3, /* master clock source mask for 4020 */
228 INTERNAL_CLOCK_4020_BITS = 0x1, /* use 40 MHz internal master clock */
229 BNC_CLOCK_4020_BITS = 0x2, /* use BNC input for master clock */
230 EXT_CLOCK_4020_BITS = 0x3, /* use dio input for master clock */
231 EXT_QUEUE_BIT = 0x200, /* use external channel/gain queue */
232 /* use 225 nanosec strobe when loading dac instead of 50 nanosec */
233 SLOW_DAC_BIT = 0x400,
234 /* bit with unknown function yet given as default value in pci-das64
236 HW_CONFIG_DUMMY_BITS = 0x2000,
237 /* bit selects channels 1/0 for analog input/output, otherwise 0/1 */
238 DMA_CH_SELECT_BIT = 0x8000,
239 FIFO_SIZE_REG = 0x4, /* allows adjustment of fifo sizes */
240 DAC_FIFO_SIZE_MASK = 0xff00, /* bits that set dac fifo size */
241 DAC_FIFO_BITS = 0xf800, /* 8k sample ao fifo */
243 #define DAC_FIFO_SIZE 0x2000
245 enum daq_atrig_low_4020_contents {
246 /* use trig/ext clk bnc input for analog gate signal */
247 EXT_AGATE_BNC_BIT = 0x8000,
248 /* use trig/ext clk bnc input for external stop trigger signal */
249 EXT_STOP_TRIG_BNC_BIT = 0x4000,
250 /* use trig/ext clk bnc input for external start trigger signal */
251 EXT_START_TRIG_BNC_BIT = 0x2000,
254 static inline uint16_t analog_trig_low_threshold_bits(uint16_t threshold)
256 return threshold & 0xfff;
259 enum adc_control0_contents {
260 ADC_GATE_SRC_MASK = 0x3, /* bits that select gate */
261 ADC_SOFT_GATE_BITS = 0x1, /* software gate */
262 ADC_EXT_GATE_BITS = 0x2, /* external digital gate */
263 ADC_ANALOG_GATE_BITS = 0x3, /* analog level gate */
264 ADC_GATE_LEVEL_BIT = 0x4, /* level-sensitive gate (for digital) */
265 ADC_GATE_POLARITY_BIT = 0x8, /* gate active low */
266 ADC_START_TRIG_SOFT_BITS = 0x10,
267 ADC_START_TRIG_EXT_BITS = 0x20,
268 ADC_START_TRIG_ANALOG_BITS = 0x30,
269 ADC_START_TRIG_MASK = 0x30,
270 ADC_START_TRIG_FALLING_BIT = 0x40, /* trig 1 uses falling edge */
271 /* external pacing uses falling edge */
272 ADC_EXT_CONV_FALLING_BIT = 0x800,
273 /* enable hardware scan counter */
274 ADC_SAMPLE_COUNTER_EN_BIT = 0x1000,
275 ADC_DMA_DISABLE_BIT = 0x4000, /* disables dma */
276 ADC_ENABLE_BIT = 0x8000, /* master adc enable */
279 enum adc_control1_contents {
280 /* should be set for boards with > 16 channels */
281 ADC_QUEUE_CONFIG_BIT = 0x1,
282 CONVERT_POLARITY_BIT = 0x10,
283 EOC_POLARITY_BIT = 0x20,
284 ADC_SW_GATE_BIT = 0x40, /* software gate of adc */
285 ADC_DITHER_BIT = 0x200, /* turn on extra noise for dithering */
286 RETRIGGER_BIT = 0x800,
287 ADC_LO_CHANNEL_4020_MASK = 0x300,
288 ADC_HI_CHANNEL_4020_MASK = 0xc00,
289 TWO_CHANNEL_4020_BITS = 0x1000, /* two channel mode for 4020 */
290 FOUR_CHANNEL_4020_BITS = 0x2000, /* four channel mode for 4020 */
291 CHANNEL_MODE_4020_MASK = 0x3000,
292 ADC_MODE_MASK = 0xf000,
295 static inline uint16_t adc_lo_chan_4020_bits(unsigned int channel)
297 return (channel & 0x3) << 8;
300 static inline uint16_t adc_hi_chan_4020_bits(unsigned int channel)
302 return (channel & 0x3) << 10;
305 static inline uint16_t adc_mode_bits(unsigned int mode)
307 return (mode & 0xf) << 12;
310 enum calibration_contents {
311 SELECT_8800_BIT = 0x1,
312 SELECT_8402_64XX_BIT = 0x2,
313 SELECT_1590_60XX_BIT = 0x2,
314 CAL_EN_64XX_BIT = 0x40, /* calibration enable for 64xx series */
315 SERIAL_DATA_IN_BIT = 0x80,
316 SERIAL_CLOCK_BIT = 0x100,
317 CAL_EN_60XX_BIT = 0x200, /* calibration enable for 60xx series */
318 CAL_GAIN_BIT = 0x800,
321 /* calibration sources for 6025 are:
332 static inline uint16_t adc_src_bits(unsigned int source)
334 return (source & 0xf) << 3;
337 static inline uint16_t adc_convert_chan_4020_bits(unsigned int channel)
339 return (channel & 0x3) << 8;
342 enum adc_queue_load_contents {
343 UNIP_BIT = 0x800, /* unipolar/bipolar bit */
344 ADC_SE_DIFF_BIT = 0x1000, /* single-ended/ differential bit */
345 /* non-referenced single-ended (common-mode input) */
346 ADC_COMMON_BIT = 0x2000,
347 QUEUE_EOSEQ_BIT = 0x4000, /* queue end of sequence */
348 QUEUE_EOSCAN_BIT = 0x8000, /* queue end of scan */
351 static inline uint16_t adc_chan_bits(unsigned int channel)
353 return channel & 0x3f;
356 enum dac_control0_contents {
357 DAC_ENABLE_BIT = 0x8000, /* dac controller enable bit */
358 DAC_CYCLIC_STOP_BIT = 0x4000,
359 DAC_WAVEFORM_MODE_BIT = 0x100,
360 DAC_EXT_UPDATE_FALLING_BIT = 0x80,
361 DAC_EXT_UPDATE_ENABLE_BIT = 0x40,
362 WAVEFORM_TRIG_MASK = 0x30,
363 WAVEFORM_TRIG_DISABLED_BITS = 0x0,
364 WAVEFORM_TRIG_SOFT_BITS = 0x10,
365 WAVEFORM_TRIG_EXT_BITS = 0x20,
366 WAVEFORM_TRIG_ADC1_BITS = 0x30,
367 WAVEFORM_TRIG_FALLING_BIT = 0x8,
368 WAVEFORM_GATE_LEVEL_BIT = 0x4,
369 WAVEFORM_GATE_ENABLE_BIT = 0x2,
370 WAVEFORM_GATE_SELECT_BIT = 0x1,
373 enum dac_control1_contents {
374 DAC_WRITE_POLARITY_BIT = 0x800, /* board-dependent setting */
375 DAC1_EXT_REF_BIT = 0x200,
376 DAC0_EXT_REF_BIT = 0x100,
377 DAC_OUTPUT_ENABLE_BIT = 0x80, /* dac output enable bit */
378 DAC_UPDATE_POLARITY_BIT = 0x40, /* board-dependent setting */
379 DAC_SW_GATE_BIT = 0x20,
380 DAC1_UNIPOLAR_BIT = 0x8,
381 DAC0_UNIPOLAR_BIT = 0x2,
384 /* bit definitions for read-only registers */
385 enum hw_status_contents {
386 DAC_UNDERRUN_BIT = 0x1,
387 ADC_OVERRUN_BIT = 0x2,
388 DAC_ACTIVE_BIT = 0x4,
389 ADC_ACTIVE_BIT = 0x8,
390 DAC_INTR_PENDING_BIT = 0x10,
391 ADC_INTR_PENDING_BIT = 0x20,
394 EXT_INTR_PENDING_BIT = 0x100,
395 ADC_STOP_BIT = 0x200,
398 static inline uint16_t pipe_full_bits(uint16_t hw_status_bits)
400 return (hw_status_bits >> 10) & 0x3;
403 static inline unsigned int dma_chain_flag_bits(uint16_t prepost_bits)
405 return (prepost_bits >> 6) & 0x3;
408 static inline unsigned int adc_upper_read_ptr_code(uint16_t prepost_bits)
410 return (prepost_bits >> 12) & 0x3;
413 static inline unsigned int adc_upper_write_ptr_code(uint16_t prepost_bits)
415 return (prepost_bits >> 14) & 0x3;
418 /* I2C addresses for 4020 */
420 RANGE_CAL_I2C_ADDR = 0x20,
421 CALDAC0_I2C_ADDR = 0xc,
422 CALDAC1_I2C_ADDR = 0xd,
425 enum range_cal_i2c_contents {
426 /* bits that set what source the adc converter measures */
427 ADC_SRC_4020_MASK = 0x70,
428 /* make bnc trig/ext clock threshold 0V instead of 2.5V */
429 BNC_TRIG_THRESHOLD_0V_BIT = 0x80,
432 static inline uint8_t adc_src_4020_bits(unsigned int source)
434 return (source << 4) & ADC_SRC_4020_MASK;
437 static inline uint8_t attenuate_bit(unsigned int channel)
439 /* attenuate channel (+-5V input range) */
440 return 1 << (channel & 0x3);
443 /* analog input ranges for 64xx boards */
444 static const struct comedi_lrange ai_ranges_64xx = {
458 /* analog input ranges for 60xx boards */
459 static const struct comedi_lrange ai_ranges_60xx = {
469 /* analog input ranges for 6030, etc boards */
470 static const struct comedi_lrange ai_ranges_6030 = {
490 /* analog input ranges for 6052, etc boards */
491 static const struct comedi_lrange ai_ranges_6052 = {
512 /* analog input ranges for 4020 board */
513 static const struct comedi_lrange ai_ranges_4020 = {
521 /* analog output ranges */
522 static const struct comedi_lrange ao_ranges_64xx = {
532 static const int ao_range_code_64xx[] = {
539 static const int ao_range_code_60xx[] = {
543 static const struct comedi_lrange ao_ranges_6030 = {
551 static const int ao_range_code_6030[] = {
556 static const struct comedi_lrange ao_ranges_4020 = {
564 static const int ao_range_code_4020[] = {
569 enum register_layout {
575 struct hw_fifo_info {
576 unsigned int num_segments;
577 unsigned int max_segment_length;
578 unsigned int sample_packing_ratio;
579 uint16_t fifo_size_reg_mask;
582 enum pcidas64_boardid {
585 BOARD_PCIDAS64_M1_16,
586 BOARD_PCIDAS64_M2_16,
587 BOARD_PCIDAS64_M3_16,
604 BOARD_PCIDAS6402_16_JR,
605 BOARD_PCIDAS64_M1_16_JR,
606 BOARD_PCIDAS64_M2_16_JR,
607 BOARD_PCIDAS64_M3_16_JR,
608 BOARD_PCIDAS64_M1_14,
609 BOARD_PCIDAS64_M2_14,
610 BOARD_PCIDAS64_M3_14,
613 struct pcidas64_board {
615 int ai_se_chans; /* number of ai inputs in single-ended mode */
616 int ai_bits; /* analog input resolution */
617 int ai_speed; /* fastest conversion period in ns */
618 const struct comedi_lrange *ai_range_table;
619 int ao_nchan; /* number of analog out channels */
620 int ao_bits; /* analog output resolution */
621 int ao_scan_speed; /* analog output scan speed */
622 const struct comedi_lrange *ao_range_table;
623 const int *ao_range_code;
624 const struct hw_fifo_info *const ai_fifo;
625 /* different board families have slightly different registers */
626 enum register_layout layout;
630 static const struct hw_fifo_info ai_fifo_4020 = {
632 .max_segment_length = 0x8000,
633 .sample_packing_ratio = 2,
634 .fifo_size_reg_mask = 0x7f,
637 static const struct hw_fifo_info ai_fifo_64xx = {
639 .max_segment_length = 0x800,
640 .sample_packing_ratio = 1,
641 .fifo_size_reg_mask = 0x3f,
644 static const struct hw_fifo_info ai_fifo_60xx = {
646 .max_segment_length = 0x800,
647 .sample_packing_ratio = 1,
648 .fifo_size_reg_mask = 0x7f,
651 /* maximum number of dma transfers we will chain together into a ring
652 * (and the maximum number of dma buffers we maintain) */
653 #define MAX_AI_DMA_RING_COUNT (0x80000 / DMA_BUFFER_SIZE)
654 #define MIN_AI_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
655 #define AO_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
656 static inline unsigned int ai_dma_ring_count(const struct pcidas64_board *board)
658 if (board->layout == LAYOUT_4020)
659 return MAX_AI_DMA_RING_COUNT;
661 return MIN_AI_DMA_RING_COUNT;
664 static const int bytes_in_sample = 2;
666 static const struct pcidas64_board pcidas64_boards[] = {
667 [BOARD_PCIDAS6402_16] = {
668 .name = "pci-das6402/16",
674 .ao_scan_speed = 10000,
675 .layout = LAYOUT_64XX,
676 .ai_range_table = &ai_ranges_64xx,
677 .ao_range_table = &ao_ranges_64xx,
678 .ao_range_code = ao_range_code_64xx,
679 .ai_fifo = &ai_fifo_64xx,
682 [BOARD_PCIDAS6402_12] = {
683 .name = "pci-das6402/12", /* XXX check */
689 .ao_scan_speed = 10000,
690 .layout = LAYOUT_64XX,
691 .ai_range_table = &ai_ranges_64xx,
692 .ao_range_table = &ao_ranges_64xx,
693 .ao_range_code = ao_range_code_64xx,
694 .ai_fifo = &ai_fifo_64xx,
697 [BOARD_PCIDAS64_M1_16] = {
698 .name = "pci-das64/m1/16",
704 .ao_scan_speed = 10000,
705 .layout = LAYOUT_64XX,
706 .ai_range_table = &ai_ranges_64xx,
707 .ao_range_table = &ao_ranges_64xx,
708 .ao_range_code = ao_range_code_64xx,
709 .ai_fifo = &ai_fifo_64xx,
712 [BOARD_PCIDAS64_M2_16] = {
713 .name = "pci-das64/m2/16",
719 .ao_scan_speed = 10000,
720 .layout = LAYOUT_64XX,
721 .ai_range_table = &ai_ranges_64xx,
722 .ao_range_table = &ao_ranges_64xx,
723 .ao_range_code = ao_range_code_64xx,
724 .ai_fifo = &ai_fifo_64xx,
727 [BOARD_PCIDAS64_M3_16] = {
728 .name = "pci-das64/m3/16",
734 .ao_scan_speed = 10000,
735 .layout = LAYOUT_64XX,
736 .ai_range_table = &ai_ranges_64xx,
737 .ao_range_table = &ao_ranges_64xx,
738 .ao_range_code = ao_range_code_64xx,
739 .ai_fifo = &ai_fifo_64xx,
742 [BOARD_PCIDAS6013] = {
743 .name = "pci-das6013",
749 .layout = LAYOUT_60XX,
750 .ai_range_table = &ai_ranges_60xx,
751 .ao_range_table = &range_bipolar10,
752 .ao_range_code = ao_range_code_60xx,
753 .ai_fifo = &ai_fifo_60xx,
756 [BOARD_PCIDAS6014] = {
757 .name = "pci-das6014",
763 .ao_scan_speed = 100000,
764 .layout = LAYOUT_60XX,
765 .ai_range_table = &ai_ranges_60xx,
766 .ao_range_table = &range_bipolar10,
767 .ao_range_code = ao_range_code_60xx,
768 .ai_fifo = &ai_fifo_60xx,
771 [BOARD_PCIDAS6023] = {
772 .name = "pci-das6023",
777 .ao_scan_speed = 100000,
778 .layout = LAYOUT_60XX,
779 .ai_range_table = &ai_ranges_60xx,
780 .ao_range_table = &range_bipolar10,
781 .ao_range_code = ao_range_code_60xx,
782 .ai_fifo = &ai_fifo_60xx,
785 [BOARD_PCIDAS6025] = {
786 .name = "pci-das6025",
792 .ao_scan_speed = 100000,
793 .layout = LAYOUT_60XX,
794 .ai_range_table = &ai_ranges_60xx,
795 .ao_range_table = &range_bipolar10,
796 .ao_range_code = ao_range_code_60xx,
797 .ai_fifo = &ai_fifo_60xx,
800 [BOARD_PCIDAS6030] = {
801 .name = "pci-das6030",
807 .ao_scan_speed = 10000,
808 .layout = LAYOUT_60XX,
809 .ai_range_table = &ai_ranges_6030,
810 .ao_range_table = &ao_ranges_6030,
811 .ao_range_code = ao_range_code_6030,
812 .ai_fifo = &ai_fifo_60xx,
815 [BOARD_PCIDAS6031] = {
816 .name = "pci-das6031",
822 .ao_scan_speed = 10000,
823 .layout = LAYOUT_60XX,
824 .ai_range_table = &ai_ranges_6030,
825 .ao_range_table = &ao_ranges_6030,
826 .ao_range_code = ao_range_code_6030,
827 .ai_fifo = &ai_fifo_60xx,
830 [BOARD_PCIDAS6032] = {
831 .name = "pci-das6032",
836 .layout = LAYOUT_60XX,
837 .ai_range_table = &ai_ranges_6030,
838 .ai_fifo = &ai_fifo_60xx,
841 [BOARD_PCIDAS6033] = {
842 .name = "pci-das6033",
847 .layout = LAYOUT_60XX,
848 .ai_range_table = &ai_ranges_6030,
849 .ai_fifo = &ai_fifo_60xx,
852 [BOARD_PCIDAS6034] = {
853 .name = "pci-das6034",
859 .layout = LAYOUT_60XX,
860 .ai_range_table = &ai_ranges_60xx,
861 .ai_fifo = &ai_fifo_60xx,
864 [BOARD_PCIDAS6035] = {
865 .name = "pci-das6035",
871 .ao_scan_speed = 100000,
872 .layout = LAYOUT_60XX,
873 .ai_range_table = &ai_ranges_60xx,
874 .ao_range_table = &range_bipolar10,
875 .ao_range_code = ao_range_code_60xx,
876 .ai_fifo = &ai_fifo_60xx,
879 [BOARD_PCIDAS6036] = {
880 .name = "pci-das6036",
886 .ao_scan_speed = 100000,
887 .layout = LAYOUT_60XX,
888 .ai_range_table = &ai_ranges_60xx,
889 .ao_range_table = &range_bipolar10,
890 .ao_range_code = ao_range_code_60xx,
891 .ai_fifo = &ai_fifo_60xx,
894 [BOARD_PCIDAS6040] = {
895 .name = "pci-das6040",
901 .ao_scan_speed = 1000,
902 .layout = LAYOUT_60XX,
903 .ai_range_table = &ai_ranges_6052,
904 .ao_range_table = &ao_ranges_6030,
905 .ao_range_code = ao_range_code_6030,
906 .ai_fifo = &ai_fifo_60xx,
909 [BOARD_PCIDAS6052] = {
910 .name = "pci-das6052",
916 .ao_scan_speed = 3333,
917 .layout = LAYOUT_60XX,
918 .ai_range_table = &ai_ranges_6052,
919 .ao_range_table = &ao_ranges_6030,
920 .ao_range_code = ao_range_code_6030,
921 .ai_fifo = &ai_fifo_60xx,
924 [BOARD_PCIDAS6070] = {
925 .name = "pci-das6070",
931 .ao_scan_speed = 1000,
932 .layout = LAYOUT_60XX,
933 .ai_range_table = &ai_ranges_6052,
934 .ao_range_table = &ao_ranges_6030,
935 .ao_range_code = ao_range_code_6030,
936 .ai_fifo = &ai_fifo_60xx,
939 [BOARD_PCIDAS6071] = {
940 .name = "pci-das6071",
946 .ao_scan_speed = 1000,
947 .layout = LAYOUT_60XX,
948 .ai_range_table = &ai_ranges_6052,
949 .ao_range_table = &ao_ranges_6030,
950 .ao_range_code = ao_range_code_6030,
951 .ai_fifo = &ai_fifo_60xx,
954 [BOARD_PCIDAS4020_12] = {
955 .name = "pci-das4020/12",
961 .ao_scan_speed = 0, /* no hardware pacing on ao */
962 .layout = LAYOUT_4020,
963 .ai_range_table = &ai_ranges_4020,
964 .ao_range_table = &ao_ranges_4020,
965 .ao_range_code = ao_range_code_4020,
966 .ai_fifo = &ai_fifo_4020,
971 * The device id for these boards is unknown
974 [BOARD_PCIDAS6402_16_JR] = {
975 .name = "pci-das6402/16/jr",
980 .ao_scan_speed = 10000,
981 .layout = LAYOUT_64XX,
982 .ai_range_table = &ai_ranges_64xx,
983 .ai_fifo = ai_fifo_64xx,
986 [BOARD_PCIDAS64_M1_16_JR] = {
987 .name = "pci-das64/m1/16/jr",
992 .ao_scan_speed = 10000,
993 .layout = LAYOUT_64XX,
994 .ai_range_table = &ai_ranges_64xx,
995 .ai_fifo = ai_fifo_64xx,
998 [BOARD_PCIDAS64_M2_16_JR] = {
999 .name = "pci-das64/m2/16/jr",
1004 .ao_scan_speed = 10000,
1005 .layout = LAYOUT_64XX,
1006 .ai_range_table = &ai_ranges_64xx,
1007 .ai_fifo = ai_fifo_64xx,
1010 [BOARD_PCIDAS64_M3_16_JR] = {
1011 .name = "pci-das64/m3/16/jr",
1016 .ao_scan_speed = 10000,
1017 .layout = LAYOUT_64XX,
1018 .ai_range_table = &ai_ranges_64xx,
1019 .ai_fifo = ai_fifo_64xx,
1022 [BOARD_PCIDAS64_M1_14] = {
1023 .name = "pci-das64/m1/14",
1028 .ao_scan_speed = 10000,
1029 .layout = LAYOUT_64XX,
1030 .ai_range_table = &ai_ranges_64xx,
1031 .ai_fifo = ai_fifo_64xx,
1034 [BOARD_PCIDAS64_M2_14] = {
1035 .name = "pci-das64/m2/14",
1040 .ao_scan_speed = 10000,
1041 .layout = LAYOUT_64XX,
1042 .ai_range_table = &ai_ranges_64xx,
1043 .ai_fifo = ai_fifo_64xx,
1046 [BOARD_PCIDAS64_M3_14] = {
1047 .name = "pci-das64/m3/14",
1052 .ao_scan_speed = 10000,
1053 .layout = LAYOUT_64XX,
1054 .ai_range_table = &ai_ranges_64xx,
1055 .ai_fifo = ai_fifo_64xx,
1061 static inline unsigned short se_diff_bit_6xxx(struct comedi_device *dev,
1062 int use_differential)
1064 const struct pcidas64_board *thisboard = comedi_board(dev);
1066 if ((thisboard->layout == LAYOUT_64XX && !use_differential) ||
1067 (thisboard->layout == LAYOUT_60XX && use_differential))
1068 return ADC_SE_DIFF_BIT;
1073 struct ext_clock_info {
1074 /* master clock divisor to use for scans with external master clock */
1075 unsigned int divisor;
1076 /* chanspec for master clock input when used as scan begin src */
1077 unsigned int chanspec;
1080 /* this structure is for data unique to this hardware driver. */
1081 struct pcidas64_private {
1082 /* base addresses (physical) */
1083 resource_size_t main_phys_iobase;
1084 resource_size_t dio_counter_phys_iobase;
1085 /* base addresses (ioremapped) */
1086 void __iomem *plx9080_iobase;
1087 void __iomem *main_iobase;
1088 void __iomem *dio_counter_iobase;
1089 /* local address (used by dma controller) */
1090 uint32_t local0_iobase;
1091 uint32_t local1_iobase;
1092 /* number of analog input samples remaining */
1093 volatile unsigned int ai_count;
1094 /* dma buffers for analog input */
1095 uint16_t *ai_buffer[MAX_AI_DMA_RING_COUNT];
1096 /* physical addresses of ai dma buffers */
1097 dma_addr_t ai_buffer_bus_addr[MAX_AI_DMA_RING_COUNT];
1098 /* array of ai dma descriptors read by plx9080,
1099 * allocated to get proper alignment */
1100 struct plx_dma_desc *ai_dma_desc;
1101 /* physical address of ai dma descriptor array */
1102 dma_addr_t ai_dma_desc_bus_addr;
1103 /* index of the ai dma descriptor/buffer
1104 * that is currently being used */
1105 volatile unsigned int ai_dma_index;
1106 /* dma buffers for analog output */
1107 uint16_t *ao_buffer[AO_DMA_RING_COUNT];
1108 /* physical addresses of ao dma buffers */
1109 dma_addr_t ao_buffer_bus_addr[AO_DMA_RING_COUNT];
1110 struct plx_dma_desc *ao_dma_desc;
1111 dma_addr_t ao_dma_desc_bus_addr;
1112 /* keeps track of buffer where the next ao sample should go */
1113 volatile unsigned int ao_dma_index;
1114 /* number of analog output samples remaining */
1115 volatile unsigned long ao_count;
1116 /* remember what the analog outputs are set to, to allow readback */
1117 volatile unsigned int ao_value[2];
1118 unsigned int hw_revision; /* stc chip hardware revision number */
1119 /* last bits sent to INTR_ENABLE_REG register */
1120 volatile unsigned int intr_enable_bits;
1121 /* last bits sent to ADC_CONTROL1_REG register */
1122 volatile uint16_t adc_control1_bits;
1123 /* last bits sent to FIFO_SIZE_REG register */
1124 volatile uint16_t fifo_size_bits;
1125 /* last bits sent to HW_CONFIG_REG register */
1126 volatile uint16_t hw_config_bits;
1127 volatile uint16_t dac_control1_bits;
1128 /* last bits written to plx9080 control register */
1129 volatile uint32_t plx_control_bits;
1130 /* last bits written to plx interrupt control and status register */
1131 volatile uint32_t plx_intcsr_bits;
1132 /* index of calibration source readable through ai ch0 */
1133 volatile int calibration_source;
1134 /* bits written to i2c calibration/range register */
1135 volatile uint8_t i2c_cal_range_bits;
1136 /* configure digital triggers to trigger on falling edge */
1137 volatile unsigned int ext_trig_falling;
1138 /* states of various devices stored to enable read-back */
1139 unsigned int ad8402_state[2];
1140 unsigned int caldac_state[8];
1141 volatile short ai_cmd_running;
1142 unsigned int ai_fifo_segment_length;
1143 struct ext_clock_info ext_clock;
1144 short ao_bounce_buffer[DAC_FIFO_SIZE];
1147 static unsigned int ai_range_bits_6xxx(const struct comedi_device *dev,
1148 unsigned int range_index)
1150 const struct pcidas64_board *thisboard = comedi_board(dev);
1151 const struct comedi_krange *range =
1152 &thisboard->ai_range_table->range[range_index];
1153 unsigned int bits = 0;
1155 switch (range->max) {
1184 comedi_error(dev, "bug! in ai_range_bits_6xxx");
1187 if (range->min == 0)
1192 static unsigned int hw_revision(const struct comedi_device *dev,
1193 uint16_t hw_status_bits)
1195 const struct pcidas64_board *thisboard = comedi_board(dev);
1197 if (thisboard->layout == LAYOUT_4020)
1198 return (hw_status_bits >> 13) & 0x7;
1200 return (hw_status_bits >> 12) & 0xf;
1203 static void set_dac_range_bits(struct comedi_device *dev,
1204 volatile uint16_t *bits, unsigned int channel,
1207 const struct pcidas64_board *thisboard = comedi_board(dev);
1208 unsigned int code = thisboard->ao_range_code[range];
1211 comedi_error(dev, "bug! bad channel?");
1213 comedi_error(dev, "bug! bad range code?");
1215 *bits &= ~(0x3 << (2 * channel));
1216 *bits |= code << (2 * channel);
1219 static inline int ao_cmd_is_supported(const struct pcidas64_board *board)
1221 return board->ao_nchan && board->layout != LAYOUT_4020;
1224 static void abort_dma(struct comedi_device *dev, unsigned int channel)
1226 struct pcidas64_private *devpriv = dev->private;
1227 unsigned long flags;
1229 /* spinlock for plx dma control/status reg */
1230 spin_lock_irqsave(&dev->spinlock, flags);
1232 plx9080_abort_dma(devpriv->plx9080_iobase, channel);
1234 spin_unlock_irqrestore(&dev->spinlock, flags);
1237 static void disable_plx_interrupts(struct comedi_device *dev)
1239 struct pcidas64_private *devpriv = dev->private;
1241 devpriv->plx_intcsr_bits = 0;
1242 writel(devpriv->plx_intcsr_bits,
1243 devpriv->plx9080_iobase + PLX_INTRCS_REG);
1246 static void disable_ai_interrupts(struct comedi_device *dev)
1248 struct pcidas64_private *devpriv = dev->private;
1249 unsigned long flags;
1251 spin_lock_irqsave(&dev->spinlock, flags);
1252 devpriv->intr_enable_bits &=
1253 ~EN_ADC_INTR_SRC_BIT & ~EN_ADC_DONE_INTR_BIT &
1254 ~EN_ADC_ACTIVE_INTR_BIT & ~EN_ADC_STOP_INTR_BIT &
1255 ~EN_ADC_OVERRUN_BIT & ~ADC_INTR_SRC_MASK;
1256 writew(devpriv->intr_enable_bits,
1257 devpriv->main_iobase + INTR_ENABLE_REG);
1258 spin_unlock_irqrestore(&dev->spinlock, flags);
1260 DEBUG_PRINT("intr enable bits 0x%x\n", devpriv->intr_enable_bits);
1263 static void enable_ai_interrupts(struct comedi_device *dev,
1264 const struct comedi_cmd *cmd)
1266 const struct pcidas64_board *thisboard = comedi_board(dev);
1267 struct pcidas64_private *devpriv = dev->private;
1269 unsigned long flags;
1271 bits = EN_ADC_OVERRUN_BIT | EN_ADC_DONE_INTR_BIT |
1272 EN_ADC_ACTIVE_INTR_BIT | EN_ADC_STOP_INTR_BIT;
1273 /* Use pio transfer and interrupt on end of conversion
1274 * if TRIG_WAKE_EOS flag is set. */
1275 if (cmd->flags & TRIG_WAKE_EOS) {
1276 /* 4020 doesn't support pio transfers except for fifo dregs */
1277 if (thisboard->layout != LAYOUT_4020)
1278 bits |= ADC_INTR_EOSCAN_BITS | EN_ADC_INTR_SRC_BIT;
1280 spin_lock_irqsave(&dev->spinlock, flags);
1281 devpriv->intr_enable_bits |= bits;
1282 writew(devpriv->intr_enable_bits,
1283 devpriv->main_iobase + INTR_ENABLE_REG);
1284 DEBUG_PRINT("intr enable bits 0x%x\n", devpriv->intr_enable_bits);
1285 spin_unlock_irqrestore(&dev->spinlock, flags);
1288 /* initialize plx9080 chip */
1289 static void init_plx9080(struct comedi_device *dev)
1291 const struct pcidas64_board *thisboard = comedi_board(dev);
1292 struct pcidas64_private *devpriv = dev->private;
1294 void __iomem *plx_iobase = devpriv->plx9080_iobase;
1296 devpriv->plx_control_bits =
1297 readl(devpriv->plx9080_iobase + PLX_CONTROL_REG);
1300 DEBUG_PRINT(" plx interrupt status 0x%x\n",
1301 readl(plx_iobase + PLX_INTRCS_REG));
1302 DEBUG_PRINT(" plx id bits 0x%x\n", readl(plx_iobase + PLX_ID_REG));
1303 DEBUG_PRINT(" plx control reg 0x%x\n", devpriv->plx_control_bits);
1304 DEBUG_PRINT(" plx mode/arbitration reg 0x%x\n",
1305 readl(plx_iobase + PLX_MARB_REG));
1306 DEBUG_PRINT(" plx region0 reg 0x%x\n",
1307 readl(plx_iobase + PLX_REGION0_REG));
1308 DEBUG_PRINT(" plx region1 reg 0x%x\n",
1309 readl(plx_iobase + PLX_REGION1_REG));
1311 DEBUG_PRINT(" plx revision 0x%x\n",
1312 readl(plx_iobase + PLX_REVISION_REG));
1313 DEBUG_PRINT(" plx dma channel 0 mode 0x%x\n",
1314 readl(plx_iobase + PLX_DMA0_MODE_REG));
1315 DEBUG_PRINT(" plx dma channel 1 mode 0x%x\n",
1316 readl(plx_iobase + PLX_DMA1_MODE_REG));
1317 DEBUG_PRINT(" plx dma channel 0 pci address 0x%x\n",
1318 readl(plx_iobase + PLX_DMA0_PCI_ADDRESS_REG));
1319 DEBUG_PRINT(" plx dma channel 0 local address 0x%x\n",
1320 readl(plx_iobase + PLX_DMA0_LOCAL_ADDRESS_REG));
1321 DEBUG_PRINT(" plx dma channel 0 transfer size 0x%x\n",
1322 readl(plx_iobase + PLX_DMA0_TRANSFER_SIZE_REG));
1323 DEBUG_PRINT(" plx dma channel 0 descriptor 0x%x\n",
1324 readl(plx_iobase + PLX_DMA0_DESCRIPTOR_REG));
1325 DEBUG_PRINT(" plx dma channel 0 command status 0x%x\n",
1326 readb(plx_iobase + PLX_DMA0_CS_REG));
1327 DEBUG_PRINT(" plx dma channel 0 threshold 0x%x\n",
1328 readl(plx_iobase + PLX_DMA0_THRESHOLD_REG));
1329 DEBUG_PRINT(" plx bigend 0x%x\n", readl(plx_iobase + PLX_BIGEND_REG));
1332 bits = BIGEND_DMA0 | BIGEND_DMA1;
1336 writel(bits, devpriv->plx9080_iobase + PLX_BIGEND_REG);
1338 disable_plx_interrupts(dev);
1343 /* configure dma0 mode */
1345 /* enable ready input, not sure if this is necessary */
1346 bits |= PLX_DMA_EN_READYIN_BIT;
1347 /* enable bterm, not sure if this is necessary */
1348 bits |= PLX_EN_BTERM_BIT;
1349 /* enable dma chaining */
1350 bits |= PLX_EN_CHAIN_BIT;
1351 /* enable interrupt on dma done
1352 * (probably don't need this, since chain never finishes) */
1353 bits |= PLX_EN_DMA_DONE_INTR_BIT;
1354 /* don't increment local address during transfers
1355 * (we are transferring from a fixed fifo register) */
1356 bits |= PLX_LOCAL_ADDR_CONST_BIT;
1357 /* route dma interrupt to pci bus */
1358 bits |= PLX_DMA_INTR_PCI_BIT;
1359 /* enable demand mode */
1360 bits |= PLX_DEMAND_MODE_BIT;
1361 /* enable local burst mode */
1362 bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
1363 /* 4020 uses 32 bit dma */
1364 if (thisboard->layout == LAYOUT_4020)
1365 bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
1366 else /* localspace0 bus is 16 bits wide */
1367 bits |= PLX_LOCAL_BUS_16_WIDE_BITS;
1368 writel(bits, plx_iobase + PLX_DMA1_MODE_REG);
1369 if (ao_cmd_is_supported(thisboard))
1370 writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
1372 /* enable interrupts on plx 9080 */
1373 devpriv->plx_intcsr_bits |=
1374 ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
1375 ICS_DMA0_E | ICS_DMA1_E;
1376 writel(devpriv->plx_intcsr_bits,
1377 devpriv->plx9080_iobase + PLX_INTRCS_REG);
1380 static void disable_ai_pacing(struct comedi_device *dev)
1382 struct pcidas64_private *devpriv = dev->private;
1383 unsigned long flags;
1385 disable_ai_interrupts(dev);
1387 spin_lock_irqsave(&dev->spinlock, flags);
1388 devpriv->adc_control1_bits &= ~ADC_SW_GATE_BIT;
1389 writew(devpriv->adc_control1_bits,
1390 devpriv->main_iobase + ADC_CONTROL1_REG);
1391 spin_unlock_irqrestore(&dev->spinlock, flags);
1393 /* disable pacing, triggering, etc */
1394 writew(ADC_DMA_DISABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT,
1395 devpriv->main_iobase + ADC_CONTROL0_REG);
1398 static int set_ai_fifo_segment_length(struct comedi_device *dev,
1399 unsigned int num_entries)
1401 const struct pcidas64_board *thisboard = comedi_board(dev);
1402 struct pcidas64_private *devpriv = dev->private;
1403 static const int increment_size = 0x100;
1404 const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1405 unsigned int num_increments;
1408 if (num_entries < increment_size)
1409 num_entries = increment_size;
1410 if (num_entries > fifo->max_segment_length)
1411 num_entries = fifo->max_segment_length;
1413 /* 1 == 256 entries, 2 == 512 entries, etc */
1414 num_increments = (num_entries + increment_size / 2) / increment_size;
1416 bits = (~(num_increments - 1)) & fifo->fifo_size_reg_mask;
1417 devpriv->fifo_size_bits &= ~fifo->fifo_size_reg_mask;
1418 devpriv->fifo_size_bits |= bits;
1419 writew(devpriv->fifo_size_bits,
1420 devpriv->main_iobase + FIFO_SIZE_REG);
1422 devpriv->ai_fifo_segment_length = num_increments * increment_size;
1424 DEBUG_PRINT("set hardware fifo segment length to %i\n",
1425 devpriv->ai_fifo_segment_length);
1427 return devpriv->ai_fifo_segment_length;
1430 /* adjusts the size of hardware fifo (which determines block size for dma xfers) */
1431 static int set_ai_fifo_size(struct comedi_device *dev, unsigned int num_samples)
1433 const struct pcidas64_board *thisboard = comedi_board(dev);
1434 unsigned int num_fifo_entries;
1436 const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1438 num_fifo_entries = num_samples / fifo->sample_packing_ratio;
1440 retval = set_ai_fifo_segment_length(dev,
1442 fifo->num_segments);
1446 num_samples = retval * fifo->num_segments * fifo->sample_packing_ratio;
1448 DEBUG_PRINT("set hardware fifo size to %i\n", num_samples);
1453 /* query length of fifo */
1454 static unsigned int ai_fifo_size(struct comedi_device *dev)
1456 const struct pcidas64_board *thisboard = comedi_board(dev);
1457 struct pcidas64_private *devpriv = dev->private;
1459 return devpriv->ai_fifo_segment_length *
1460 thisboard->ai_fifo->num_segments *
1461 thisboard->ai_fifo->sample_packing_ratio;
1464 static void init_stc_registers(struct comedi_device *dev)
1466 const struct pcidas64_board *thisboard = comedi_board(dev);
1467 struct pcidas64_private *devpriv = dev->private;
1469 unsigned long flags;
1471 spin_lock_irqsave(&dev->spinlock, flags);
1473 /* bit should be set for 6025,
1474 * although docs say boards with <= 16 chans should be cleared XXX */
1476 devpriv->adc_control1_bits |= ADC_QUEUE_CONFIG_BIT;
1477 writew(devpriv->adc_control1_bits,
1478 devpriv->main_iobase + ADC_CONTROL1_REG);
1480 /* 6402/16 manual says this register must be initialized to 0xff? */
1481 writew(0xff, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1483 bits = SLOW_DAC_BIT | DMA_CH_SELECT_BIT;
1484 if (thisboard->layout == LAYOUT_4020)
1485 bits |= INTERNAL_CLOCK_4020_BITS;
1486 devpriv->hw_config_bits |= bits;
1487 writew(devpriv->hw_config_bits,
1488 devpriv->main_iobase + HW_CONFIG_REG);
1490 writew(0, devpriv->main_iobase + DAQ_SYNC_REG);
1491 writew(0, devpriv->main_iobase + CALIBRATION_REG);
1493 spin_unlock_irqrestore(&dev->spinlock, flags);
1495 /* set fifos to maximum size */
1496 devpriv->fifo_size_bits |= DAC_FIFO_BITS;
1497 set_ai_fifo_segment_length(dev,
1498 thisboard->ai_fifo->max_segment_length);
1500 devpriv->dac_control1_bits = DAC_OUTPUT_ENABLE_BIT;
1501 devpriv->intr_enable_bits =
1502 /* EN_DAC_INTR_SRC_BIT | DAC_INTR_QEMPTY_BITS | */
1503 EN_DAC_DONE_INTR_BIT | EN_DAC_UNDERRUN_BIT;
1504 writew(devpriv->intr_enable_bits,
1505 devpriv->main_iobase + INTR_ENABLE_REG);
1507 disable_ai_pacing(dev);
1510 static int alloc_and_init_dma_members(struct comedi_device *dev)
1512 const struct pcidas64_board *thisboard = comedi_board(dev);
1513 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1514 struct pcidas64_private *devpriv = dev->private;
1517 /* allocate pci dma buffers */
1518 for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
1519 devpriv->ai_buffer[i] =
1520 pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
1521 &devpriv->ai_buffer_bus_addr[i]);
1522 if (devpriv->ai_buffer[i] == NULL)
1526 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1527 if (ao_cmd_is_supported(thisboard)) {
1528 devpriv->ao_buffer[i] =
1529 pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
1531 ao_buffer_bus_addr[i]);
1532 if (devpriv->ao_buffer[i] == NULL)
1537 /* allocate dma descriptors */
1538 devpriv->ai_dma_desc =
1539 pci_alloc_consistent(pcidev, sizeof(struct plx_dma_desc) *
1540 ai_dma_ring_count(thisboard),
1541 &devpriv->ai_dma_desc_bus_addr);
1542 if (devpriv->ai_dma_desc == NULL)
1545 DEBUG_PRINT("ai dma descriptors start at bus addr 0x%llx\n",
1546 (unsigned long long)devpriv->ai_dma_desc_bus_addr);
1547 if (ao_cmd_is_supported(thisboard)) {
1548 devpriv->ao_dma_desc =
1549 pci_alloc_consistent(pcidev,
1550 sizeof(struct plx_dma_desc) *
1552 &devpriv->ao_dma_desc_bus_addr);
1553 if (devpriv->ao_dma_desc == NULL)
1556 DEBUG_PRINT("ao dma descriptors start at bus addr 0x%llx\n",
1557 (unsigned long long)devpriv->ao_dma_desc_bus_addr);
1559 /* initialize dma descriptors */
1560 for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
1561 devpriv->ai_dma_desc[i].pci_start_addr =
1562 cpu_to_le32(devpriv->ai_buffer_bus_addr[i]);
1563 if (thisboard->layout == LAYOUT_4020)
1564 devpriv->ai_dma_desc[i].local_start_addr =
1565 cpu_to_le32(devpriv->local1_iobase +
1568 devpriv->ai_dma_desc[i].local_start_addr =
1569 cpu_to_le32(devpriv->local0_iobase +
1571 devpriv->ai_dma_desc[i].transfer_size = cpu_to_le32(0);
1572 devpriv->ai_dma_desc[i].next =
1573 cpu_to_le32((devpriv->ai_dma_desc_bus_addr +
1574 ((i + 1) % ai_dma_ring_count(thisboard)) *
1575 sizeof(devpriv->ai_dma_desc[0])) |
1576 PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
1577 PLX_XFER_LOCAL_TO_PCI);
1579 if (ao_cmd_is_supported(thisboard)) {
1580 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1581 devpriv->ao_dma_desc[i].pci_start_addr =
1582 cpu_to_le32(devpriv->ao_buffer_bus_addr[i]);
1583 devpriv->ao_dma_desc[i].local_start_addr =
1584 cpu_to_le32(devpriv->local0_iobase +
1586 devpriv->ao_dma_desc[i].transfer_size = cpu_to_le32(0);
1587 devpriv->ao_dma_desc[i].next =
1588 cpu_to_le32((devpriv->ao_dma_desc_bus_addr +
1589 ((i + 1) % (AO_DMA_RING_COUNT)) *
1590 sizeof(devpriv->ao_dma_desc[0])) |
1591 PLX_DESC_IN_PCI_BIT |
1592 PLX_INTR_TERM_COUNT);
1598 static inline void warn_external_queue(struct comedi_device *dev)
1601 "AO command and AI external channel queue cannot be used simultaneously.");
1603 "Use internal AI channel queue (channels must be consecutive and use same range/aref)");
1606 /* Their i2c requires a huge delay on setting clock or data high for some reason */
1607 static const int i2c_high_udelay = 1000;
1608 static const int i2c_low_udelay = 10;
1610 /* set i2c data line high or low */
1611 static void i2c_set_sda(struct comedi_device *dev, int state)
1613 struct pcidas64_private *devpriv = dev->private;
1614 static const int data_bit = CTL_EE_W;
1615 void __iomem *plx_control_addr = devpriv->plx9080_iobase +
1619 /* set data line high */
1620 devpriv->plx_control_bits &= ~data_bit;
1621 writel(devpriv->plx_control_bits, plx_control_addr);
1622 udelay(i2c_high_udelay);
1623 } else { /* set data line low */
1625 devpriv->plx_control_bits |= data_bit;
1626 writel(devpriv->plx_control_bits, plx_control_addr);
1627 udelay(i2c_low_udelay);
1631 /* set i2c clock line high or low */
1632 static void i2c_set_scl(struct comedi_device *dev, int state)
1634 struct pcidas64_private *devpriv = dev->private;
1635 static const int clock_bit = CTL_USERO;
1636 void __iomem *plx_control_addr = devpriv->plx9080_iobase +
1640 /* set clock line high */
1641 devpriv->plx_control_bits &= ~clock_bit;
1642 writel(devpriv->plx_control_bits, plx_control_addr);
1643 udelay(i2c_high_udelay);
1644 } else { /* set clock line low */
1646 devpriv->plx_control_bits |= clock_bit;
1647 writel(devpriv->plx_control_bits, plx_control_addr);
1648 udelay(i2c_low_udelay);
1652 static void i2c_write_byte(struct comedi_device *dev, uint8_t byte)
1655 unsigned int num_bits = 8;
1657 DEBUG_PRINT("writing to i2c byte 0x%x\n", byte);
1659 for (bit = 1 << (num_bits - 1); bit; bit >>= 1) {
1660 i2c_set_scl(dev, 0);
1662 i2c_set_sda(dev, 1);
1664 i2c_set_sda(dev, 0);
1665 i2c_set_scl(dev, 1);
1669 /* we can't really read the lines, so fake it */
1670 static int i2c_read_ack(struct comedi_device *dev)
1672 i2c_set_scl(dev, 0);
1673 i2c_set_sda(dev, 1);
1674 i2c_set_scl(dev, 1);
1676 return 0; /* return fake acknowledge bit */
1679 /* send start bit */
1680 static void i2c_start(struct comedi_device *dev)
1682 i2c_set_scl(dev, 1);
1683 i2c_set_sda(dev, 1);
1684 i2c_set_sda(dev, 0);
1688 static void i2c_stop(struct comedi_device *dev)
1690 i2c_set_scl(dev, 0);
1691 i2c_set_sda(dev, 0);
1692 i2c_set_scl(dev, 1);
1693 i2c_set_sda(dev, 1);
1696 static void i2c_write(struct comedi_device *dev, unsigned int address,
1697 const uint8_t *data, unsigned int length)
1699 struct pcidas64_private *devpriv = dev->private;
1702 static const int read_bit = 0x1;
1704 /* XXX need mutex to prevent simultaneous attempts to access
1705 * eeprom and i2c bus */
1707 /* make sure we dont send anything to eeprom */
1708 devpriv->plx_control_bits &= ~CTL_EE_CS;
1713 /* send address and write bit */
1714 bitstream = (address << 1) & ~read_bit;
1715 i2c_write_byte(dev, bitstream);
1717 /* get acknowledge */
1718 if (i2c_read_ack(dev) != 0) {
1719 comedi_error(dev, "i2c write failed: no acknowledge");
1723 /* write data bytes */
1724 for (i = 0; i < length; i++) {
1725 i2c_write_byte(dev, data[i]);
1726 if (i2c_read_ack(dev) != 0) {
1727 comedi_error(dev, "i2c write failed: no acknowledge");
1735 static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1736 struct comedi_insn *insn, unsigned int *data)
1738 const struct pcidas64_board *thisboard = comedi_board(dev);
1739 struct pcidas64_private *devpriv = dev->private;
1740 unsigned int bits = 0, n, i;
1741 unsigned int channel, range, aref;
1742 unsigned long flags;
1743 static const int timeout = 100;
1745 DEBUG_PRINT("chanspec 0x%x\n", insn->chanspec);
1746 channel = CR_CHAN(insn->chanspec);
1747 range = CR_RANGE(insn->chanspec);
1748 aref = CR_AREF(insn->chanspec);
1750 /* disable card's analog input interrupt sources and pacing */
1751 /* 4020 generates dac done interrupts even though they are disabled */
1752 disable_ai_pacing(dev);
1754 spin_lock_irqsave(&dev->spinlock, flags);
1755 if (insn->chanspec & CR_ALT_FILTER)
1756 devpriv->adc_control1_bits |= ADC_DITHER_BIT;
1758 devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
1759 writew(devpriv->adc_control1_bits,
1760 devpriv->main_iobase + ADC_CONTROL1_REG);
1761 spin_unlock_irqrestore(&dev->spinlock, flags);
1763 if (thisboard->layout != LAYOUT_4020) {
1764 /* use internal queue */
1765 devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
1766 writew(devpriv->hw_config_bits,
1767 devpriv->main_iobase + HW_CONFIG_REG);
1769 /* ALT_SOURCE is internal calibration reference */
1770 if (insn->chanspec & CR_ALT_SOURCE) {
1771 unsigned int cal_en_bit;
1773 DEBUG_PRINT("reading calibration source\n");
1774 if (thisboard->layout == LAYOUT_60XX)
1775 cal_en_bit = CAL_EN_60XX_BIT;
1777 cal_en_bit = CAL_EN_64XX_BIT;
1778 /* select internal reference source to connect
1781 adc_src_bits(devpriv->calibration_source),
1782 devpriv->main_iobase + CALIBRATION_REG);
1784 /* make sure internal calibration source
1786 writew(0, devpriv->main_iobase + CALIBRATION_REG);
1788 /* load internal queue */
1791 bits |= ai_range_bits_6xxx(dev, CR_RANGE(insn->chanspec));
1792 /* set single-ended / differential */
1793 bits |= se_diff_bit_6xxx(dev, aref == AREF_DIFF);
1794 if (aref == AREF_COMMON)
1795 bits |= ADC_COMMON_BIT;
1796 bits |= adc_chan_bits(channel);
1797 /* set stop channel */
1798 writew(adc_chan_bits(channel),
1799 devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
1800 /* set start channel, and rest of settings */
1801 writew(bits, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
1803 uint8_t old_cal_range_bits = devpriv->i2c_cal_range_bits;
1805 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
1806 if (insn->chanspec & CR_ALT_SOURCE) {
1807 DEBUG_PRINT("reading calibration source\n");
1808 devpriv->i2c_cal_range_bits |=
1809 adc_src_4020_bits(devpriv->calibration_source);
1810 } else { /* select BNC inputs */
1811 devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
1815 devpriv->i2c_cal_range_bits |= attenuate_bit(channel);
1817 devpriv->i2c_cal_range_bits &= ~attenuate_bit(channel);
1818 /* update calibration/range i2c register only if necessary,
1819 * as it is very slow */
1820 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
1821 uint8_t i2c_data = devpriv->i2c_cal_range_bits;
1822 i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
1826 /* 4020 manual asks that sample interval register to be set
1827 * before writing to convert register.
1828 * Using somewhat arbitrary setting of 4 master clock ticks
1830 writew(0, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1831 writew(2, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
1834 for (n = 0; n < insn->n; n++) {
1836 /* clear adc buffer (inside loop for 4020 sake) */
1837 writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
1839 /* trigger conversion, bits sent only matter for 4020 */
1840 writew(adc_convert_chan_4020_bits(CR_CHAN(insn->chanspec)),
1841 devpriv->main_iobase + ADC_CONVERT_REG);
1844 for (i = 0; i < timeout; i++) {
1845 bits = readw(devpriv->main_iobase + HW_STATUS_REG);
1846 DEBUG_PRINT(" pipe bits 0x%x\n", pipe_full_bits(bits));
1847 if (thisboard->layout == LAYOUT_4020) {
1848 if (readw(devpriv->main_iobase +
1849 ADC_WRITE_PNTR_REG))
1852 if (pipe_full_bits(bits))
1857 DEBUG_PRINT(" looped %i times waiting for data\n", i);
1859 comedi_error(dev, " analog input read insn timed out");
1860 dev_info(dev->class_dev, "status 0x%x\n", bits);
1863 if (thisboard->layout == LAYOUT_4020)
1864 data[n] = readl(devpriv->dio_counter_iobase +
1865 ADC_FIFO_REG) & 0xffff;
1867 data[n] = readw(devpriv->main_iobase + PIPE1_READ_REG);
1873 static int ai_config_calibration_source(struct comedi_device *dev,
1876 const struct pcidas64_board *thisboard = comedi_board(dev);
1877 struct pcidas64_private *devpriv = dev->private;
1878 unsigned int source = data[1];
1879 int num_calibration_sources;
1881 if (thisboard->layout == LAYOUT_60XX)
1882 num_calibration_sources = 16;
1884 num_calibration_sources = 8;
1885 if (source >= num_calibration_sources) {
1886 dev_dbg(dev->class_dev, "invalid calibration source: %i\n",
1891 DEBUG_PRINT("setting calibration source to %i\n", source);
1892 devpriv->calibration_source = source;
1897 static int ai_config_block_size(struct comedi_device *dev, unsigned int *data)
1899 const struct pcidas64_board *thisboard = comedi_board(dev);
1901 const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1902 unsigned int block_size, requested_block_size;
1905 requested_block_size = data[1];
1907 if (requested_block_size) {
1908 fifo_size = requested_block_size * fifo->num_segments /
1911 retval = set_ai_fifo_size(dev, fifo_size);
1917 block_size = ai_fifo_size(dev) / fifo->num_segments * bytes_in_sample;
1919 data[1] = block_size;
1924 static int ai_config_master_clock_4020(struct comedi_device *dev,
1927 struct pcidas64_private *devpriv = dev->private;
1928 unsigned int divisor = data[4];
1937 case COMEDI_EV_SCAN_BEGIN:
1938 devpriv->ext_clock.divisor = divisor;
1939 devpriv->ext_clock.chanspec = data[2];
1948 return retval ? retval : 5;
1951 /* XXX could add support for 60xx series */
1952 static int ai_config_master_clock(struct comedi_device *dev, unsigned int *data)
1954 const struct pcidas64_board *thisboard = comedi_board(dev);
1956 switch (thisboard->layout) {
1958 return ai_config_master_clock_4020(dev, data);
1968 static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s,
1969 struct comedi_insn *insn, unsigned int *data)
1974 case INSN_CONFIG_ALT_SOURCE:
1975 return ai_config_calibration_source(dev, data);
1977 case INSN_CONFIG_BLOCK_SIZE:
1978 return ai_config_block_size(dev, data);
1980 case INSN_CONFIG_TIMER_1:
1981 return ai_config_master_clock(dev, data);
1990 /* Gets nearest achievable timing given master clock speed, does not
1991 * take into account possible minimum/maximum divisor values. Used
1992 * by other timing checking functions. */
1993 static unsigned int get_divisor(unsigned int ns, unsigned int flags)
1995 unsigned int divisor;
1997 switch (flags & TRIG_ROUND_MASK) {
1999 divisor = (ns + TIMER_BASE - 1) / TIMER_BASE;
2001 case TRIG_ROUND_DOWN:
2002 divisor = ns / TIMER_BASE;
2004 case TRIG_ROUND_NEAREST:
2006 divisor = (ns + TIMER_BASE / 2) / TIMER_BASE;
2012 /* utility function that rounds desired timing to an achievable time, and
2013 * sets cmd members appropriately.
2014 * adc paces conversions from master clock by dividing by (x + 3) where x is 24 bit number
2016 static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd)
2018 const struct pcidas64_board *thisboard = comedi_board(dev);
2019 unsigned int convert_divisor = 0, scan_divisor;
2020 static const int min_convert_divisor = 3;
2021 static const int max_convert_divisor =
2022 max_counter_value + min_convert_divisor;
2023 static const int min_scan_divisor_4020 = 2;
2024 unsigned long long max_scan_divisor, min_scan_divisor;
2026 if (cmd->convert_src == TRIG_TIMER) {
2027 if (thisboard->layout == LAYOUT_4020) {
2028 cmd->convert_arg = 0;
2030 convert_divisor = get_divisor(cmd->convert_arg,
2032 if (convert_divisor > max_convert_divisor)
2033 convert_divisor = max_convert_divisor;
2034 if (convert_divisor < min_convert_divisor)
2035 convert_divisor = min_convert_divisor;
2036 cmd->convert_arg = convert_divisor * TIMER_BASE;
2038 } else if (cmd->convert_src == TRIG_NOW) {
2039 cmd->convert_arg = 0;
2042 if (cmd->scan_begin_src == TRIG_TIMER) {
2043 scan_divisor = get_divisor(cmd->scan_begin_arg, cmd->flags);
2044 if (cmd->convert_src == TRIG_TIMER) {
2045 /* XXX check for integer overflows */
2046 min_scan_divisor = convert_divisor * cmd->chanlist_len;
2048 (convert_divisor * cmd->chanlist_len - 1) +
2051 min_scan_divisor = min_scan_divisor_4020;
2052 max_scan_divisor = max_counter_value + min_scan_divisor;
2054 if (scan_divisor > max_scan_divisor)
2055 scan_divisor = max_scan_divisor;
2056 if (scan_divisor < min_scan_divisor)
2057 scan_divisor = min_scan_divisor;
2058 cmd->scan_begin_arg = scan_divisor * TIMER_BASE;
2064 static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2065 struct comedi_cmd *cmd)
2067 const struct pcidas64_board *thisboard = comedi_board(dev);
2069 unsigned int tmp_arg, tmp_arg2;
2072 unsigned int triggers;
2074 /* Step 1 : check if triggers are trivially valid */
2076 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
2078 triggers = TRIG_TIMER;
2079 if (thisboard->layout == LAYOUT_4020)
2080 triggers |= TRIG_OTHER;
2082 triggers |= TRIG_FOLLOW;
2083 err |= cfc_check_trigger_src(&cmd->scan_begin_src, triggers);
2085 triggers = TRIG_TIMER;
2086 if (thisboard->layout == LAYOUT_4020)
2087 triggers |= TRIG_NOW;
2089 triggers |= TRIG_EXT;
2090 err |= cfc_check_trigger_src(&cmd->convert_src, triggers);
2091 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2092 err |= cfc_check_trigger_src(&cmd->stop_src,
2093 TRIG_COUNT | TRIG_EXT | TRIG_NONE);
2098 /* Step 2a : make sure trigger sources are unique */
2100 err |= cfc_check_trigger_is_unique(cmd->start_src);
2101 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2102 err |= cfc_check_trigger_is_unique(cmd->convert_src);
2103 err |= cfc_check_trigger_is_unique(cmd->stop_src);
2105 /* Step 2b : and mutually compatible */
2107 if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
2109 if (cmd->stop_src != TRIG_COUNT &&
2110 cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
2116 /* Step 3: check if arguments are trivially valid */
2118 if (cmd->convert_src == TRIG_TIMER) {
2119 if (thisboard->layout == LAYOUT_4020) {
2120 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2122 err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
2123 thisboard->ai_speed);
2124 /* if scans are timed faster than conversion rate allows */
2125 if (cmd->scan_begin_src == TRIG_TIMER)
2126 err |= cfc_check_trigger_arg_min(
2127 &cmd->scan_begin_arg,
2133 err |= cfc_check_trigger_arg_min(&cmd->chanlist_len, 1);
2134 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
2136 switch (cmd->stop_src) {
2140 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
2143 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
2152 /* step 4: fix up any arguments */
2154 if (cmd->convert_src == TRIG_TIMER) {
2155 tmp_arg = cmd->convert_arg;
2156 tmp_arg2 = cmd->scan_begin_arg;
2157 check_adc_timing(dev, cmd);
2158 if (tmp_arg != cmd->convert_arg)
2160 if (tmp_arg2 != cmd->scan_begin_arg)
2167 /* make sure user is doesn't change analog reference mid chanlist */
2168 if (cmd->chanlist) {
2169 aref = CR_AREF(cmd->chanlist[0]);
2170 for (i = 1; i < cmd->chanlist_len; i++) {
2171 if (aref != CR_AREF(cmd->chanlist[i])) {
2173 "all elements in chanlist must use the same analog reference");
2178 /* check 4020 chanlist */
2179 if (thisboard->layout == LAYOUT_4020) {
2180 unsigned int first_channel = CR_CHAN(cmd->chanlist[0]);
2181 for (i = 1; i < cmd->chanlist_len; i++) {
2182 if (CR_CHAN(cmd->chanlist[i]) !=
2183 first_channel + i) {
2185 "chanlist must use consecutive channels");
2190 if (cmd->chanlist_len == 3) {
2192 "chanlist cannot be 3 channels long, use 1, 2, or 4 channels");
2204 static int use_hw_sample_counter(struct comedi_cmd *cmd)
2206 /* disable for now until I work out a race */
2209 if (cmd->stop_src == TRIG_COUNT && cmd->stop_arg <= max_counter_value)
2215 static void setup_sample_counters(struct comedi_device *dev,
2216 struct comedi_cmd *cmd)
2218 struct pcidas64_private *devpriv = dev->private;
2220 if (cmd->stop_src == TRIG_COUNT) {
2221 /* set software count */
2222 devpriv->ai_count = cmd->stop_arg * cmd->chanlist_len;
2224 /* load hardware conversion counter */
2225 if (use_hw_sample_counter(cmd)) {
2226 writew(cmd->stop_arg & 0xffff,
2227 devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2228 writew((cmd->stop_arg >> 16) & 0xff,
2229 devpriv->main_iobase + ADC_COUNT_UPPER_REG);
2231 writew(1, devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2235 static inline unsigned int dma_transfer_size(struct comedi_device *dev)
2237 const struct pcidas64_board *thisboard = comedi_board(dev);
2238 struct pcidas64_private *devpriv = dev->private;
2239 unsigned int num_samples;
2241 num_samples = devpriv->ai_fifo_segment_length *
2242 thisboard->ai_fifo->sample_packing_ratio;
2243 if (num_samples > DMA_BUFFER_SIZE / sizeof(uint16_t))
2244 num_samples = DMA_BUFFER_SIZE / sizeof(uint16_t);
2249 static uint32_t ai_convert_counter_6xxx(const struct comedi_device *dev,
2250 const struct comedi_cmd *cmd)
2252 /* supposed to load counter with desired divisor minus 3 */
2253 return cmd->convert_arg / TIMER_BASE - 3;
2256 static uint32_t ai_scan_counter_6xxx(struct comedi_device *dev,
2257 struct comedi_cmd *cmd)
2261 /* figure out how long we need to delay at end of scan */
2262 switch (cmd->scan_begin_src) {
2264 count = (cmd->scan_begin_arg -
2265 (cmd->convert_arg * (cmd->chanlist_len - 1))) /
2269 count = cmd->convert_arg / TIMER_BASE;
2278 static uint32_t ai_convert_counter_4020(struct comedi_device *dev,
2279 struct comedi_cmd *cmd)
2281 struct pcidas64_private *devpriv = dev->private;
2282 unsigned int divisor;
2284 switch (cmd->scan_begin_src) {
2286 divisor = cmd->scan_begin_arg / TIMER_BASE;
2289 divisor = devpriv->ext_clock.divisor;
2291 default: /* should never happen */
2292 comedi_error(dev, "bug! failed to set ai pacing!");
2297 /* supposed to load counter with desired divisor minus 2 for 4020 */
2301 static void select_master_clock_4020(struct comedi_device *dev,
2302 const struct comedi_cmd *cmd)
2304 struct pcidas64_private *devpriv = dev->private;
2306 /* select internal/external master clock */
2307 devpriv->hw_config_bits &= ~MASTER_CLOCK_4020_MASK;
2308 if (cmd->scan_begin_src == TRIG_OTHER) {
2309 int chanspec = devpriv->ext_clock.chanspec;
2311 if (CR_CHAN(chanspec))
2312 devpriv->hw_config_bits |= BNC_CLOCK_4020_BITS;
2314 devpriv->hw_config_bits |= EXT_CLOCK_4020_BITS;
2316 devpriv->hw_config_bits |= INTERNAL_CLOCK_4020_BITS;
2318 writew(devpriv->hw_config_bits,
2319 devpriv->main_iobase + HW_CONFIG_REG);
2322 static void select_master_clock(struct comedi_device *dev,
2323 const struct comedi_cmd *cmd)
2325 const struct pcidas64_board *thisboard = comedi_board(dev);
2327 switch (thisboard->layout) {
2329 select_master_clock_4020(dev, cmd);
2336 static inline void dma_start_sync(struct comedi_device *dev,
2337 unsigned int channel)
2339 struct pcidas64_private *devpriv = dev->private;
2340 unsigned long flags;
2342 /* spinlock for plx dma control/status reg */
2343 spin_lock_irqsave(&dev->spinlock, flags);
2345 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2346 PLX_CLEAR_DMA_INTR_BIT,
2347 devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2349 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2350 PLX_CLEAR_DMA_INTR_BIT,
2351 devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2352 spin_unlock_irqrestore(&dev->spinlock, flags);
2355 static void set_ai_pacing(struct comedi_device *dev, struct comedi_cmd *cmd)
2357 const struct pcidas64_board *thisboard = comedi_board(dev);
2358 struct pcidas64_private *devpriv = dev->private;
2359 uint32_t convert_counter = 0, scan_counter = 0;
2361 check_adc_timing(dev, cmd);
2363 select_master_clock(dev, cmd);
2365 if (thisboard->layout == LAYOUT_4020) {
2366 convert_counter = ai_convert_counter_4020(dev, cmd);
2368 convert_counter = ai_convert_counter_6xxx(dev, cmd);
2369 scan_counter = ai_scan_counter_6xxx(dev, cmd);
2372 /* load lower 16 bits of convert interval */
2373 writew(convert_counter & 0xffff,
2374 devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
2375 DEBUG_PRINT("convert counter 0x%x\n", convert_counter);
2376 /* load upper 8 bits of convert interval */
2377 writew((convert_counter >> 16) & 0xff,
2378 devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
2379 /* load lower 16 bits of scan delay */
2380 writew(scan_counter & 0xffff,
2381 devpriv->main_iobase + ADC_DELAY_INTERVAL_LOWER_REG);
2382 /* load upper 8 bits of scan delay */
2383 writew((scan_counter >> 16) & 0xff,
2384 devpriv->main_iobase + ADC_DELAY_INTERVAL_UPPER_REG);
2385 DEBUG_PRINT("scan counter 0x%x\n", scan_counter);
2388 static int use_internal_queue_6xxx(const struct comedi_cmd *cmd)
2392 for (i = 0; i + 1 < cmd->chanlist_len; i++) {
2393 if (CR_CHAN(cmd->chanlist[i + 1]) !=
2394 CR_CHAN(cmd->chanlist[i]) + 1)
2396 if (CR_RANGE(cmd->chanlist[i + 1]) !=
2397 CR_RANGE(cmd->chanlist[i]))
2399 if (CR_AREF(cmd->chanlist[i + 1]) != CR_AREF(cmd->chanlist[i]))
2405 static int setup_channel_queue(struct comedi_device *dev,
2406 const struct comedi_cmd *cmd)
2408 const struct pcidas64_board *thisboard = comedi_board(dev);
2409 struct pcidas64_private *devpriv = dev->private;
2410 unsigned short bits;
2413 if (thisboard->layout != LAYOUT_4020) {
2414 if (use_internal_queue_6xxx(cmd)) {
2415 devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
2416 writew(devpriv->hw_config_bits,
2417 devpriv->main_iobase + HW_CONFIG_REG);
2420 bits |= adc_chan_bits(CR_CHAN(cmd->chanlist[0]));
2422 bits |= ai_range_bits_6xxx(dev,
2423 CR_RANGE(cmd->chanlist[0]));
2424 /* set single-ended / differential */
2425 bits |= se_diff_bit_6xxx(dev,
2426 CR_AREF(cmd->chanlist[0]) ==
2428 if (CR_AREF(cmd->chanlist[0]) == AREF_COMMON)
2429 bits |= ADC_COMMON_BIT;
2430 /* set stop channel */
2431 writew(adc_chan_bits
2432 (CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1])),
2433 devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
2434 /* set start channel, and rest of settings */
2436 devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2438 /* use external queue */
2439 if (dev->write_subdev && dev->write_subdev->busy) {
2440 warn_external_queue(dev);
2443 devpriv->hw_config_bits |= EXT_QUEUE_BIT;
2444 writew(devpriv->hw_config_bits,
2445 devpriv->main_iobase + HW_CONFIG_REG);
2446 /* clear DAC buffer to prevent weird interactions */
2448 devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
2449 /* clear queue pointer */
2450 writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2451 /* load external queue */
2452 for (i = 0; i < cmd->chanlist_len; i++) {
2455 bits |= adc_chan_bits(CR_CHAN(cmd->
2458 bits |= ai_range_bits_6xxx(dev,
2462 /* set single-ended / differential */
2463 bits |= se_diff_bit_6xxx(dev,
2467 if (CR_AREF(cmd->chanlist[i]) == AREF_COMMON)
2468 bits |= ADC_COMMON_BIT;
2469 /* mark end of queue */
2470 if (i == cmd->chanlist_len - 1)
2471 bits |= QUEUE_EOSCAN_BIT |
2474 devpriv->main_iobase +
2475 ADC_QUEUE_FIFO_REG);
2477 "wrote 0x%x to external channel queue\n",
2480 /* doing a queue clear is not specified in board docs,
2481 * but required for reliable operation */
2482 writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2483 /* prime queue holding register */
2484 writew(0, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2487 unsigned short old_cal_range_bits = devpriv->i2c_cal_range_bits;
2489 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
2490 /* select BNC inputs */
2491 devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
2493 for (i = 0; i < cmd->chanlist_len; i++) {
2494 unsigned int channel = CR_CHAN(cmd->chanlist[i]);
2495 unsigned int range = CR_RANGE(cmd->chanlist[i]);
2498 devpriv->i2c_cal_range_bits |=
2499 attenuate_bit(channel);
2501 devpriv->i2c_cal_range_bits &=
2502 ~attenuate_bit(channel);
2504 /* update calibration/range i2c register only if necessary,
2505 * as it is very slow */
2506 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
2507 uint8_t i2c_data = devpriv->i2c_cal_range_bits;
2508 i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
2515 static inline void load_first_dma_descriptor(struct comedi_device *dev,
2516 unsigned int dma_channel,
2517 unsigned int descriptor_bits)
2519 struct pcidas64_private *devpriv = dev->private;
2521 /* The transfer size, pci address, and local address registers
2522 * are supposedly unused during chained dma,
2523 * but I have found that left over values from last operation
2524 * occasionally cause problems with transfer of first dma
2525 * block. Initializing them to zero seems to fix the problem. */
2528 devpriv->plx9080_iobase + PLX_DMA1_TRANSFER_SIZE_REG);
2529 writel(0, devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG);
2531 devpriv->plx9080_iobase + PLX_DMA1_LOCAL_ADDRESS_REG);
2532 writel(descriptor_bits,
2533 devpriv->plx9080_iobase + PLX_DMA1_DESCRIPTOR_REG);
2536 devpriv->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG);
2537 writel(0, devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
2539 devpriv->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG);
2540 writel(descriptor_bits,
2541 devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
2545 static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2547 const struct pcidas64_board *thisboard = comedi_board(dev);
2548 struct pcidas64_private *devpriv = dev->private;
2549 struct comedi_async *async = s->async;
2550 struct comedi_cmd *cmd = &async->cmd;
2553 unsigned long flags;
2556 disable_ai_pacing(dev);
2559 retval = setup_channel_queue(dev, cmd);
2563 /* make sure internal calibration source is turned off */
2564 writew(0, devpriv->main_iobase + CALIBRATION_REG);
2566 set_ai_pacing(dev, cmd);
2568 setup_sample_counters(dev, cmd);
2570 enable_ai_interrupts(dev, cmd);
2572 spin_lock_irqsave(&dev->spinlock, flags);
2573 /* set mode, allow conversions through software gate */
2574 devpriv->adc_control1_bits |= ADC_SW_GATE_BIT;
2575 devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
2576 if (thisboard->layout != LAYOUT_4020) {
2577 devpriv->adc_control1_bits &= ~ADC_MODE_MASK;
2578 if (cmd->convert_src == TRIG_EXT)
2579 /* good old mode 13 */
2580 devpriv->adc_control1_bits |= adc_mode_bits(13);
2582 /* mode 8. What else could you need? */
2583 devpriv->adc_control1_bits |= adc_mode_bits(8);
2585 devpriv->adc_control1_bits &= ~CHANNEL_MODE_4020_MASK;
2586 if (cmd->chanlist_len == 4)
2587 devpriv->adc_control1_bits |= FOUR_CHANNEL_4020_BITS;
2588 else if (cmd->chanlist_len == 2)
2589 devpriv->adc_control1_bits |= TWO_CHANNEL_4020_BITS;
2590 devpriv->adc_control1_bits &= ~ADC_LO_CHANNEL_4020_MASK;
2591 devpriv->adc_control1_bits |=
2592 adc_lo_chan_4020_bits(CR_CHAN(cmd->chanlist[0]));
2593 devpriv->adc_control1_bits &= ~ADC_HI_CHANNEL_4020_MASK;
2594 devpriv->adc_control1_bits |=
2595 adc_hi_chan_4020_bits(CR_CHAN(cmd->chanlist
2596 [cmd->chanlist_len - 1]));
2598 writew(devpriv->adc_control1_bits,
2599 devpriv->main_iobase + ADC_CONTROL1_REG);
2600 DEBUG_PRINT("control1 bits 0x%x\n", devpriv->adc_control1_bits);
2601 spin_unlock_irqrestore(&dev->spinlock, flags);
2603 /* clear adc buffer */
2604 writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
2606 if ((cmd->flags & TRIG_WAKE_EOS) == 0 ||
2607 thisboard->layout == LAYOUT_4020) {
2608 devpriv->ai_dma_index = 0;
2610 /* set dma transfer size */
2611 for (i = 0; i < ai_dma_ring_count(thisboard); i++)
2612 devpriv->ai_dma_desc[i].transfer_size =
2613 cpu_to_le32(dma_transfer_size(dev) *
2616 /* give location of first dma descriptor */
2617 load_first_dma_descriptor(dev, 1,
2618 devpriv->ai_dma_desc_bus_addr |
2619 PLX_DESC_IN_PCI_BIT |
2620 PLX_INTR_TERM_COUNT |
2621 PLX_XFER_LOCAL_TO_PCI);
2623 dma_start_sync(dev, 1);
2626 if (thisboard->layout == LAYOUT_4020) {
2627 /* set source for external triggers */
2629 if (cmd->start_src == TRIG_EXT && CR_CHAN(cmd->start_arg))
2630 bits |= EXT_START_TRIG_BNC_BIT;
2631 if (cmd->stop_src == TRIG_EXT && CR_CHAN(cmd->stop_arg))
2632 bits |= EXT_STOP_TRIG_BNC_BIT;
2633 writew(bits, devpriv->main_iobase + DAQ_ATRIG_LOW_4020_REG);
2636 spin_lock_irqsave(&dev->spinlock, flags);
2638 /* enable pacing, triggering, etc */
2639 bits = ADC_ENABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT;
2640 if (cmd->flags & TRIG_WAKE_EOS)
2641 bits |= ADC_DMA_DISABLE_BIT;
2642 /* set start trigger */
2643 if (cmd->start_src == TRIG_EXT) {
2644 bits |= ADC_START_TRIG_EXT_BITS;
2645 if (cmd->start_arg & CR_INVERT)
2646 bits |= ADC_START_TRIG_FALLING_BIT;
2647 } else if (cmd->start_src == TRIG_NOW)
2648 bits |= ADC_START_TRIG_SOFT_BITS;
2649 if (use_hw_sample_counter(cmd))
2650 bits |= ADC_SAMPLE_COUNTER_EN_BIT;
2651 writew(bits, devpriv->main_iobase + ADC_CONTROL0_REG);
2652 DEBUG_PRINT("control0 bits 0x%x\n", bits);
2654 devpriv->ai_cmd_running = 1;
2656 spin_unlock_irqrestore(&dev->spinlock, flags);
2658 /* start acquisition */
2659 if (cmd->start_src == TRIG_NOW) {
2660 writew(0, devpriv->main_iobase + ADC_START_REG);
2661 DEBUG_PRINT("soft trig\n");
2667 /* read num_samples from 16 bit wide ai fifo */
2668 static void pio_drain_ai_fifo_16(struct comedi_device *dev)
2670 struct pcidas64_private *devpriv = dev->private;
2671 struct comedi_subdevice *s = dev->read_subdev;
2672 struct comedi_async *async = s->async;
2673 struct comedi_cmd *cmd = &async->cmd;
2675 uint16_t prepost_bits;
2676 int read_segment, read_index, write_segment, write_index;
2680 /* get least significant 15 bits */
2681 read_index = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) &
2683 write_index = readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) &
2685 /* Get most significant bits (grey code).
2686 * Different boards use different code so use a scheme
2687 * that doesn't depend on encoding. This read must
2688 * occur after reading least significant 15 bits to avoid race
2689 * with fifo switching to next segment. */
2690 prepost_bits = readw(devpriv->main_iobase + PREPOST_REG);
2692 /* if read and write pointers are not on the same fifo segment,
2693 * read to the end of the read segment */
2694 read_segment = adc_upper_read_ptr_code(prepost_bits);
2695 write_segment = adc_upper_write_ptr_code(prepost_bits);
2697 DEBUG_PRINT(" rd seg %i, wrt seg %i, rd idx %i, wrt idx %i\n",
2698 read_segment, write_segment, read_index,
2701 if (read_segment != write_segment)
2703 devpriv->ai_fifo_segment_length - read_index;
2705 num_samples = write_index - read_index;
2707 if (cmd->stop_src == TRIG_COUNT) {
2708 if (devpriv->ai_count == 0)
2710 if (num_samples > devpriv->ai_count)
2711 num_samples = devpriv->ai_count;
2713 devpriv->ai_count -= num_samples;
2716 if (num_samples < 0) {
2717 dev_err(dev->class_dev,
2718 "cb_pcidas64: bug! num_samples < 0\n");
2722 DEBUG_PRINT(" read %i samples from fifo\n", num_samples);
2724 for (i = 0; i < num_samples; i++) {
2725 cfc_write_to_buffer(s,
2726 readw(devpriv->main_iobase +
2730 } while (read_segment != write_segment);
2733 /* Read from 32 bit wide ai fifo of 4020 - deal with insane grey coding of
2734 * pointers. The pci-4020 hardware only supports dma transfers (it only
2735 * supports the use of pio for draining the last remaining points from the
2736 * fifo when a data acquisition operation has completed).
2738 static void pio_drain_ai_fifo_32(struct comedi_device *dev)
2740 struct pcidas64_private *devpriv = dev->private;
2741 struct comedi_subdevice *s = dev->read_subdev;
2742 struct comedi_async *async = s->async;
2743 struct comedi_cmd *cmd = &async->cmd;
2745 unsigned int max_transfer = 100000;
2748 readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff;
2750 readw(devpriv->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2752 if (cmd->stop_src == TRIG_COUNT) {
2753 if (max_transfer > devpriv->ai_count)
2754 max_transfer = devpriv->ai_count;
2757 for (i = 0; read_code != write_code && i < max_transfer;) {
2758 fifo_data = readl(devpriv->dio_counter_iobase + ADC_FIFO_REG);
2759 cfc_write_to_buffer(s, fifo_data & 0xffff);
2761 if (i < max_transfer) {
2762 cfc_write_to_buffer(s, (fifo_data >> 16) & 0xffff);
2765 read_code = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) &
2768 devpriv->ai_count -= i;
2772 static void pio_drain_ai_fifo(struct comedi_device *dev)
2774 const struct pcidas64_board *thisboard = comedi_board(dev);
2776 if (thisboard->layout == LAYOUT_4020)
2777 pio_drain_ai_fifo_32(dev);
2779 pio_drain_ai_fifo_16(dev);
2782 static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
2784 const struct pcidas64_board *thisboard = comedi_board(dev);
2785 struct pcidas64_private *devpriv = dev->private;
2786 struct comedi_async *async = dev->read_subdev->async;
2787 uint32_t next_transfer_addr;
2789 int num_samples = 0;
2790 void __iomem *pci_addr_reg;
2794 devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
2797 devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
2799 /* loop until we have read all the full buffers */
2800 for (j = 0, next_transfer_addr = readl(pci_addr_reg);
2801 (next_transfer_addr <
2802 devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] ||
2803 next_transfer_addr >=
2804 devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] +
2805 DMA_BUFFER_SIZE) && j < ai_dma_ring_count(thisboard); j++) {
2806 /* transfer data from dma buffer to comedi buffer */
2807 num_samples = dma_transfer_size(dev);
2808 if (async->cmd.stop_src == TRIG_COUNT) {
2809 if (num_samples > devpriv->ai_count)
2810 num_samples = devpriv->ai_count;
2811 devpriv->ai_count -= num_samples;
2813 cfc_write_array_to_buffer(dev->read_subdev,
2814 devpriv->ai_buffer[devpriv->
2816 num_samples * sizeof(uint16_t));
2817 devpriv->ai_dma_index = (devpriv->ai_dma_index + 1) %
2818 ai_dma_ring_count(thisboard);
2820 DEBUG_PRINT("next buffer addr 0x%lx\n",
2821 (unsigned long)devpriv->
2822 ai_buffer_bus_addr[devpriv->ai_dma_index]);
2823 DEBUG_PRINT("pci addr reg 0x%x\n", next_transfer_addr);
2825 /* XXX check for dma ring buffer overrun
2826 * (use end-of-chain bit to mark last unused buffer) */
2829 static void handle_ai_interrupt(struct comedi_device *dev,
2830 unsigned short status,
2831 unsigned int plx_status)
2833 const struct pcidas64_board *thisboard = comedi_board(dev);
2834 struct pcidas64_private *devpriv = dev->private;
2835 struct comedi_subdevice *s = dev->read_subdev;
2836 struct comedi_async *async = s->async;
2837 struct comedi_cmd *cmd = &async->cmd;
2838 uint8_t dma1_status;
2839 unsigned long flags;
2841 /* check for fifo overrun */
2842 if (status & ADC_OVERRUN_BIT) {
2843 comedi_error(dev, "fifo overrun");
2844 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
2846 /* spin lock makes sure no one else changes plx dma control reg */
2847 spin_lock_irqsave(&dev->spinlock, flags);
2848 dma1_status = readb(devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2849 if (plx_status & ICS_DMA1_A) { /* dma chan 1 interrupt */
2850 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
2851 devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2852 DEBUG_PRINT("dma1 status 0x%x\n", dma1_status);
2854 if (dma1_status & PLX_DMA_EN_BIT)
2855 drain_dma_buffers(dev, 1);
2857 DEBUG_PRINT(" cleared dma ch1 interrupt\n");
2859 spin_unlock_irqrestore(&dev->spinlock, flags);
2861 if (status & ADC_DONE_BIT)
2862 DEBUG_PRINT("adc done interrupt\n");
2864 /* drain fifo with pio */
2865 if ((status & ADC_DONE_BIT) ||
2866 ((cmd->flags & TRIG_WAKE_EOS) &&
2867 (status & ADC_INTR_PENDING_BIT) &&
2868 (thisboard->layout != LAYOUT_4020))) {
2869 DEBUG_PRINT("pio fifo drain\n");
2870 spin_lock_irqsave(&dev->spinlock, flags);
2871 if (devpriv->ai_cmd_running) {
2872 spin_unlock_irqrestore(&dev->spinlock, flags);
2873 pio_drain_ai_fifo(dev);
2875 spin_unlock_irqrestore(&dev->spinlock, flags);
2877 /* if we are have all the data, then quit */
2878 if ((cmd->stop_src == TRIG_COUNT && (int)devpriv->ai_count <= 0) ||
2879 (cmd->stop_src == TRIG_EXT && (status & ADC_STOP_BIT))) {
2880 async->events |= COMEDI_CB_EOA;
2883 cfc_handle_events(dev, s);
2886 static inline unsigned int prev_ao_dma_index(struct comedi_device *dev)
2888 struct pcidas64_private *devpriv = dev->private;
2889 unsigned int buffer_index;
2891 if (devpriv->ao_dma_index == 0)
2892 buffer_index = AO_DMA_RING_COUNT - 1;
2894 buffer_index = devpriv->ao_dma_index - 1;
2895 return buffer_index;
2898 static int last_ao_dma_load_completed(struct comedi_device *dev)
2900 struct pcidas64_private *devpriv = dev->private;
2901 unsigned int buffer_index;
2902 unsigned int transfer_address;
2903 unsigned short dma_status;
2905 buffer_index = prev_ao_dma_index(dev);
2906 dma_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2907 if ((dma_status & PLX_DMA_DONE_BIT) == 0)
2911 readl(devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
2912 if (transfer_address != devpriv->ao_buffer_bus_addr[buffer_index])
2918 static int ao_stopped_by_error(struct comedi_device *dev,
2919 const struct comedi_cmd *cmd)
2921 struct pcidas64_private *devpriv = dev->private;
2923 if (cmd->stop_src == TRIG_NONE)
2925 if (cmd->stop_src == TRIG_COUNT) {
2926 if (devpriv->ao_count)
2928 if (last_ao_dma_load_completed(dev) == 0)
2934 static inline int ao_dma_needs_restart(struct comedi_device *dev,
2935 unsigned short dma_status)
2937 if ((dma_status & PLX_DMA_DONE_BIT) == 0 ||
2938 (dma_status & PLX_DMA_EN_BIT) == 0)
2940 if (last_ao_dma_load_completed(dev))
2946 static void restart_ao_dma(struct comedi_device *dev)
2948 struct pcidas64_private *devpriv = dev->private;
2949 unsigned int dma_desc_bits;
2952 readl(devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
2953 dma_desc_bits &= ~PLX_END_OF_CHAIN_BIT;
2954 DEBUG_PRINT("restarting ao dma, descriptor reg 0x%x\n", dma_desc_bits);
2955 load_first_dma_descriptor(dev, 0, dma_desc_bits);
2957 dma_start_sync(dev, 0);
2960 static unsigned int load_ao_dma_buffer(struct comedi_device *dev,
2961 const struct comedi_cmd *cmd)
2963 struct pcidas64_private *devpriv = dev->private;
2964 unsigned int num_bytes, buffer_index, prev_buffer_index;
2965 unsigned int next_bits;
2967 buffer_index = devpriv->ao_dma_index;
2968 prev_buffer_index = prev_ao_dma_index(dev);
2970 DEBUG_PRINT("attempting to load ao buffer %i (0x%llx)\n", buffer_index,
2971 (unsigned long long)devpriv->ao_buffer_bus_addr[
2974 num_bytes = comedi_buf_read_n_available(dev->write_subdev->async);
2975 if (num_bytes > DMA_BUFFER_SIZE)
2976 num_bytes = DMA_BUFFER_SIZE;
2977 if (cmd->stop_src == TRIG_COUNT && num_bytes > devpriv->ao_count)
2978 num_bytes = devpriv->ao_count;
2979 num_bytes -= num_bytes % bytes_in_sample;
2984 DEBUG_PRINT("loading %i bytes\n", num_bytes);
2986 num_bytes = cfc_read_array_from_buffer(dev->write_subdev,
2988 ao_buffer[buffer_index],
2990 devpriv->ao_dma_desc[buffer_index].transfer_size =
2991 cpu_to_le32(num_bytes);
2992 /* set end of chain bit so we catch underruns */
2993 next_bits = le32_to_cpu(devpriv->ao_dma_desc[buffer_index].next);
2994 next_bits |= PLX_END_OF_CHAIN_BIT;
2995 devpriv->ao_dma_desc[buffer_index].next = cpu_to_le32(next_bits);
2996 /* clear end of chain bit on previous buffer now that we have set it
2997 * for the last buffer */
2998 next_bits = le32_to_cpu(devpriv->ao_dma_desc[prev_buffer_index].next);
2999 next_bits &= ~PLX_END_OF_CHAIN_BIT;
3000 devpriv->ao_dma_desc[prev_buffer_index].next = cpu_to_le32(next_bits);
3002 devpriv->ao_dma_index = (buffer_index + 1) % AO_DMA_RING_COUNT;
3003 devpriv->ao_count -= num_bytes;
3008 static void load_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3010 struct pcidas64_private *devpriv = dev->private;
3011 unsigned int num_bytes;
3012 unsigned int next_transfer_addr;
3013 void __iomem *pci_addr_reg =
3014 devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
3015 unsigned int buffer_index;
3018 buffer_index = devpriv->ao_dma_index;
3019 /* don't overwrite data that hasn't been transferred yet */
3020 next_transfer_addr = readl(pci_addr_reg);
3021 if (next_transfer_addr >=
3022 devpriv->ao_buffer_bus_addr[buffer_index] &&
3023 next_transfer_addr <
3024 devpriv->ao_buffer_bus_addr[buffer_index] +
3027 num_bytes = load_ao_dma_buffer(dev, cmd);
3028 } while (num_bytes >= DMA_BUFFER_SIZE);
3031 static void handle_ao_interrupt(struct comedi_device *dev,
3032 unsigned short status, unsigned int plx_status)
3034 struct pcidas64_private *devpriv = dev->private;
3035 struct comedi_subdevice *s = dev->write_subdev;
3036 struct comedi_async *async;
3037 struct comedi_cmd *cmd;
3038 uint8_t dma0_status;
3039 unsigned long flags;
3041 /* board might not support ao, in which case write_subdev is NULL */
3047 /* spin lock makes sure no one else changes plx dma control reg */
3048 spin_lock_irqsave(&dev->spinlock, flags);
3049 dma0_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
3050 if (plx_status & ICS_DMA0_A) { /* dma chan 0 interrupt */
3051 if ((dma0_status & PLX_DMA_EN_BIT) &&
3052 !(dma0_status & PLX_DMA_DONE_BIT))
3053 writeb(PLX_DMA_EN_BIT | PLX_CLEAR_DMA_INTR_BIT,
3054 devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
3056 writeb(PLX_CLEAR_DMA_INTR_BIT,
3057 devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
3058 spin_unlock_irqrestore(&dev->spinlock, flags);
3059 DEBUG_PRINT("dma0 status 0x%x\n", dma0_status);
3060 if (dma0_status & PLX_DMA_EN_BIT) {
3061 load_ao_dma(dev, cmd);
3062 /* try to recover from dma end-of-chain event */
3063 if (ao_dma_needs_restart(dev, dma0_status))
3064 restart_ao_dma(dev);
3066 DEBUG_PRINT(" cleared dma ch0 interrupt\n");
3068 spin_unlock_irqrestore(&dev->spinlock, flags);
3071 if ((status & DAC_DONE_BIT)) {
3072 async->events |= COMEDI_CB_EOA;
3073 if (ao_stopped_by_error(dev, cmd))
3074 async->events |= COMEDI_CB_ERROR;
3075 DEBUG_PRINT("plx dma0 desc reg 0x%x\n",
3076 readl(devpriv->plx9080_iobase +
3077 PLX_DMA0_DESCRIPTOR_REG));
3078 DEBUG_PRINT("plx dma0 address reg 0x%x\n",
3079 readl(devpriv->plx9080_iobase +
3080 PLX_DMA0_PCI_ADDRESS_REG));
3082 cfc_handle_events(dev, s);
3085 static irqreturn_t handle_interrupt(int irq, void *d)
3087 struct comedi_device *dev = d;
3088 struct pcidas64_private *devpriv = dev->private;
3089 unsigned short status;
3090 uint32_t plx_status;
3093 plx_status = readl(devpriv->plx9080_iobase + PLX_INTRCS_REG);
3094 status = readw(devpriv->main_iobase + HW_STATUS_REG);
3096 DEBUG_PRINT("hw status 0x%x, plx status 0x%x\n", status, plx_status);
3098 /* an interrupt before all the postconfig stuff gets done could
3099 * cause a NULL dereference if we continue through the
3100 * interrupt handler */
3101 if (!dev->attached) {
3102 DEBUG_PRINT("premature interrupt, ignoring\n");
3105 handle_ai_interrupt(dev, status, plx_status);
3106 handle_ao_interrupt(dev, status, plx_status);
3108 /* clear possible plx9080 interrupt sources */
3109 if (plx_status & ICS_LDIA) { /* clear local doorbell interrupt */
3110 plx_bits = readl(devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
3111 writel(plx_bits, devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
3112 DEBUG_PRINT(" cleared local doorbell bits 0x%x\n", plx_bits);
3115 DEBUG_PRINT("exiting handler\n");
3120 static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3122 struct pcidas64_private *devpriv = dev->private;
3123 unsigned long flags;
3125 spin_lock_irqsave(&dev->spinlock, flags);
3126 if (devpriv->ai_cmd_running == 0) {
3127 spin_unlock_irqrestore(&dev->spinlock, flags);
3130 devpriv->ai_cmd_running = 0;
3131 spin_unlock_irqrestore(&dev->spinlock, flags);
3133 disable_ai_pacing(dev);
3137 DEBUG_PRINT("ai canceled\n");
3141 static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
3142 struct comedi_insn *insn, unsigned int *data)
3144 const struct pcidas64_board *thisboard = comedi_board(dev);
3145 struct pcidas64_private *devpriv = dev->private;
3146 int chan = CR_CHAN(insn->chanspec);
3147 int range = CR_RANGE(insn->chanspec);
3149 /* do some initializing */
3150 writew(0, devpriv->main_iobase + DAC_CONTROL0_REG);
3153 set_dac_range_bits(dev, &devpriv->dac_control1_bits, chan, range);
3154 writew(devpriv->dac_control1_bits,
3155 devpriv->main_iobase + DAC_CONTROL1_REG);
3157 /* write to channel */
3158 if (thisboard->layout == LAYOUT_4020) {
3159 writew(data[0] & 0xff,
3160 devpriv->main_iobase + dac_lsb_4020_reg(chan));
3161 writew((data[0] >> 8) & 0xf,
3162 devpriv->main_iobase + dac_msb_4020_reg(chan));
3164 writew(data[0], devpriv->main_iobase + dac_convert_reg(chan));
3167 /* remember output value */
3168 devpriv->ao_value[chan] = data[0];
3173 static int ao_readback_insn(struct comedi_device *dev,
3174 struct comedi_subdevice *s,
3175 struct comedi_insn *insn, unsigned int *data)
3177 struct pcidas64_private *devpriv = dev->private;
3179 data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)];
3184 static void set_dac_control0_reg(struct comedi_device *dev,
3185 const struct comedi_cmd *cmd)
3187 struct pcidas64_private *devpriv = dev->private;
3188 unsigned int bits = DAC_ENABLE_BIT | WAVEFORM_GATE_LEVEL_BIT |
3189 WAVEFORM_GATE_ENABLE_BIT | WAVEFORM_GATE_SELECT_BIT;
3191 if (cmd->start_src == TRIG_EXT) {
3192 bits |= WAVEFORM_TRIG_EXT_BITS;
3193 if (cmd->start_arg & CR_INVERT)
3194 bits |= WAVEFORM_TRIG_FALLING_BIT;
3196 bits |= WAVEFORM_TRIG_SOFT_BITS;
3198 if (cmd->scan_begin_src == TRIG_EXT) {
3199 bits |= DAC_EXT_UPDATE_ENABLE_BIT;
3200 if (cmd->scan_begin_arg & CR_INVERT)
3201 bits |= DAC_EXT_UPDATE_FALLING_BIT;
3203 writew(bits, devpriv->main_iobase + DAC_CONTROL0_REG);
3206 static void set_dac_control1_reg(struct comedi_device *dev,
3207 const struct comedi_cmd *cmd)
3209 struct pcidas64_private *devpriv = dev->private;
3212 for (i = 0; i < cmd->chanlist_len; i++) {
3215 channel = CR_CHAN(cmd->chanlist[i]);
3216 range = CR_RANGE(cmd->chanlist[i]);
3217 set_dac_range_bits(dev, &devpriv->dac_control1_bits, channel,
3220 devpriv->dac_control1_bits |= DAC_SW_GATE_BIT;
3221 writew(devpriv->dac_control1_bits,
3222 devpriv->main_iobase + DAC_CONTROL1_REG);
3225 static void set_dac_select_reg(struct comedi_device *dev,
3226 const struct comedi_cmd *cmd)
3228 struct pcidas64_private *devpriv = dev->private;
3230 unsigned int first_channel, last_channel;
3232 first_channel = CR_CHAN(cmd->chanlist[0]);
3233 last_channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
3234 if (last_channel < first_channel)
3235 comedi_error(dev, "bug! last ao channel < first ao channel");
3237 bits = (first_channel & 0x7) | (last_channel & 0x7) << 3;
3239 writew(bits, devpriv->main_iobase + DAC_SELECT_REG);
3242 static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags)
3244 return get_divisor(ns, flags) - 2;
3247 static void set_dac_interval_regs(struct comedi_device *dev,
3248 const struct comedi_cmd *cmd)
3250 struct pcidas64_private *devpriv = dev->private;
3251 unsigned int divisor;
3253 if (cmd->scan_begin_src != TRIG_TIMER)
3256 divisor = get_ao_divisor(cmd->scan_begin_arg, cmd->flags);
3257 if (divisor > max_counter_value) {
3258 comedi_error(dev, "bug! ao divisor too big");
3259 divisor = max_counter_value;
3261 writew(divisor & 0xffff,
3262 devpriv->main_iobase + DAC_SAMPLE_INTERVAL_LOWER_REG);
3263 writew((divisor >> 16) & 0xff,
3264 devpriv->main_iobase + DAC_SAMPLE_INTERVAL_UPPER_REG);
3267 static int prep_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3269 struct pcidas64_private *devpriv = dev->private;
3270 unsigned int num_bytes;
3273 /* clear queue pointer too, since external queue has
3274 * weird interactions with ao fifo */
3275 writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
3276 writew(0, devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
3278 num_bytes = (DAC_FIFO_SIZE / 2) * bytes_in_sample;
3279 if (cmd->stop_src == TRIG_COUNT &&
3280 num_bytes / bytes_in_sample > devpriv->ao_count)
3281 num_bytes = devpriv->ao_count * bytes_in_sample;
3282 num_bytes = cfc_read_array_from_buffer(dev->write_subdev,
3283 devpriv->ao_bounce_buffer,
3285 for (i = 0; i < num_bytes / bytes_in_sample; i++) {
3286 writew(devpriv->ao_bounce_buffer[i],
3287 devpriv->main_iobase + DAC_FIFO_REG);
3289 devpriv->ao_count -= num_bytes / bytes_in_sample;
3290 if (cmd->stop_src == TRIG_COUNT && devpriv->ao_count == 0)
3292 num_bytes = load_ao_dma_buffer(dev, cmd);
3295 load_ao_dma(dev, cmd);
3297 dma_start_sync(dev, 0);
3302 static inline int external_ai_queue_in_use(struct comedi_device *dev)
3304 const struct pcidas64_board *thisboard = comedi_board(dev);
3306 if (dev->read_subdev->busy)
3308 if (thisboard->layout == LAYOUT_4020)
3310 else if (use_internal_queue_6xxx(&dev->read_subdev->async->cmd))
3315 static int ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3316 unsigned int trig_num)
3318 struct pcidas64_private *devpriv = dev->private;
3319 struct comedi_cmd *cmd = &s->async->cmd;
3325 retval = prep_ao_dma(dev, cmd);
3329 set_dac_control0_reg(dev, cmd);
3331 if (cmd->start_src == TRIG_INT)
3332 writew(0, devpriv->main_iobase + DAC_START_REG);
3334 s->async->inttrig = NULL;
3339 static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3341 struct pcidas64_private *devpriv = dev->private;
3342 struct comedi_cmd *cmd = &s->async->cmd;
3344 if (external_ai_queue_in_use(dev)) {
3345 warn_external_queue(dev);
3348 /* disable analog output system during setup */
3349 writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3351 devpriv->ao_dma_index = 0;
3352 devpriv->ao_count = cmd->stop_arg * cmd->chanlist_len;
3354 set_dac_select_reg(dev, cmd);
3355 set_dac_interval_regs(dev, cmd);
3356 load_first_dma_descriptor(dev, 0, devpriv->ao_dma_desc_bus_addr |
3357 PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT);
3359 set_dac_control1_reg(dev, cmd);
3360 s->async->inttrig = ao_inttrig;
3365 static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3366 struct comedi_cmd *cmd)
3368 const struct pcidas64_board *thisboard = comedi_board(dev);
3370 unsigned int tmp_arg;
3373 /* Step 1 : check if triggers are trivially valid */
3375 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3376 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
3377 TRIG_TIMER | TRIG_EXT);
3378 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3379 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3380 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3385 /* Step 2a : make sure trigger sources are unique */
3387 err |= cfc_check_trigger_is_unique(cmd->start_src);
3388 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
3390 /* Step 2b : and mutually compatible */
3392 if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
3394 if (cmd->stop_src != TRIG_COUNT &&
3395 cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
3401 /* Step 3: check if arguments are trivially valid */
3403 if (cmd->scan_begin_src == TRIG_TIMER) {
3404 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
3405 thisboard->ao_scan_speed);
3406 if (get_ao_divisor(cmd->scan_begin_arg, cmd->flags) >
3407 max_counter_value) {
3408 cmd->scan_begin_arg = (max_counter_value + 2) *
3414 err |= cfc_check_trigger_arg_min(&cmd->chanlist_len, 1);
3415 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3420 /* step 4: fix up any arguments */
3422 if (cmd->scan_begin_src == TRIG_TIMER) {
3423 tmp_arg = cmd->scan_begin_arg;
3424 cmd->scan_begin_arg = get_divisor(cmd->scan_begin_arg,
3425 cmd->flags) * TIMER_BASE;
3426 if (tmp_arg != cmd->scan_begin_arg)
3433 if (cmd->chanlist) {
3434 unsigned int first_channel = CR_CHAN(cmd->chanlist[0]);
3435 for (i = 1; i < cmd->chanlist_len; i++) {
3436 if (CR_CHAN(cmd->chanlist[i]) != first_channel + i) {
3438 "chanlist must use consecutive channels");
3451 static int ao_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3453 struct pcidas64_private *devpriv = dev->private;
3455 writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3460 static int dio_callback(int dir, int port, int data, unsigned long arg)
3462 void __iomem *iobase = (void __iomem *)arg;
3464 writeb(data, iobase + port);
3465 DEBUG_PRINT("wrote 0x%x to port %i\n", data, port);
3468 return readb(iobase + port);
3472 static int dio_callback_4020(int dir, int port, int data, unsigned long arg)
3474 void __iomem *iobase = (void __iomem *)arg;
3476 writew(data, iobase + 2 * port);
3479 return readw(iobase + 2 * port);
3483 static int di_rbits(struct comedi_device *dev, struct comedi_subdevice *s,
3484 struct comedi_insn *insn, unsigned int *data)
3486 struct pcidas64_private *devpriv = dev->private;
3489 bits = readb(devpriv->dio_counter_iobase + DI_REG);
3497 static int do_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
3498 struct comedi_insn *insn, unsigned int *data)
3500 struct pcidas64_private *devpriv = dev->private;
3503 /* zero bits we are going to change */
3504 s->state &= ~data[0];
3506 s->state |= data[0] & data[1];
3508 writeb(s->state, devpriv->dio_counter_iobase + DO_REG);
3515 static int dio_60xx_config_insn(struct comedi_device *dev,
3516 struct comedi_subdevice *s,
3517 struct comedi_insn *insn, unsigned int *data)
3519 struct pcidas64_private *devpriv = dev->private;
3522 mask = 1 << CR_CHAN(insn->chanspec);
3525 case INSN_CONFIG_DIO_INPUT:
3526 s->io_bits &= ~mask;
3528 case INSN_CONFIG_DIO_OUTPUT:
3531 case INSN_CONFIG_DIO_QUERY:
3532 data[1] = (s->io_bits & mask) ? COMEDI_OUTPUT : COMEDI_INPUT;
3539 devpriv->dio_counter_iobase + DIO_DIRECTION_60XX_REG);
3544 static int dio_60xx_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
3545 struct comedi_insn *insn, unsigned int *data)
3547 struct pcidas64_private *devpriv = dev->private;
3550 s->state &= ~data[0];
3551 s->state |= (data[0] & data[1]);
3553 devpriv->dio_counter_iobase + DIO_DATA_60XX_REG);
3556 data[1] = readb(devpriv->dio_counter_iobase + DIO_DATA_60XX_REG);
3561 /* pci-6025 8800 caldac:
3562 * address 0 == dac channel 0 offset
3563 * address 1 == dac channel 0 gain
3564 * address 2 == dac channel 1 offset
3565 * address 3 == dac channel 1 gain
3566 * address 4 == fine adc offset
3567 * address 5 == coarse adc offset
3568 * address 6 == coarse adc gain
3569 * address 7 == fine adc gain
3571 /* pci-6402/16 uses all 8 channels for dac:
3572 * address 0 == dac channel 0 fine gain
3573 * address 1 == dac channel 0 coarse gain
3574 * address 2 == dac channel 0 coarse offset
3575 * address 3 == dac channel 1 coarse offset
3576 * address 4 == dac channel 1 fine gain
3577 * address 5 == dac channel 1 coarse gain
3578 * address 6 == dac channel 0 fine offset
3579 * address 7 == dac channel 1 fine offset
3582 static int caldac_8800_write(struct comedi_device *dev, unsigned int address,
3585 struct pcidas64_private *devpriv = dev->private;
3586 static const int num_caldac_channels = 8;
3587 static const int bitstream_length = 11;
3588 unsigned int bitstream = ((address & 0x7) << 8) | value;
3589 unsigned int bit, register_bits;
3590 static const int caldac_8800_udelay = 1;
3592 if (address >= num_caldac_channels) {
3593 comedi_error(dev, "illegal caldac channel");
3596 for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3598 if (bitstream & bit)
3599 register_bits |= SERIAL_DATA_IN_BIT;
3600 udelay(caldac_8800_udelay);
3601 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3602 register_bits |= SERIAL_CLOCK_BIT;
3603 udelay(caldac_8800_udelay);
3604 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3606 udelay(caldac_8800_udelay);
3607 writew(SELECT_8800_BIT, devpriv->main_iobase + CALIBRATION_REG);
3608 udelay(caldac_8800_udelay);
3609 writew(0, devpriv->main_iobase + CALIBRATION_REG);
3610 udelay(caldac_8800_udelay);
3615 static int caldac_i2c_write(struct comedi_device *dev,
3616 unsigned int caldac_channel, unsigned int value)
3618 uint8_t serial_bytes[3];
3621 /* manual has gain and offset bits switched */
3628 NOT_CLEAR_REGISTERS = 0x20,
3631 switch (caldac_channel) {
3632 case 0: /* chan 0 offset */
3633 i2c_addr = CALDAC0_I2C_ADDR;
3634 serial_bytes[0] = OFFSET_0_2;
3636 case 1: /* chan 1 offset */
3637 i2c_addr = CALDAC0_I2C_ADDR;
3638 serial_bytes[0] = OFFSET_1_3;
3640 case 2: /* chan 2 offset */
3641 i2c_addr = CALDAC1_I2C_ADDR;
3642 serial_bytes[0] = OFFSET_0_2;
3644 case 3: /* chan 3 offset */
3645 i2c_addr = CALDAC1_I2C_ADDR;
3646 serial_bytes[0] = OFFSET_1_3;
3648 case 4: /* chan 0 gain */
3649 i2c_addr = CALDAC0_I2C_ADDR;
3650 serial_bytes[0] = GAIN_0_2;
3652 case 5: /* chan 1 gain */
3653 i2c_addr = CALDAC0_I2C_ADDR;
3654 serial_bytes[0] = GAIN_1_3;
3656 case 6: /* chan 2 gain */
3657 i2c_addr = CALDAC1_I2C_ADDR;
3658 serial_bytes[0] = GAIN_0_2;
3660 case 7: /* chan 3 gain */
3661 i2c_addr = CALDAC1_I2C_ADDR;
3662 serial_bytes[0] = GAIN_1_3;
3665 comedi_error(dev, "invalid caldac channel\n");
3669 serial_bytes[1] = NOT_CLEAR_REGISTERS | ((value >> 8) & 0xf);
3670 serial_bytes[2] = value & 0xff;
3671 i2c_write(dev, i2c_addr, serial_bytes, 3);
3675 static void caldac_write(struct comedi_device *dev, unsigned int channel,
3678 const struct pcidas64_board *thisboard = comedi_board(dev);
3679 struct pcidas64_private *devpriv = dev->private;
3681 devpriv->caldac_state[channel] = value;
3683 switch (thisboard->layout) {
3686 caldac_8800_write(dev, channel, value);
3689 caldac_i2c_write(dev, channel, value);
3696 static int calib_write_insn(struct comedi_device *dev,
3697 struct comedi_subdevice *s,
3698 struct comedi_insn *insn, unsigned int *data)
3700 struct pcidas64_private *devpriv = dev->private;
3701 int channel = CR_CHAN(insn->chanspec);
3703 /* return immediately if setting hasn't changed, since
3704 * programming these things is slow */
3705 if (devpriv->caldac_state[channel] == data[0])
3708 caldac_write(dev, channel, data[0]);
3713 static int calib_read_insn(struct comedi_device *dev,
3714 struct comedi_subdevice *s, struct comedi_insn *insn,
3717 struct pcidas64_private *devpriv = dev->private;
3718 unsigned int channel = CR_CHAN(insn->chanspec);
3720 data[0] = devpriv->caldac_state[channel];
3725 static void ad8402_write(struct comedi_device *dev, unsigned int channel,
3728 struct pcidas64_private *devpriv = dev->private;
3729 static const int bitstream_length = 10;
3730 unsigned int bit, register_bits;
3731 unsigned int bitstream = ((channel & 0x3) << 8) | (value & 0xff);
3732 static const int ad8402_udelay = 1;
3734 devpriv->ad8402_state[channel] = value;
3736 register_bits = SELECT_8402_64XX_BIT;
3737 udelay(ad8402_udelay);
3738 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3740 for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3741 if (bitstream & bit)
3742 register_bits |= SERIAL_DATA_IN_BIT;
3744 register_bits &= ~SERIAL_DATA_IN_BIT;
3745 udelay(ad8402_udelay);
3746 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3747 udelay(ad8402_udelay);
3748 writew(register_bits | SERIAL_CLOCK_BIT,
3749 devpriv->main_iobase + CALIBRATION_REG);
3752 udelay(ad8402_udelay);
3753 writew(0, devpriv->main_iobase + CALIBRATION_REG);
3756 /* for pci-das6402/16, channel 0 is analog input gain and channel 1 is offset */
3757 static int ad8402_write_insn(struct comedi_device *dev,
3758 struct comedi_subdevice *s,
3759 struct comedi_insn *insn, unsigned int *data)
3761 struct pcidas64_private *devpriv = dev->private;
3762 int channel = CR_CHAN(insn->chanspec);
3764 /* return immediately if setting hasn't changed, since
3765 * programming these things is slow */
3766 if (devpriv->ad8402_state[channel] == data[0])
3769 devpriv->ad8402_state[channel] = data[0];
3771 ad8402_write(dev, channel, data[0]);
3776 static int ad8402_read_insn(struct comedi_device *dev,
3777 struct comedi_subdevice *s,
3778 struct comedi_insn *insn, unsigned int *data)
3780 struct pcidas64_private *devpriv = dev->private;
3781 unsigned int channel = CR_CHAN(insn->chanspec);
3783 data[0] = devpriv->ad8402_state[channel];
3788 static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address)
3790 struct pcidas64_private *devpriv = dev->private;
3791 static const int bitstream_length = 11;
3792 static const int read_command = 0x6;
3793 unsigned int bitstream = (read_command << 8) | address;
3795 void __iomem * const plx_control_addr =
3796 devpriv->plx9080_iobase + PLX_CONTROL_REG;
3798 static const int value_length = 16;
3799 static const int eeprom_udelay = 1;
3801 udelay(eeprom_udelay);
3802 devpriv->plx_control_bits &= ~CTL_EE_CLK & ~CTL_EE_CS;
3803 /* make sure we don't send anything to the i2c bus on 4020 */
3804 devpriv->plx_control_bits |= CTL_USERO;
3805 writel(devpriv->plx_control_bits, plx_control_addr);
3806 /* activate serial eeprom */
3807 udelay(eeprom_udelay);
3808 devpriv->plx_control_bits |= CTL_EE_CS;
3809 writel(devpriv->plx_control_bits, plx_control_addr);
3811 /* write read command and desired memory address */
3812 for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3813 /* set bit to be written */
3814 udelay(eeprom_udelay);
3815 if (bitstream & bit)
3816 devpriv->plx_control_bits |= CTL_EE_W;
3818 devpriv->plx_control_bits &= ~CTL_EE_W;
3819 writel(devpriv->plx_control_bits, plx_control_addr);
3821 udelay(eeprom_udelay);
3822 devpriv->plx_control_bits |= CTL_EE_CLK;
3823 writel(devpriv->plx_control_bits, plx_control_addr);
3824 udelay(eeprom_udelay);
3825 devpriv->plx_control_bits &= ~CTL_EE_CLK;
3826 writel(devpriv->plx_control_bits, plx_control_addr);
3828 /* read back value from eeprom memory location */
3830 for (bit = 1 << (value_length - 1); bit; bit >>= 1) {
3832 udelay(eeprom_udelay);
3833 devpriv->plx_control_bits |= CTL_EE_CLK;
3834 writel(devpriv->plx_control_bits, plx_control_addr);
3835 udelay(eeprom_udelay);
3836 devpriv->plx_control_bits &= ~CTL_EE_CLK;
3837 writel(devpriv->plx_control_bits, plx_control_addr);
3838 udelay(eeprom_udelay);
3839 if (readl(plx_control_addr) & CTL_EE_R)
3843 /* deactivate eeprom serial input */
3844 udelay(eeprom_udelay);
3845 devpriv->plx_control_bits &= ~CTL_EE_CS;
3846 writel(devpriv->plx_control_bits, plx_control_addr);
3851 static int eeprom_read_insn(struct comedi_device *dev,
3852 struct comedi_subdevice *s,
3853 struct comedi_insn *insn, unsigned int *data)
3855 data[0] = read_eeprom(dev, CR_CHAN(insn->chanspec));
3860 /* Allocate and initialize the subdevice structures.
3862 static int setup_subdevices(struct comedi_device *dev)
3864 const struct pcidas64_board *thisboard = comedi_board(dev);
3865 struct pcidas64_private *devpriv = dev->private;
3866 struct comedi_subdevice *s;
3867 void __iomem *dio_8255_iobase;
3871 ret = comedi_alloc_subdevices(dev, 10);
3875 s = &dev->subdevices[0];
3876 /* analog input subdevice */
3877 dev->read_subdev = s;
3878 s->type = COMEDI_SUBD_AI;
3879 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DITHER | SDF_CMD_READ;
3880 if (thisboard->layout == LAYOUT_60XX)
3881 s->subdev_flags |= SDF_COMMON | SDF_DIFF;
3882 else if (thisboard->layout == LAYOUT_64XX)
3883 s->subdev_flags |= SDF_DIFF;
3884 /* XXX Number of inputs in differential mode is ignored */
3885 s->n_chan = thisboard->ai_se_chans;
3886 s->len_chanlist = 0x2000;
3887 s->maxdata = (1 << thisboard->ai_bits) - 1;
3888 s->range_table = thisboard->ai_range_table;
3889 s->insn_read = ai_rinsn;
3890 s->insn_config = ai_config_insn;
3892 s->do_cmdtest = ai_cmdtest;
3893 s->cancel = ai_cancel;
3894 if (thisboard->layout == LAYOUT_4020) {
3896 /* set adc to read from inputs
3897 * (not internal calibration sources) */
3898 devpriv->i2c_cal_range_bits = adc_src_4020_bits(4);
3899 /* set channels to +-5 volt input ranges */
3900 for (i = 0; i < s->n_chan; i++)
3901 devpriv->i2c_cal_range_bits |= attenuate_bit(i);
3902 data = devpriv->i2c_cal_range_bits;
3903 i2c_write(dev, RANGE_CAL_I2C_ADDR, &data, sizeof(data));
3906 /* analog output subdevice */
3907 s = &dev->subdevices[1];
3908 if (thisboard->ao_nchan) {
3909 s->type = COMEDI_SUBD_AO;
3910 s->subdev_flags = SDF_READABLE | SDF_WRITABLE |
3911 SDF_GROUND | SDF_CMD_WRITE;
3912 s->n_chan = thisboard->ao_nchan;
3913 s->maxdata = (1 << thisboard->ao_bits) - 1;
3914 s->range_table = thisboard->ao_range_table;
3915 s->insn_read = ao_readback_insn;
3916 s->insn_write = ao_winsn;
3917 if (ao_cmd_is_supported(thisboard)) {
3918 dev->write_subdev = s;
3919 s->do_cmdtest = ao_cmdtest;
3921 s->len_chanlist = thisboard->ao_nchan;
3922 s->cancel = ao_cancel;
3925 s->type = COMEDI_SUBD_UNUSED;
3929 s = &dev->subdevices[2];
3930 if (thisboard->layout == LAYOUT_64XX) {
3931 s->type = COMEDI_SUBD_DI;
3932 s->subdev_flags = SDF_READABLE;
3935 s->range_table = &range_digital;
3936 s->insn_bits = di_rbits;
3938 s->type = COMEDI_SUBD_UNUSED;
3940 /* digital output */
3941 if (thisboard->layout == LAYOUT_64XX) {
3942 s = &dev->subdevices[3];
3943 s->type = COMEDI_SUBD_DO;
3944 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
3947 s->range_table = &range_digital;
3948 s->insn_bits = do_wbits;
3950 s->type = COMEDI_SUBD_UNUSED;
3953 s = &dev->subdevices[4];
3954 if (thisboard->has_8255) {
3955 if (thisboard->layout == LAYOUT_4020) {
3956 dio_8255_iobase = devpriv->main_iobase + I8255_4020_REG;
3957 subdev_8255_init(dev, s, dio_callback_4020,
3958 (unsigned long)dio_8255_iobase);
3961 devpriv->dio_counter_iobase + DIO_8255_OFFSET;
3962 subdev_8255_init(dev, s, dio_callback,
3963 (unsigned long)dio_8255_iobase);
3966 s->type = COMEDI_SUBD_UNUSED;
3968 /* 8 channel dio for 60xx */
3969 s = &dev->subdevices[5];
3970 if (thisboard->layout == LAYOUT_60XX) {
3971 s->type = COMEDI_SUBD_DIO;
3972 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
3975 s->range_table = &range_digital;
3976 s->insn_config = dio_60xx_config_insn;
3977 s->insn_bits = dio_60xx_wbits;
3979 s->type = COMEDI_SUBD_UNUSED;
3982 s = &dev->subdevices[6];
3983 s->type = COMEDI_SUBD_CALIB;
3984 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3986 if (thisboard->layout == LAYOUT_4020)
3990 s->insn_read = calib_read_insn;
3991 s->insn_write = calib_write_insn;
3992 for (i = 0; i < s->n_chan; i++)
3993 caldac_write(dev, i, s->maxdata / 2);
3995 /* 2 channel ad8402 potentiometer */
3996 s = &dev->subdevices[7];
3997 if (thisboard->layout == LAYOUT_64XX) {
3998 s->type = COMEDI_SUBD_CALIB;
3999 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4001 s->insn_read = ad8402_read_insn;
4002 s->insn_write = ad8402_write_insn;
4004 for (i = 0; i < s->n_chan; i++)
4005 ad8402_write(dev, i, s->maxdata / 2);
4007 s->type = COMEDI_SUBD_UNUSED;
4009 /* serial EEPROM, if present */
4010 s = &dev->subdevices[8];
4011 if (readl(devpriv->plx9080_iobase + PLX_CONTROL_REG) & CTL_EECHK) {
4012 s->type = COMEDI_SUBD_MEMORY;
4013 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
4015 s->maxdata = 0xffff;
4016 s->insn_read = eeprom_read_insn;
4018 s->type = COMEDI_SUBD_UNUSED;
4020 /* user counter subd XXX */
4021 s = &dev->subdevices[9];
4022 s->type = COMEDI_SUBD_UNUSED;
4027 static int auto_attach(struct comedi_device *dev,
4028 unsigned long context)
4030 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
4031 const struct pcidas64_board *thisboard = NULL;
4032 struct pcidas64_private *devpriv;
4033 uint32_t local_range, local_decode;
4036 if (context < ARRAY_SIZE(pcidas64_boards))
4037 thisboard = &pcidas64_boards[context];
4040 dev->board_ptr = thisboard;
4042 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
4045 dev->private = devpriv;
4047 retval = comedi_pci_enable(dev);
4050 pci_set_master(pcidev);
4052 /* Initialize dev->board_name */
4053 dev->board_name = thisboard->name;
4055 devpriv->main_phys_iobase = pci_resource_start(pcidev, 2);
4056 devpriv->dio_counter_phys_iobase = pci_resource_start(pcidev, 3);
4058 devpriv->plx9080_iobase = pci_ioremap_bar(pcidev, 0);
4059 devpriv->main_iobase = pci_ioremap_bar(pcidev, 2);
4060 devpriv->dio_counter_iobase = pci_ioremap_bar(pcidev, 3);
4062 if (!devpriv->plx9080_iobase || !devpriv->main_iobase
4063 || !devpriv->dio_counter_iobase) {
4064 dev_warn(dev->class_dev, "failed to remap io memory\n");
4068 DEBUG_PRINT(" plx9080 remapped to 0x%p\n", devpriv->plx9080_iobase);
4069 DEBUG_PRINT(" main remapped to 0x%p\n", devpriv->main_iobase);
4070 DEBUG_PRINT(" diocounter remapped to 0x%p\n",
4071 devpriv->dio_counter_iobase);
4073 /* figure out what local addresses are */
4074 local_range = readl(devpriv->plx9080_iobase + PLX_LAS0RNG_REG) &
4076 local_decode = readl(devpriv->plx9080_iobase + PLX_LAS0MAP_REG) &
4077 local_range & LMAP_MEM_MASK;
4078 devpriv->local0_iobase = ((uint32_t)devpriv->main_phys_iobase &
4079 ~local_range) | local_decode;
4080 local_range = readl(devpriv->plx9080_iobase + PLX_LAS1RNG_REG) &
4082 local_decode = readl(devpriv->plx9080_iobase + PLX_LAS1MAP_REG) &
4083 local_range & LMAP_MEM_MASK;
4084 devpriv->local1_iobase = ((uint32_t)devpriv->dio_counter_phys_iobase &
4085 ~local_range) | local_decode;
4087 DEBUG_PRINT(" local 0 io addr 0x%x\n", devpriv->local0_iobase);
4088 DEBUG_PRINT(" local 1 io addr 0x%x\n", devpriv->local1_iobase);
4090 retval = alloc_and_init_dma_members(dev);
4094 devpriv->hw_revision =
4095 hw_revision(dev, readw(devpriv->main_iobase + HW_STATUS_REG));
4096 dev_dbg(dev->class_dev, "stc hardware revision %i\n",
4097 devpriv->hw_revision);
4099 init_stc_registers(dev);
4101 if (request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
4102 "cb_pcidas64", dev)) {
4103 dev_dbg(dev->class_dev, "unable to allocate irq %u\n",
4107 dev->irq = pcidev->irq;
4108 dev_dbg(dev->class_dev, "irq %u\n", dev->irq);
4110 retval = setup_subdevices(dev);
4117 static void detach(struct comedi_device *dev)
4119 const struct pcidas64_board *thisboard = comedi_board(dev);
4120 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
4121 struct pcidas64_private *devpriv = dev->private;
4125 free_irq(dev->irq, dev);
4128 if (devpriv->plx9080_iobase) {
4129 disable_plx_interrupts(dev);
4130 iounmap(devpriv->plx9080_iobase);
4132 if (devpriv->main_iobase)
4133 iounmap(devpriv->main_iobase);
4134 if (devpriv->dio_counter_iobase)
4135 iounmap(devpriv->dio_counter_iobase);
4136 /* free pci dma buffers */
4137 for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
4138 if (devpriv->ai_buffer[i])
4139 pci_free_consistent(pcidev,
4141 devpriv->ai_buffer[i],
4142 devpriv->ai_buffer_bus_addr[i]);
4144 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
4145 if (devpriv->ao_buffer[i])
4146 pci_free_consistent(pcidev,
4148 devpriv->ao_buffer[i],
4149 devpriv->ao_buffer_bus_addr[i]);
4151 /* free dma descriptors */
4152 if (devpriv->ai_dma_desc)
4153 pci_free_consistent(pcidev,
4154 sizeof(struct plx_dma_desc) *
4155 ai_dma_ring_count(thisboard),
4156 devpriv->ai_dma_desc,
4157 devpriv->ai_dma_desc_bus_addr);
4158 if (devpriv->ao_dma_desc)
4159 pci_free_consistent(pcidev,
4160 sizeof(struct plx_dma_desc) *
4162 devpriv->ao_dma_desc,
4163 devpriv->ao_dma_desc_bus_addr);
4166 comedi_spriv_free(dev, 4);
4167 comedi_pci_disable(dev);
4170 static struct comedi_driver cb_pcidas64_driver = {
4171 .driver_name = "cb_pcidas64",
4172 .module = THIS_MODULE,
4173 .auto_attach = auto_attach,
4177 static int cb_pcidas64_pci_probe(struct pci_dev *dev,
4178 const struct pci_device_id *id)
4180 return comedi_pci_auto_config(dev, &cb_pcidas64_driver,
4184 static DEFINE_PCI_DEVICE_TABLE(cb_pcidas64_pci_table) = {
4185 { PCI_VDEVICE(CB, 0x001d), BOARD_PCIDAS6402_16 },
4186 { PCI_VDEVICE(CB, 0x001e), BOARD_PCIDAS6402_12 },
4187 { PCI_VDEVICE(CB, 0x0035), BOARD_PCIDAS64_M1_16 },
4188 { PCI_VDEVICE(CB, 0x0036), BOARD_PCIDAS64_M2_16 },
4189 { PCI_VDEVICE(CB, 0x0037), BOARD_PCIDAS64_M3_16 },
4190 { PCI_VDEVICE(CB, 0x0052), BOARD_PCIDAS4020_12 },
4191 { PCI_VDEVICE(CB, 0x005d), BOARD_PCIDAS6023 },
4192 { PCI_VDEVICE(CB, 0x005e), BOARD_PCIDAS6025 },
4193 { PCI_VDEVICE(CB, 0x005f), BOARD_PCIDAS6030 },
4194 { PCI_VDEVICE(CB, 0x0060), BOARD_PCIDAS6031 },
4195 { PCI_VDEVICE(CB, 0x0061), BOARD_PCIDAS6032 },
4196 { PCI_VDEVICE(CB, 0x0062), BOARD_PCIDAS6033 },
4197 { PCI_VDEVICE(CB, 0x0063), BOARD_PCIDAS6034 },
4198 { PCI_VDEVICE(CB, 0x0064), BOARD_PCIDAS6035 },
4199 { PCI_VDEVICE(CB, 0x0065), BOARD_PCIDAS6040 },
4200 { PCI_VDEVICE(CB, 0x0066), BOARD_PCIDAS6052 },
4201 { PCI_VDEVICE(CB, 0x0067), BOARD_PCIDAS6070 },
4202 { PCI_VDEVICE(CB, 0x0068), BOARD_PCIDAS6071 },
4203 { PCI_VDEVICE(CB, 0x006f), BOARD_PCIDAS6036 },
4204 { PCI_VDEVICE(CB, 0x0078), BOARD_PCIDAS6013 },
4205 { PCI_VDEVICE(CB, 0x0079), BOARD_PCIDAS6014 },
4208 MODULE_DEVICE_TABLE(pci, cb_pcidas64_pci_table);
4210 static struct pci_driver cb_pcidas64_pci_driver = {
4211 .name = "cb_pcidas64",
4212 .id_table = cb_pcidas64_pci_table,
4213 .probe = cb_pcidas64_pci_probe,
4214 .remove = comedi_pci_auto_unconfig,
4216 module_comedi_pci_driver(cb_pcidas64_driver, cb_pcidas64_pci_driver);
4218 MODULE_AUTHOR("Comedi http://www.comedi.org");
4219 MODULE_DESCRIPTION("Comedi low-level driver");
4220 MODULE_LICENSE("GPL");