drivers/staging/comedi/drivers/cb_pcidas64.c

   1 /*
   2     comedi/drivers/cb_pcidas64.c
   3     This is a driver for the ComputerBoards/MeasurementComputing PCI-DAS
   4     64xx, 60xx, and 4020 cards.
   5
   6     Author:  Frank Mori Hess <fmhess@users.sourceforge.net>
   7     Copyright (C) 2001, 2002 Frank Mori Hess
   8
   9     Thanks also go to the following people:
  10
  11     Steve Rosenbluth, for providing the source code for
  12     his pci-das6402 driver, and source code for working QNX pci-6402
  13     drivers by Greg Laird and Mariusz Bogacz.  None of the code was
  14     used directly here, but it was useful as an additional source of
  15     documentation on how to program the boards.
  16
  17     John Sims, for much testing and feedback on pcidas-4020 support.
  18
  19     COMEDI - Linux Control and Measurement Device Interface
  20     Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
  21
  22     This program is free software; you can redistribute it and/or modify
  23     it under the terms of the GNU General Public License as published by
  24     the Free Software Foundation; either version 2 of the License, or
  25     (at your option) any later version.
  26
  27     This program is distributed in the hope that it will be useful,
  28     but WITHOUT ANY WARRANTY; without even the implied warranty of
  29     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  30     GNU General Public License for more details.
  31 */
  32
  33 /*
  34  * Driver: cb_pcidas64
  35  * Description: MeasurementComputing PCI-DAS64xx, 60XX, and 4020 series
  36  *   with the PLX 9080 PCI controller
  37  * Author: Frank Mori Hess <fmhess@users.sourceforge.net>
  38  * Status: works
  39  * Updated: Fri, 02 Nov 2012 18:58:55 +0000
  40  * Devices: [Measurement Computing] PCI-DAS6402/16 (cb_pcidas64),
  41  *   PCI-DAS6402/12, PCI-DAS64/M1/16, PCI-DAS64/M2/16,
  42  *   PCI-DAS64/M3/16, PCI-DAS6402/16/JR, PCI-DAS64/M1/16/JR,
  43  *   PCI-DAS64/M2/16/JR, PCI-DAS64/M3/16/JR, PCI-DAS64/M1/14,
  44  *   PCI-DAS64/M2/14, PCI-DAS64/M3/14, PCI-DAS6013, PCI-DAS6014,
  45  *   PCI-DAS6023, PCI-DAS6025, PCI-DAS6030,
  46  *   PCI-DAS6031, PCI-DAS6032, PCI-DAS6033, PCI-DAS6034,
  47  *   PCI-DAS6035, PCI-DAS6036, PCI-DAS6040, PCI-DAS6052,
  48  *   PCI-DAS6070, PCI-DAS6071, PCI-DAS4020/12
  49  *
  50  * Configuration options:
  51  *   None.
  52  *
  53  * Manual attachment of PCI cards with the comedi_config utility is not
  54  * supported by this driver; they are attached automatically.
  55  *
  56  * These boards may be autocalibrated with the comedi_calibrate utility.
  57  *
  58  * To select the bnc trigger input on the 4020 (instead of the dio input),
  59  * specify a nonzero channel in the chanspec.  If you wish to use an external
  60  * master clock on the 4020, you may do so by setting the scan_begin_src
  61  * to TRIG_OTHER, and using an INSN_CONFIG_TIMER_1 configuration insn
  62  * to configure the divisor to use for the external clock.
  63  *
  64  * Some devices are not identified because the PCI device IDs are not yet
  65  * known. If you have such a board, please let the maintainers know.
  66  */
  67
  68 /*
  69
  70 TODO:
  71         make it return error if user attempts an ai command that uses the
  72         external queue, and an ao command simultaneously user counter subdevice
  73         there are a number of boards this driver will support when they are
  74         fully released, but does not yet since the pci device id numbers
  75         are not yet available.
  76
  77         support prescaled 100khz clock for slow pacing (not available on 6000
  78         series?)
  79
  80         make ao fifo size adjustable like ai fifo
  81 */
  82
  83 #include <linux/module.h>
  84 #include <linux/pci.h>
  85 #include <linux/delay.h>
  86 #include <linux/interrupt.h>
  87
  88 #include "../comedidev.h"
  89
  90 #include "8253.h"
  91 #include "8255.h"
  92 #include "plx9080.h"
  93 #include "comedi_fc.h"
  94
  95 #define TIMER_BASE 25           /*  40MHz master clock */
  96 /* 100kHz 'prescaled' clock for slow acquisition,
  97  * maybe I'll support this someday */
  98 #define PRESCALED_TIMER_BASE    10000
  99 #define DMA_BUFFER_SIZE 0x1000
 100
 101 /* maximum value that can be loaded into board's 24-bit counters*/
 102 static const int max_counter_value = 0xffffff;
 103
 104 /* PCI-DAS64xxx base addresses */
 105
 106 /* devpriv->main_iobase registers */
 107 enum write_only_registers {
 108         INTR_ENABLE_REG = 0x0,  /*  interrupt enable register */
 109         HW_CONFIG_REG = 0x2,    /*  hardware config register */
 110         DAQ_SYNC_REG = 0xc,
 111         DAQ_ATRIG_LOW_4020_REG = 0xc,
 112         ADC_CONTROL0_REG = 0x10,        /*  adc control register 0 */
 113         ADC_CONTROL1_REG = 0x12,        /*  adc control register 1 */
 114         CALIBRATION_REG = 0x14,
 115         /*  lower 16 bits of adc sample interval counter */
 116         ADC_SAMPLE_INTERVAL_LOWER_REG = 0x16,
 117         /*  upper 8 bits of adc sample interval counter */
 118         ADC_SAMPLE_INTERVAL_UPPER_REG = 0x18,
 119         /*  lower 16 bits of delay interval counter */
 120         ADC_DELAY_INTERVAL_LOWER_REG = 0x1a,
 121         /*  upper 8 bits of delay interval counter */
 122         ADC_DELAY_INTERVAL_UPPER_REG = 0x1c,
 123         /*  lower 16 bits of hardware conversion/scan counter */
 124         ADC_COUNT_LOWER_REG = 0x1e,
 125         /*  upper 8 bits of hardware conversion/scan counter */
 126         ADC_COUNT_UPPER_REG = 0x20,
 127         ADC_START_REG = 0x22,   /*  software trigger to start acquisition */
 128         ADC_CONVERT_REG = 0x24, /*  initiates single conversion */
 129         ADC_QUEUE_CLEAR_REG = 0x26,     /*  clears adc queue */
 130         ADC_QUEUE_LOAD_REG = 0x28,      /*  loads adc queue */
 131         ADC_BUFFER_CLEAR_REG = 0x2a,
 132         /*  high channel for internal queue, use adc_chan_bits() inline above */
 133         ADC_QUEUE_HIGH_REG = 0x2c,
 134         DAC_CONTROL0_REG = 0x50,        /*  dac control register 0 */
 135         DAC_CONTROL1_REG = 0x52,        /*  dac control register 0 */
 136         /*  lower 16 bits of dac sample interval counter */
 137         DAC_SAMPLE_INTERVAL_LOWER_REG = 0x54,
 138         /*  upper 8 bits of dac sample interval counter */
 139         DAC_SAMPLE_INTERVAL_UPPER_REG = 0x56,
 140         DAC_SELECT_REG = 0x60,
 141         DAC_START_REG = 0x64,
 142         DAC_BUFFER_CLEAR_REG = 0x66,    /*  clear dac buffer */
 143 };
 144
 145 static inline unsigned int dac_convert_reg(unsigned int channel)
 146 {
 147         return 0x70 + (2 * (channel & 0x1));
 148 }
 149
 150 static inline unsigned int dac_lsb_4020_reg(unsigned int channel)
 151 {
 152         return 0x70 + (4 * (channel & 0x1));
 153 }
 154
 155 static inline unsigned int dac_msb_4020_reg(unsigned int channel)
 156 {
 157         return 0x72 + (4 * (channel & 0x1));
 158 }
 159
 160 enum read_only_registers {
 161         /*  hardware status register,
 162          *  reading this apparently clears pending interrupts as well */
 163         HW_STATUS_REG = 0x0,
 164         PIPE1_READ_REG = 0x4,
 165         ADC_READ_PNTR_REG = 0x8,
 166         LOWER_XFER_REG = 0x10,
 167         ADC_WRITE_PNTR_REG = 0xc,
 168         PREPOST_REG = 0x14,
 169 };
 170
 171 enum read_write_registers {
 172         I8255_4020_REG = 0x48,  /*  8255 offset, for 4020 only */
 173         /*  external channel/gain queue, uses same bits as ADC_QUEUE_LOAD_REG */
 174         ADC_QUEUE_FIFO_REG = 0x100,
 175         ADC_FIFO_REG = 0x200,   /* adc data fifo */
 176         /* dac data fifo, has weird interactions with external channel queue */
 177         DAC_FIFO_REG = 0x300,
 178 };
 179
 180 /* dev->mmio registers */
 181 enum dio_counter_registers {
 182         DIO_8255_OFFSET = 0x0,
 183         DO_REG = 0x20,
 184         DI_REG = 0x28,
 185         DIO_DIRECTION_60XX_REG = 0x40,
 186         DIO_DATA_60XX_REG = 0x48,
 187 };
 188
 189 /* bit definitions for write-only registers */
 190
 191 enum intr_enable_contents {
 192         ADC_INTR_SRC_MASK = 0x3,        /*  adc interrupt source mask */
 193         ADC_INTR_QFULL_BITS = 0x0,      /*  interrupt fifo quarter full */
 194         ADC_INTR_EOC_BITS = 0x1,        /*  interrupt end of conversion */
 195         ADC_INTR_EOSCAN_BITS = 0x2,     /*  interrupt end of scan */
 196         ADC_INTR_EOSEQ_BITS = 0x3,      /*  interrupt end of sequence mask */
 197         EN_ADC_INTR_SRC_BIT = 0x4,      /*  enable adc interrupt source */
 198         EN_ADC_DONE_INTR_BIT = 0x8,     /*  enable adc acquisition done intr */
 199         DAC_INTR_SRC_MASK = 0x30,
 200         DAC_INTR_QEMPTY_BITS = 0x0,
 201         DAC_INTR_HIGH_CHAN_BITS = 0x10,
 202         EN_DAC_INTR_SRC_BIT = 0x40,     /*  enable dac interrupt source */
 203         EN_DAC_DONE_INTR_BIT = 0x80,
 204         EN_ADC_ACTIVE_INTR_BIT = 0x200, /*  enable adc active interrupt */
 205         EN_ADC_STOP_INTR_BIT = 0x400,   /*  enable adc stop trigger interrupt */
 206         EN_DAC_ACTIVE_INTR_BIT = 0x800, /*  enable dac active interrupt */
 207         EN_DAC_UNDERRUN_BIT = 0x4000,   /*  enable dac underrun status bit */
 208         EN_ADC_OVERRUN_BIT = 0x8000,    /*  enable adc overrun status bit */
 209 };
 210
 211 enum hw_config_contents {
 212         MASTER_CLOCK_4020_MASK = 0x3,   /*  master clock source mask for 4020 */
 213         INTERNAL_CLOCK_4020_BITS = 0x1, /*  use 40 MHz internal master clock */
 214         BNC_CLOCK_4020_BITS = 0x2,      /*  use BNC input for master clock */
 215         EXT_CLOCK_4020_BITS = 0x3,      /*  use dio input for master clock */
 216         EXT_QUEUE_BIT = 0x200,          /*  use external channel/gain queue */
 217         /*  use 225 nanosec strobe when loading dac instead of 50 nanosec */
 218         SLOW_DAC_BIT = 0x400,
 219         /*  bit with unknown function yet given as default value in pci-das64
 220          *  manual */
 221         HW_CONFIG_DUMMY_BITS = 0x2000,
 222         /*  bit selects channels 1/0 for analog input/output, otherwise 0/1 */
 223         DMA_CH_SELECT_BIT = 0x8000,
 224         FIFO_SIZE_REG = 0x4,            /*  allows adjustment of fifo sizes */
 225         DAC_FIFO_SIZE_MASK = 0xff00,    /*  bits that set dac fifo size */
 226         DAC_FIFO_BITS = 0xf800,         /*  8k sample ao fifo */
 227 };
 228 #define DAC_FIFO_SIZE 0x2000
 229
 230 enum daq_atrig_low_4020_contents {
 231         /*  use trig/ext clk bnc input for analog gate signal */
 232         EXT_AGATE_BNC_BIT = 0x8000,
 233         /*  use trig/ext clk bnc input for external stop trigger signal */
 234         EXT_STOP_TRIG_BNC_BIT = 0x4000,
 235         /*  use trig/ext clk bnc input for external start trigger signal */
 236         EXT_START_TRIG_BNC_BIT = 0x2000,
 237 };
 238
 239 static inline uint16_t analog_trig_low_threshold_bits(uint16_t threshold)
 240 {
 241         return threshold & 0xfff;
 242 }
 243
 244 enum adc_control0_contents {
 245         ADC_GATE_SRC_MASK = 0x3,        /*  bits that select gate */
 246         ADC_SOFT_GATE_BITS = 0x1,       /*  software gate */
 247         ADC_EXT_GATE_BITS = 0x2,        /*  external digital gate */
 248         ADC_ANALOG_GATE_BITS = 0x3,     /*  analog level gate */
 249         ADC_GATE_LEVEL_BIT = 0x4,       /*  level-sensitive gate (for digital) */
 250         ADC_GATE_POLARITY_BIT = 0x8,    /*  gate active low */
 251         ADC_START_TRIG_SOFT_BITS = 0x10,
 252         ADC_START_TRIG_EXT_BITS = 0x20,
 253         ADC_START_TRIG_ANALOG_BITS = 0x30,
 254         ADC_START_TRIG_MASK = 0x30,
 255         ADC_START_TRIG_FALLING_BIT = 0x40,      /*  trig 1 uses falling edge */
 256         /*  external pacing uses falling edge */
 257         ADC_EXT_CONV_FALLING_BIT = 0x800,
 258         /*  enable hardware scan counter */
 259         ADC_SAMPLE_COUNTER_EN_BIT = 0x1000,
 260         ADC_DMA_DISABLE_BIT = 0x4000,   /*  disables dma */
 261         ADC_ENABLE_BIT = 0x8000,        /*  master adc enable */
 262 };
 263
 264 enum adc_control1_contents {
 265         /*  should be set for boards with > 16 channels */
 266         ADC_QUEUE_CONFIG_BIT = 0x1,
 267         CONVERT_POLARITY_BIT = 0x10,
 268         EOC_POLARITY_BIT = 0x20,
 269         ADC_SW_GATE_BIT = 0x40, /*  software gate of adc */
 270         ADC_DITHER_BIT = 0x200, /*  turn on extra noise for dithering */
 271         RETRIGGER_BIT = 0x800,
 272         ADC_LO_CHANNEL_4020_MASK = 0x300,
 273         ADC_HI_CHANNEL_4020_MASK = 0xc00,
 274         TWO_CHANNEL_4020_BITS = 0x1000, /*  two channel mode for 4020 */
 275         FOUR_CHANNEL_4020_BITS = 0x2000, /*  four channel mode for 4020 */
 276         CHANNEL_MODE_4020_MASK = 0x3000,
 277         ADC_MODE_MASK = 0xf000,
 278 };
 279
 280 static inline uint16_t adc_lo_chan_4020_bits(unsigned int channel)
 281 {
 282         return (channel & 0x3) << 8;
 283 };
 284
 285 static inline uint16_t adc_hi_chan_4020_bits(unsigned int channel)
 286 {
 287         return (channel & 0x3) << 10;
 288 };
 289
 290 static inline uint16_t adc_mode_bits(unsigned int mode)
 291 {
 292         return (mode & 0xf) << 12;
 293 };
 294
 295 enum calibration_contents {
 296         SELECT_8800_BIT = 0x1,
 297         SELECT_8402_64XX_BIT = 0x2,
 298         SELECT_1590_60XX_BIT = 0x2,
 299         CAL_EN_64XX_BIT = 0x40, /*  calibration enable for 64xx series */
 300         SERIAL_DATA_IN_BIT = 0x80,
 301         SERIAL_CLOCK_BIT = 0x100,
 302         CAL_EN_60XX_BIT = 0x200, /*  calibration enable for 60xx series */
 303         CAL_GAIN_BIT = 0x800,
 304 };
 305
 306 /* calibration sources for 6025 are:
 307  *  0 : ground
 308  *  1 : 10V
 309  *  2 : 5V
 310  *  3 : 0.5V
 311  *  4 : 0.05V
 312  *  5 : ground
 313  *  6 : dac channel 0
 314  *  7 : dac channel 1
 315  */
 316
 317 static inline uint16_t adc_src_bits(unsigned int source)
 318 {
 319         return (source & 0xf) << 3;
 320 };
 321
 322 static inline uint16_t adc_convert_chan_4020_bits(unsigned int channel)
 323 {
 324         return (channel & 0x3) << 8;
 325 };
 326
 327 enum adc_queue_load_contents {
 328         UNIP_BIT = 0x800,       /*  unipolar/bipolar bit */
 329         ADC_SE_DIFF_BIT = 0x1000,       /*  single-ended/ differential bit */
 330         /*  non-referenced single-ended (common-mode input) */
 331         ADC_COMMON_BIT = 0x2000,
 332         QUEUE_EOSEQ_BIT = 0x4000,       /*  queue end of sequence */
 333         QUEUE_EOSCAN_BIT = 0x8000,      /*  queue end of scan */
 334 };
 335
 336 static inline uint16_t adc_chan_bits(unsigned int channel)
 337 {
 338         return channel & 0x3f;
 339 };
 340
 341 enum dac_control0_contents {
 342         DAC_ENABLE_BIT = 0x8000,        /*  dac controller enable bit */
 343         DAC_CYCLIC_STOP_BIT = 0x4000,
 344         DAC_WAVEFORM_MODE_BIT = 0x100,
 345         DAC_EXT_UPDATE_FALLING_BIT = 0x80,
 346         DAC_EXT_UPDATE_ENABLE_BIT = 0x40,
 347         WAVEFORM_TRIG_MASK = 0x30,
 348         WAVEFORM_TRIG_DISABLED_BITS = 0x0,
 349         WAVEFORM_TRIG_SOFT_BITS = 0x10,
 350         WAVEFORM_TRIG_EXT_BITS = 0x20,
 351         WAVEFORM_TRIG_ADC1_BITS = 0x30,
 352         WAVEFORM_TRIG_FALLING_BIT = 0x8,
 353         WAVEFORM_GATE_LEVEL_BIT = 0x4,
 354         WAVEFORM_GATE_ENABLE_BIT = 0x2,
 355         WAVEFORM_GATE_SELECT_BIT = 0x1,
 356 };
 357
 358 enum dac_control1_contents {
 359         DAC_WRITE_POLARITY_BIT = 0x800, /* board-dependent setting */
 360         DAC1_EXT_REF_BIT = 0x200,
 361         DAC0_EXT_REF_BIT = 0x100,
 362         DAC_OUTPUT_ENABLE_BIT = 0x80,   /*  dac output enable bit */
 363         DAC_UPDATE_POLARITY_BIT = 0x40, /* board-dependent setting */
 364         DAC_SW_GATE_BIT = 0x20,
 365         DAC1_UNIPOLAR_BIT = 0x8,
 366         DAC0_UNIPOLAR_BIT = 0x2,
 367 };
 368
 369 /* bit definitions for read-only registers */
 370 enum hw_status_contents {
 371         DAC_UNDERRUN_BIT = 0x1,
 372         ADC_OVERRUN_BIT = 0x2,
 373         DAC_ACTIVE_BIT = 0x4,
 374         ADC_ACTIVE_BIT = 0x8,
 375         DAC_INTR_PENDING_BIT = 0x10,
 376         ADC_INTR_PENDING_BIT = 0x20,
 377         DAC_DONE_BIT = 0x40,
 378         ADC_DONE_BIT = 0x80,
 379         EXT_INTR_PENDING_BIT = 0x100,
 380         ADC_STOP_BIT = 0x200,
 381 };
 382
 383 static inline uint16_t pipe_full_bits(uint16_t hw_status_bits)
 384 {
 385         return (hw_status_bits >> 10) & 0x3;
 386 };
 387
 388 static inline unsigned int dma_chain_flag_bits(uint16_t prepost_bits)
 389 {
 390         return (prepost_bits >> 6) & 0x3;
 391 }
 392
 393 static inline unsigned int adc_upper_read_ptr_code(uint16_t prepost_bits)
 394 {
 395         return (prepost_bits >> 12) & 0x3;
 396 }
 397
 398 static inline unsigned int adc_upper_write_ptr_code(uint16_t prepost_bits)
 399 {
 400         return (prepost_bits >> 14) & 0x3;
 401 }
 402
 403 /* I2C addresses for 4020 */
 404 enum i2c_addresses {
 405         RANGE_CAL_I2C_ADDR = 0x20,
 406         CALDAC0_I2C_ADDR = 0xc,
 407         CALDAC1_I2C_ADDR = 0xd,
 408 };
 409
 410 enum range_cal_i2c_contents {
 411         /*  bits that set what source the adc converter measures */
 412         ADC_SRC_4020_MASK = 0x70,
 413         /*  make bnc trig/ext clock threshold 0V instead of 2.5V */
 414         BNC_TRIG_THRESHOLD_0V_BIT = 0x80,
 415 };
 416
 417 static inline uint8_t adc_src_4020_bits(unsigned int source)
 418 {
 419         return (source << 4) & ADC_SRC_4020_MASK;
 420 };
 421
 422 static inline uint8_t attenuate_bit(unsigned int channel)
 423 {
 424         /*  attenuate channel (+-5V input range) */
 425         return 1 << (channel & 0x3);
 426 };
 427
 428 /* analog input ranges for 64xx boards */
 429 static const struct comedi_lrange ai_ranges_64xx = {
 430         8, {
 431                 BIP_RANGE(10),
 432                 BIP_RANGE(5),
 433                 BIP_RANGE(2.5),
 434                 BIP_RANGE(1.25),
 435                 UNI_RANGE(10),
 436                 UNI_RANGE(5),
 437                 UNI_RANGE(2.5),
 438                 UNI_RANGE(1.25)
 439         }
 440 };
 441
 442 /* analog input ranges for 60xx boards */
 443 static const struct comedi_lrange ai_ranges_60xx = {
 444         4, {
 445                 BIP_RANGE(10),
 446                 BIP_RANGE(5),
 447                 BIP_RANGE(0.5),
 448                 BIP_RANGE(0.05)
 449         }
 450 };
 451
 452 /* analog input ranges for 6030, etc boards */
 453 static const struct comedi_lrange ai_ranges_6030 = {
 454         14, {
 455                 BIP_RANGE(10),
 456                 BIP_RANGE(5),
 457                 BIP_RANGE(2),
 458                 BIP_RANGE(1),
 459                 BIP_RANGE(0.5),
 460                 BIP_RANGE(0.2),
 461                 BIP_RANGE(0.1),
 462                 UNI_RANGE(10),
 463                 UNI_RANGE(5),
 464                 UNI_RANGE(2),
 465                 UNI_RANGE(1),
 466                 UNI_RANGE(0.5),
 467                 UNI_RANGE(0.2),
 468                 UNI_RANGE(0.1)
 469         }
 470 };
 471
 472 /* analog input ranges for 6052, etc boards */
 473 static const struct comedi_lrange ai_ranges_6052 = {
 474         15, {
 475                 BIP_RANGE(10),
 476                 BIP_RANGE(5),
 477                 BIP_RANGE(2.5),
 478                 BIP_RANGE(1),
 479                 BIP_RANGE(0.5),
 480                 BIP_RANGE(0.25),
 481                 BIP_RANGE(0.1),
 482                 BIP_RANGE(0.05),
 483                 UNI_RANGE(10),
 484                 UNI_RANGE(5),
 485                 UNI_RANGE(2),
 486                 UNI_RANGE(1),
 487                 UNI_RANGE(0.5),
 488                 UNI_RANGE(0.2),
 489                 UNI_RANGE(0.1)
 490         }
 491 };
 492
 493 /* analog input ranges for 4020 board */
 494 static const struct comedi_lrange ai_ranges_4020 = {
 495         2, {
 496                 BIP_RANGE(5),
 497                 BIP_RANGE(1)
 498         }
 499 };
 500
 501 /* analog output ranges */
 502 static const struct comedi_lrange ao_ranges_64xx = {
 503         4, {
 504                 BIP_RANGE(5),
 505                 BIP_RANGE(10),
 506                 UNI_RANGE(5),
 507                 UNI_RANGE(10)
 508         }
 509 };
 510
 511 static const int ao_range_code_64xx[] = {
 512         0x0,
 513         0x1,
 514         0x2,
 515         0x3,
 516 };
 517
 518 static const int ao_range_code_60xx[] = {
 519         0x0,
 520 };
 521
 522 static const struct comedi_lrange ao_ranges_6030 = {
 523         2, {
 524                 BIP_RANGE(10),
 525                 UNI_RANGE(10)
 526         }
 527 };
 528
 529 static const int ao_range_code_6030[] = {
 530         0x0,
 531         0x2,
 532 };
 533
 534 static const struct comedi_lrange ao_ranges_4020 = {
 535         2, {
 536                 BIP_RANGE(5),
 537                 BIP_RANGE(10)
 538         }
 539 };
 540
 541 static const int ao_range_code_4020[] = {
 542         0x1,
 543         0x0,
 544 };
 545
 546 enum register_layout {
 547         LAYOUT_60XX,
 548         LAYOUT_64XX,
 549         LAYOUT_4020,
 550 };
 551
 552 struct hw_fifo_info {
 553         unsigned int num_segments;
 554         unsigned int max_segment_length;
 555         unsigned int sample_packing_ratio;
 556         uint16_t fifo_size_reg_mask;
 557 };
 558
 559 enum pcidas64_boardid {
 560         BOARD_PCIDAS6402_16,
 561         BOARD_PCIDAS6402_12,
 562         BOARD_PCIDAS64_M1_16,
 563         BOARD_PCIDAS64_M2_16,
 564         BOARD_PCIDAS64_M3_16,
 565         BOARD_PCIDAS6013,
 566         BOARD_PCIDAS6014,
 567         BOARD_PCIDAS6023,
 568         BOARD_PCIDAS6025,
 569         BOARD_PCIDAS6030,
 570         BOARD_PCIDAS6031,
 571         BOARD_PCIDAS6032,
 572         BOARD_PCIDAS6033,
 573         BOARD_PCIDAS6034,
 574         BOARD_PCIDAS6035,
 575         BOARD_PCIDAS6036,
 576         BOARD_PCIDAS6040,
 577         BOARD_PCIDAS6052,
 578         BOARD_PCIDAS6070,
 579         BOARD_PCIDAS6071,
 580         BOARD_PCIDAS4020_12,
 581         BOARD_PCIDAS6402_16_JR,
 582         BOARD_PCIDAS64_M1_16_JR,
 583         BOARD_PCIDAS64_M2_16_JR,
 584         BOARD_PCIDAS64_M3_16_JR,
 585         BOARD_PCIDAS64_M1_14,
 586         BOARD_PCIDAS64_M2_14,
 587         BOARD_PCIDAS64_M3_14,
 588 };
 589
 590 struct pcidas64_board {
 591         const char *name;
 592         int ai_se_chans;        /*  number of ai inputs in single-ended mode */
 593         int ai_bits;            /*  analog input resolution */
 594         int ai_speed;           /*  fastest conversion period in ns */
 595         const struct comedi_lrange *ai_range_table;
 596         int ao_nchan;           /*  number of analog out channels */
 597         int ao_bits;            /*  analog output resolution */
 598         int ao_scan_speed;      /*  analog output scan speed */
 599         const struct comedi_lrange *ao_range_table;
 600         const int *ao_range_code;
 601         const struct hw_fifo_info *const ai_fifo;
 602         /*  different board families have slightly different registers */
 603         enum register_layout layout;
 604         unsigned has_8255:1;
 605 };
 606
 607 static const struct hw_fifo_info ai_fifo_4020 = {
 608         .num_segments = 2,
 609         .max_segment_length = 0x8000,
 610         .sample_packing_ratio = 2,
 611         .fifo_size_reg_mask = 0x7f,
 612 };
 613
 614 static const struct hw_fifo_info ai_fifo_64xx = {
 615         .num_segments = 4,
 616         .max_segment_length = 0x800,
 617         .sample_packing_ratio = 1,
 618         .fifo_size_reg_mask = 0x3f,
 619 };
 620
 621 static const struct hw_fifo_info ai_fifo_60xx = {
 622         .num_segments = 4,
 623         .max_segment_length = 0x800,
 624         .sample_packing_ratio = 1,
 625         .fifo_size_reg_mask = 0x7f,
 626 };
 627
 628 /* maximum number of dma transfers we will chain together into a ring
 629  * (and the maximum number of dma buffers we maintain) */
 630 #define MAX_AI_DMA_RING_COUNT (0x80000 / DMA_BUFFER_SIZE)
 631 #define MIN_AI_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
 632 #define AO_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
 633 static inline unsigned int ai_dma_ring_count(const struct pcidas64_board *board)
 634 {
 635         if (board->layout == LAYOUT_4020)
 636                 return MAX_AI_DMA_RING_COUNT;
 637
 638         return MIN_AI_DMA_RING_COUNT;
 639 }
 640
 641 static const int bytes_in_sample = 2;
 642
 643 static const struct pcidas64_board pcidas64_boards[] = {
 644         [BOARD_PCIDAS6402_16] = {
 645                 .name           = "pci-das6402/16",
 646                 .ai_se_chans    = 64,
 647                 .ai_bits        = 16,
 648                 .ai_speed       = 5000,
 649                 .ao_nchan       = 2,
 650                 .ao_bits        = 16,
 651                 .ao_scan_speed  = 10000,
 652                 .layout         = LAYOUT_64XX,
 653                 .ai_range_table = &ai_ranges_64xx,
 654                 .ao_range_table = &ao_ranges_64xx,
 655                 .ao_range_code  = ao_range_code_64xx,
 656                 .ai_fifo        = &ai_fifo_64xx,
 657                 .has_8255       = 1,
 658         },
 659         [BOARD_PCIDAS6402_12] = {
 660                 .name           = "pci-das6402/12",     /*  XXX check */
 661                 .ai_se_chans    = 64,
 662                 .ai_bits        = 12,
 663                 .ai_speed       = 5000,
 664                 .ao_nchan       = 2,
 665                 .ao_bits        = 12,
 666                 .ao_scan_speed  = 10000,
 667                 .layout         = LAYOUT_64XX,
 668                 .ai_range_table = &ai_ranges_64xx,
 669                 .ao_range_table = &ao_ranges_64xx,
 670                 .ao_range_code  = ao_range_code_64xx,
 671                 .ai_fifo        = &ai_fifo_64xx,
 672                 .has_8255       = 1,
 673         },
 674         [BOARD_PCIDAS64_M1_16] = {
 675                 .name           = "pci-das64/m1/16",
 676                 .ai_se_chans    = 64,
 677                 .ai_bits        = 16,
 678                 .ai_speed       = 1000,
 679                 .ao_nchan       = 2,
 680                 .ao_bits        = 16,
 681                 .ao_scan_speed  = 10000,
 682                 .layout         = LAYOUT_64XX,
 683                 .ai_range_table = &ai_ranges_64xx,
 684                 .ao_range_table = &ao_ranges_64xx,
 685                 .ao_range_code  = ao_range_code_64xx,
 686                 .ai_fifo        = &ai_fifo_64xx,
 687                 .has_8255       = 1,
 688         },
 689         [BOARD_PCIDAS64_M2_16] = {
 690                 .name = "pci-das64/m2/16",
 691                 .ai_se_chans    = 64,
 692                 .ai_bits        = 16,
 693                 .ai_speed       = 500,
 694                 .ao_nchan       = 2,
 695                 .ao_bits        = 16,
 696                 .ao_scan_speed  = 10000,
 697                 .layout         = LAYOUT_64XX,
 698                 .ai_range_table = &ai_ranges_64xx,
 699                 .ao_range_table = &ao_ranges_64xx,
 700                 .ao_range_code  = ao_range_code_64xx,
 701                 .ai_fifo        = &ai_fifo_64xx,
 702                 .has_8255       = 1,
 703         },
 704         [BOARD_PCIDAS64_M3_16] = {
 705                 .name           = "pci-das64/m3/16",
 706                 .ai_se_chans    = 64,
 707                 .ai_bits        = 16,
 708                 .ai_speed       = 333,
 709                 .ao_nchan       = 2,
 710                 .ao_bits        = 16,
 711                 .ao_scan_speed  = 10000,
 712                 .layout         = LAYOUT_64XX,
 713                 .ai_range_table = &ai_ranges_64xx,
 714                 .ao_range_table = &ao_ranges_64xx,
 715                 .ao_range_code  = ao_range_code_64xx,
 716                 .ai_fifo        = &ai_fifo_64xx,
 717                 .has_8255       = 1,
 718         },
 719         [BOARD_PCIDAS6013] = {
 720                 .name           = "pci-das6013",
 721                 .ai_se_chans    = 16,
 722                 .ai_bits        = 16,
 723                 .ai_speed       = 5000,
 724                 .ao_nchan       = 0,
 725                 .ao_bits        = 16,
 726                 .layout         = LAYOUT_60XX,
 727                 .ai_range_table = &ai_ranges_60xx,
 728                 .ao_range_table = &range_bipolar10,
 729                 .ao_range_code  = ao_range_code_60xx,
 730                 .ai_fifo        = &ai_fifo_60xx,
 731                 .has_8255       = 0,
 732         },
 733         [BOARD_PCIDAS6014] = {
 734                 .name           = "pci-das6014",
 735                 .ai_se_chans    = 16,
 736                 .ai_bits        = 16,
 737                 .ai_speed       = 5000,
 738                 .ao_nchan       = 2,
 739                 .ao_bits        = 16,
 740                 .ao_scan_speed  = 100000,
 741                 .layout         = LAYOUT_60XX,
 742                 .ai_range_table = &ai_ranges_60xx,
 743                 .ao_range_table = &range_bipolar10,
 744                 .ao_range_code  = ao_range_code_60xx,
 745                 .ai_fifo        = &ai_fifo_60xx,
 746                 .has_8255       = 0,
 747         },
 748         [BOARD_PCIDAS6023] = {
 749                 .name           = "pci-das6023",
 750                 .ai_se_chans    = 16,
 751                 .ai_bits        = 12,
 752                 .ai_speed       = 5000,
 753                 .ao_nchan       = 0,
 754                 .ao_scan_speed  = 100000,
 755                 .layout         = LAYOUT_60XX,
 756                 .ai_range_table = &ai_ranges_60xx,
 757                 .ao_range_table = &range_bipolar10,
 758                 .ao_range_code  = ao_range_code_60xx,
 759                 .ai_fifo        = &ai_fifo_60xx,
 760                 .has_8255       = 1,
 761         },
 762         [BOARD_PCIDAS6025] = {
 763                 .name           = "pci-das6025",
 764                 .ai_se_chans    = 16,
 765                 .ai_bits        = 12,
 766                 .ai_speed       = 5000,
 767                 .ao_nchan       = 2,
 768                 .ao_bits        = 12,
 769                 .ao_scan_speed  = 100000,
 770                 .layout         = LAYOUT_60XX,
 771                 .ai_range_table = &ai_ranges_60xx,
 772                 .ao_range_table = &range_bipolar10,
 773                 .ao_range_code  = ao_range_code_60xx,
 774                 .ai_fifo        = &ai_fifo_60xx,
 775                 .has_8255       = 1,
 776         },
 777         [BOARD_PCIDAS6030] = {
 778                 .name           = "pci-das6030",
 779                 .ai_se_chans    = 16,
 780                 .ai_bits        = 16,
 781                 .ai_speed       = 10000,
 782                 .ao_nchan       = 2,
 783                 .ao_bits        = 16,
 784                 .ao_scan_speed  = 10000,
 785                 .layout         = LAYOUT_60XX,
 786                 .ai_range_table = &ai_ranges_6030,
 787                 .ao_range_table = &ao_ranges_6030,
 788                 .ao_range_code  = ao_range_code_6030,
 789                 .ai_fifo        = &ai_fifo_60xx,
 790                 .has_8255       = 0,
 791         },
 792         [BOARD_PCIDAS6031] = {
 793                 .name           = "pci-das6031",
 794                 .ai_se_chans    = 64,
 795                 .ai_bits        = 16,
 796                 .ai_speed       = 10000,
 797                 .ao_nchan       = 2,
 798                 .ao_bits        = 16,
 799                 .ao_scan_speed  = 10000,
 800                 .layout         = LAYOUT_60XX,
 801                 .ai_range_table = &ai_ranges_6030,
 802                 .ao_range_table = &ao_ranges_6030,
 803                 .ao_range_code  = ao_range_code_6030,
 804                 .ai_fifo        = &ai_fifo_60xx,
 805                 .has_8255       = 0,
 806         },
 807         [BOARD_PCIDAS6032] = {
 808                 .name           = "pci-das6032",
 809                 .ai_se_chans    = 16,
 810                 .ai_bits        = 16,
 811                 .ai_speed       = 10000,
 812                 .ao_nchan       = 0,
 813                 .layout         = LAYOUT_60XX,
 814                 .ai_range_table = &ai_ranges_6030,
 815                 .ai_fifo        = &ai_fifo_60xx,
 816                 .has_8255       = 0,
 817         },
 818         [BOARD_PCIDAS6033] = {
 819                 .name           = "pci-das6033",
 820                 .ai_se_chans    = 64,
 821                 .ai_bits        = 16,
 822                 .ai_speed       = 10000,
 823                 .ao_nchan       = 0,
 824                 .layout         = LAYOUT_60XX,
 825                 .ai_range_table = &ai_ranges_6030,
 826                 .ai_fifo        = &ai_fifo_60xx,
 827                 .has_8255       = 0,
 828         },
 829         [BOARD_PCIDAS6034] = {
 830                 .name           = "pci-das6034",
 831                 .ai_se_chans    = 16,
 832                 .ai_bits        = 16,
 833                 .ai_speed       = 5000,
 834                 .ao_nchan       = 0,
 835                 .ao_scan_speed  = 0,
 836                 .layout         = LAYOUT_60XX,
 837                 .ai_range_table = &ai_ranges_60xx,
 838                 .ai_fifo        = &ai_fifo_60xx,
 839                 .has_8255       = 0,
 840         },
 841         [BOARD_PCIDAS6035] = {
 842                 .name           = "pci-das6035",
 843                 .ai_se_chans    = 16,
 844                 .ai_bits        = 16,
 845                 .ai_speed       = 5000,
 846                 .ao_nchan       = 2,
 847                 .ao_bits        = 12,
 848                 .ao_scan_speed  = 100000,
 849                 .layout         = LAYOUT_60XX,
 850                 .ai_range_table = &ai_ranges_60xx,
 851                 .ao_range_table = &range_bipolar10,
 852                 .ao_range_code  = ao_range_code_60xx,
 853                 .ai_fifo        = &ai_fifo_60xx,
 854                 .has_8255       = 0,
 855         },
 856         [BOARD_PCIDAS6036] = {
 857                 .name           = "pci-das6036",
 858                 .ai_se_chans    = 16,
 859                 .ai_bits        = 16,
 860                 .ai_speed       = 5000,
 861                 .ao_nchan       = 2,
 862                 .ao_bits        = 16,
 863                 .ao_scan_speed  = 100000,
 864                 .layout         = LAYOUT_60XX,
 865                 .ai_range_table = &ai_ranges_60xx,
 866                 .ao_range_table = &range_bipolar10,
 867                 .ao_range_code  = ao_range_code_60xx,
 868                 .ai_fifo        = &ai_fifo_60xx,
 869                 .has_8255       = 0,
 870         },
 871         [BOARD_PCIDAS6040] = {
 872                 .name           = "pci-das6040",
 873                 .ai_se_chans    = 16,
 874                 .ai_bits        = 12,
 875                 .ai_speed       = 2000,
 876                 .ao_nchan       = 2,
 877                 .ao_bits        = 12,
 878                 .ao_scan_speed  = 1000,
 879                 .layout         = LAYOUT_60XX,
 880                 .ai_range_table = &ai_ranges_6052,
 881                 .ao_range_table = &ao_ranges_6030,
 882                 .ao_range_code  = ao_range_code_6030,
 883                 .ai_fifo        = &ai_fifo_60xx,
 884                 .has_8255       = 0,
 885         },
 886         [BOARD_PCIDAS6052] = {
 887                 .name           = "pci-das6052",
 888                 .ai_se_chans    = 16,
 889                 .ai_bits        = 16,
 890                 .ai_speed       = 3333,
 891                 .ao_nchan       = 2,
 892                 .ao_bits        = 16,
 893                 .ao_scan_speed  = 3333,
 894                 .layout         = LAYOUT_60XX,
 895                 .ai_range_table = &ai_ranges_6052,
 896                 .ao_range_table = &ao_ranges_6030,
 897                 .ao_range_code  = ao_range_code_6030,
 898                 .ai_fifo        = &ai_fifo_60xx,
 899                 .has_8255       = 0,
 900         },
 901         [BOARD_PCIDAS6070] = {
 902                 .name           = "pci-das6070",
 903                 .ai_se_chans    = 16,
 904                 .ai_bits        = 12,
 905                 .ai_speed       = 800,
 906                 .ao_nchan       = 2,
 907                 .ao_bits        = 12,
 908                 .ao_scan_speed  = 1000,
 909                 .layout         = LAYOUT_60XX,
 910                 .ai_range_table = &ai_ranges_6052,
 911                 .ao_range_table = &ao_ranges_6030,
 912                 .ao_range_code  = ao_range_code_6030,
 913                 .ai_fifo        = &ai_fifo_60xx,
 914                 .has_8255       = 0,
 915         },
 916         [BOARD_PCIDAS6071] = {
 917                 .name           = "pci-das6071",
 918                 .ai_se_chans    = 64,
 919                 .ai_bits        = 12,
 920                 .ai_speed       = 800,
 921                 .ao_nchan       = 2,
 922                 .ao_bits        = 12,
 923                 .ao_scan_speed  = 1000,
 924                 .layout         = LAYOUT_60XX,
 925                 .ai_range_table = &ai_ranges_6052,
 926                 .ao_range_table = &ao_ranges_6030,
 927                 .ao_range_code  = ao_range_code_6030,
 928                 .ai_fifo        = &ai_fifo_60xx,
 929                 .has_8255       = 0,
 930         },
 931         [BOARD_PCIDAS4020_12] = {
 932                 .name           = "pci-das4020/12",
 933                 .ai_se_chans    = 4,
 934                 .ai_bits        = 12,
 935                 .ai_speed       = 50,
 936                 .ao_bits        = 12,
 937                 .ao_nchan       = 2,
 938                 .ao_scan_speed  = 0,    /*  no hardware pacing on ao */
 939                 .layout         = LAYOUT_4020,
 940                 .ai_range_table = &ai_ranges_4020,
 941                 .ao_range_table = &ao_ranges_4020,
 942                 .ao_range_code  = ao_range_code_4020,
 943                 .ai_fifo        = &ai_fifo_4020,
 944                 .has_8255       = 1,
 945         },
 946 #if 0
 947         /*
 948          * The device id for these boards is unknown
 949          */
 950
 951         [BOARD_PCIDAS6402_16_JR] = {
 952                 .name           = "pci-das6402/16/jr",
 953                 .ai_se_chans    = 64,
 954                 .ai_bits        = 16,
 955                 .ai_speed       = 5000,
 956                 .ao_nchan       = 0,
 957                 .ao_scan_speed  = 10000,
 958                 .layout         = LAYOUT_64XX,
 959                 .ai_range_table = &ai_ranges_64xx,
 960                 .ai_fifo        = ai_fifo_64xx,
 961                 .has_8255       = 1,
 962         },
 963         [BOARD_PCIDAS64_M1_16_JR] = {
 964                 .name           = "pci-das64/m1/16/jr",
 965                 .ai_se_chans    = 64,
 966                 .ai_bits        = 16,
 967                 .ai_speed       = 1000,
 968                 .ao_nchan       = 0,
 969                 .ao_scan_speed  = 10000,
 970                 .layout         = LAYOUT_64XX,
 971                 .ai_range_table = &ai_ranges_64xx,
 972                 .ai_fifo        = ai_fifo_64xx,
 973                 .has_8255       = 1,
 974         },
 975         [BOARD_PCIDAS64_M2_16_JR] = {
 976                 .name = "pci-das64/m2/16/jr",
 977                 .ai_se_chans    = 64,
 978                 .ai_bits        = 16,
 979                 .ai_speed       = 500,
 980                 .ao_nchan       = 0,
 981                 .ao_scan_speed  = 10000,
 982                 .layout         = LAYOUT_64XX,
 983                 .ai_range_table = &ai_ranges_64xx,
 984                 .ai_fifo        = ai_fifo_64xx,
 985                 .has_8255       = 1,
 986         },
 987         [BOARD_PCIDAS64_M3_16_JR] = {
 988                 .name           = "pci-das64/m3/16/jr",
 989                 .ai_se_chans    = 64,
 990                 .ai_bits        = 16,
 991                 .ai_speed       = 333,
 992                 .ao_nchan       = 0,
 993                 .ao_scan_speed  = 10000,
 994                 .layout         = LAYOUT_64XX,
 995                 .ai_range_table = &ai_ranges_64xx,
 996                 .ai_fifo        = ai_fifo_64xx,
 997                 .has_8255       = 1,
 998         },
 999         [BOARD_PCIDAS64_M1_14] = {
1000                 .name           = "pci-das64/m1/14",
1001                 .ai_se_chans    = 64,
1002                 .ai_bits        = 14,
1003                 .ai_speed       = 1000,
1004                 .ao_nchan       = 2,
1005                 .ao_scan_speed  = 10000,
1006                 .layout         = LAYOUT_64XX,
1007                 .ai_range_table = &ai_ranges_64xx,
1008                 .ai_fifo        = ai_fifo_64xx,
1009                 .has_8255       = 1,
1010         },
1011         [BOARD_PCIDAS64_M2_14] = {
1012                 .name           = "pci-das64/m2/14",
1013                 .ai_se_chans    = 64,
1014                 .ai_bits        = 14,
1015                 .ai_speed       = 500,
1016                 .ao_nchan       = 2,
1017                 .ao_scan_speed  = 10000,
1018                 .layout         = LAYOUT_64XX,
1019                 .ai_range_table = &ai_ranges_64xx,
1020                 .ai_fifo        = ai_fifo_64xx,
1021                 .has_8255       = 1,
1022         },
1023         [BOARD_PCIDAS64_M3_14] = {
1024                 .name           = "pci-das64/m3/14",
1025                 .ai_se_chans    = 64,
1026                 .ai_bits        = 14,
1027                 .ai_speed       = 333,
1028                 .ao_nchan       = 2,
1029                 .ao_scan_speed  = 10000,
1030                 .layout         = LAYOUT_64XX,
1031                 .ai_range_table = &ai_ranges_64xx,
1032                 .ai_fifo        = ai_fifo_64xx,
1033                 .has_8255       = 1,
1034         },
1035 #endif
1036 };
1037
1038 static inline unsigned short se_diff_bit_6xxx(struct comedi_device *dev,
1039                                               int use_differential)
1040 {
1041         const struct pcidas64_board *thisboard = dev->board_ptr;
1042
1043         if ((thisboard->layout == LAYOUT_64XX && !use_differential) ||
1044             (thisboard->layout == LAYOUT_60XX && use_differential))
1045                 return ADC_SE_DIFF_BIT;
1046
1047         return 0;
1048 }
1049
1050 struct ext_clock_info {
1051         /*  master clock divisor to use for scans with external master clock */
1052         unsigned int divisor;
1053         /*  chanspec for master clock input when used as scan begin src */
1054         unsigned int chanspec;
1055 };
1056
1057 /* this structure is for data unique to this hardware driver. */
1058 struct pcidas64_private {
1059         /*  base addresses (physical) */
1060         resource_size_t main_phys_iobase;
1061         resource_size_t dio_counter_phys_iobase;
1062         /*  base addresses (ioremapped) */
1063         void __iomem *plx9080_iobase;
1064         void __iomem *main_iobase;
1065         /*  local address (used by dma controller) */
1066         uint32_t local0_iobase;
1067         uint32_t local1_iobase;
1068         /*  dma buffers for analog input */
1069         uint16_t *ai_buffer[MAX_AI_DMA_RING_COUNT];
1070         /*  physical addresses of ai dma buffers */
1071         dma_addr_t ai_buffer_bus_addr[MAX_AI_DMA_RING_COUNT];
1072         /*  array of ai dma descriptors read by plx9080,
1073          *  allocated to get proper alignment */
1074         struct plx_dma_desc *ai_dma_desc;
1075         /*  physical address of ai dma descriptor array */
1076         dma_addr_t ai_dma_desc_bus_addr;
1077         /*  index of the ai dma descriptor/buffer
1078          *  that is currently being used */
1079         unsigned int ai_dma_index;
1080         /*  dma buffers for analog output */
1081         uint16_t *ao_buffer[AO_DMA_RING_COUNT];
1082         /*  physical addresses of ao dma buffers */
1083         dma_addr_t ao_buffer_bus_addr[AO_DMA_RING_COUNT];
1084         struct plx_dma_desc *ao_dma_desc;
1085         dma_addr_t ao_dma_desc_bus_addr;
1086         /*  keeps track of buffer where the next ao sample should go */
1087         unsigned int ao_dma_index;
1088         unsigned int hw_revision;       /*  stc chip hardware revision number */
1089         /*  last bits sent to INTR_ENABLE_REG register */
1090         unsigned int intr_enable_bits;
1091         /*  last bits sent to ADC_CONTROL1_REG register */
1092         uint16_t adc_control1_bits;
1093         /*  last bits sent to FIFO_SIZE_REG register */
1094         uint16_t fifo_size_bits;
1095         /*  last bits sent to HW_CONFIG_REG register */
1096         uint16_t hw_config_bits;
1097         uint16_t dac_control1_bits;
1098         /*  last bits written to plx9080 control register */
1099         uint32_t plx_control_bits;
1100         /*  last bits written to plx interrupt control and status register */
1101         uint32_t plx_intcsr_bits;
1102         /*  index of calibration source readable through ai ch0 */
1103         int calibration_source;
1104         /*  bits written to i2c calibration/range register */
1105         uint8_t i2c_cal_range_bits;
1106         /*  configure digital triggers to trigger on falling edge */
1107         unsigned int ext_trig_falling;
1108         /*  states of various devices stored to enable read-back */
1109         unsigned int ad8402_state[2];
1110         short ai_cmd_running;
1111         unsigned int ai_fifo_segment_length;
1112         struct ext_clock_info ext_clock;
1113         unsigned short ao_bounce_buffer[DAC_FIFO_SIZE];
1114 };
1115
1116 static unsigned int ai_range_bits_6xxx(const struct comedi_device *dev,
1117                                        unsigned int range_index)
1118 {
1119         const struct pcidas64_board *thisboard = dev->board_ptr;
1120         const struct comedi_krange *range =
1121                 &thisboard->ai_range_table->range[range_index];
1122         unsigned int bits = 0;
1123
1124         switch (range->max) {
1125         case 10000000:
1126                 bits = 0x000;
1127                 break;
1128         case 5000000:
1129                 bits = 0x100;
1130                 break;
1131         case 2000000:
1132         case 2500000:
1133                 bits = 0x200;
1134                 break;
1135         case 1000000:
1136         case 1250000:
1137                 bits = 0x300;
1138                 break;
1139         case 500000:
1140                 bits = 0x400;
1141                 break;
1142         case 200000:
1143         case 250000:
1144                 bits = 0x500;
1145                 break;
1146         case 100000:
1147                 bits = 0x600;
1148                 break;
1149         case 50000:
1150                 bits = 0x700;
1151                 break;
1152         default:
1153                 dev_err(dev->class_dev, "bug! in %s\n", __func__);
1154                 break;
1155         }
1156         if (range->min == 0)
1157                 bits += 0x900;
1158         return bits;
1159 }
1160
1161 static unsigned int hw_revision(const struct comedi_device *dev,
1162                                 uint16_t hw_status_bits)
1163 {
1164         const struct pcidas64_board *thisboard = dev->board_ptr;
1165
1166         if (thisboard->layout == LAYOUT_4020)
1167                 return (hw_status_bits >> 13) & 0x7;
1168
1169         return (hw_status_bits >> 12) & 0xf;
1170 }
1171
1172 static void set_dac_range_bits(struct comedi_device *dev,
1173                                uint16_t *bits, unsigned int channel,
1174                                unsigned int range)
1175 {
1176         const struct pcidas64_board *thisboard = dev->board_ptr;
1177         unsigned int code = thisboard->ao_range_code[range];
1178
1179         if (channel > 1)
1180                 dev_err(dev->class_dev, "bug! bad channel?\n");
1181         if (code & ~0x3)
1182                 dev_err(dev->class_dev, "bug! bad range code?\n");
1183
1184         *bits &= ~(0x3 << (2 * channel));
1185         *bits |= code << (2 * channel);
1186 };
1187
1188 static inline int ao_cmd_is_supported(const struct pcidas64_board *board)
1189 {
1190         return board->ao_nchan && board->layout != LAYOUT_4020;
1191 }
1192
1193 static void abort_dma(struct comedi_device *dev, unsigned int channel)
1194 {
1195         struct pcidas64_private *devpriv = dev->private;
1196         unsigned long flags;
1197
1198         /*  spinlock for plx dma control/status reg */
1199         spin_lock_irqsave(&dev->spinlock, flags);
1200
1201         plx9080_abort_dma(devpriv->plx9080_iobase, channel);
1202
1203         spin_unlock_irqrestore(&dev->spinlock, flags);
1204 }
1205
1206 static void disable_plx_interrupts(struct comedi_device *dev)
1207 {
1208         struct pcidas64_private *devpriv = dev->private;
1209
1210         devpriv->plx_intcsr_bits = 0;
1211         writel(devpriv->plx_intcsr_bits,
1212                devpriv->plx9080_iobase + PLX_INTRCS_REG);
1213 }
1214
1215 static void disable_ai_interrupts(struct comedi_device *dev)
1216 {
1217         struct pcidas64_private *devpriv = dev->private;
1218         unsigned long flags;
1219
1220         spin_lock_irqsave(&dev->spinlock, flags);
1221         devpriv->intr_enable_bits &=
1222                 ~EN_ADC_INTR_SRC_BIT & ~EN_ADC_DONE_INTR_BIT &
1223                 ~EN_ADC_ACTIVE_INTR_BIT & ~EN_ADC_STOP_INTR_BIT &
1224                 ~EN_ADC_OVERRUN_BIT & ~ADC_INTR_SRC_MASK;
1225         writew(devpriv->intr_enable_bits,
1226                devpriv->main_iobase + INTR_ENABLE_REG);
1227         spin_unlock_irqrestore(&dev->spinlock, flags);
1228 }
1229
1230 static void enable_ai_interrupts(struct comedi_device *dev,
1231                                  const struct comedi_cmd *cmd)
1232 {
1233         const struct pcidas64_board *thisboard = dev->board_ptr;
1234         struct pcidas64_private *devpriv = dev->private;
1235         uint32_t bits;
1236         unsigned long flags;
1237
1238         bits = EN_ADC_OVERRUN_BIT | EN_ADC_DONE_INTR_BIT |
1239                EN_ADC_ACTIVE_INTR_BIT | EN_ADC_STOP_INTR_BIT;
1240         /*  Use pio transfer and interrupt on end of conversion
1241          *  if CMDF_WAKE_EOS flag is set. */
1242         if (cmd->flags & CMDF_WAKE_EOS) {
1243                 /*  4020 doesn't support pio transfers except for fifo dregs */
1244                 if (thisboard->layout != LAYOUT_4020)
1245                         bits |= ADC_INTR_EOSCAN_BITS | EN_ADC_INTR_SRC_BIT;
1246         }
1247         spin_lock_irqsave(&dev->spinlock, flags);
1248         devpriv->intr_enable_bits |= bits;
1249         writew(devpriv->intr_enable_bits,
1250                devpriv->main_iobase + INTR_ENABLE_REG);
1251         spin_unlock_irqrestore(&dev->spinlock, flags);
1252 }
1253
1254 /* initialize plx9080 chip */
1255 static void init_plx9080(struct comedi_device *dev)
1256 {
1257         const struct pcidas64_board *thisboard = dev->board_ptr;
1258         struct pcidas64_private *devpriv = dev->private;
1259         uint32_t bits;
1260         void __iomem *plx_iobase = devpriv->plx9080_iobase;
1261
1262         devpriv->plx_control_bits =
1263                 readl(devpriv->plx9080_iobase + PLX_CONTROL_REG);
1264
1265 #ifdef __BIG_ENDIAN
1266         bits = BIGEND_DMA0 | BIGEND_DMA1;
1267 #else
1268         bits = 0;
1269 #endif
1270         writel(bits, devpriv->plx9080_iobase + PLX_BIGEND_REG);
1271
1272         disable_plx_interrupts(dev);
1273
1274         abort_dma(dev, 0);
1275         abort_dma(dev, 1);
1276
1277         /*  configure dma0 mode */
1278         bits = 0;
1279         /*  enable ready input, not sure if this is necessary */
1280         bits |= PLX_DMA_EN_READYIN_BIT;
1281         /*  enable bterm, not sure if this is necessary */
1282         bits |= PLX_EN_BTERM_BIT;
1283         /*  enable dma chaining */
1284         bits |= PLX_EN_CHAIN_BIT;
1285         /*  enable interrupt on dma done
1286          *  (probably don't need this, since chain never finishes) */
1287         bits |= PLX_EN_DMA_DONE_INTR_BIT;
1288         /*  don't increment local address during transfers
1289          *  (we are transferring from a fixed fifo register) */
1290         bits |= PLX_LOCAL_ADDR_CONST_BIT;
1291         /*  route dma interrupt to pci bus */
1292         bits |= PLX_DMA_INTR_PCI_BIT;
1293         /*  enable demand mode */
1294         bits |= PLX_DEMAND_MODE_BIT;
1295         /*  enable local burst mode */
1296         bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
1297         /*  4020 uses 32 bit dma */
1298         if (thisboard->layout == LAYOUT_4020)
1299                 bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
1300         else            /*  localspace0 bus is 16 bits wide */
1301                 bits |= PLX_LOCAL_BUS_16_WIDE_BITS;
1302         writel(bits, plx_iobase + PLX_DMA1_MODE_REG);
1303         if (ao_cmd_is_supported(thisboard))
1304                 writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
1305
1306         /*  enable interrupts on plx 9080 */
1307         devpriv->plx_intcsr_bits |=
1308             ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
1309             ICS_DMA0_E | ICS_DMA1_E;
1310         writel(devpriv->plx_intcsr_bits,
1311                devpriv->plx9080_iobase + PLX_INTRCS_REG);
1312 }
1313
1314 static void disable_ai_pacing(struct comedi_device *dev)
1315 {
1316         struct pcidas64_private *devpriv = dev->private;
1317         unsigned long flags;
1318
1319         disable_ai_interrupts(dev);
1320
1321         spin_lock_irqsave(&dev->spinlock, flags);
1322         devpriv->adc_control1_bits &= ~ADC_SW_GATE_BIT;
1323         writew(devpriv->adc_control1_bits,
1324                devpriv->main_iobase + ADC_CONTROL1_REG);
1325         spin_unlock_irqrestore(&dev->spinlock, flags);
1326
1327         /* disable pacing, triggering, etc */
1328         writew(ADC_DMA_DISABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT,
1329                devpriv->main_iobase + ADC_CONTROL0_REG);
1330 }
1331
1332 static int set_ai_fifo_segment_length(struct comedi_device *dev,
1333                                       unsigned int num_entries)
1334 {
1335         const struct pcidas64_board *thisboard = dev->board_ptr;
1336         struct pcidas64_private *devpriv = dev->private;
1337         static const int increment_size = 0x100;
1338         const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1339         unsigned int num_increments;
1340         uint16_t bits;
1341
1342         if (num_entries < increment_size)
1343                 num_entries = increment_size;
1344         if (num_entries > fifo->max_segment_length)
1345                 num_entries = fifo->max_segment_length;
1346
1347         /*  1 == 256 entries, 2 == 512 entries, etc */
1348         num_increments = (num_entries + increment_size / 2) / increment_size;
1349
1350         bits = (~(num_increments - 1)) & fifo->fifo_size_reg_mask;
1351         devpriv->fifo_size_bits &= ~fifo->fifo_size_reg_mask;
1352         devpriv->fifo_size_bits |= bits;
1353         writew(devpriv->fifo_size_bits,
1354                devpriv->main_iobase + FIFO_SIZE_REG);
1355
1356         devpriv->ai_fifo_segment_length = num_increments * increment_size;
1357
1358         return devpriv->ai_fifo_segment_length;
1359 }
1360
1361 /* adjusts the size of hardware fifo (which determines block size for dma xfers) */
1362 static int set_ai_fifo_size(struct comedi_device *dev, unsigned int num_samples)
1363 {
1364         const struct pcidas64_board *thisboard = dev->board_ptr;
1365         unsigned int num_fifo_entries;
1366         int retval;
1367         const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1368
1369         num_fifo_entries = num_samples / fifo->sample_packing_ratio;
1370
1371         retval = set_ai_fifo_segment_length(dev,
1372                                             num_fifo_entries /
1373                                             fifo->num_segments);
1374         if (retval < 0)
1375                 return retval;
1376
1377         num_samples = retval * fifo->num_segments * fifo->sample_packing_ratio;
1378
1379         return num_samples;
1380 }
1381
1382 /* query length of fifo */
1383 static unsigned int ai_fifo_size(struct comedi_device *dev)
1384 {
1385         const struct pcidas64_board *thisboard = dev->board_ptr;
1386         struct pcidas64_private *devpriv = dev->private;
1387
1388         return devpriv->ai_fifo_segment_length *
1389                thisboard->ai_fifo->num_segments *
1390                thisboard->ai_fifo->sample_packing_ratio;
1391 }
1392
1393 static void init_stc_registers(struct comedi_device *dev)
1394 {
1395         const struct pcidas64_board *thisboard = dev->board_ptr;
1396         struct pcidas64_private *devpriv = dev->private;
1397         uint16_t bits;
1398         unsigned long flags;
1399
1400         spin_lock_irqsave(&dev->spinlock, flags);
1401
1402         /*  bit should be set for 6025,
1403          *  although docs say boards with <= 16 chans should be cleared XXX */
1404         if (1)
1405                 devpriv->adc_control1_bits |= ADC_QUEUE_CONFIG_BIT;
1406         writew(devpriv->adc_control1_bits,
1407                devpriv->main_iobase + ADC_CONTROL1_REG);
1408
1409         /*  6402/16 manual says this register must be initialized to 0xff? */
1410         writew(0xff, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1411
1412         bits = SLOW_DAC_BIT | DMA_CH_SELECT_BIT;
1413         if (thisboard->layout == LAYOUT_4020)
1414                 bits |= INTERNAL_CLOCK_4020_BITS;
1415         devpriv->hw_config_bits |= bits;
1416         writew(devpriv->hw_config_bits,
1417                devpriv->main_iobase + HW_CONFIG_REG);
1418
1419         writew(0, devpriv->main_iobase + DAQ_SYNC_REG);
1420         writew(0, devpriv->main_iobase + CALIBRATION_REG);
1421
1422         spin_unlock_irqrestore(&dev->spinlock, flags);
1423
1424         /*  set fifos to maximum size */
1425         devpriv->fifo_size_bits |= DAC_FIFO_BITS;
1426         set_ai_fifo_segment_length(dev,
1427                                    thisboard->ai_fifo->max_segment_length);
1428
1429         devpriv->dac_control1_bits = DAC_OUTPUT_ENABLE_BIT;
1430         devpriv->intr_enable_bits =
1431                 /* EN_DAC_INTR_SRC_BIT | DAC_INTR_QEMPTY_BITS | */
1432                 EN_DAC_DONE_INTR_BIT | EN_DAC_UNDERRUN_BIT;
1433         writew(devpriv->intr_enable_bits,
1434                devpriv->main_iobase + INTR_ENABLE_REG);
1435
1436         disable_ai_pacing(dev);
1437 };
1438
1439 static int alloc_and_init_dma_members(struct comedi_device *dev)
1440 {
1441         const struct pcidas64_board *thisboard = dev->board_ptr;
1442         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1443         struct pcidas64_private *devpriv = dev->private;
1444         int i;
1445
1446         /*  allocate pci dma buffers */
1447         for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
1448                 devpriv->ai_buffer[i] =
1449                         pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
1450                                              &devpriv->ai_buffer_bus_addr[i]);
1451                 if (devpriv->ai_buffer[i] == NULL)
1452                         return -ENOMEM;
1453
1454         }
1455         for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1456                 if (ao_cmd_is_supported(thisboard)) {
1457                         devpriv->ao_buffer[i] =
1458                                 pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
1459                                                      &devpriv->
1460                                                       ao_buffer_bus_addr[i]);
1461                         if (devpriv->ao_buffer[i] == NULL)
1462                                 return -ENOMEM;
1463
1464                 }
1465         }
1466         /*  allocate dma descriptors */
1467         devpriv->ai_dma_desc =
1468                 pci_alloc_consistent(pcidev, sizeof(struct plx_dma_desc) *
1469                                      ai_dma_ring_count(thisboard),
1470                                      &devpriv->ai_dma_desc_bus_addr);
1471         if (devpriv->ai_dma_desc == NULL)
1472                 return -ENOMEM;
1473
1474         if (ao_cmd_is_supported(thisboard)) {
1475                 devpriv->ao_dma_desc =
1476                         pci_alloc_consistent(pcidev,
1477                                              sizeof(struct plx_dma_desc) *
1478                                              AO_DMA_RING_COUNT,
1479                                              &devpriv->ao_dma_desc_bus_addr);
1480                 if (devpriv->ao_dma_desc == NULL)
1481                         return -ENOMEM;
1482         }
1483         /*  initialize dma descriptors */
1484         for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
1485                 devpriv->ai_dma_desc[i].pci_start_addr =
1486                         cpu_to_le32(devpriv->ai_buffer_bus_addr[i]);
1487                 if (thisboard->layout == LAYOUT_4020)
1488                         devpriv->ai_dma_desc[i].local_start_addr =
1489                                 cpu_to_le32(devpriv->local1_iobase +
1490                                             ADC_FIFO_REG);
1491                 else
1492                         devpriv->ai_dma_desc[i].local_start_addr =
1493                                 cpu_to_le32(devpriv->local0_iobase +
1494                                             ADC_FIFO_REG);
1495                 devpriv->ai_dma_desc[i].transfer_size = cpu_to_le32(0);
1496                 devpriv->ai_dma_desc[i].next =
1497                         cpu_to_le32((devpriv->ai_dma_desc_bus_addr +
1498                                      ((i + 1) % ai_dma_ring_count(thisboard)) *
1499                                      sizeof(devpriv->ai_dma_desc[0])) |
1500                                     PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
1501                                     PLX_XFER_LOCAL_TO_PCI);
1502         }
1503         if (ao_cmd_is_supported(thisboard)) {
1504                 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1505                         devpriv->ao_dma_desc[i].pci_start_addr =
1506                                 cpu_to_le32(devpriv->ao_buffer_bus_addr[i]);
1507                         devpriv->ao_dma_desc[i].local_start_addr =
1508                                 cpu_to_le32(devpriv->local0_iobase +
1509                                             DAC_FIFO_REG);
1510                         devpriv->ao_dma_desc[i].transfer_size = cpu_to_le32(0);
1511                         devpriv->ao_dma_desc[i].next =
1512                                 cpu_to_le32((devpriv->ao_dma_desc_bus_addr +
1513                                              ((i + 1) % (AO_DMA_RING_COUNT)) *
1514                                              sizeof(devpriv->ao_dma_desc[0])) |
1515                                             PLX_DESC_IN_PCI_BIT |
1516                                             PLX_INTR_TERM_COUNT);
1517                 }
1518         }
1519         return 0;
1520 }
1521
1522 static void cb_pcidas64_free_dma(struct comedi_device *dev)
1523 {
1524         const struct pcidas64_board *thisboard = dev->board_ptr;
1525         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1526         struct pcidas64_private *devpriv = dev->private;
1527         int i;
1528
1529         if (!devpriv)
1530                 return;
1531
1532         /* free pci dma buffers */
1533         for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
1534                 if (devpriv->ai_buffer[i])
1535                         pci_free_consistent(pcidev,
1536                                             DMA_BUFFER_SIZE,
1537                                             devpriv->ai_buffer[i],
1538                                             devpriv->ai_buffer_bus_addr[i]);
1539         }
1540         for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1541                 if (devpriv->ao_buffer[i])
1542                         pci_free_consistent(pcidev,
1543                                             DMA_BUFFER_SIZE,
1544                                             devpriv->ao_buffer[i],
1545                                             devpriv->ao_buffer_bus_addr[i]);
1546         }
1547         /* free dma descriptors */
1548         if (devpriv->ai_dma_desc)
1549                 pci_free_consistent(pcidev,
1550                                     sizeof(struct plx_dma_desc) *
1551                                     ai_dma_ring_count(thisboard),
1552                                     devpriv->ai_dma_desc,
1553                                     devpriv->ai_dma_desc_bus_addr);
1554         if (devpriv->ao_dma_desc)
1555                 pci_free_consistent(pcidev,
1556                                     sizeof(struct plx_dma_desc) *
1557                                     AO_DMA_RING_COUNT,
1558                                     devpriv->ao_dma_desc,
1559                                     devpriv->ao_dma_desc_bus_addr);
1560 }
1561
1562 static inline void warn_external_queue(struct comedi_device *dev)
1563 {
1564         dev_err(dev->class_dev,
1565                 "AO command and AI external channel queue cannot be used simultaneously\n");
1566         dev_err(dev->class_dev,
1567                 "Use internal AI channel queue (channels must be consecutive and use same range/aref)\n");
1568 }
1569
1570 /* Their i2c requires a huge delay on setting clock or data high for some reason */
1571 static const int i2c_high_udelay = 1000;
1572 static const int i2c_low_udelay = 10;
1573
1574 /* set i2c data line high or low */
1575 static void i2c_set_sda(struct comedi_device *dev, int state)
1576 {
1577         struct pcidas64_private *devpriv = dev->private;
1578         static const int data_bit = CTL_EE_W;
1579         void __iomem *plx_control_addr = devpriv->plx9080_iobase +
1580                                          PLX_CONTROL_REG;
1581
1582         if (state) {
1583                 /*  set data line high */
1584                 devpriv->plx_control_bits &= ~data_bit;
1585                 writel(devpriv->plx_control_bits, plx_control_addr);
1586                 udelay(i2c_high_udelay);
1587         } else {                /*  set data line low */
1588
1589                 devpriv->plx_control_bits |= data_bit;
1590                 writel(devpriv->plx_control_bits, plx_control_addr);
1591                 udelay(i2c_low_udelay);
1592         }
1593 }
1594
1595 /* set i2c clock line high or low */
1596 static void i2c_set_scl(struct comedi_device *dev, int state)
1597 {
1598         struct pcidas64_private *devpriv = dev->private;
1599         static const int clock_bit = CTL_USERO;
1600         void __iomem *plx_control_addr = devpriv->plx9080_iobase +
1601                                          PLX_CONTROL_REG;
1602
1603         if (state) {
1604                 /*  set clock line high */
1605                 devpriv->plx_control_bits &= ~clock_bit;
1606                 writel(devpriv->plx_control_bits, plx_control_addr);
1607                 udelay(i2c_high_udelay);
1608         } else {                /*  set clock line low */
1609
1610                 devpriv->plx_control_bits |= clock_bit;
1611                 writel(devpriv->plx_control_bits, plx_control_addr);
1612                 udelay(i2c_low_udelay);
1613         }
1614 }
1615
1616 static void i2c_write_byte(struct comedi_device *dev, uint8_t byte)
1617 {
1618         uint8_t bit;
1619         unsigned int num_bits = 8;
1620
1621         for (bit = 1 << (num_bits - 1); bit; bit >>= 1) {
1622                 i2c_set_scl(dev, 0);
1623                 if ((byte & bit))
1624                         i2c_set_sda(dev, 1);
1625                 else
1626                         i2c_set_sda(dev, 0);
1627                 i2c_set_scl(dev, 1);
1628         }
1629 }
1630
1631 /* we can't really read the lines, so fake it */
1632 static int i2c_read_ack(struct comedi_device *dev)
1633 {
1634         i2c_set_scl(dev, 0);
1635         i2c_set_sda(dev, 1);
1636         i2c_set_scl(dev, 1);
1637
1638         return 0;               /*  return fake acknowledge bit */
1639 }
1640
1641 /* send start bit */
1642 static void i2c_start(struct comedi_device *dev)
1643 {
1644         i2c_set_scl(dev, 1);
1645         i2c_set_sda(dev, 1);
1646         i2c_set_sda(dev, 0);
1647 }
1648
1649 /* send stop bit */
1650 static void i2c_stop(struct comedi_device *dev)
1651 {
1652         i2c_set_scl(dev, 0);
1653         i2c_set_sda(dev, 0);
1654         i2c_set_scl(dev, 1);
1655         i2c_set_sda(dev, 1);
1656 }
1657
1658 static void i2c_write(struct comedi_device *dev, unsigned int address,
1659                       const uint8_t *data, unsigned int length)
1660 {
1661         struct pcidas64_private *devpriv = dev->private;
1662         unsigned int i;
1663         uint8_t bitstream;
1664         static const int read_bit = 0x1;
1665
1666         /* XXX need mutex to prevent simultaneous attempts to access
1667          * eeprom and i2c bus */
1668
1669         /*  make sure we dont send anything to eeprom */
1670         devpriv->plx_control_bits &= ~CTL_EE_CS;
1671
1672         i2c_stop(dev);
1673         i2c_start(dev);
1674
1675         /*  send address and write bit */
1676         bitstream = (address << 1) & ~read_bit;
1677         i2c_write_byte(dev, bitstream);
1678
1679         /*  get acknowledge */
1680         if (i2c_read_ack(dev) != 0) {
1681                 dev_err(dev->class_dev, "%s failed: no acknowledge\n",
1682                         __func__);
1683                 i2c_stop(dev);
1684                 return;
1685         }
1686         /*  write data bytes */
1687         for (i = 0; i < length; i++) {
1688                 i2c_write_byte(dev, data[i]);
1689                 if (i2c_read_ack(dev) != 0) {
1690                         dev_err(dev->class_dev, "%s failed: no acknowledge\n",
1691                                 __func__);
1692                         i2c_stop(dev);
1693                         return;
1694                 }
1695         }
1696         i2c_stop(dev);
1697 }
1698
1699 static int cb_pcidas64_ai_eoc(struct comedi_device *dev,
1700                               struct comedi_subdevice *s,
1701                               struct comedi_insn *insn,
1702                               unsigned long context)
1703 {
1704         const struct pcidas64_board *thisboard = dev->board_ptr;
1705         struct pcidas64_private *devpriv = dev->private;
1706         unsigned int status;
1707
1708         status = readw(devpriv->main_iobase + HW_STATUS_REG);
1709         if (thisboard->layout == LAYOUT_4020) {
1710                 status = readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG);
1711                 if (status)
1712                         return 0;
1713         } else {
1714                 if (pipe_full_bits(status))
1715                         return 0;
1716         }
1717         return -EBUSY;
1718 }
1719
1720 static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1721                     struct comedi_insn *insn, unsigned int *data)
1722 {
1723         const struct pcidas64_board *thisboard = dev->board_ptr;
1724         struct pcidas64_private *devpriv = dev->private;
1725         unsigned int bits = 0, n;
1726         unsigned int channel, range, aref;
1727         unsigned long flags;
1728         int ret;
1729
1730         channel = CR_CHAN(insn->chanspec);
1731         range = CR_RANGE(insn->chanspec);
1732         aref = CR_AREF(insn->chanspec);
1733
1734         /*  disable card's analog input interrupt sources and pacing */
1735         /*  4020 generates dac done interrupts even though they are disabled */
1736         disable_ai_pacing(dev);
1737
1738         spin_lock_irqsave(&dev->spinlock, flags);
1739         if (insn->chanspec & CR_ALT_FILTER)
1740                 devpriv->adc_control1_bits |= ADC_DITHER_BIT;
1741         else
1742                 devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
1743         writew(devpriv->adc_control1_bits,
1744                devpriv->main_iobase + ADC_CONTROL1_REG);
1745         spin_unlock_irqrestore(&dev->spinlock, flags);
1746
1747         if (thisboard->layout != LAYOUT_4020) {
1748                 /*  use internal queue */
1749                 devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
1750                 writew(devpriv->hw_config_bits,
1751                        devpriv->main_iobase + HW_CONFIG_REG);
1752
1753                 /*  ALT_SOURCE is internal calibration reference */
1754                 if (insn->chanspec & CR_ALT_SOURCE) {
1755                         unsigned int cal_en_bit;
1756
1757                         if (thisboard->layout == LAYOUT_60XX)
1758                                 cal_en_bit = CAL_EN_60XX_BIT;
1759                         else
1760                                 cal_en_bit = CAL_EN_64XX_BIT;
1761                         /*  select internal reference source to connect
1762                          *  to channel 0 */
1763                         writew(cal_en_bit |
1764                                adc_src_bits(devpriv->calibration_source),
1765                                devpriv->main_iobase + CALIBRATION_REG);
1766                 } else {
1767                         /*  make sure internal calibration source
1768                          *  is turned off */
1769                         writew(0, devpriv->main_iobase + CALIBRATION_REG);
1770                 }
1771                 /*  load internal queue */
1772                 bits = 0;
1773                 /*  set gain */
1774                 bits |= ai_range_bits_6xxx(dev, CR_RANGE(insn->chanspec));
1775                 /*  set single-ended / differential */
1776                 bits |= se_diff_bit_6xxx(dev, aref == AREF_DIFF);
1777                 if (aref == AREF_COMMON)
1778                         bits |= ADC_COMMON_BIT;
1779                 bits |= adc_chan_bits(channel);
1780                 /*  set stop channel */
1781                 writew(adc_chan_bits(channel),
1782                        devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
1783                 /*  set start channel, and rest of settings */
1784                 writew(bits, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
1785         } else {
1786                 uint8_t old_cal_range_bits = devpriv->i2c_cal_range_bits;
1787
1788                 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
1789                 if (insn->chanspec & CR_ALT_SOURCE) {
1790                         devpriv->i2c_cal_range_bits |=
1791                                 adc_src_4020_bits(devpriv->calibration_source);
1792                 } else {        /* select BNC inputs */
1793                         devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
1794                 }
1795                 /*  select range */
1796                 if (range == 0)
1797                         devpriv->i2c_cal_range_bits |= attenuate_bit(channel);
1798                 else
1799                         devpriv->i2c_cal_range_bits &= ~attenuate_bit(channel);
1800                 /*  update calibration/range i2c register only if necessary,
1801                  *  as it is very slow */
1802                 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
1803                         uint8_t i2c_data = devpriv->i2c_cal_range_bits;
1804
1805                         i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
1806                                   sizeof(i2c_data));
1807                 }
1808
1809                 /* 4020 manual asks that sample interval register to be set
1810                  * before writing to convert register.
1811                  * Using somewhat arbitrary setting of 4 master clock ticks
1812                  * = 0.1 usec */
1813                 writew(0, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1814                 writew(2, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
1815         }
1816
1817         for (n = 0; n < insn->n; n++) {
1818
1819                 /*  clear adc buffer (inside loop for 4020 sake) */
1820                 writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
1821
1822                 /* trigger conversion, bits sent only matter for 4020 */
1823                 writew(adc_convert_chan_4020_bits(CR_CHAN(insn->chanspec)),
1824                        devpriv->main_iobase + ADC_CONVERT_REG);
1825
1826                 /*  wait for data */
1827                 ret = comedi_timeout(dev, s, insn, cb_pcidas64_ai_eoc, 0);
1828                 if (ret)
1829                         return ret;
1830
1831                 if (thisboard->layout == LAYOUT_4020)
1832                         data[n] = readl(dev->mmio + ADC_FIFO_REG) & 0xffff;
1833                 else
1834                         data[n] = readw(devpriv->main_iobase + PIPE1_READ_REG);
1835         }
1836
1837         return n;
1838 }
1839
1840 static int ai_config_calibration_source(struct comedi_device *dev,
1841                                         unsigned int *data)
1842 {
1843         const struct pcidas64_board *thisboard = dev->board_ptr;
1844         struct pcidas64_private *devpriv = dev->private;
1845         unsigned int source = data[1];
1846         int num_calibration_sources;
1847
1848         if (thisboard->layout == LAYOUT_60XX)
1849                 num_calibration_sources = 16;
1850         else
1851                 num_calibration_sources = 8;
1852         if (source >= num_calibration_sources) {
1853                 dev_dbg(dev->class_dev, "invalid calibration source: %i\n",
1854                         source);
1855                 return -EINVAL;
1856         }
1857
1858         devpriv->calibration_source = source;
1859
1860         return 2;
1861 }
1862
1863 static int ai_config_block_size(struct comedi_device *dev, unsigned int *data)
1864 {
1865         const struct pcidas64_board *thisboard = dev->board_ptr;
1866         int fifo_size;
1867         const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1868         unsigned int block_size, requested_block_size;
1869         int retval;
1870
1871         requested_block_size = data[1];
1872
1873         if (requested_block_size) {
1874                 fifo_size = requested_block_size * fifo->num_segments /
1875                             bytes_in_sample;
1876
1877                 retval = set_ai_fifo_size(dev, fifo_size);
1878                 if (retval < 0)
1879                         return retval;
1880
1881         }
1882
1883         block_size = ai_fifo_size(dev) / fifo->num_segments * bytes_in_sample;
1884
1885         data[1] = block_size;
1886
1887         return 2;
1888 }
1889
1890 static int ai_config_master_clock_4020(struct comedi_device *dev,
1891                                        unsigned int *data)
1892 {
1893         struct pcidas64_private *devpriv = dev->private;
1894         unsigned int divisor = data[4];
1895         int retval = 0;
1896
1897         if (divisor < 2) {
1898                 divisor = 2;
1899                 retval = -EAGAIN;
1900         }
1901
1902         switch (data[1]) {
1903         case COMEDI_EV_SCAN_BEGIN:
1904                 devpriv->ext_clock.divisor = divisor;
1905                 devpriv->ext_clock.chanspec = data[2];
1906                 break;
1907         default:
1908                 return -EINVAL;
1909         }
1910
1911         data[4] = divisor;
1912
1913         return retval ? retval : 5;
1914 }
1915
1916 /* XXX could add support for 60xx series */
1917 static int ai_config_master_clock(struct comedi_device *dev, unsigned int *data)
1918 {
1919         const struct pcidas64_board *thisboard = dev->board_ptr;
1920
1921         switch (thisboard->layout) {
1922         case LAYOUT_4020:
1923                 return ai_config_master_clock_4020(dev, data);
1924         default:
1925                 return -EINVAL;
1926         }
1927
1928         return -EINVAL;
1929 }
1930
1931 static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s,
1932                           struct comedi_insn *insn, unsigned int *data)
1933 {
1934         int id = data[0];
1935
1936         switch (id) {
1937         case INSN_CONFIG_ALT_SOURCE:
1938                 return ai_config_calibration_source(dev, data);
1939         case INSN_CONFIG_BLOCK_SIZE:
1940                 return ai_config_block_size(dev, data);
1941         case INSN_CONFIG_TIMER_1:
1942                 return ai_config_master_clock(dev, data);
1943         default:
1944                 return -EINVAL;
1945         }
1946         return -EINVAL;
1947 }
1948
1949 /* Gets nearest achievable timing given master clock speed, does not
1950  * take into account possible minimum/maximum divisor values.  Used
1951  * by other timing checking functions. */
1952 static unsigned int get_divisor(unsigned int ns, unsigned int flags)
1953 {
1954         unsigned int divisor;
1955
1956         switch (flags & CMDF_ROUND_MASK) {
1957         case CMDF_ROUND_UP:
1958                 divisor = (ns + TIMER_BASE - 1) / TIMER_BASE;
1959                 break;
1960         case CMDF_ROUND_DOWN:
1961                 divisor = ns / TIMER_BASE;
1962                 break;
1963         case CMDF_ROUND_NEAREST:
1964         default:
1965                 divisor = (ns + TIMER_BASE / 2) / TIMER_BASE;
1966                 break;
1967         }
1968         return divisor;
1969 }
1970
1971 /* utility function that rounds desired timing to an achievable time, and
1972  * sets cmd members appropriately.
1973  * adc paces conversions from master clock by dividing by (x + 3) where x is 24 bit number
1974  */
1975 static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd)
1976 {
1977         const struct pcidas64_board *thisboard = dev->board_ptr;
1978         unsigned int convert_divisor = 0, scan_divisor;
1979         static const int min_convert_divisor = 3;
1980         static const int max_convert_divisor =
1981                 max_counter_value + min_convert_divisor;
1982         static const int min_scan_divisor_4020 = 2;
1983         unsigned long long max_scan_divisor, min_scan_divisor;
1984
1985         if (cmd->convert_src == TRIG_TIMER) {
1986                 if (thisboard->layout == LAYOUT_4020) {
1987                         cmd->convert_arg = 0;
1988                 } else {
1989                         convert_divisor = get_divisor(cmd->convert_arg,
1990                                                       cmd->flags);
1991                         if (convert_divisor > max_convert_divisor)
1992                                 convert_divisor = max_convert_divisor;
1993                         if (convert_divisor < min_convert_divisor)
1994                                 convert_divisor = min_convert_divisor;
1995                         cmd->convert_arg = convert_divisor * TIMER_BASE;
1996                 }
1997         } else if (cmd->convert_src == TRIG_NOW) {
1998                 cmd->convert_arg = 0;
1999         }
2000
2001         if (cmd->scan_begin_src == TRIG_TIMER) {
2002                 scan_divisor = get_divisor(cmd->scan_begin_arg, cmd->flags);
2003                 if (cmd->convert_src == TRIG_TIMER) {
2004                         /*  XXX check for integer overflows */
2005                         min_scan_divisor = convert_divisor * cmd->chanlist_len;
2006                         max_scan_divisor =
2007                                 (convert_divisor * cmd->chanlist_len - 1) +
2008                                 max_counter_value;
2009                 } else {
2010                         min_scan_divisor = min_scan_divisor_4020;
2011                         max_scan_divisor = max_counter_value + min_scan_divisor;
2012                 }
2013                 if (scan_divisor > max_scan_divisor)
2014                         scan_divisor = max_scan_divisor;
2015                 if (scan_divisor < min_scan_divisor)
2016                         scan_divisor = min_scan_divisor;
2017                 cmd->scan_begin_arg = scan_divisor * TIMER_BASE;
2018         }
2019 }
2020
2021 static int cb_pcidas64_ai_check_chanlist(struct comedi_device *dev,
2022                                          struct comedi_subdevice *s,
2023                                          struct comedi_cmd *cmd)
2024 {
2025         const struct pcidas64_board *board = dev->board_ptr;
2026         unsigned int aref0 = CR_AREF(cmd->chanlist[0]);
2027         int i;
2028
2029         for (i = 1; i < cmd->chanlist_len; i++) {
2030                 unsigned int aref = CR_AREF(cmd->chanlist[i]);
2031
2032                 if (aref != aref0) {
2033                         dev_dbg(dev->class_dev,
2034                                 "all elements in chanlist must use the same analog reference\n");
2035                         return -EINVAL;
2036                 }
2037         }
2038
2039         if (board->layout == LAYOUT_4020) {
2040                 unsigned int chan0 = CR_CHAN(cmd->chanlist[0]);
2041
2042                 for (i = 1; i < cmd->chanlist_len; i++) {
2043                         unsigned int chan = CR_CHAN(cmd->chanlist[i]);
2044
2045                         if (chan != (chan0 + i)) {
2046                                 dev_dbg(dev->class_dev,
2047                                         "chanlist must use consecutive channels\n");
2048                                 return -EINVAL;
2049                         }
2050                 }
2051                 if (cmd->chanlist_len == 3) {
2052                         dev_dbg(dev->class_dev,
2053                                 "chanlist cannot be 3 channels long, use 1, 2, or 4 channels\n");
2054                         return -EINVAL;
2055                 }
2056         }
2057
2058         return 0;
2059 }
2060
2061 static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2062                       struct comedi_cmd *cmd)
2063 {
2064         const struct pcidas64_board *thisboard = dev->board_ptr;
2065         int err = 0;
2066         unsigned int tmp_arg, tmp_arg2;
2067         unsigned int triggers;
2068
2069         /* Step 1 : check if triggers are trivially valid */
2070
2071         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
2072
2073         triggers = TRIG_TIMER;
2074         if (thisboard->layout == LAYOUT_4020)
2075                 triggers |= TRIG_OTHER;
2076         else
2077                 triggers |= TRIG_FOLLOW;
2078         err |= cfc_check_trigger_src(&cmd->scan_begin_src, triggers);
2079
2080         triggers = TRIG_TIMER;
2081         if (thisboard->layout == LAYOUT_4020)
2082                 triggers |= TRIG_NOW;
2083         else
2084                 triggers |= TRIG_EXT;
2085         err |= cfc_check_trigger_src(&cmd->convert_src, triggers);
2086         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2087         err |= cfc_check_trigger_src(&cmd->stop_src,
2088                                      TRIG_COUNT | TRIG_EXT | TRIG_NONE);
2089
2090         if (err)
2091                 return 1;
2092
2093         /* Step 2a : make sure trigger sources are unique */
2094
2095         err |= cfc_check_trigger_is_unique(cmd->start_src);
2096         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2097         err |= cfc_check_trigger_is_unique(cmd->convert_src);
2098         err |= cfc_check_trigger_is_unique(cmd->stop_src);
2099
2100         /* Step 2b : and mutually compatible */
2101
2102         if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
2103                 err |= -EINVAL;
2104
2105         if (err)
2106                 return 2;
2107
2108         /* Step 3: check if arguments are trivially valid */
2109
2110         switch (cmd->start_src) {
2111         case TRIG_NOW:
2112                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
2113                 break;
2114         case TRIG_EXT:
2115                 /*
2116                  * start_arg is the CR_CHAN | CR_INVERT of the
2117                  * external trigger.
2118                  */
2119                 break;
2120         }
2121
2122         if (cmd->convert_src == TRIG_TIMER) {
2123                 if (thisboard->layout == LAYOUT_4020) {
2124                         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2125                 } else {
2126                         err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
2127                                                          thisboard->ai_speed);
2128                         /* if scans are timed faster than conversion rate allows */
2129                         if (cmd->scan_begin_src == TRIG_TIMER)
2130                                 err |= cfc_check_trigger_arg_min(
2131                                                 &cmd->scan_begin_arg,
2132                                                 cmd->convert_arg *
2133                                                 cmd->chanlist_len);
2134                 }
2135         }
2136
2137         err |= cfc_check_trigger_arg_min(&cmd->chanlist_len, 1);
2138         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
2139
2140         switch (cmd->stop_src) {
2141         case TRIG_EXT:
2142                 break;
2143         case TRIG_COUNT:
2144                 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
2145                 break;
2146         case TRIG_NONE:
2147                 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
2148                 break;
2149         default:
2150                 break;
2151         }
2152
2153         if (err)
2154                 return 3;
2155
2156         /* step 4: fix up any arguments */
2157
2158         if (cmd->convert_src == TRIG_TIMER) {
2159                 tmp_arg = cmd->convert_arg;
2160                 tmp_arg2 = cmd->scan_begin_arg;
2161                 check_adc_timing(dev, cmd);
2162                 if (tmp_arg != cmd->convert_arg)
2163                         err++;
2164                 if (tmp_arg2 != cmd->scan_begin_arg)
2165                         err++;
2166         }
2167
2168         if (err)
2169                 return 4;
2170
2171         /* Step 5: check channel list if it exists */
2172         if (cmd->chanlist && cmd->chanlist_len > 0)
2173                 err |= cb_pcidas64_ai_check_chanlist(dev, s, cmd);
2174
2175         if (err)
2176                 return 5;
2177
2178         return 0;
2179 }
2180
2181 static int use_hw_sample_counter(struct comedi_cmd *cmd)
2182 {
2183 /* disable for now until I work out a race */
2184         return 0;
2185
2186         if (cmd->stop_src == TRIG_COUNT && cmd->stop_arg <= max_counter_value)
2187                 return 1;
2188
2189         return 0;
2190 }
2191
2192 static void setup_sample_counters(struct comedi_device *dev,
2193                                   struct comedi_cmd *cmd)
2194 {
2195         struct pcidas64_private *devpriv = dev->private;
2196
2197         /*  load hardware conversion counter */
2198         if (use_hw_sample_counter(cmd)) {
2199                 writew(cmd->stop_arg & 0xffff,
2200                        devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2201                 writew((cmd->stop_arg >> 16) & 0xff,
2202                        devpriv->main_iobase + ADC_COUNT_UPPER_REG);
2203         } else {
2204                 writew(1, devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2205         }
2206 }
2207
2208 static inline unsigned int dma_transfer_size(struct comedi_device *dev)
2209 {
2210         const struct pcidas64_board *thisboard = dev->board_ptr;
2211         struct pcidas64_private *devpriv = dev->private;
2212         unsigned int num_samples;
2213
2214         num_samples = devpriv->ai_fifo_segment_length *
2215                       thisboard->ai_fifo->sample_packing_ratio;
2216         if (num_samples > DMA_BUFFER_SIZE / sizeof(uint16_t))
2217                 num_samples = DMA_BUFFER_SIZE / sizeof(uint16_t);
2218
2219         return num_samples;
2220 }
2221
2222 static uint32_t ai_convert_counter_6xxx(const struct comedi_device *dev,
2223                                         const struct comedi_cmd *cmd)
2224 {
2225         /*  supposed to load counter with desired divisor minus 3 */
2226         return cmd->convert_arg / TIMER_BASE - 3;
2227 }
2228
2229 static uint32_t ai_scan_counter_6xxx(struct comedi_device *dev,
2230                                      struct comedi_cmd *cmd)
2231 {
2232         uint32_t count;
2233
2234         /*  figure out how long we need to delay at end of scan */
2235         switch (cmd->scan_begin_src) {
2236         case TRIG_TIMER:
2237                 count = (cmd->scan_begin_arg -
2238                          (cmd->convert_arg * (cmd->chanlist_len - 1))) /
2239                         TIMER_BASE;
2240                 break;
2241         case TRIG_FOLLOW:
2242                 count = cmd->convert_arg / TIMER_BASE;
2243                 break;
2244         default:
2245                 return 0;
2246         }
2247         return count - 3;
2248 }
2249
2250 static uint32_t ai_convert_counter_4020(struct comedi_device *dev,
2251                                         struct comedi_cmd *cmd)
2252 {
2253         struct pcidas64_private *devpriv = dev->private;
2254         unsigned int divisor;
2255
2256         switch (cmd->scan_begin_src) {
2257         case TRIG_TIMER:
2258                 divisor = cmd->scan_begin_arg / TIMER_BASE;
2259                 break;
2260         case TRIG_OTHER:
2261                 divisor = devpriv->ext_clock.divisor;
2262                 break;
2263         default:                /*  should never happen */
2264                 dev_err(dev->class_dev, "bug! failed to set ai pacing!\n");
2265                 divisor = 1000;
2266                 break;
2267         }
2268
2269         /*  supposed to load counter with desired divisor minus 2 for 4020 */
2270         return divisor - 2;
2271 }
2272
2273 static void select_master_clock_4020(struct comedi_device *dev,
2274                                      const struct comedi_cmd *cmd)
2275 {
2276         struct pcidas64_private *devpriv = dev->private;
2277
2278         /*  select internal/external master clock */
2279         devpriv->hw_config_bits &= ~MASTER_CLOCK_4020_MASK;
2280         if (cmd->scan_begin_src == TRIG_OTHER) {
2281                 int chanspec = devpriv->ext_clock.chanspec;
2282
2283                 if (CR_CHAN(chanspec))
2284                         devpriv->hw_config_bits |= BNC_CLOCK_4020_BITS;
2285                 else
2286                         devpriv->hw_config_bits |= EXT_CLOCK_4020_BITS;
2287         } else {
2288                 devpriv->hw_config_bits |= INTERNAL_CLOCK_4020_BITS;
2289         }
2290         writew(devpriv->hw_config_bits,
2291                devpriv->main_iobase + HW_CONFIG_REG);
2292 }
2293
2294 static void select_master_clock(struct comedi_device *dev,
2295                                 const struct comedi_cmd *cmd)
2296 {
2297         const struct pcidas64_board *thisboard = dev->board_ptr;
2298
2299         switch (thisboard->layout) {
2300         case LAYOUT_4020:
2301                 select_master_clock_4020(dev, cmd);
2302                 break;
2303         default:
2304                 break;
2305         }
2306 }
2307
2308 static inline void dma_start_sync(struct comedi_device *dev,
2309                                   unsigned int channel)
2310 {
2311         struct pcidas64_private *devpriv = dev->private;
2312         unsigned long flags;
2313
2314         /*  spinlock for plx dma control/status reg */
2315         spin_lock_irqsave(&dev->spinlock, flags);
2316         if (channel)
2317                 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2318                        PLX_CLEAR_DMA_INTR_BIT,
2319                        devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2320         else
2321                 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2322                        PLX_CLEAR_DMA_INTR_BIT,
2323                        devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2324         spin_unlock_irqrestore(&dev->spinlock, flags);
2325 }
2326
2327 static void set_ai_pacing(struct comedi_device *dev, struct comedi_cmd *cmd)
2328 {
2329         const struct pcidas64_board *thisboard = dev->board_ptr;
2330         struct pcidas64_private *devpriv = dev->private;
2331         uint32_t convert_counter = 0, scan_counter = 0;
2332
2333         check_adc_timing(dev, cmd);
2334
2335         select_master_clock(dev, cmd);
2336
2337         if (thisboard->layout == LAYOUT_4020) {
2338                 convert_counter = ai_convert_counter_4020(dev, cmd);
2339         } else {
2340                 convert_counter = ai_convert_counter_6xxx(dev, cmd);
2341                 scan_counter = ai_scan_counter_6xxx(dev, cmd);
2342         }
2343
2344         /*  load lower 16 bits of convert interval */
2345         writew(convert_counter & 0xffff,
2346                devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
2347         /*  load upper 8 bits of convert interval */
2348         writew((convert_counter >> 16) & 0xff,
2349                devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
2350         /*  load lower 16 bits of scan delay */
2351         writew(scan_counter & 0xffff,
2352                devpriv->main_iobase + ADC_DELAY_INTERVAL_LOWER_REG);
2353         /*  load upper 8 bits of scan delay */
2354         writew((scan_counter >> 16) & 0xff,
2355                devpriv->main_iobase + ADC_DELAY_INTERVAL_UPPER_REG);
2356 }
2357
2358 static int use_internal_queue_6xxx(const struct comedi_cmd *cmd)
2359 {
2360         int i;
2361
2362         for (i = 0; i + 1 < cmd->chanlist_len; i++) {
2363                 if (CR_CHAN(cmd->chanlist[i + 1]) !=
2364                     CR_CHAN(cmd->chanlist[i]) + 1)
2365                         return 0;
2366                 if (CR_RANGE(cmd->chanlist[i + 1]) !=
2367                     CR_RANGE(cmd->chanlist[i]))
2368                         return 0;
2369                 if (CR_AREF(cmd->chanlist[i + 1]) != CR_AREF(cmd->chanlist[i]))
2370                         return 0;
2371         }
2372         return 1;
2373 }
2374
2375 static int setup_channel_queue(struct comedi_device *dev,
2376                                const struct comedi_cmd *cmd)
2377 {
2378         const struct pcidas64_board *thisboard = dev->board_ptr;
2379         struct pcidas64_private *devpriv = dev->private;
2380         unsigned short bits;
2381         int i;
2382
2383         if (thisboard->layout != LAYOUT_4020) {
2384                 if (use_internal_queue_6xxx(cmd)) {
2385                         devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
2386                         writew(devpriv->hw_config_bits,
2387                                devpriv->main_iobase + HW_CONFIG_REG);
2388                         bits = 0;
2389                         /*  set channel */
2390                         bits |= adc_chan_bits(CR_CHAN(cmd->chanlist[0]));
2391                         /*  set gain */
2392                         bits |= ai_range_bits_6xxx(dev,
2393                                                    CR_RANGE(cmd->chanlist[0]));
2394                         /*  set single-ended / differential */
2395                         bits |= se_diff_bit_6xxx(dev,
2396                                                  CR_AREF(cmd->chanlist[0]) ==
2397                                                  AREF_DIFF);
2398                         if (CR_AREF(cmd->chanlist[0]) == AREF_COMMON)
2399                                 bits |= ADC_COMMON_BIT;
2400                         /*  set stop channel */
2401                         writew(adc_chan_bits
2402                                (CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1])),
2403                                devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
2404                         /*  set start channel, and rest of settings */
2405                         writew(bits,
2406                                devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2407                 } else {
2408                         /*  use external queue */
2409                         if (dev->write_subdev && dev->write_subdev->busy) {
2410                                 warn_external_queue(dev);
2411                                 return -EBUSY;
2412                         }
2413                         devpriv->hw_config_bits |= EXT_QUEUE_BIT;
2414                         writew(devpriv->hw_config_bits,
2415                                devpriv->main_iobase + HW_CONFIG_REG);
2416                         /*  clear DAC buffer to prevent weird interactions */
2417                         writew(0,
2418                                devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
2419                         /*  clear queue pointer */
2420                         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2421                         /*  load external queue */
2422                         for (i = 0; i < cmd->chanlist_len; i++) {
2423                                 bits = 0;
2424                                 /*  set channel */
2425                                 bits |= adc_chan_bits(CR_CHAN(cmd->
2426                                                               chanlist[i]));
2427                                 /*  set gain */
2428                                 bits |= ai_range_bits_6xxx(dev,
2429                                                            CR_RANGE(cmd->
2430                                                                     chanlist
2431                                                                     [i]));
2432                                 /*  set single-ended / differential */
2433                                 bits |= se_diff_bit_6xxx(dev,
2434                                                          CR_AREF(cmd->
2435                                                                  chanlist[i]) ==
2436                                                          AREF_DIFF);
2437                                 if (CR_AREF(cmd->chanlist[i]) == AREF_COMMON)
2438                                         bits |= ADC_COMMON_BIT;
2439                                 /*  mark end of queue */
2440                                 if (i == cmd->chanlist_len - 1)
2441                                         bits |= QUEUE_EOSCAN_BIT |
2442                                                 QUEUE_EOSEQ_BIT;
2443                                 writew(bits,
2444                                        devpriv->main_iobase +
2445                                        ADC_QUEUE_FIFO_REG);
2446                         }
2447                         /* doing a queue clear is not specified in board docs,
2448                          * but required for reliable operation */
2449                         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2450                         /*  prime queue holding register */
2451                         writew(0, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2452                 }
2453         } else {
2454                 unsigned short old_cal_range_bits = devpriv->i2c_cal_range_bits;
2455
2456                 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
2457                 /* select BNC inputs */
2458                 devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
2459                 /*  select ranges */
2460                 for (i = 0; i < cmd->chanlist_len; i++) {
2461                         unsigned int channel = CR_CHAN(cmd->chanlist[i]);
2462                         unsigned int range = CR_RANGE(cmd->chanlist[i]);
2463
2464                         if (range == 0)
2465                                 devpriv->i2c_cal_range_bits |=
2466                                         attenuate_bit(channel);
2467                         else
2468                                 devpriv->i2c_cal_range_bits &=
2469                                         ~attenuate_bit(channel);
2470                 }
2471                 /*  update calibration/range i2c register only if necessary,
2472                  *  as it is very slow */
2473                 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
2474                         uint8_t i2c_data = devpriv->i2c_cal_range_bits;
2475
2476                         i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
2477                                   sizeof(i2c_data));
2478                 }
2479         }
2480         return 0;
2481 }
2482
2483 static inline void load_first_dma_descriptor(struct comedi_device *dev,
2484                                              unsigned int dma_channel,
2485                                              unsigned int descriptor_bits)
2486 {
2487         struct pcidas64_private *devpriv = dev->private;
2488
2489         /* The transfer size, pci address, and local address registers
2490          * are supposedly unused during chained dma,
2491          * but I have found that left over values from last operation
2492          * occasionally cause problems with transfer of first dma
2493          * block.  Initializing them to zero seems to fix the problem. */
2494         if (dma_channel) {
2495                 writel(0,
2496                        devpriv->plx9080_iobase + PLX_DMA1_TRANSFER_SIZE_REG);
2497                 writel(0, devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG);
2498                 writel(0,
2499                        devpriv->plx9080_iobase + PLX_DMA1_LOCAL_ADDRESS_REG);
2500                 writel(descriptor_bits,
2501                        devpriv->plx9080_iobase + PLX_DMA1_DESCRIPTOR_REG);
2502         } else {
2503                 writel(0,
2504                        devpriv->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG);
2505                 writel(0, devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
2506                 writel(0,
2507                        devpriv->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG);
2508                 writel(descriptor_bits,
2509                        devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
2510         }
2511 }
2512
2513 static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2514 {
2515         const struct pcidas64_board *thisboard = dev->board_ptr;
2516         struct pcidas64_private *devpriv = dev->private;
2517         struct comedi_async *async = s->async;
2518         struct comedi_cmd *cmd = &async->cmd;
2519         uint32_t bits;
2520         unsigned int i;
2521         unsigned long flags;
2522         int retval;
2523
2524         disable_ai_pacing(dev);
2525         abort_dma(dev, 1);
2526
2527         retval = setup_channel_queue(dev, cmd);
2528         if (retval < 0)
2529                 return retval;
2530
2531         /*  make sure internal calibration source is turned off */
2532         writew(0, devpriv->main_iobase + CALIBRATION_REG);
2533
2534         set_ai_pacing(dev, cmd);
2535
2536         setup_sample_counters(dev, cmd);
2537
2538         enable_ai_interrupts(dev, cmd);
2539
2540         spin_lock_irqsave(&dev->spinlock, flags);
2541         /* set mode, allow conversions through software gate */
2542         devpriv->adc_control1_bits |= ADC_SW_GATE_BIT;
2543         devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
2544         if (thisboard->layout != LAYOUT_4020) {
2545                 devpriv->adc_control1_bits &= ~ADC_MODE_MASK;
2546                 if (cmd->convert_src == TRIG_EXT)
2547                         /*  good old mode 13 */
2548                         devpriv->adc_control1_bits |= adc_mode_bits(13);
2549                 else
2550                         /*  mode 8.  What else could you need? */
2551                         devpriv->adc_control1_bits |= adc_mode_bits(8);
2552         } else {
2553                 devpriv->adc_control1_bits &= ~CHANNEL_MODE_4020_MASK;
2554                 if (cmd->chanlist_len == 4)
2555                         devpriv->adc_control1_bits |= FOUR_CHANNEL_4020_BITS;
2556                 else if (cmd->chanlist_len == 2)
2557                         devpriv->adc_control1_bits |= TWO_CHANNEL_4020_BITS;
2558                 devpriv->adc_control1_bits &= ~ADC_LO_CHANNEL_4020_MASK;
2559                 devpriv->adc_control1_bits |=
2560                         adc_lo_chan_4020_bits(CR_CHAN(cmd->chanlist[0]));
2561                 devpriv->adc_control1_bits &= ~ADC_HI_CHANNEL_4020_MASK;
2562                 devpriv->adc_control1_bits |=
2563                         adc_hi_chan_4020_bits(CR_CHAN(cmd->chanlist
2564                                                       [cmd->chanlist_len - 1]));
2565         }
2566         writew(devpriv->adc_control1_bits,
2567                devpriv->main_iobase + ADC_CONTROL1_REG);
2568         spin_unlock_irqrestore(&dev->spinlock, flags);
2569
2570         /*  clear adc buffer */
2571         writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
2572
2573         if ((cmd->flags & CMDF_WAKE_EOS) == 0 ||
2574             thisboard->layout == LAYOUT_4020) {
2575                 devpriv->ai_dma_index = 0;
2576
2577                 /*  set dma transfer size */
2578                 for (i = 0; i < ai_dma_ring_count(thisboard); i++)
2579                         devpriv->ai_dma_desc[i].transfer_size =
2580                                 cpu_to_le32(dma_transfer_size(dev) *
2581                                             sizeof(uint16_t));
2582
2583                 /*  give location of first dma descriptor */
2584                 load_first_dma_descriptor(dev, 1,
2585                                           devpriv->ai_dma_desc_bus_addr |
2586                                           PLX_DESC_IN_PCI_BIT |
2587                                           PLX_INTR_TERM_COUNT |
2588                                           PLX_XFER_LOCAL_TO_PCI);
2589
2590                 dma_start_sync(dev, 1);
2591         }
2592
2593         if (thisboard->layout == LAYOUT_4020) {
2594                 /* set source for external triggers */
2595                 bits = 0;
2596                 if (cmd->start_src == TRIG_EXT && CR_CHAN(cmd->start_arg))
2597                         bits |= EXT_START_TRIG_BNC_BIT;
2598                 if (cmd->stop_src == TRIG_EXT && CR_CHAN(cmd->stop_arg))
2599                         bits |= EXT_STOP_TRIG_BNC_BIT;
2600                 writew(bits, devpriv->main_iobase + DAQ_ATRIG_LOW_4020_REG);
2601         }
2602
2603         spin_lock_irqsave(&dev->spinlock, flags);
2604
2605         /* enable pacing, triggering, etc */
2606         bits = ADC_ENABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT;
2607         if (cmd->flags & CMDF_WAKE_EOS)
2608                 bits |= ADC_DMA_DISABLE_BIT;
2609         /*  set start trigger */
2610         if (cmd->start_src == TRIG_EXT) {
2611                 bits |= ADC_START_TRIG_EXT_BITS;
2612                 if (cmd->start_arg & CR_INVERT)
2613                         bits |= ADC_START_TRIG_FALLING_BIT;
2614         } else if (cmd->start_src == TRIG_NOW)
2615                 bits |= ADC_START_TRIG_SOFT_BITS;
2616         if (use_hw_sample_counter(cmd))
2617                 bits |= ADC_SAMPLE_COUNTER_EN_BIT;
2618         writew(bits, devpriv->main_iobase + ADC_CONTROL0_REG);
2619
2620         devpriv->ai_cmd_running = 1;
2621
2622         spin_unlock_irqrestore(&dev->spinlock, flags);
2623
2624         /*  start acquisition */
2625         if (cmd->start_src == TRIG_NOW)
2626                 writew(0, devpriv->main_iobase + ADC_START_REG);
2627
2628         return 0;
2629 }
2630
2631 /* read num_samples from 16 bit wide ai fifo */
2632 static void pio_drain_ai_fifo_16(struct comedi_device *dev)
2633 {
2634         struct pcidas64_private *devpriv = dev->private;
2635         struct comedi_subdevice *s = dev->read_subdev;
2636         unsigned int i;
2637         uint16_t prepost_bits;
2638         int read_segment, read_index, write_segment, write_index;
2639         int num_samples;
2640
2641         do {
2642                 /*  get least significant 15 bits */
2643                 read_index = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) &
2644                              0x7fff;
2645                 write_index = readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) &
2646                               0x7fff;
2647                 /* Get most significant bits (grey code).
2648                  * Different boards use different code so use a scheme
2649                  * that doesn't depend on encoding.  This read must
2650                  * occur after reading least significant 15 bits to avoid race
2651                  * with fifo switching to next segment. */
2652                 prepost_bits = readw(devpriv->main_iobase + PREPOST_REG);
2653
2654                 /* if read and write pointers are not on the same fifo segment,
2655                  * read to the end of the read segment */
2656                 read_segment = adc_upper_read_ptr_code(prepost_bits);
2657                 write_segment = adc_upper_write_ptr_code(prepost_bits);
2658
2659                 if (read_segment != write_segment)
2660                         num_samples =
2661                                 devpriv->ai_fifo_segment_length - read_index;
2662                 else
2663                         num_samples = write_index - read_index;
2664                 if (num_samples < 0) {
2665                         dev_err(dev->class_dev,
2666                                 "cb_pcidas64: bug! num_samples < 0\n");
2667                         break;
2668                 }
2669
2670                 num_samples = comedi_nsamples_left(s, num_samples);
2671                 if (num_samples == 0)
2672                         break;
2673
2674                 for (i = 0; i < num_samples; i++) {
2675                         unsigned short val;
2676
2677                         val = readw(devpriv->main_iobase + ADC_FIFO_REG);
2678                         comedi_buf_write_samples(s, &val, 1);
2679                 }
2680
2681         } while (read_segment != write_segment);
2682 }
2683
2684 /* Read from 32 bit wide ai fifo of 4020 - deal with insane grey coding of
2685  * pointers.  The pci-4020 hardware only supports dma transfers (it only
2686  * supports the use of pio for draining the last remaining points from the
2687  * fifo when a data acquisition operation has completed).
2688  */
2689 static void pio_drain_ai_fifo_32(struct comedi_device *dev)
2690 {
2691         struct pcidas64_private *devpriv = dev->private;
2692         struct comedi_subdevice *s = dev->read_subdev;
2693         unsigned int nsamples;
2694         unsigned int i;
2695         uint32_t fifo_data;
2696         int write_code =
2697                 readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff;
2698         int read_code =
2699                 readw(devpriv->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2700
2701         nsamples = comedi_nsamples_left(s, 100000);
2702         for (i = 0; read_code != write_code && i < nsamples;) {
2703                 unsigned short val;
2704
2705                 fifo_data = readl(dev->mmio + ADC_FIFO_REG);
2706                 val = fifo_data & 0xffff;
2707                 comedi_buf_write_samples(s, &val, 1);
2708                 i++;
2709                 if (i < nsamples) {
2710                         val = (fifo_data >> 16) & 0xffff;
2711                         comedi_buf_write_samples(s, &val, 1);
2712                         i++;
2713                 }
2714                 read_code = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) &
2715                             0x7fff;
2716         }
2717 }
2718
2719 /* empty fifo */
2720 static void pio_drain_ai_fifo(struct comedi_device *dev)
2721 {
2722         const struct pcidas64_board *thisboard = dev->board_ptr;
2723
2724         if (thisboard->layout == LAYOUT_4020)
2725                 pio_drain_ai_fifo_32(dev);
2726         else
2727                 pio_drain_ai_fifo_16(dev);
2728 }
2729
2730 static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
2731 {
2732         const struct pcidas64_board *thisboard = dev->board_ptr;
2733         struct pcidas64_private *devpriv = dev->private;
2734         struct comedi_subdevice *s = dev->read_subdev;
2735         uint32_t next_transfer_addr;
2736         int j;
2737         int num_samples = 0;
2738         void __iomem *pci_addr_reg;
2739
2740         if (channel)
2741                 pci_addr_reg =
2742                     devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
2743         else
2744                 pci_addr_reg =
2745                     devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
2746
2747         /*  loop until we have read all the full buffers */
2748         for (j = 0, next_transfer_addr = readl(pci_addr_reg);
2749              (next_transfer_addr <
2750               devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] ||
2751               next_transfer_addr >=
2752               devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] +
2753               DMA_BUFFER_SIZE) && j < ai_dma_ring_count(thisboard); j++) {
2754                 /*  transfer data from dma buffer to comedi buffer */
2755                 num_samples = comedi_nsamples_left(s, dma_transfer_size(dev));
2756                 comedi_buf_write_samples(s,
2757                                 devpriv->ai_buffer[devpriv->ai_dma_index],
2758                                 num_samples);
2759                 devpriv->ai_dma_index = (devpriv->ai_dma_index + 1) %
2760                                         ai_dma_ring_count(thisboard);
2761         }
2762         /* XXX check for dma ring buffer overrun
2763          * (use end-of-chain bit to mark last unused buffer) */
2764 }
2765
2766 static void handle_ai_interrupt(struct comedi_device *dev,
2767                                 unsigned short status,
2768                                 unsigned int plx_status)
2769 {
2770         const struct pcidas64_board *thisboard = dev->board_ptr;
2771         struct pcidas64_private *devpriv = dev->private;
2772         struct comedi_subdevice *s = dev->read_subdev;
2773         struct comedi_async *async = s->async;
2774         struct comedi_cmd *cmd = &async->cmd;
2775         uint8_t dma1_status;
2776         unsigned long flags;
2777
2778         /*  check for fifo overrun */
2779         if (status & ADC_OVERRUN_BIT) {
2780                 dev_err(dev->class_dev, "fifo overrun\n");
2781                 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
2782         }
2783         /*  spin lock makes sure no one else changes plx dma control reg */
2784         spin_lock_irqsave(&dev->spinlock, flags);
2785         dma1_status = readb(devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2786         if (plx_status & ICS_DMA1_A) {  /*  dma chan 1 interrupt */
2787                 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
2788                        devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2789
2790                 if (dma1_status & PLX_DMA_EN_BIT)
2791                         drain_dma_buffers(dev, 1);
2792         }
2793         spin_unlock_irqrestore(&dev->spinlock, flags);
2794
2795         /*  drain fifo with pio */
2796         if ((status & ADC_DONE_BIT) ||
2797             ((cmd->flags & CMDF_WAKE_EOS) &&
2798              (status & ADC_INTR_PENDING_BIT) &&
2799              (thisboard->layout != LAYOUT_4020))) {
2800                 spin_lock_irqsave(&dev->spinlock, flags);
2801                 if (devpriv->ai_cmd_running) {
2802                         spin_unlock_irqrestore(&dev->spinlock, flags);
2803                         pio_drain_ai_fifo(dev);
2804                 } else
2805                         spin_unlock_irqrestore(&dev->spinlock, flags);
2806         }
2807         /*  if we are have all the data, then quit */
2808         if ((cmd->stop_src == TRIG_COUNT &&
2809              async->scans_done >= cmd->stop_arg) ||
2810             (cmd->stop_src == TRIG_EXT && (status & ADC_STOP_BIT)))
2811                 async->events |= COMEDI_CB_EOA;
2812
2813         comedi_handle_events(dev, s);
2814 }
2815
2816 static inline unsigned int prev_ao_dma_index(struct comedi_device *dev)
2817 {
2818         struct pcidas64_private *devpriv = dev->private;
2819         unsigned int buffer_index;
2820
2821         if (devpriv->ao_dma_index == 0)
2822                 buffer_index = AO_DMA_RING_COUNT - 1;
2823         else
2824                 buffer_index = devpriv->ao_dma_index - 1;
2825         return buffer_index;
2826 }
2827
2828 static int last_ao_dma_load_completed(struct comedi_device *dev)
2829 {
2830         struct pcidas64_private *devpriv = dev->private;
2831         unsigned int buffer_index;
2832         unsigned int transfer_address;
2833         unsigned short dma_status;
2834
2835         buffer_index = prev_ao_dma_index(dev);
2836         dma_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2837         if ((dma_status & PLX_DMA_DONE_BIT) == 0)
2838                 return 0;
2839
2840         transfer_address =
2841                 readl(devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
2842         if (transfer_address != devpriv->ao_buffer_bus_addr[buffer_index])
2843                 return 0;
2844
2845         return 1;
2846 }
2847
2848 static inline int ao_dma_needs_restart(struct comedi_device *dev,
2849                                        unsigned short dma_status)
2850 {
2851         if ((dma_status & PLX_DMA_DONE_BIT) == 0 ||
2852             (dma_status & PLX_DMA_EN_BIT) == 0)
2853                 return 0;
2854         if (last_ao_dma_load_completed(dev))
2855                 return 0;
2856
2857         return 1;
2858 }
2859
2860 static void restart_ao_dma(struct comedi_device *dev)
2861 {
2862         struct pcidas64_private *devpriv = dev->private;
2863         unsigned int dma_desc_bits;
2864
2865         dma_desc_bits =
2866                 readl(devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
2867         dma_desc_bits &= ~PLX_END_OF_CHAIN_BIT;
2868         load_first_dma_descriptor(dev, 0, dma_desc_bits);
2869
2870         dma_start_sync(dev, 0);
2871 }
2872
2873 static unsigned int cb_pcidas64_ao_fill_buffer(struct comedi_device *dev,
2874                                                struct comedi_subdevice *s,
2875                                                unsigned short *dest,
2876                                                unsigned int max_bytes)
2877 {
2878         unsigned int nsamples = comedi_bytes_to_samples(s, max_bytes);
2879         unsigned int actual_bytes;
2880
2881         nsamples = comedi_nsamples_left(s, nsamples);
2882         actual_bytes = comedi_buf_read_samples(s, dest, nsamples);
2883
2884         return comedi_bytes_to_samples(s, actual_bytes);
2885 }
2886
2887 static unsigned int load_ao_dma_buffer(struct comedi_device *dev,
2888                                        const struct comedi_cmd *cmd)
2889 {
2890         struct pcidas64_private *devpriv = dev->private;
2891         struct comedi_subdevice *s = dev->write_subdev;
2892         unsigned int buffer_index = devpriv->ao_dma_index;
2893         unsigned int prev_buffer_index = prev_ao_dma_index(dev);
2894         unsigned int nsamples;
2895         unsigned int nbytes;
2896         unsigned int next_bits;
2897
2898         nsamples = cb_pcidas64_ao_fill_buffer(dev, s,
2899                                               devpriv->ao_buffer[buffer_index],
2900                                               DMA_BUFFER_SIZE);
2901         if (nsamples == 0)
2902                 return 0;
2903
2904         nbytes = comedi_samples_to_bytes(s, nsamples);
2905         devpriv->ao_dma_desc[buffer_index].transfer_size = cpu_to_le32(nbytes);
2906         /* set end of chain bit so we catch underruns */
2907         next_bits = le32_to_cpu(devpriv->ao_dma_desc[buffer_index].next);
2908         next_bits |= PLX_END_OF_CHAIN_BIT;
2909         devpriv->ao_dma_desc[buffer_index].next = cpu_to_le32(next_bits);
2910         /* clear end of chain bit on previous buffer now that we have set it
2911          * for the last buffer */
2912         next_bits = le32_to_cpu(devpriv->ao_dma_desc[prev_buffer_index].next);
2913         next_bits &= ~PLX_END_OF_CHAIN_BIT;
2914         devpriv->ao_dma_desc[prev_buffer_index].next = cpu_to_le32(next_bits);
2915
2916         devpriv->ao_dma_index = (buffer_index + 1) % AO_DMA_RING_COUNT;
2917
2918         return nbytes;
2919 }
2920
2921 static void load_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
2922 {
2923         struct pcidas64_private *devpriv = dev->private;
2924         unsigned int num_bytes;
2925         unsigned int next_transfer_addr;
2926         void __iomem *pci_addr_reg =
2927                 devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
2928         unsigned int buffer_index;
2929
2930         do {
2931                 buffer_index = devpriv->ao_dma_index;
2932                 /* don't overwrite data that hasn't been transferred yet */
2933                 next_transfer_addr = readl(pci_addr_reg);
2934                 if (next_transfer_addr >=
2935                     devpriv->ao_buffer_bus_addr[buffer_index] &&
2936                     next_transfer_addr <
2937                     devpriv->ao_buffer_bus_addr[buffer_index] +
2938                     DMA_BUFFER_SIZE)
2939                         return;
2940                 num_bytes = load_ao_dma_buffer(dev, cmd);
2941         } while (num_bytes >= DMA_BUFFER_SIZE);
2942 }
2943
2944 static void handle_ao_interrupt(struct comedi_device *dev,
2945                                 unsigned short status, unsigned int plx_status)
2946 {
2947         struct pcidas64_private *devpriv = dev->private;
2948         struct comedi_subdevice *s = dev->write_subdev;
2949         struct comedi_async *async;
2950         struct comedi_cmd *cmd;
2951         uint8_t dma0_status;
2952         unsigned long flags;
2953
2954         /* board might not support ao, in which case write_subdev is NULL */
2955         if (s == NULL)
2956                 return;
2957         async = s->async;
2958         cmd = &async->cmd;
2959
2960         /*  spin lock makes sure no one else changes plx dma control reg */
2961         spin_lock_irqsave(&dev->spinlock, flags);
2962         dma0_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2963         if (plx_status & ICS_DMA0_A) {  /*  dma chan 0 interrupt */
2964                 if ((dma0_status & PLX_DMA_EN_BIT) &&
2965                     !(dma0_status & PLX_DMA_DONE_BIT))
2966                         writeb(PLX_DMA_EN_BIT | PLX_CLEAR_DMA_INTR_BIT,
2967                                devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2968                 else
2969                         writeb(PLX_CLEAR_DMA_INTR_BIT,
2970                                devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2971                 spin_unlock_irqrestore(&dev->spinlock, flags);
2972                 if (dma0_status & PLX_DMA_EN_BIT) {
2973                         load_ao_dma(dev, cmd);
2974                         /* try to recover from dma end-of-chain event */
2975                         if (ao_dma_needs_restart(dev, dma0_status))
2976                                 restart_ao_dma(dev);
2977                 }
2978         } else {
2979                 spin_unlock_irqrestore(&dev->spinlock, flags);
2980         }
2981
2982         if ((status & DAC_DONE_BIT)) {
2983                 if ((cmd->stop_src == TRIG_COUNT &&
2984                      async->scans_done >= cmd->stop_arg) ||
2985                     last_ao_dma_load_completed(dev))
2986                         async->events |= COMEDI_CB_EOA;
2987                 else
2988                         async->events |= COMEDI_CB_ERROR;
2989         }
2990         comedi_handle_events(dev, s);
2991 }
2992
2993 static irqreturn_t handle_interrupt(int irq, void *d)
2994 {
2995         struct comedi_device *dev = d;
2996         struct pcidas64_private *devpriv = dev->private;
2997         unsigned short status;
2998         uint32_t plx_status;
2999         uint32_t plx_bits;
3000
3001         plx_status = readl(devpriv->plx9080_iobase + PLX_INTRCS_REG);
3002         status = readw(devpriv->main_iobase + HW_STATUS_REG);
3003
3004         /* an interrupt before all the postconfig stuff gets done could
3005          * cause a NULL dereference if we continue through the
3006          * interrupt handler */
3007         if (!dev->attached)
3008                 return IRQ_HANDLED;
3009
3010         handle_ai_interrupt(dev, status, plx_status);
3011         handle_ao_interrupt(dev, status, plx_status);
3012
3013         /*  clear possible plx9080 interrupt sources */
3014         if (plx_status & ICS_LDIA) {    /*  clear local doorbell interrupt */
3015                 plx_bits = readl(devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
3016                 writel(plx_bits, devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
3017         }
3018
3019         return IRQ_HANDLED;
3020 }
3021
3022 static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3023 {
3024         struct pcidas64_private *devpriv = dev->private;
3025         unsigned long flags;
3026
3027         spin_lock_irqsave(&dev->spinlock, flags);
3028         if (devpriv->ai_cmd_running == 0) {
3029                 spin_unlock_irqrestore(&dev->spinlock, flags);
3030                 return 0;
3031         }
3032         devpriv->ai_cmd_running = 0;
3033         spin_unlock_irqrestore(&dev->spinlock, flags);
3034
3035         disable_ai_pacing(dev);
3036
3037         abort_dma(dev, 1);
3038
3039         return 0;
3040 }
3041
3042 static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
3043                     struct comedi_insn *insn, unsigned int *data)
3044 {
3045         const struct pcidas64_board *thisboard = dev->board_ptr;
3046         struct pcidas64_private *devpriv = dev->private;
3047         int chan = CR_CHAN(insn->chanspec);
3048         int range = CR_RANGE(insn->chanspec);
3049
3050         /*  do some initializing */
3051         writew(0, devpriv->main_iobase + DAC_CONTROL0_REG);
3052
3053         /*  set range */
3054         set_dac_range_bits(dev, &devpriv->dac_control1_bits, chan, range);
3055         writew(devpriv->dac_control1_bits,
3056                devpriv->main_iobase + DAC_CONTROL1_REG);
3057
3058         /*  write to channel */
3059         if (thisboard->layout == LAYOUT_4020) {
3060                 writew(data[0] & 0xff,
3061                        devpriv->main_iobase + dac_lsb_4020_reg(chan));
3062                 writew((data[0] >> 8) & 0xf,
3063                        devpriv->main_iobase + dac_msb_4020_reg(chan));
3064         } else {
3065                 writew(data[0], devpriv->main_iobase + dac_convert_reg(chan));
3066         }
3067
3068         /*  remember output value */
3069         s->readback[chan] = data[0];
3070
3071         return 1;
3072 }
3073
3074 static void set_dac_control0_reg(struct comedi_device *dev,
3075                                  const struct comedi_cmd *cmd)
3076 {
3077         struct pcidas64_private *devpriv = dev->private;
3078         unsigned int bits = DAC_ENABLE_BIT | WAVEFORM_GATE_LEVEL_BIT |
3079                             WAVEFORM_GATE_ENABLE_BIT | WAVEFORM_GATE_SELECT_BIT;
3080
3081         if (cmd->start_src == TRIG_EXT) {
3082                 bits |= WAVEFORM_TRIG_EXT_BITS;
3083                 if (cmd->start_arg & CR_INVERT)
3084                         bits |= WAVEFORM_TRIG_FALLING_BIT;
3085         } else {
3086                 bits |= WAVEFORM_TRIG_SOFT_BITS;
3087         }
3088         if (cmd->scan_begin_src == TRIG_EXT) {
3089                 bits |= DAC_EXT_UPDATE_ENABLE_BIT;
3090                 if (cmd->scan_begin_arg & CR_INVERT)
3091                         bits |= DAC_EXT_UPDATE_FALLING_BIT;
3092         }
3093         writew(bits, devpriv->main_iobase + DAC_CONTROL0_REG);
3094 }
3095
3096 static void set_dac_control1_reg(struct comedi_device *dev,
3097                                  const struct comedi_cmd *cmd)
3098 {
3099         struct pcidas64_private *devpriv = dev->private;
3100         int i;
3101
3102         for (i = 0; i < cmd->chanlist_len; i++) {
3103                 int channel, range;
3104
3105                 channel = CR_CHAN(cmd->chanlist[i]);
3106                 range = CR_RANGE(cmd->chanlist[i]);
3107                 set_dac_range_bits(dev, &devpriv->dac_control1_bits, channel,
3108                                    range);
3109         }
3110         devpriv->dac_control1_bits |= DAC_SW_GATE_BIT;
3111         writew(devpriv->dac_control1_bits,
3112                devpriv->main_iobase + DAC_CONTROL1_REG);
3113 }
3114
3115 static void set_dac_select_reg(struct comedi_device *dev,
3116                                const struct comedi_cmd *cmd)
3117 {
3118         struct pcidas64_private *devpriv = dev->private;
3119         uint16_t bits;
3120         unsigned int first_channel, last_channel;
3121
3122         first_channel = CR_CHAN(cmd->chanlist[0]);
3123         last_channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
3124         if (last_channel < first_channel)
3125                 dev_err(dev->class_dev,
3126                         "bug! last ao channel < first ao channel\n");
3127
3128         bits = (first_channel & 0x7) | (last_channel & 0x7) << 3;
3129
3130         writew(bits, devpriv->main_iobase + DAC_SELECT_REG);
3131 }
3132
3133 static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags)
3134 {
3135         return get_divisor(ns, flags) - 2;
3136 }
3137
3138 static void set_dac_interval_regs(struct comedi_device *dev,
3139                                   const struct comedi_cmd *cmd)
3140 {
3141         struct pcidas64_private *devpriv = dev->private;
3142         unsigned int divisor;
3143
3144         if (cmd->scan_begin_src != TRIG_TIMER)
3145                 return;
3146
3147         divisor = get_ao_divisor(cmd->scan_begin_arg, cmd->flags);
3148         if (divisor > max_counter_value) {
3149                 dev_err(dev->class_dev, "bug! ao divisor too big\n");
3150                 divisor = max_counter_value;
3151         }
3152         writew(divisor & 0xffff,
3153                devpriv->main_iobase + DAC_SAMPLE_INTERVAL_LOWER_REG);
3154         writew((divisor >> 16) & 0xff,
3155                devpriv->main_iobase + DAC_SAMPLE_INTERVAL_UPPER_REG);
3156 }
3157
3158 static int prep_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3159 {
3160         struct pcidas64_private *devpriv = dev->private;
3161         struct comedi_subdevice *s = dev->write_subdev;
3162         unsigned int nsamples;
3163         unsigned int nbytes;
3164         int i;
3165
3166         /* clear queue pointer too, since external queue has
3167          * weird interactions with ao fifo */
3168         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
3169         writew(0, devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
3170
3171         nsamples = cb_pcidas64_ao_fill_buffer(dev, s,
3172                                               devpriv->ao_bounce_buffer,
3173                                               DAC_FIFO_SIZE);
3174         if (nsamples == 0)
3175                 return -1;
3176
3177         for (i = 0; i < nsamples; i++) {
3178                 writew(devpriv->ao_bounce_buffer[i],
3179                        devpriv->main_iobase + DAC_FIFO_REG);
3180         }
3181
3182         if (cmd->stop_src == TRIG_COUNT &&
3183             s->async->scans_done >= cmd->stop_arg)
3184                 return 0;
3185
3186         nbytes = load_ao_dma_buffer(dev, cmd);
3187         if (nbytes == 0)
3188                 return -1;
3189         load_ao_dma(dev, cmd);
3190
3191         dma_start_sync(dev, 0);
3192
3193         return 0;
3194 }
3195
3196 static inline int external_ai_queue_in_use(struct comedi_device *dev,
3197                                            struct comedi_subdevice *s,
3198                                            struct comedi_cmd *cmd)
3199 {
3200         const struct pcidas64_board *thisboard = dev->board_ptr;
3201
3202         if (s->busy)
3203                 return 0;
3204         if (thisboard->layout == LAYOUT_4020)
3205                 return 0;
3206         else if (use_internal_queue_6xxx(cmd))
3207                 return 0;
3208         return 1;
3209 }
3210
3211 static int ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3212                       unsigned int trig_num)
3213 {
3214         struct pcidas64_private *devpriv = dev->private;
3215         struct comedi_cmd *cmd = &s->async->cmd;
3216         int retval;
3217
3218         if (trig_num != cmd->start_arg)
3219                 return -EINVAL;
3220
3221         retval = prep_ao_dma(dev, cmd);
3222         if (retval < 0)
3223                 return -EPIPE;
3224
3225         set_dac_control0_reg(dev, cmd);
3226
3227         if (cmd->start_src == TRIG_INT)
3228                 writew(0, devpriv->main_iobase + DAC_START_REG);
3229
3230         s->async->inttrig = NULL;
3231
3232         return 0;
3233 }
3234
3235 static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3236 {
3237         struct pcidas64_private *devpriv = dev->private;
3238         struct comedi_cmd *cmd = &s->async->cmd;
3239
3240         if (external_ai_queue_in_use(dev, s, cmd)) {
3241                 warn_external_queue(dev);
3242                 return -EBUSY;
3243         }
3244         /* disable analog output system during setup */
3245         writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3246
3247         devpriv->ao_dma_index = 0;
3248
3249         set_dac_select_reg(dev, cmd);
3250         set_dac_interval_regs(dev, cmd);
3251         load_first_dma_descriptor(dev, 0, devpriv->ao_dma_desc_bus_addr |
3252                                   PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT);
3253
3254         set_dac_control1_reg(dev, cmd);
3255         s->async->inttrig = ao_inttrig;
3256
3257         return 0;
3258 }
3259
3260 static int cb_pcidas64_ao_check_chanlist(struct comedi_device *dev,
3261                                          struct comedi_subdevice *s,
3262                                          struct comedi_cmd *cmd)
3263 {
3264         unsigned int chan0 = CR_CHAN(cmd->chanlist[0]);
3265         int i;
3266
3267         for (i = 1; i < cmd->chanlist_len; i++) {
3268                 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3269
3270                 if (chan != (chan0 + i)) {
3271                         dev_dbg(dev->class_dev,
3272                                 "chanlist must use consecutive channels\n");
3273                         return -EINVAL;
3274                 }
3275         }
3276
3277         return 0;
3278 }
3279
3280 static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3281                       struct comedi_cmd *cmd)
3282 {
3283         const struct pcidas64_board *thisboard = dev->board_ptr;
3284         int err = 0;
3285         unsigned int tmp_arg;
3286
3287         /* Step 1 : check if triggers are trivially valid */
3288
3289         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3290         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
3291                                      TRIG_TIMER | TRIG_EXT);
3292         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3293         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3294         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3295
3296         if (err)
3297                 return 1;
3298
3299         /* Step 2a : make sure trigger sources are unique */
3300
3301         err |= cfc_check_trigger_is_unique(cmd->start_src);
3302         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
3303
3304         /* Step 2b : and mutually compatible */
3305
3306         if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
3307                 err |= -EINVAL;
3308         if (cmd->stop_src != TRIG_COUNT &&
3309             cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
3310                 err |= -EINVAL;
3311
3312         if (err)
3313                 return 2;
3314
3315         /* Step 3: check if arguments are trivially valid */
3316
3317         err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3318
3319         if (cmd->scan_begin_src == TRIG_TIMER) {
3320                 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
3321                                                  thisboard->ao_scan_speed);
3322                 if (get_ao_divisor(cmd->scan_begin_arg, cmd->flags) >
3323                     max_counter_value) {
3324                         cmd->scan_begin_arg = (max_counter_value + 2) *
3325                                               TIMER_BASE;
3326                         err |= -EINVAL;
3327                 }
3328         }
3329
3330         err |= cfc_check_trigger_arg_min(&cmd->chanlist_len, 1);
3331         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3332
3333         if (err)
3334                 return 3;
3335
3336         /* step 4: fix up any arguments */
3337
3338         if (cmd->scan_begin_src == TRIG_TIMER) {
3339                 tmp_arg = cmd->scan_begin_arg;
3340                 cmd->scan_begin_arg = get_divisor(cmd->scan_begin_arg,
3341                                                   cmd->flags) * TIMER_BASE;
3342                 if (tmp_arg != cmd->scan_begin_arg)
3343                         err++;
3344         }
3345
3346         if (err)
3347                 return 4;
3348
3349         /* Step 5: check channel list if it exists */
3350         if (cmd->chanlist && cmd->chanlist_len > 0)
3351                 err |= cb_pcidas64_ao_check_chanlist(dev, s, cmd);
3352
3353         if (err)
3354                 return 5;
3355
3356         return 0;
3357 }
3358
3359 static int ao_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3360 {
3361         struct pcidas64_private *devpriv = dev->private;
3362
3363         writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3364         abort_dma(dev, 0);
3365         return 0;
3366 }
3367
3368 static int dio_callback_4020(struct comedi_device *dev,
3369                              int dir, int port, int data, unsigned long iobase)
3370 {
3371         struct pcidas64_private *devpriv = dev->private;
3372
3373         if (dir) {
3374                 writew(data, devpriv->main_iobase + iobase + 2 * port);
3375                 return 0;
3376         }
3377         return readw(devpriv->main_iobase + iobase + 2 * port);
3378 }
3379
3380 static int di_rbits(struct comedi_device *dev, struct comedi_subdevice *s,
3381                     struct comedi_insn *insn, unsigned int *data)
3382 {
3383         unsigned int bits;
3384
3385         bits = readb(dev->mmio + DI_REG);
3386         bits &= 0xf;
3387         data[1] = bits;
3388         data[0] = 0;
3389
3390         return insn->n;
3391 }
3392
3393 static int do_wbits(struct comedi_device *dev,
3394                     struct comedi_subdevice *s,
3395                     struct comedi_insn *insn,
3396                     unsigned int *data)
3397 {
3398         if (comedi_dio_update_state(s, data))
3399                 writeb(s->state, dev->mmio + DO_REG);
3400
3401         data[1] = s->state;
3402
3403         return insn->n;
3404 }
3405
3406 static int dio_60xx_config_insn(struct comedi_device *dev,
3407                                 struct comedi_subdevice *s,
3408                                 struct comedi_insn *insn,
3409                                 unsigned int *data)
3410 {
3411         int ret;
3412
3413         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3414         if (ret)
3415                 return ret;
3416
3417         writeb(s->io_bits, dev->mmio + DIO_DIRECTION_60XX_REG);
3418
3419         return insn->n;
3420 }
3421
3422 static int dio_60xx_wbits(struct comedi_device *dev,
3423                           struct comedi_subdevice *s,
3424                           struct comedi_insn *insn,
3425                           unsigned int *data)
3426 {
3427         if (comedi_dio_update_state(s, data))
3428                 writeb(s->state, dev->mmio + DIO_DATA_60XX_REG);
3429
3430         data[1] = readb(dev->mmio + DIO_DATA_60XX_REG);
3431
3432         return insn->n;
3433 }
3434
3435 /* pci-6025 8800 caldac:
3436  * address 0 == dac channel 0 offset
3437  * address 1 == dac channel 0 gain
3438  * address 2 == dac channel 1 offset
3439  * address 3 == dac channel 1 gain
3440  * address 4 == fine adc offset
3441  * address 5 == coarse adc offset
3442  * address 6 == coarse adc gain
3443  * address 7 == fine adc gain
3444  */
3445 /* pci-6402/16 uses all 8 channels for dac:
3446  * address 0 == dac channel 0 fine gain
3447  * address 1 == dac channel 0 coarse gain
3448  * address 2 == dac channel 0 coarse offset
3449  * address 3 == dac channel 1 coarse offset
3450  * address 4 == dac channel 1 fine gain
3451  * address 5 == dac channel 1 coarse gain
3452  * address 6 == dac channel 0 fine offset
3453  * address 7 == dac channel 1 fine offset
3454 */
3455
3456 static int caldac_8800_write(struct comedi_device *dev, unsigned int address,
3457                              uint8_t value)
3458 {
3459         struct pcidas64_private *devpriv = dev->private;
3460         static const int num_caldac_channels = 8;
3461         static const int bitstream_length = 11;
3462         unsigned int bitstream = ((address & 0x7) << 8) | value;
3463         unsigned int bit, register_bits;
3464         static const int caldac_8800_udelay = 1;
3465
3466         if (address >= num_caldac_channels) {
3467                 dev_err(dev->class_dev, "illegal caldac channel\n");
3468                 return -1;
3469         }
3470         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3471                 register_bits = 0;
3472                 if (bitstream & bit)
3473                         register_bits |= SERIAL_DATA_IN_BIT;
3474                 udelay(caldac_8800_udelay);
3475                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3476                 register_bits |= SERIAL_CLOCK_BIT;
3477                 udelay(caldac_8800_udelay);
3478                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3479         }
3480         udelay(caldac_8800_udelay);
3481         writew(SELECT_8800_BIT, devpriv->main_iobase + CALIBRATION_REG);
3482         udelay(caldac_8800_udelay);
3483         writew(0, devpriv->main_iobase + CALIBRATION_REG);
3484         udelay(caldac_8800_udelay);
3485         return 0;
3486 }
3487
3488 /* 4020 caldacs */
3489 static int caldac_i2c_write(struct comedi_device *dev,
3490                             unsigned int caldac_channel, unsigned int value)
3491 {
3492         uint8_t serial_bytes[3];
3493         uint8_t i2c_addr;
3494         enum pointer_bits {
3495                 /*  manual has gain and offset bits switched */
3496                 OFFSET_0_2 = 0x1,
3497                 GAIN_0_2 = 0x2,
3498                 OFFSET_1_3 = 0x4,
3499                 GAIN_1_3 = 0x8,
3500         };
3501         enum data_bits {
3502                 NOT_CLEAR_REGISTERS = 0x20,
3503         };
3504
3505         switch (caldac_channel) {
3506         case 0:         /*  chan 0 offset */
3507                 i2c_addr = CALDAC0_I2C_ADDR;
3508                 serial_bytes[0] = OFFSET_0_2;
3509                 break;
3510         case 1:         /*  chan 1 offset */
3511                 i2c_addr = CALDAC0_I2C_ADDR;
3512                 serial_bytes[0] = OFFSET_1_3;
3513                 break;
3514         case 2:         /*  chan 2 offset */
3515                 i2c_addr = CALDAC1_I2C_ADDR;
3516                 serial_bytes[0] = OFFSET_0_2;
3517                 break;
3518         case 3:         /*  chan 3 offset */
3519                 i2c_addr = CALDAC1_I2C_ADDR;
3520                 serial_bytes[0] = OFFSET_1_3;
3521                 break;
3522         case 4:         /*  chan 0 gain */
3523                 i2c_addr = CALDAC0_I2C_ADDR;
3524                 serial_bytes[0] = GAIN_0_2;
3525                 break;
3526         case 5:         /*  chan 1 gain */
3527                 i2c_addr = CALDAC0_I2C_ADDR;
3528                 serial_bytes[0] = GAIN_1_3;
3529                 break;
3530         case 6:         /*  chan 2 gain */
3531                 i2c_addr = CALDAC1_I2C_ADDR;
3532                 serial_bytes[0] = GAIN_0_2;
3533                 break;
3534         case 7:         /*  chan 3 gain */
3535                 i2c_addr = CALDAC1_I2C_ADDR;
3536                 serial_bytes[0] = GAIN_1_3;
3537                 break;
3538         default:
3539                 dev_err(dev->class_dev, "invalid caldac channel\n");
3540                 return -1;
3541         }
3542         serial_bytes[1] = NOT_CLEAR_REGISTERS | ((value >> 8) & 0xf);
3543         serial_bytes[2] = value & 0xff;
3544         i2c_write(dev, i2c_addr, serial_bytes, 3);
3545         return 0;
3546 }
3547
3548 static void caldac_write(struct comedi_device *dev, unsigned int channel,
3549                          unsigned int value)
3550 {
3551         const struct pcidas64_board *thisboard = dev->board_ptr;
3552
3553         switch (thisboard->layout) {
3554         case LAYOUT_60XX:
3555         case LAYOUT_64XX:
3556                 caldac_8800_write(dev, channel, value);
3557                 break;
3558         case LAYOUT_4020:
3559                 caldac_i2c_write(dev, channel, value);
3560                 break;
3561         default:
3562                 break;
3563         }
3564 }
3565
3566 static int calib_write_insn(struct comedi_device *dev,
3567                             struct comedi_subdevice *s,
3568                             struct comedi_insn *insn, unsigned int *data)
3569 {
3570         int channel = CR_CHAN(insn->chanspec);
3571
3572         /* return immediately if setting hasn't changed, since
3573          * programming these things is slow */
3574         if (s->readback[channel] == data[0])
3575                 return 1;
3576
3577         caldac_write(dev, channel, data[0]);
3578         s->readback[channel] = data[0];
3579
3580         return 1;
3581 }
3582
3583 static void ad8402_write(struct comedi_device *dev, unsigned int channel,
3584                          unsigned int value)
3585 {
3586         struct pcidas64_private *devpriv = dev->private;
3587         static const int bitstream_length = 10;
3588         unsigned int bit, register_bits;
3589         unsigned int bitstream = ((channel & 0x3) << 8) | (value & 0xff);
3590         static const int ad8402_udelay = 1;
3591
3592         devpriv->ad8402_state[channel] = value;
3593
3594         register_bits = SELECT_8402_64XX_BIT;
3595         udelay(ad8402_udelay);
3596         writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3597
3598         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3599                 if (bitstream & bit)
3600                         register_bits |= SERIAL_DATA_IN_BIT;
3601                 else
3602                         register_bits &= ~SERIAL_DATA_IN_BIT;
3603                 udelay(ad8402_udelay);
3604                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3605                 udelay(ad8402_udelay);
3606                 writew(register_bits | SERIAL_CLOCK_BIT,
3607                        devpriv->main_iobase + CALIBRATION_REG);
3608         }
3609
3610         udelay(ad8402_udelay);
3611         writew(0, devpriv->main_iobase + CALIBRATION_REG);
3612 }
3613
3614 /* for pci-das6402/16, channel 0 is analog input gain and channel 1 is offset */
3615 static int ad8402_write_insn(struct comedi_device *dev,
3616                              struct comedi_subdevice *s,
3617                              struct comedi_insn *insn, unsigned int *data)
3618 {
3619         struct pcidas64_private *devpriv = dev->private;
3620         int channel = CR_CHAN(insn->chanspec);
3621
3622         /* return immediately if setting hasn't changed, since
3623          * programming these things is slow */
3624         if (devpriv->ad8402_state[channel] == data[0])
3625                 return 1;
3626
3627         devpriv->ad8402_state[channel] = data[0];
3628
3629         ad8402_write(dev, channel, data[0]);
3630
3631         return 1;
3632 }
3633
3634 static int ad8402_read_insn(struct comedi_device *dev,
3635                             struct comedi_subdevice *s,
3636                             struct comedi_insn *insn, unsigned int *data)
3637 {
3638         struct pcidas64_private *devpriv = dev->private;
3639         unsigned int channel = CR_CHAN(insn->chanspec);
3640
3641         data[0] = devpriv->ad8402_state[channel];
3642
3643         return 1;
3644 }
3645
3646 static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address)
3647 {
3648         struct pcidas64_private *devpriv = dev->private;
3649         static const int bitstream_length = 11;
3650         static const int read_command = 0x6;
3651         unsigned int bitstream = (read_command << 8) | address;
3652         unsigned int bit;
3653         void __iomem * const plx_control_addr =
3654                 devpriv->plx9080_iobase + PLX_CONTROL_REG;
3655         uint16_t value;
3656         static const int value_length = 16;
3657         static const int eeprom_udelay = 1;
3658
3659         udelay(eeprom_udelay);
3660         devpriv->plx_control_bits &= ~CTL_EE_CLK & ~CTL_EE_CS;
3661         /*  make sure we don't send anything to the i2c bus on 4020 */
3662         devpriv->plx_control_bits |= CTL_USERO;
3663         writel(devpriv->plx_control_bits, plx_control_addr);
3664         /*  activate serial eeprom */
3665         udelay(eeprom_udelay);
3666         devpriv->plx_control_bits |= CTL_EE_CS;
3667         writel(devpriv->plx_control_bits, plx_control_addr);
3668
3669         /*  write read command and desired memory address */
3670         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3671                 /*  set bit to be written */
3672                 udelay(eeprom_udelay);
3673                 if (bitstream & bit)
3674                         devpriv->plx_control_bits |= CTL_EE_W;
3675                 else
3676                         devpriv->plx_control_bits &= ~CTL_EE_W;
3677                 writel(devpriv->plx_control_bits, plx_control_addr);
3678                 /*  clock in bit */
3679                 udelay(eeprom_udelay);
3680                 devpriv->plx_control_bits |= CTL_EE_CLK;
3681                 writel(devpriv->plx_control_bits, plx_control_addr);
3682                 udelay(eeprom_udelay);
3683                 devpriv->plx_control_bits &= ~CTL_EE_CLK;
3684                 writel(devpriv->plx_control_bits, plx_control_addr);
3685         }
3686         /*  read back value from eeprom memory location */
3687         value = 0;
3688         for (bit = 1 << (value_length - 1); bit; bit >>= 1) {
3689                 /*  clock out bit */
3690                 udelay(eeprom_udelay);
3691                 devpriv->plx_control_bits |= CTL_EE_CLK;
3692                 writel(devpriv->plx_control_bits, plx_control_addr);
3693                 udelay(eeprom_udelay);
3694                 devpriv->plx_control_bits &= ~CTL_EE_CLK;
3695                 writel(devpriv->plx_control_bits, plx_control_addr);
3696                 udelay(eeprom_udelay);
3697                 if (readl(plx_control_addr) & CTL_EE_R)
3698                         value |= bit;
3699         }
3700
3701         /*  deactivate eeprom serial input */
3702         udelay(eeprom_udelay);
3703         devpriv->plx_control_bits &= ~CTL_EE_CS;
3704         writel(devpriv->plx_control_bits, plx_control_addr);
3705
3706         return value;
3707 }
3708
3709 static int eeprom_read_insn(struct comedi_device *dev,
3710                             struct comedi_subdevice *s,
3711                             struct comedi_insn *insn, unsigned int *data)
3712 {
3713         data[0] = read_eeprom(dev, CR_CHAN(insn->chanspec));
3714
3715         return 1;
3716 }
3717
3718 /* Allocate and initialize the subdevice structures.
3719  */
3720 static int setup_subdevices(struct comedi_device *dev)
3721 {
3722         const struct pcidas64_board *thisboard = dev->board_ptr;
3723         struct pcidas64_private *devpriv = dev->private;
3724         struct comedi_subdevice *s;
3725         int i;
3726         int ret;
3727
3728         ret = comedi_alloc_subdevices(dev, 10);
3729         if (ret)
3730                 return ret;
3731
3732         s = &dev->subdevices[0];
3733         /* analog input subdevice */
3734         dev->read_subdev = s;
3735         s->type = COMEDI_SUBD_AI;
3736         s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DITHER | SDF_CMD_READ;
3737         if (thisboard->layout == LAYOUT_60XX)
3738                 s->subdev_flags |= SDF_COMMON | SDF_DIFF;
3739         else if (thisboard->layout == LAYOUT_64XX)
3740                 s->subdev_flags |= SDF_DIFF;
3741         /* XXX Number of inputs in differential mode is ignored */
3742         s->n_chan = thisboard->ai_se_chans;
3743         s->len_chanlist = 0x2000;
3744         s->maxdata = (1 << thisboard->ai_bits) - 1;
3745         s->range_table = thisboard->ai_range_table;
3746         s->insn_read = ai_rinsn;
3747         s->insn_config = ai_config_insn;
3748         s->do_cmd = ai_cmd;
3749         s->do_cmdtest = ai_cmdtest;
3750         s->cancel = ai_cancel;
3751         if (thisboard->layout == LAYOUT_4020) {
3752                 uint8_t data;
3753                 /*  set adc to read from inputs
3754                  *  (not internal calibration sources) */
3755                 devpriv->i2c_cal_range_bits = adc_src_4020_bits(4);
3756                 /*  set channels to +-5 volt input ranges */
3757                 for (i = 0; i < s->n_chan; i++)
3758                         devpriv->i2c_cal_range_bits |= attenuate_bit(i);
3759                 data = devpriv->i2c_cal_range_bits;
3760                 i2c_write(dev, RANGE_CAL_I2C_ADDR, &data, sizeof(data));
3761         }
3762
3763         /* analog output subdevice */
3764         s = &dev->subdevices[1];
3765         if (thisboard->ao_nchan) {
3766                 s->type = COMEDI_SUBD_AO;
3767                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE |
3768                                   SDF_GROUND | SDF_CMD_WRITE;
3769                 s->n_chan = thisboard->ao_nchan;
3770                 s->maxdata = (1 << thisboard->ao_bits) - 1;
3771                 s->range_table = thisboard->ao_range_table;
3772                 s->insn_write = ao_winsn;
3773
3774                 ret = comedi_alloc_subdev_readback(s);
3775                 if (ret)
3776                         return ret;
3777
3778                 if (ao_cmd_is_supported(thisboard)) {
3779                         dev->write_subdev = s;
3780                         s->do_cmdtest = ao_cmdtest;
3781                         s->do_cmd = ao_cmd;
3782                         s->len_chanlist = thisboard->ao_nchan;
3783                         s->cancel = ao_cancel;
3784                 }
3785         } else {
3786                 s->type = COMEDI_SUBD_UNUSED;
3787         }
3788
3789         /*  digital input */
3790         s = &dev->subdevices[2];
3791         if (thisboard->layout == LAYOUT_64XX) {
3792                 s->type = COMEDI_SUBD_DI;
3793                 s->subdev_flags = SDF_READABLE;
3794                 s->n_chan = 4;
3795                 s->maxdata = 1;
3796                 s->range_table = &range_digital;
3797                 s->insn_bits = di_rbits;
3798         } else
3799                 s->type = COMEDI_SUBD_UNUSED;
3800
3801         /*  digital output */
3802         if (thisboard->layout == LAYOUT_64XX) {
3803                 s = &dev->subdevices[3];
3804                 s->type = COMEDI_SUBD_DO;
3805                 s->subdev_flags = SDF_WRITABLE;
3806                 s->n_chan = 4;
3807                 s->maxdata = 1;
3808                 s->range_table = &range_digital;
3809                 s->insn_bits = do_wbits;
3810         } else
3811                 s->type = COMEDI_SUBD_UNUSED;
3812
3813         /* 8255 */
3814         s = &dev->subdevices[4];
3815         if (thisboard->has_8255) {
3816                 if (thisboard->layout == LAYOUT_4020) {
3817                         ret = subdev_8255_init(dev, s, dio_callback_4020,
3818                                                I8255_4020_REG);
3819                 } else {
3820                         ret = subdev_8255_mm_init(dev, s, NULL,
3821                                                   DIO_8255_OFFSET);
3822                 }
3823                 if (ret)
3824                         return ret;
3825         } else {
3826                 s->type = COMEDI_SUBD_UNUSED;
3827         }
3828
3829         /*  8 channel dio for 60xx */
3830         s = &dev->subdevices[5];
3831         if (thisboard->layout == LAYOUT_60XX) {
3832                 s->type = COMEDI_SUBD_DIO;
3833                 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
3834                 s->n_chan = 8;
3835                 s->maxdata = 1;
3836                 s->range_table = &range_digital;
3837                 s->insn_config = dio_60xx_config_insn;
3838                 s->insn_bits = dio_60xx_wbits;
3839         } else
3840                 s->type = COMEDI_SUBD_UNUSED;
3841
3842         /*  caldac */
3843         s = &dev->subdevices[6];
3844         s->type = COMEDI_SUBD_CALIB;
3845         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3846         s->n_chan = 8;
3847         if (thisboard->layout == LAYOUT_4020)
3848                 s->maxdata = 0xfff;
3849         else
3850                 s->maxdata = 0xff;
3851         s->insn_write = calib_write_insn;
3852
3853         ret = comedi_alloc_subdev_readback(s);
3854         if (ret)
3855                 return ret;
3856
3857         for (i = 0; i < s->n_chan; i++) {
3858                 caldac_write(dev, i, s->maxdata / 2);
3859                 s->readback[i] = s->maxdata / 2;
3860         }
3861
3862         /*  2 channel ad8402 potentiometer */
3863         s = &dev->subdevices[7];
3864         if (thisboard->layout == LAYOUT_64XX) {
3865                 s->type = COMEDI_SUBD_CALIB;
3866                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3867                 s->n_chan = 2;
3868                 s->insn_read = ad8402_read_insn;
3869                 s->insn_write = ad8402_write_insn;
3870                 s->maxdata = 0xff;
3871                 for (i = 0; i < s->n_chan; i++)
3872                         ad8402_write(dev, i, s->maxdata / 2);
3873         } else
3874                 s->type = COMEDI_SUBD_UNUSED;
3875
3876         /* serial EEPROM, if present */
3877         s = &dev->subdevices[8];
3878         if (readl(devpriv->plx9080_iobase + PLX_CONTROL_REG) & CTL_EECHK) {
3879                 s->type = COMEDI_SUBD_MEMORY;
3880                 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
3881                 s->n_chan = 128;
3882                 s->maxdata = 0xffff;
3883                 s->insn_read = eeprom_read_insn;
3884         } else
3885                 s->type = COMEDI_SUBD_UNUSED;
3886
3887         /*  user counter subd XXX */
3888         s = &dev->subdevices[9];
3889         s->type = COMEDI_SUBD_UNUSED;
3890
3891         return 0;
3892 }
3893
3894 static int auto_attach(struct comedi_device *dev,
3895                        unsigned long context)
3896 {
3897         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
3898         const struct pcidas64_board *thisboard = NULL;
3899         struct pcidas64_private *devpriv;
3900         uint32_t local_range, local_decode;
3901         int retval;
3902
3903         if (context < ARRAY_SIZE(pcidas64_boards))
3904                 thisboard = &pcidas64_boards[context];
3905         if (!thisboard)
3906                 return -ENODEV;
3907         dev->board_ptr = thisboard;
3908
3909         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
3910         if (!devpriv)
3911                 return -ENOMEM;
3912
3913         retval = comedi_pci_enable(dev);
3914         if (retval)
3915                 return retval;
3916         pci_set_master(pcidev);
3917
3918         /* Initialize dev->board_name */
3919         dev->board_name = thisboard->name;
3920
3921         devpriv->main_phys_iobase = pci_resource_start(pcidev, 2);
3922         devpriv->dio_counter_phys_iobase = pci_resource_start(pcidev, 3);
3923
3924         devpriv->plx9080_iobase = pci_ioremap_bar(pcidev, 0);
3925         devpriv->main_iobase = pci_ioremap_bar(pcidev, 2);
3926         dev->mmio = pci_ioremap_bar(pcidev, 3);
3927
3928         if (!devpriv->plx9080_iobase || !devpriv->main_iobase || !dev->mmio) {
3929                 dev_warn(dev->class_dev, "failed to remap io memory\n");
3930                 return -ENOMEM;
3931         }
3932
3933         /*  figure out what local addresses are */
3934         local_range = readl(devpriv->plx9080_iobase + PLX_LAS0RNG_REG) &
3935                       LRNG_MEM_MASK;
3936         local_decode = readl(devpriv->plx9080_iobase + PLX_LAS0MAP_REG) &
3937                        local_range & LMAP_MEM_MASK;
3938         devpriv->local0_iobase = ((uint32_t)devpriv->main_phys_iobase &
3939                                   ~local_range) | local_decode;
3940         local_range = readl(devpriv->plx9080_iobase + PLX_LAS1RNG_REG) &
3941                       LRNG_MEM_MASK;
3942         local_decode = readl(devpriv->plx9080_iobase + PLX_LAS1MAP_REG) &
3943                        local_range & LMAP_MEM_MASK;
3944         devpriv->local1_iobase = ((uint32_t)devpriv->dio_counter_phys_iobase &
3945                                   ~local_range) | local_decode;
3946
3947         retval = alloc_and_init_dma_members(dev);
3948         if (retval < 0)
3949                 return retval;
3950
3951         devpriv->hw_revision =
3952                 hw_revision(dev, readw(devpriv->main_iobase + HW_STATUS_REG));
3953         dev_dbg(dev->class_dev, "stc hardware revision %i\n",
3954                 devpriv->hw_revision);
3955         init_plx9080(dev);
3956         init_stc_registers(dev);
3957
3958         retval = request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
3959                              dev->board_name, dev);
3960         if (retval) {
3961                 dev_dbg(dev->class_dev, "unable to allocate irq %u\n",
3962                         pcidev->irq);
3963                 return retval;
3964         }
3965         dev->irq = pcidev->irq;
3966         dev_dbg(dev->class_dev, "irq %u\n", dev->irq);
3967
3968         retval = setup_subdevices(dev);
3969         if (retval < 0)
3970                 return retval;
3971
3972         return 0;
3973 }
3974
3975 static void detach(struct comedi_device *dev)
3976 {
3977         struct pcidas64_private *devpriv = dev->private;
3978
3979         if (dev->irq)
3980                 free_irq(dev->irq, dev);
3981         if (devpriv) {
3982                 if (devpriv->plx9080_iobase) {
3983                         disable_plx_interrupts(dev);
3984                         iounmap(devpriv->plx9080_iobase);
3985                 }
3986                 if (devpriv->main_iobase)
3987                         iounmap(devpriv->main_iobase);
3988                 if (dev->mmio)
3989                         iounmap(dev->mmio);
3990         }
3991         comedi_pci_disable(dev);
3992         cb_pcidas64_free_dma(dev);
3993 }
3994
3995 static struct comedi_driver cb_pcidas64_driver = {
3996         .driver_name    = "cb_pcidas64",
3997         .module         = THIS_MODULE,
3998         .auto_attach    = auto_attach,
3999         .detach         = detach,
4000 };
4001
4002 static int cb_pcidas64_pci_probe(struct pci_dev *dev,
4003                                  const struct pci_device_id *id)
4004 {
4005         return comedi_pci_auto_config(dev, &cb_pcidas64_driver,
4006                                       id->driver_data);
4007 }
4008
4009 static const struct pci_device_id cb_pcidas64_pci_table[] = {
4010         { PCI_VDEVICE(CB, 0x001d), BOARD_PCIDAS6402_16 },
4011         { PCI_VDEVICE(CB, 0x001e), BOARD_PCIDAS6402_12 },
4012         { PCI_VDEVICE(CB, 0x0035), BOARD_PCIDAS64_M1_16 },
4013         { PCI_VDEVICE(CB, 0x0036), BOARD_PCIDAS64_M2_16 },
4014         { PCI_VDEVICE(CB, 0x0037), BOARD_PCIDAS64_M3_16 },
4015         { PCI_VDEVICE(CB, 0x0052), BOARD_PCIDAS4020_12 },
4016         { PCI_VDEVICE(CB, 0x005d), BOARD_PCIDAS6023 },
4017         { PCI_VDEVICE(CB, 0x005e), BOARD_PCIDAS6025 },
4018         { PCI_VDEVICE(CB, 0x005f), BOARD_PCIDAS6030 },
4019         { PCI_VDEVICE(CB, 0x0060), BOARD_PCIDAS6031 },
4020         { PCI_VDEVICE(CB, 0x0061), BOARD_PCIDAS6032 },
4021         { PCI_VDEVICE(CB, 0x0062), BOARD_PCIDAS6033 },
4022         { PCI_VDEVICE(CB, 0x0063), BOARD_PCIDAS6034 },
4023         { PCI_VDEVICE(CB, 0x0064), BOARD_PCIDAS6035 },
4024         { PCI_VDEVICE(CB, 0x0065), BOARD_PCIDAS6040 },
4025         { PCI_VDEVICE(CB, 0x0066), BOARD_PCIDAS6052 },
4026         { PCI_VDEVICE(CB, 0x0067), BOARD_PCIDAS6070 },
4027         { PCI_VDEVICE(CB, 0x0068), BOARD_PCIDAS6071 },
4028         { PCI_VDEVICE(CB, 0x006f), BOARD_PCIDAS6036 },
4029         { PCI_VDEVICE(CB, 0x0078), BOARD_PCIDAS6013 },
4030         { PCI_VDEVICE(CB, 0x0079), BOARD_PCIDAS6014 },
4031         { 0 }
4032 };
4033 MODULE_DEVICE_TABLE(pci, cb_pcidas64_pci_table);
4034
4035 static struct pci_driver cb_pcidas64_pci_driver = {
4036         .name           = "cb_pcidas64",
4037         .id_table       = cb_pcidas64_pci_table,
4038         .probe          = cb_pcidas64_pci_probe,
4039         .remove         = comedi_pci_auto_unconfig,
4040 };
4041 module_comedi_pci_driver(cb_pcidas64_driver, cb_pcidas64_pci_driver);
4042
4043 MODULE_AUTHOR("Comedi http://www.comedi.org");
4044 MODULE_DESCRIPTION("Comedi low-level driver");
4045 MODULE_LICENSE("GPL");