2 comedi/drivers/cb_pcidas64.c
3 This is a driver for the ComputerBoards/MeasurementComputing PCI-DAS
4 64xx, 60xx, and 4020 cards.
6 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
7 Copyright (C) 2001, 2002 Frank Mori Hess
9 Thanks also go to the following people:
11 Steve Rosenbluth, for providing the source code for
12 his pci-das6402 driver, and source code for working QNX pci-6402
13 drivers by Greg Laird and Mariusz Bogacz. None of the code was
14 used directly here, but it was useful as an additional source of
15 documentation on how to program the boards.
17 John Sims, for much testing and feedback on pcidas-4020 support.
19 COMEDI - Linux Control and Measurement Device Interface
20 Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
22 This program is free software; you can redistribute it and/or modify
23 it under the terms of the GNU General Public License as published by
24 the Free Software Foundation; either version 2 of the License, or
25 (at your option) any later version.
27 This program is distributed in the hope that it will be useful,
28 but WITHOUT ANY WARRANTY; without even the implied warranty of
29 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 GNU General Public License for more details.
32 You should have received a copy of the GNU General Public License
33 along with this program; if not, write to the Free Software
34 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
36 ************************************************************************/
40 * Description: MeasurementComputing PCI-DAS64xx, 60XX, and 4020 series
41 * with the PLX 9080 PCI controller
42 * Author: Frank Mori Hess <fmhess@users.sourceforge.net>
44 * Updated: Fri, 02 Nov 2012 18:58:55 +0000
45 * Devices: [Measurement Computing] PCI-DAS6402/16 (cb_pcidas64),
46 * PCI-DAS6402/12, PCI-DAS64/M1/16, PCI-DAS64/M2/16,
47 * PCI-DAS64/M3/16, PCI-DAS6402/16/JR, PCI-DAS64/M1/16/JR,
48 * PCI-DAS64/M2/16/JR, PCI-DAS64/M3/16/JR, PCI-DAS64/M1/14,
49 * PCI-DAS64/M2/14, PCI-DAS64/M3/14, PCI-DAS6013, PCI-DAS6014,
50 * PCI-DAS6023, PCI-DAS6025, PCI-DAS6030,
51 * PCI-DAS6031, PCI-DAS6032, PCI-DAS6033, PCI-DAS6034,
52 * PCI-DAS6035, PCI-DAS6036, PCI-DAS6040, PCI-DAS6052,
53 * PCI-DAS6070, PCI-DAS6071, PCI-DAS4020/12
55 * Configuration options:
58 * Manual attachment of PCI cards with the comedi_config utility is not
59 * supported by this driver; they are attached automatically.
61 * These boards may be autocalibrated with the comedi_calibrate utility.
63 * To select the bnc trigger input on the 4020 (instead of the dio input),
64 * specify a nonzero channel in the chanspec. If you wish to use an external
65 * master clock on the 4020, you may do so by setting the scan_begin_src
66 * to TRIG_OTHER, and using an INSN_CONFIG_TIMER_1 configuration insn
67 * to configure the divisor to use for the external clock.
69 * Some devices are not identified because the PCI device IDs are not yet
70 * known. If you have such a board, please let the maintainers know.
76 make it return error if user attempts an ai command that uses the
77 external queue, and an ao command simultaneously user counter subdevice
78 there are a number of boards this driver will support when they are
79 fully released, but does not yet since the pci device id numbers
80 are not yet available.
82 support prescaled 100khz clock for slow pacing (not available on 6000
85 make ao fifo size adjustable like ai fifo
88 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
90 #include <linux/pci.h>
91 #include <linux/delay.h>
92 #include <linux/interrupt.h>
94 #include "../comedidev.h"
99 #include "comedi_fc.h"
101 #undef PCIDAS64_DEBUG /* disable debugging code */
102 /* #define PCIDAS64_DEBUG enable debugging code */
104 #ifdef PCIDAS64_DEBUG
105 #define DEBUG_PRINT(format, args...) pr_debug(format, ## args)
107 #define DEBUG_PRINT(format, args...) no_printk(format, ## args)
110 #define TIMER_BASE 25 /* 40MHz master clock */
111 /* 100kHz 'prescaled' clock for slow acquisition,
112 * maybe I'll support this someday */
113 #define PRESCALED_TIMER_BASE 10000
114 #define DMA_BUFFER_SIZE 0x1000
116 /* maximum value that can be loaded into board's 24-bit counters*/
117 static const int max_counter_value = 0xffffff;
119 /* PCI-DAS64xxx base addresses */
121 /* devpriv->main_iobase registers */
122 enum write_only_registers {
123 INTR_ENABLE_REG = 0x0, /* interrupt enable register */
124 HW_CONFIG_REG = 0x2, /* hardware config register */
126 DAQ_ATRIG_LOW_4020_REG = 0xc,
127 ADC_CONTROL0_REG = 0x10, /* adc control register 0 */
128 ADC_CONTROL1_REG = 0x12, /* adc control register 1 */
129 CALIBRATION_REG = 0x14,
130 /* lower 16 bits of adc sample interval counter */
131 ADC_SAMPLE_INTERVAL_LOWER_REG = 0x16,
132 /* upper 8 bits of adc sample interval counter */
133 ADC_SAMPLE_INTERVAL_UPPER_REG = 0x18,
134 /* lower 16 bits of delay interval counter */
135 ADC_DELAY_INTERVAL_LOWER_REG = 0x1a,
136 /* upper 8 bits of delay interval counter */
137 ADC_DELAY_INTERVAL_UPPER_REG = 0x1c,
138 /* lower 16 bits of hardware conversion/scan counter */
139 ADC_COUNT_LOWER_REG = 0x1e,
140 /* upper 8 bits of hardware conversion/scan counter */
141 ADC_COUNT_UPPER_REG = 0x20,
142 ADC_START_REG = 0x22, /* software trigger to start acquisition */
143 ADC_CONVERT_REG = 0x24, /* initiates single conversion */
144 ADC_QUEUE_CLEAR_REG = 0x26, /* clears adc queue */
145 ADC_QUEUE_LOAD_REG = 0x28, /* loads adc queue */
146 ADC_BUFFER_CLEAR_REG = 0x2a,
147 /* high channel for internal queue, use adc_chan_bits() inline above */
148 ADC_QUEUE_HIGH_REG = 0x2c,
149 DAC_CONTROL0_REG = 0x50, /* dac control register 0 */
150 DAC_CONTROL1_REG = 0x52, /* dac control register 0 */
151 /* lower 16 bits of dac sample interval counter */
152 DAC_SAMPLE_INTERVAL_LOWER_REG = 0x54,
153 /* upper 8 bits of dac sample interval counter */
154 DAC_SAMPLE_INTERVAL_UPPER_REG = 0x56,
155 DAC_SELECT_REG = 0x60,
156 DAC_START_REG = 0x64,
157 DAC_BUFFER_CLEAR_REG = 0x66, /* clear dac buffer */
160 static inline unsigned int dac_convert_reg(unsigned int channel)
162 return 0x70 + (2 * (channel & 0x1));
165 static inline unsigned int dac_lsb_4020_reg(unsigned int channel)
167 return 0x70 + (4 * (channel & 0x1));
170 static inline unsigned int dac_msb_4020_reg(unsigned int channel)
172 return 0x72 + (4 * (channel & 0x1));
175 enum read_only_registers {
176 /* hardware status register,
177 * reading this apparently clears pending interrupts as well */
179 PIPE1_READ_REG = 0x4,
180 ADC_READ_PNTR_REG = 0x8,
181 LOWER_XFER_REG = 0x10,
182 ADC_WRITE_PNTR_REG = 0xc,
186 enum read_write_registers {
187 I8255_4020_REG = 0x48, /* 8255 offset, for 4020 only */
188 /* external channel/gain queue, uses same bits as ADC_QUEUE_LOAD_REG */
189 ADC_QUEUE_FIFO_REG = 0x100,
190 ADC_FIFO_REG = 0x200, /* adc data fifo */
191 /* dac data fifo, has weird interactions with external channel queue */
192 DAC_FIFO_REG = 0x300,
195 /* devpriv->dio_counter_iobase registers */
196 enum dio_counter_registers {
197 DIO_8255_OFFSET = 0x0,
200 DIO_DIRECTION_60XX_REG = 0x40,
201 DIO_DATA_60XX_REG = 0x48,
204 /* bit definitions for write-only registers */
206 enum intr_enable_contents {
207 ADC_INTR_SRC_MASK = 0x3, /* adc interrupt source mask */
208 ADC_INTR_QFULL_BITS = 0x0, /* interrupt fifo quarter full */
209 ADC_INTR_EOC_BITS = 0x1, /* interrupt end of conversion */
210 ADC_INTR_EOSCAN_BITS = 0x2, /* interrupt end of scan */
211 ADC_INTR_EOSEQ_BITS = 0x3, /* interrupt end of sequence mask */
212 EN_ADC_INTR_SRC_BIT = 0x4, /* enable adc interrupt source */
213 EN_ADC_DONE_INTR_BIT = 0x8, /* enable adc acquisition done intr */
214 DAC_INTR_SRC_MASK = 0x30,
215 DAC_INTR_QEMPTY_BITS = 0x0,
216 DAC_INTR_HIGH_CHAN_BITS = 0x10,
217 EN_DAC_INTR_SRC_BIT = 0x40, /* enable dac interrupt source */
218 EN_DAC_DONE_INTR_BIT = 0x80,
219 EN_ADC_ACTIVE_INTR_BIT = 0x200, /* enable adc active interrupt */
220 EN_ADC_STOP_INTR_BIT = 0x400, /* enable adc stop trigger interrupt */
221 EN_DAC_ACTIVE_INTR_BIT = 0x800, /* enable dac active interrupt */
222 EN_DAC_UNDERRUN_BIT = 0x4000, /* enable dac underrun status bit */
223 EN_ADC_OVERRUN_BIT = 0x8000, /* enable adc overrun status bit */
226 enum hw_config_contents {
227 MASTER_CLOCK_4020_MASK = 0x3, /* master clock source mask for 4020 */
228 INTERNAL_CLOCK_4020_BITS = 0x1, /* use 40 MHz internal master clock */
229 BNC_CLOCK_4020_BITS = 0x2, /* use BNC input for master clock */
230 EXT_CLOCK_4020_BITS = 0x3, /* use dio input for master clock */
231 EXT_QUEUE_BIT = 0x200, /* use external channel/gain queue */
232 /* use 225 nanosec strobe when loading dac instead of 50 nanosec */
233 SLOW_DAC_BIT = 0x400,
234 /* bit with unknown function yet given as default value in pci-das64
236 HW_CONFIG_DUMMY_BITS = 0x2000,
237 /* bit selects channels 1/0 for analog input/output, otherwise 0/1 */
238 DMA_CH_SELECT_BIT = 0x8000,
239 FIFO_SIZE_REG = 0x4, /* allows adjustment of fifo sizes */
240 DAC_FIFO_SIZE_MASK = 0xff00, /* bits that set dac fifo size */
241 DAC_FIFO_BITS = 0xf800, /* 8k sample ao fifo */
243 #define DAC_FIFO_SIZE 0x2000
245 enum daq_atrig_low_4020_contents {
246 /* use trig/ext clk bnc input for analog gate signal */
247 EXT_AGATE_BNC_BIT = 0x8000,
248 /* use trig/ext clk bnc input for external stop trigger signal */
249 EXT_STOP_TRIG_BNC_BIT = 0x4000,
250 /* use trig/ext clk bnc input for external start trigger signal */
251 EXT_START_TRIG_BNC_BIT = 0x2000,
254 static inline uint16_t analog_trig_low_threshold_bits(uint16_t threshold)
256 return threshold & 0xfff;
259 enum adc_control0_contents {
260 ADC_GATE_SRC_MASK = 0x3, /* bits that select gate */
261 ADC_SOFT_GATE_BITS = 0x1, /* software gate */
262 ADC_EXT_GATE_BITS = 0x2, /* external digital gate */
263 ADC_ANALOG_GATE_BITS = 0x3, /* analog level gate */
264 ADC_GATE_LEVEL_BIT = 0x4, /* level-sensitive gate (for digital) */
265 ADC_GATE_POLARITY_BIT = 0x8, /* gate active low */
266 ADC_START_TRIG_SOFT_BITS = 0x10,
267 ADC_START_TRIG_EXT_BITS = 0x20,
268 ADC_START_TRIG_ANALOG_BITS = 0x30,
269 ADC_START_TRIG_MASK = 0x30,
270 ADC_START_TRIG_FALLING_BIT = 0x40, /* trig 1 uses falling edge */
271 /* external pacing uses falling edge */
272 ADC_EXT_CONV_FALLING_BIT = 0x800,
273 /* enable hardware scan counter */
274 ADC_SAMPLE_COUNTER_EN_BIT = 0x1000,
275 ADC_DMA_DISABLE_BIT = 0x4000, /* disables dma */
276 ADC_ENABLE_BIT = 0x8000, /* master adc enable */
279 enum adc_control1_contents {
280 /* should be set for boards with > 16 channels */
281 ADC_QUEUE_CONFIG_BIT = 0x1,
282 CONVERT_POLARITY_BIT = 0x10,
283 EOC_POLARITY_BIT = 0x20,
284 ADC_SW_GATE_BIT = 0x40, /* software gate of adc */
285 ADC_DITHER_BIT = 0x200, /* turn on extra noise for dithering */
286 RETRIGGER_BIT = 0x800,
287 ADC_LO_CHANNEL_4020_MASK = 0x300,
288 ADC_HI_CHANNEL_4020_MASK = 0xc00,
289 TWO_CHANNEL_4020_BITS = 0x1000, /* two channel mode for 4020 */
290 FOUR_CHANNEL_4020_BITS = 0x2000, /* four channel mode for 4020 */
291 CHANNEL_MODE_4020_MASK = 0x3000,
292 ADC_MODE_MASK = 0xf000,
295 static inline uint16_t adc_lo_chan_4020_bits(unsigned int channel)
297 return (channel & 0x3) << 8;
300 static inline uint16_t adc_hi_chan_4020_bits(unsigned int channel)
302 return (channel & 0x3) << 10;
305 static inline uint16_t adc_mode_bits(unsigned int mode)
307 return (mode & 0xf) << 12;
310 enum calibration_contents {
311 SELECT_8800_BIT = 0x1,
312 SELECT_8402_64XX_BIT = 0x2,
313 SELECT_1590_60XX_BIT = 0x2,
314 CAL_EN_64XX_BIT = 0x40, /* calibration enable for 64xx series */
315 SERIAL_DATA_IN_BIT = 0x80,
316 SERIAL_CLOCK_BIT = 0x100,
317 CAL_EN_60XX_BIT = 0x200, /* calibration enable for 60xx series */
318 CAL_GAIN_BIT = 0x800,
321 /* calibration sources for 6025 are:
332 static inline uint16_t adc_src_bits(unsigned int source)
334 return (source & 0xf) << 3;
337 static inline uint16_t adc_convert_chan_4020_bits(unsigned int channel)
339 return (channel & 0x3) << 8;
342 enum adc_queue_load_contents {
343 UNIP_BIT = 0x800, /* unipolar/bipolar bit */
344 ADC_SE_DIFF_BIT = 0x1000, /* single-ended/ differential bit */
345 /* non-referenced single-ended (common-mode input) */
346 ADC_COMMON_BIT = 0x2000,
347 QUEUE_EOSEQ_BIT = 0x4000, /* queue end of sequence */
348 QUEUE_EOSCAN_BIT = 0x8000, /* queue end of scan */
351 static inline uint16_t adc_chan_bits(unsigned int channel)
353 return channel & 0x3f;
356 enum dac_control0_contents {
357 DAC_ENABLE_BIT = 0x8000, /* dac controller enable bit */
358 DAC_CYCLIC_STOP_BIT = 0x4000,
359 DAC_WAVEFORM_MODE_BIT = 0x100,
360 DAC_EXT_UPDATE_FALLING_BIT = 0x80,
361 DAC_EXT_UPDATE_ENABLE_BIT = 0x40,
362 WAVEFORM_TRIG_MASK = 0x30,
363 WAVEFORM_TRIG_DISABLED_BITS = 0x0,
364 WAVEFORM_TRIG_SOFT_BITS = 0x10,
365 WAVEFORM_TRIG_EXT_BITS = 0x20,
366 WAVEFORM_TRIG_ADC1_BITS = 0x30,
367 WAVEFORM_TRIG_FALLING_BIT = 0x8,
368 WAVEFORM_GATE_LEVEL_BIT = 0x4,
369 WAVEFORM_GATE_ENABLE_BIT = 0x2,
370 WAVEFORM_GATE_SELECT_BIT = 0x1,
373 enum dac_control1_contents {
374 DAC_WRITE_POLARITY_BIT = 0x800, /* board-dependent setting */
375 DAC1_EXT_REF_BIT = 0x200,
376 DAC0_EXT_REF_BIT = 0x100,
377 DAC_OUTPUT_ENABLE_BIT = 0x80, /* dac output enable bit */
378 DAC_UPDATE_POLARITY_BIT = 0x40, /* board-dependent setting */
379 DAC_SW_GATE_BIT = 0x20,
380 DAC1_UNIPOLAR_BIT = 0x8,
381 DAC0_UNIPOLAR_BIT = 0x2,
384 /* bit definitions for read-only registers */
385 enum hw_status_contents {
386 DAC_UNDERRUN_BIT = 0x1,
387 ADC_OVERRUN_BIT = 0x2,
388 DAC_ACTIVE_BIT = 0x4,
389 ADC_ACTIVE_BIT = 0x8,
390 DAC_INTR_PENDING_BIT = 0x10,
391 ADC_INTR_PENDING_BIT = 0x20,
394 EXT_INTR_PENDING_BIT = 0x100,
395 ADC_STOP_BIT = 0x200,
398 static inline uint16_t pipe_full_bits(uint16_t hw_status_bits)
400 return (hw_status_bits >> 10) & 0x3;
403 static inline unsigned int dma_chain_flag_bits(uint16_t prepost_bits)
405 return (prepost_bits >> 6) & 0x3;
408 static inline unsigned int adc_upper_read_ptr_code(uint16_t prepost_bits)
410 return (prepost_bits >> 12) & 0x3;
413 static inline unsigned int adc_upper_write_ptr_code(uint16_t prepost_bits)
415 return (prepost_bits >> 14) & 0x3;
418 /* I2C addresses for 4020 */
420 RANGE_CAL_I2C_ADDR = 0x20,
421 CALDAC0_I2C_ADDR = 0xc,
422 CALDAC1_I2C_ADDR = 0xd,
425 enum range_cal_i2c_contents {
426 /* bits that set what source the adc converter measures */
427 ADC_SRC_4020_MASK = 0x70,
428 /* make bnc trig/ext clock threshold 0V instead of 2.5V */
429 BNC_TRIG_THRESHOLD_0V_BIT = 0x80,
432 static inline uint8_t adc_src_4020_bits(unsigned int source)
434 return (source << 4) & ADC_SRC_4020_MASK;
437 static inline uint8_t attenuate_bit(unsigned int channel)
439 /* attenuate channel (+-5V input range) */
440 return 1 << (channel & 0x3);
443 /* analog input ranges for 64xx boards */
444 static const struct comedi_lrange ai_ranges_64xx = {
458 static const uint8_t ai_range_code_64xx[8] = {
459 0x0, 0x1, 0x2, 0x3, /* bipolar 10, 5, 2,5, 1.25 */
460 0x8, 0x9, 0xa, 0xb /* unipolar 10, 5, 2.5, 1.25 */
463 /* analog input ranges for 64-Mx boards */
464 static const struct comedi_lrange ai_ranges_64_mx = {
476 static const uint8_t ai_range_code_64_mx[7] = {
477 0x0, 0x1, 0x2, 0x3, /* bipolar 5, 2.5, 1.25, 0.625 */
478 0x9, 0xa, 0xb /* unipolar 5, 2.5, 1.25 */
481 /* analog input ranges for 60xx boards */
482 static const struct comedi_lrange ai_ranges_60xx = {
492 static const uint8_t ai_range_code_60xx[4] = {
493 0x0, 0x1, 0x4, 0x7 /* bipolar 10, 5, 0.5, 0.05 */
496 /* analog input ranges for 6030, etc boards */
497 static const struct comedi_lrange ai_ranges_6030 = {
517 static const uint8_t ai_range_code_6030[14] = {
518 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, /* bip 10, 5, 2, 1, 0.5, 0.2, 0.1 */
519 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf /* uni 10, 5, 2, 1, 0.5, 0.2, 0.1 */
522 /* analog input ranges for 6052, etc boards */
523 static const struct comedi_lrange ai_ranges_6052 = {
544 static const uint8_t ai_range_code_6052[15] = {
545 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, /* bipolar 10 ... 0.05 */
546 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf /* unipolar 10 ... 0.1 */
549 /* analog input ranges for 4020 board */
550 static const struct comedi_lrange ai_ranges_4020 = {
558 /* analog output ranges */
559 static const struct comedi_lrange ao_ranges_64xx = {
569 static const int ao_range_code_64xx[] = {
576 static const int ao_range_code_60xx[] = {
580 static const struct comedi_lrange ao_ranges_6030 = {
588 static const int ao_range_code_6030[] = {
593 static const struct comedi_lrange ao_ranges_4020 = {
601 static const int ao_range_code_4020[] = {
606 enum register_layout {
612 struct hw_fifo_info {
613 unsigned int num_segments;
614 unsigned int max_segment_length;
615 unsigned int sample_packing_ratio;
616 uint16_t fifo_size_reg_mask;
619 enum pcidas64_boardid {
622 BOARD_PCIDAS64_M1_16,
623 BOARD_PCIDAS64_M2_16,
624 BOARD_PCIDAS64_M3_16,
641 BOARD_PCIDAS6402_16_JR,
642 BOARD_PCIDAS64_M1_16_JR,
643 BOARD_PCIDAS64_M2_16_JR,
644 BOARD_PCIDAS64_M3_16_JR,
645 BOARD_PCIDAS64_M1_14,
646 BOARD_PCIDAS64_M2_14,
647 BOARD_PCIDAS64_M3_14,
650 struct pcidas64_board {
652 int ai_se_chans; /* number of ai inputs in single-ended mode */
653 int ai_bits; /* analog input resolution */
654 int ai_speed; /* fastest conversion period in ns */
655 const struct comedi_lrange *ai_range_table;
656 const uint8_t *ai_range_code;
657 int ao_nchan; /* number of analog out channels */
658 int ao_bits; /* analog output resolution */
659 int ao_scan_speed; /* analog output scan speed */
660 const struct comedi_lrange *ao_range_table;
661 const int *ao_range_code;
662 const struct hw_fifo_info *const ai_fifo;
663 /* different board families have slightly different registers */
664 enum register_layout layout;
668 static const struct hw_fifo_info ai_fifo_4020 = {
670 .max_segment_length = 0x8000,
671 .sample_packing_ratio = 2,
672 .fifo_size_reg_mask = 0x7f,
675 static const struct hw_fifo_info ai_fifo_64xx = {
677 .max_segment_length = 0x800,
678 .sample_packing_ratio = 1,
679 .fifo_size_reg_mask = 0x3f,
682 static const struct hw_fifo_info ai_fifo_60xx = {
684 .max_segment_length = 0x800,
685 .sample_packing_ratio = 1,
686 .fifo_size_reg_mask = 0x7f,
689 /* maximum number of dma transfers we will chain together into a ring
690 * (and the maximum number of dma buffers we maintain) */
691 #define MAX_AI_DMA_RING_COUNT (0x80000 / DMA_BUFFER_SIZE)
692 #define MIN_AI_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
693 #define AO_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
694 static inline unsigned int ai_dma_ring_count(const struct pcidas64_board *board)
696 if (board->layout == LAYOUT_4020)
697 return MAX_AI_DMA_RING_COUNT;
699 return MIN_AI_DMA_RING_COUNT;
702 static const int bytes_in_sample = 2;
704 static const struct pcidas64_board pcidas64_boards[] = {
705 [BOARD_PCIDAS6402_16] = {
706 .name = "pci-das6402/16",
712 .ao_scan_speed = 10000,
713 .layout = LAYOUT_64XX,
714 .ai_range_table = &ai_ranges_64xx,
715 .ai_range_code = ai_range_code_64xx,
716 .ao_range_table = &ao_ranges_64xx,
717 .ao_range_code = ao_range_code_64xx,
718 .ai_fifo = &ai_fifo_64xx,
721 [BOARD_PCIDAS6402_12] = {
722 .name = "pci-das6402/12", /* XXX check */
728 .ao_scan_speed = 10000,
729 .layout = LAYOUT_64XX,
730 .ai_range_table = &ai_ranges_64xx,
731 .ai_range_code = ai_range_code_64xx,
732 .ao_range_table = &ao_ranges_64xx,
733 .ao_range_code = ao_range_code_64xx,
734 .ai_fifo = &ai_fifo_64xx,
737 [BOARD_PCIDAS64_M1_16] = {
738 .name = "pci-das64/m1/16",
744 .ao_scan_speed = 10000,
745 .layout = LAYOUT_64XX,
746 .ai_range_table = &ai_ranges_64_mx,
747 .ai_range_code = ai_range_code_64_mx,
748 .ao_range_table = &ao_ranges_64xx,
749 .ao_range_code = ao_range_code_64xx,
750 .ai_fifo = &ai_fifo_64xx,
753 [BOARD_PCIDAS64_M2_16] = {
754 .name = "pci-das64/m2/16",
760 .ao_scan_speed = 10000,
761 .layout = LAYOUT_64XX,
762 .ai_range_table = &ai_ranges_64_mx,
763 .ai_range_code = ai_range_code_64_mx,
764 .ao_range_table = &ao_ranges_64xx,
765 .ao_range_code = ao_range_code_64xx,
766 .ai_fifo = &ai_fifo_64xx,
769 [BOARD_PCIDAS64_M3_16] = {
770 .name = "pci-das64/m3/16",
776 .ao_scan_speed = 10000,
777 .layout = LAYOUT_64XX,
778 .ai_range_table = &ai_ranges_64_mx,
779 .ai_range_code = ai_range_code_64_mx,
780 .ao_range_table = &ao_ranges_64xx,
781 .ao_range_code = ao_range_code_64xx,
782 .ai_fifo = &ai_fifo_64xx,
785 [BOARD_PCIDAS6013] = {
786 .name = "pci-das6013",
792 .layout = LAYOUT_60XX,
793 .ai_range_table = &ai_ranges_60xx,
794 .ai_range_code = ai_range_code_60xx,
795 .ao_range_table = &range_bipolar10,
796 .ao_range_code = ao_range_code_60xx,
797 .ai_fifo = &ai_fifo_60xx,
800 [BOARD_PCIDAS6014] = {
801 .name = "pci-das6014",
807 .ao_scan_speed = 100000,
808 .layout = LAYOUT_60XX,
809 .ai_range_table = &ai_ranges_60xx,
810 .ai_range_code = ai_range_code_60xx,
811 .ao_range_table = &range_bipolar10,
812 .ao_range_code = ao_range_code_60xx,
813 .ai_fifo = &ai_fifo_60xx,
816 [BOARD_PCIDAS6023] = {
817 .name = "pci-das6023",
822 .ao_scan_speed = 100000,
823 .layout = LAYOUT_60XX,
824 .ai_range_table = &ai_ranges_60xx,
825 .ai_range_code = ai_range_code_60xx,
826 .ao_range_table = &range_bipolar10,
827 .ao_range_code = ao_range_code_60xx,
828 .ai_fifo = &ai_fifo_60xx,
831 [BOARD_PCIDAS6025] = {
832 .name = "pci-das6025",
838 .ao_scan_speed = 100000,
839 .layout = LAYOUT_60XX,
840 .ai_range_table = &ai_ranges_60xx,
841 .ai_range_code = ai_range_code_60xx,
842 .ao_range_table = &range_bipolar10,
843 .ao_range_code = ao_range_code_60xx,
844 .ai_fifo = &ai_fifo_60xx,
847 [BOARD_PCIDAS6030] = {
848 .name = "pci-das6030",
854 .ao_scan_speed = 10000,
855 .layout = LAYOUT_60XX,
856 .ai_range_table = &ai_ranges_6030,
857 .ai_range_code = ai_range_code_6030,
858 .ao_range_table = &ao_ranges_6030,
859 .ao_range_code = ao_range_code_6030,
860 .ai_fifo = &ai_fifo_60xx,
863 [BOARD_PCIDAS6031] = {
864 .name = "pci-das6031",
870 .ao_scan_speed = 10000,
871 .layout = LAYOUT_60XX,
872 .ai_range_table = &ai_ranges_6030,
873 .ai_range_code = ai_range_code_6030,
874 .ao_range_table = &ao_ranges_6030,
875 .ao_range_code = ao_range_code_6030,
876 .ai_fifo = &ai_fifo_60xx,
879 [BOARD_PCIDAS6032] = {
880 .name = "pci-das6032",
885 .layout = LAYOUT_60XX,
886 .ai_range_table = &ai_ranges_6030,
887 .ai_range_code = ai_range_code_6030,
888 .ai_fifo = &ai_fifo_60xx,
891 [BOARD_PCIDAS6033] = {
892 .name = "pci-das6033",
897 .layout = LAYOUT_60XX,
898 .ai_range_table = &ai_ranges_6030,
899 .ai_range_code = ai_range_code_6030,
900 .ai_fifo = &ai_fifo_60xx,
903 [BOARD_PCIDAS6034] = {
904 .name = "pci-das6034",
910 .layout = LAYOUT_60XX,
911 .ai_range_table = &ai_ranges_60xx,
912 .ai_range_code = ai_range_code_60xx,
913 .ai_fifo = &ai_fifo_60xx,
916 [BOARD_PCIDAS6035] = {
917 .name = "pci-das6035",
923 .ao_scan_speed = 100000,
924 .layout = LAYOUT_60XX,
925 .ai_range_table = &ai_ranges_60xx,
926 .ai_range_code = ai_range_code_60xx,
927 .ao_range_table = &range_bipolar10,
928 .ao_range_code = ao_range_code_60xx,
929 .ai_fifo = &ai_fifo_60xx,
932 [BOARD_PCIDAS6036] = {
933 .name = "pci-das6036",
939 .ao_scan_speed = 100000,
940 .layout = LAYOUT_60XX,
941 .ai_range_table = &ai_ranges_60xx,
942 .ai_range_code = ai_range_code_60xx,
943 .ao_range_table = &range_bipolar10,
944 .ao_range_code = ao_range_code_60xx,
945 .ai_fifo = &ai_fifo_60xx,
948 [BOARD_PCIDAS6040] = {
949 .name = "pci-das6040",
955 .ao_scan_speed = 1000,
956 .layout = LAYOUT_60XX,
957 .ai_range_table = &ai_ranges_6052,
958 .ai_range_code = ai_range_code_6052,
959 .ao_range_table = &ao_ranges_6030,
960 .ao_range_code = ao_range_code_6030,
961 .ai_fifo = &ai_fifo_60xx,
964 [BOARD_PCIDAS6052] = {
965 .name = "pci-das6052",
971 .ao_scan_speed = 3333,
972 .layout = LAYOUT_60XX,
973 .ai_range_table = &ai_ranges_6052,
974 .ai_range_code = ai_range_code_6052,
975 .ao_range_table = &ao_ranges_6030,
976 .ao_range_code = ao_range_code_6030,
977 .ai_fifo = &ai_fifo_60xx,
980 [BOARD_PCIDAS6070] = {
981 .name = "pci-das6070",
987 .ao_scan_speed = 1000,
988 .layout = LAYOUT_60XX,
989 .ai_range_table = &ai_ranges_6052,
990 .ai_range_code = ai_range_code_6052,
991 .ao_range_table = &ao_ranges_6030,
992 .ao_range_code = ao_range_code_6030,
993 .ai_fifo = &ai_fifo_60xx,
996 [BOARD_PCIDAS6071] = {
997 .name = "pci-das6071",
1003 .ao_scan_speed = 1000,
1004 .layout = LAYOUT_60XX,
1005 .ai_range_table = &ai_ranges_6052,
1006 .ai_range_code = ai_range_code_6052,
1007 .ao_range_table = &ao_ranges_6030,
1008 .ao_range_code = ao_range_code_6030,
1009 .ai_fifo = &ai_fifo_60xx,
1012 [BOARD_PCIDAS4020_12] = {
1013 .name = "pci-das4020/12",
1019 .ao_scan_speed = 0, /* no hardware pacing on ao */
1020 .layout = LAYOUT_4020,
1021 .ai_range_table = &ai_ranges_4020,
1022 .ao_range_table = &ao_ranges_4020,
1023 .ao_range_code = ao_range_code_4020,
1024 .ai_fifo = &ai_fifo_4020,
1029 * The device id for these boards is unknown
1032 [BOARD_PCIDAS6402_16_JR] = {
1033 .name = "pci-das6402/16/jr",
1038 .ao_scan_speed = 10000,
1039 .layout = LAYOUT_64XX,
1040 .ai_range_table = &ai_ranges_64xx,
1041 .ai_range_code = ai_range_code_64xx,
1042 .ai_fifo = ai_fifo_64xx,
1045 [BOARD_PCIDAS64_M1_16_JR] = {
1046 .name = "pci-das64/m1/16/jr",
1051 .ao_scan_speed = 10000,
1052 .layout = LAYOUT_64XX,
1053 .ai_range_table = &ai_ranges_64_mx,
1054 .ai_range_code = ai_range_code_64_mx,
1055 .ai_fifo = ai_fifo_64xx,
1058 [BOARD_PCIDAS64_M2_16_JR] = {
1059 .name = "pci-das64/m2/16/jr",
1064 .ao_scan_speed = 10000,
1065 .layout = LAYOUT_64XX,
1066 .ai_range_table = &ai_ranges_64_mx,
1067 .ai_range_code = ai_range_code_64_mx,
1068 .ai_fifo = ai_fifo_64xx,
1071 [BOARD_PCIDAS64_M3_16_JR] = {
1072 .name = "pci-das64/m3/16/jr",
1077 .ao_scan_speed = 10000,
1078 .layout = LAYOUT_64XX,
1079 .ai_range_table = &ai_ranges_64_mx,
1080 .ai_range_code = ai_range_code_64_mx,
1081 .ai_fifo = ai_fifo_64xx,
1084 [BOARD_PCIDAS64_M1_14] = {
1085 .name = "pci-das64/m1/14",
1090 .ao_scan_speed = 10000,
1091 .layout = LAYOUT_64XX,
1092 .ai_range_table = &ai_ranges_64_mx,
1093 .ai_range_code = ai_range_code_64_mx,
1094 .ai_fifo = ai_fifo_64xx,
1097 [BOARD_PCIDAS64_M2_14] = {
1098 .name = "pci-das64/m2/14",
1103 .ao_scan_speed = 10000,
1104 .layout = LAYOUT_64XX,
1105 .ai_range_table = &ai_ranges_64_mx,
1106 .ai_range_code = ai_range_code_64_mx,
1107 .ai_fifo = ai_fifo_64xx,
1110 [BOARD_PCIDAS64_M3_14] = {
1111 .name = "pci-das64/m3/14",
1116 .ao_scan_speed = 10000,
1117 .layout = LAYOUT_64XX,
1118 .ai_range_table = &ai_ranges_64_mx,
1119 .ai_range_code = ai_range_code_64_mx,
1120 .ai_fifo = ai_fifo_64xx,
1126 static inline unsigned short se_diff_bit_6xxx(struct comedi_device *dev,
1127 int use_differential)
1129 const struct pcidas64_board *thisboard = comedi_board(dev);
1131 if ((thisboard->layout == LAYOUT_64XX && !use_differential) ||
1132 (thisboard->layout == LAYOUT_60XX && use_differential))
1133 return ADC_SE_DIFF_BIT;
1138 struct ext_clock_info {
1139 /* master clock divisor to use for scans with external master clock */
1140 unsigned int divisor;
1141 /* chanspec for master clock input when used as scan begin src */
1142 unsigned int chanspec;
1145 /* this structure is for data unique to this hardware driver. */
1146 struct pcidas64_private {
1147 /* base addresses (physical) */
1148 resource_size_t main_phys_iobase;
1149 resource_size_t dio_counter_phys_iobase;
1150 /* base addresses (ioremapped) */
1151 void __iomem *plx9080_iobase;
1152 void __iomem *main_iobase;
1153 void __iomem *dio_counter_iobase;
1154 /* local address (used by dma controller) */
1155 uint32_t local0_iobase;
1156 uint32_t local1_iobase;
1157 /* number of analog input samples remaining */
1158 volatile unsigned int ai_count;
1159 /* dma buffers for analog input */
1160 uint16_t *ai_buffer[MAX_AI_DMA_RING_COUNT];
1161 /* physical addresses of ai dma buffers */
1162 dma_addr_t ai_buffer_bus_addr[MAX_AI_DMA_RING_COUNT];
1163 /* array of ai dma descriptors read by plx9080,
1164 * allocated to get proper alignment */
1165 struct plx_dma_desc *ai_dma_desc;
1166 /* physical address of ai dma descriptor array */
1167 dma_addr_t ai_dma_desc_bus_addr;
1168 /* index of the ai dma descriptor/buffer
1169 * that is currently being used */
1170 volatile unsigned int ai_dma_index;
1171 /* dma buffers for analog output */
1172 uint16_t *ao_buffer[AO_DMA_RING_COUNT];
1173 /* physical addresses of ao dma buffers */
1174 dma_addr_t ao_buffer_bus_addr[AO_DMA_RING_COUNT];
1175 struct plx_dma_desc *ao_dma_desc;
1176 dma_addr_t ao_dma_desc_bus_addr;
1177 /* keeps track of buffer where the next ao sample should go */
1178 volatile unsigned int ao_dma_index;
1179 /* number of analog output samples remaining */
1180 volatile unsigned long ao_count;
1181 /* remember what the analog outputs are set to, to allow readback */
1182 volatile unsigned int ao_value[2];
1183 unsigned int hw_revision; /* stc chip hardware revision number */
1184 /* last bits sent to INTR_ENABLE_REG register */
1185 volatile unsigned int intr_enable_bits;
1186 /* last bits sent to ADC_CONTROL1_REG register */
1187 volatile uint16_t adc_control1_bits;
1188 /* last bits sent to FIFO_SIZE_REG register */
1189 volatile uint16_t fifo_size_bits;
1190 /* last bits sent to HW_CONFIG_REG register */
1191 volatile uint16_t hw_config_bits;
1192 volatile uint16_t dac_control1_bits;
1193 /* last bits written to plx9080 control register */
1194 volatile uint32_t plx_control_bits;
1195 /* last bits written to plx interrupt control and status register */
1196 volatile uint32_t plx_intcsr_bits;
1197 /* index of calibration source readable through ai ch0 */
1198 volatile int calibration_source;
1199 /* bits written to i2c calibration/range register */
1200 volatile uint8_t i2c_cal_range_bits;
1201 /* configure digital triggers to trigger on falling edge */
1202 volatile unsigned int ext_trig_falling;
1203 /* states of various devices stored to enable read-back */
1204 unsigned int ad8402_state[2];
1205 unsigned int caldac_state[8];
1206 volatile short ai_cmd_running;
1207 unsigned int ai_fifo_segment_length;
1208 struct ext_clock_info ext_clock;
1209 short ao_bounce_buffer[DAC_FIFO_SIZE];
1212 static unsigned int ai_range_bits_6xxx(const struct comedi_device *dev,
1213 unsigned int range_index)
1215 const struct pcidas64_board *thisboard = comedi_board(dev);
1217 return thisboard->ai_range_code[range_index] << 8;
1220 static unsigned int hw_revision(const struct comedi_device *dev,
1221 uint16_t hw_status_bits)
1223 const struct pcidas64_board *thisboard = comedi_board(dev);
1225 if (thisboard->layout == LAYOUT_4020)
1226 return (hw_status_bits >> 13) & 0x7;
1228 return (hw_status_bits >> 12) & 0xf;
1231 static void set_dac_range_bits(struct comedi_device *dev,
1232 volatile uint16_t *bits, unsigned int channel,
1235 const struct pcidas64_board *thisboard = comedi_board(dev);
1236 unsigned int code = thisboard->ao_range_code[range];
1239 comedi_error(dev, "bug! bad channel?");
1241 comedi_error(dev, "bug! bad range code?");
1243 *bits &= ~(0x3 << (2 * channel));
1244 *bits |= code << (2 * channel);
1247 static inline int ao_cmd_is_supported(const struct pcidas64_board *board)
1249 return board->ao_nchan && board->layout != LAYOUT_4020;
1252 static void abort_dma(struct comedi_device *dev, unsigned int channel)
1254 struct pcidas64_private *devpriv = dev->private;
1255 unsigned long flags;
1257 /* spinlock for plx dma control/status reg */
1258 spin_lock_irqsave(&dev->spinlock, flags);
1260 plx9080_abort_dma(devpriv->plx9080_iobase, channel);
1262 spin_unlock_irqrestore(&dev->spinlock, flags);
1265 static void disable_plx_interrupts(struct comedi_device *dev)
1267 struct pcidas64_private *devpriv = dev->private;
1269 devpriv->plx_intcsr_bits = 0;
1270 writel(devpriv->plx_intcsr_bits,
1271 devpriv->plx9080_iobase + PLX_INTRCS_REG);
1274 static void disable_ai_interrupts(struct comedi_device *dev)
1276 struct pcidas64_private *devpriv = dev->private;
1277 unsigned long flags;
1279 spin_lock_irqsave(&dev->spinlock, flags);
1280 devpriv->intr_enable_bits &=
1281 ~EN_ADC_INTR_SRC_BIT & ~EN_ADC_DONE_INTR_BIT &
1282 ~EN_ADC_ACTIVE_INTR_BIT & ~EN_ADC_STOP_INTR_BIT &
1283 ~EN_ADC_OVERRUN_BIT & ~ADC_INTR_SRC_MASK;
1284 writew(devpriv->intr_enable_bits,
1285 devpriv->main_iobase + INTR_ENABLE_REG);
1286 spin_unlock_irqrestore(&dev->spinlock, flags);
1288 DEBUG_PRINT("intr enable bits 0x%x\n", devpriv->intr_enable_bits);
1291 static void enable_ai_interrupts(struct comedi_device *dev,
1292 const struct comedi_cmd *cmd)
1294 const struct pcidas64_board *thisboard = comedi_board(dev);
1295 struct pcidas64_private *devpriv = dev->private;
1297 unsigned long flags;
1299 bits = EN_ADC_OVERRUN_BIT | EN_ADC_DONE_INTR_BIT |
1300 EN_ADC_ACTIVE_INTR_BIT | EN_ADC_STOP_INTR_BIT;
1301 /* Use pio transfer and interrupt on end of conversion
1302 * if TRIG_WAKE_EOS flag is set. */
1303 if (cmd->flags & TRIG_WAKE_EOS) {
1304 /* 4020 doesn't support pio transfers except for fifo dregs */
1305 if (thisboard->layout != LAYOUT_4020)
1306 bits |= ADC_INTR_EOSCAN_BITS | EN_ADC_INTR_SRC_BIT;
1308 spin_lock_irqsave(&dev->spinlock, flags);
1309 devpriv->intr_enable_bits |= bits;
1310 writew(devpriv->intr_enable_bits,
1311 devpriv->main_iobase + INTR_ENABLE_REG);
1312 DEBUG_PRINT("intr enable bits 0x%x\n", devpriv->intr_enable_bits);
1313 spin_unlock_irqrestore(&dev->spinlock, flags);
1316 /* initialize plx9080 chip */
1317 static void init_plx9080(struct comedi_device *dev)
1319 const struct pcidas64_board *thisboard = comedi_board(dev);
1320 struct pcidas64_private *devpriv = dev->private;
1322 void __iomem *plx_iobase = devpriv->plx9080_iobase;
1324 devpriv->plx_control_bits =
1325 readl(devpriv->plx9080_iobase + PLX_CONTROL_REG);
1328 DEBUG_PRINT(" plx interrupt status 0x%x\n",
1329 readl(plx_iobase + PLX_INTRCS_REG));
1330 DEBUG_PRINT(" plx id bits 0x%x\n", readl(plx_iobase + PLX_ID_REG));
1331 DEBUG_PRINT(" plx control reg 0x%x\n", devpriv->plx_control_bits);
1332 DEBUG_PRINT(" plx mode/arbitration reg 0x%x\n",
1333 readl(plx_iobase + PLX_MARB_REG));
1334 DEBUG_PRINT(" plx region0 reg 0x%x\n",
1335 readl(plx_iobase + PLX_REGION0_REG));
1336 DEBUG_PRINT(" plx region1 reg 0x%x\n",
1337 readl(plx_iobase + PLX_REGION1_REG));
1339 DEBUG_PRINT(" plx revision 0x%x\n",
1340 readl(plx_iobase + PLX_REVISION_REG));
1341 DEBUG_PRINT(" plx dma channel 0 mode 0x%x\n",
1342 readl(plx_iobase + PLX_DMA0_MODE_REG));
1343 DEBUG_PRINT(" plx dma channel 1 mode 0x%x\n",
1344 readl(plx_iobase + PLX_DMA1_MODE_REG));
1345 DEBUG_PRINT(" plx dma channel 0 pci address 0x%x\n",
1346 readl(plx_iobase + PLX_DMA0_PCI_ADDRESS_REG));
1347 DEBUG_PRINT(" plx dma channel 0 local address 0x%x\n",
1348 readl(plx_iobase + PLX_DMA0_LOCAL_ADDRESS_REG));
1349 DEBUG_PRINT(" plx dma channel 0 transfer size 0x%x\n",
1350 readl(plx_iobase + PLX_DMA0_TRANSFER_SIZE_REG));
1351 DEBUG_PRINT(" plx dma channel 0 descriptor 0x%x\n",
1352 readl(plx_iobase + PLX_DMA0_DESCRIPTOR_REG));
1353 DEBUG_PRINT(" plx dma channel 0 command status 0x%x\n",
1354 readb(plx_iobase + PLX_DMA0_CS_REG));
1355 DEBUG_PRINT(" plx dma channel 0 threshold 0x%x\n",
1356 readl(plx_iobase + PLX_DMA0_THRESHOLD_REG));
1357 DEBUG_PRINT(" plx bigend 0x%x\n", readl(plx_iobase + PLX_BIGEND_REG));
1360 bits = BIGEND_DMA0 | BIGEND_DMA1;
1364 writel(bits, devpriv->plx9080_iobase + PLX_BIGEND_REG);
1366 disable_plx_interrupts(dev);
1371 /* configure dma0 mode */
1373 /* enable ready input, not sure if this is necessary */
1374 bits |= PLX_DMA_EN_READYIN_BIT;
1375 /* enable bterm, not sure if this is necessary */
1376 bits |= PLX_EN_BTERM_BIT;
1377 /* enable dma chaining */
1378 bits |= PLX_EN_CHAIN_BIT;
1379 /* enable interrupt on dma done
1380 * (probably don't need this, since chain never finishes) */
1381 bits |= PLX_EN_DMA_DONE_INTR_BIT;
1382 /* don't increment local address during transfers
1383 * (we are transferring from a fixed fifo register) */
1384 bits |= PLX_LOCAL_ADDR_CONST_BIT;
1385 /* route dma interrupt to pci bus */
1386 bits |= PLX_DMA_INTR_PCI_BIT;
1387 /* enable demand mode */
1388 bits |= PLX_DEMAND_MODE_BIT;
1389 /* enable local burst mode */
1390 bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
1391 /* 4020 uses 32 bit dma */
1392 if (thisboard->layout == LAYOUT_4020)
1393 bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
1394 else /* localspace0 bus is 16 bits wide */
1395 bits |= PLX_LOCAL_BUS_16_WIDE_BITS;
1396 writel(bits, plx_iobase + PLX_DMA1_MODE_REG);
1397 if (ao_cmd_is_supported(thisboard))
1398 writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
1400 /* enable interrupts on plx 9080 */
1401 devpriv->plx_intcsr_bits |=
1402 ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
1403 ICS_DMA0_E | ICS_DMA1_E;
1404 writel(devpriv->plx_intcsr_bits,
1405 devpriv->plx9080_iobase + PLX_INTRCS_REG);
1408 static void disable_ai_pacing(struct comedi_device *dev)
1410 struct pcidas64_private *devpriv = dev->private;
1411 unsigned long flags;
1413 disable_ai_interrupts(dev);
1415 spin_lock_irqsave(&dev->spinlock, flags);
1416 devpriv->adc_control1_bits &= ~ADC_SW_GATE_BIT;
1417 writew(devpriv->adc_control1_bits,
1418 devpriv->main_iobase + ADC_CONTROL1_REG);
1419 spin_unlock_irqrestore(&dev->spinlock, flags);
1421 /* disable pacing, triggering, etc */
1422 writew(ADC_DMA_DISABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT,
1423 devpriv->main_iobase + ADC_CONTROL0_REG);
1426 static int set_ai_fifo_segment_length(struct comedi_device *dev,
1427 unsigned int num_entries)
1429 const struct pcidas64_board *thisboard = comedi_board(dev);
1430 struct pcidas64_private *devpriv = dev->private;
1431 static const int increment_size = 0x100;
1432 const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1433 unsigned int num_increments;
1436 if (num_entries < increment_size)
1437 num_entries = increment_size;
1438 if (num_entries > fifo->max_segment_length)
1439 num_entries = fifo->max_segment_length;
1441 /* 1 == 256 entries, 2 == 512 entries, etc */
1442 num_increments = (num_entries + increment_size / 2) / increment_size;
1444 bits = (~(num_increments - 1)) & fifo->fifo_size_reg_mask;
1445 devpriv->fifo_size_bits &= ~fifo->fifo_size_reg_mask;
1446 devpriv->fifo_size_bits |= bits;
1447 writew(devpriv->fifo_size_bits,
1448 devpriv->main_iobase + FIFO_SIZE_REG);
1450 devpriv->ai_fifo_segment_length = num_increments * increment_size;
1452 DEBUG_PRINT("set hardware fifo segment length to %i\n",
1453 devpriv->ai_fifo_segment_length);
1455 return devpriv->ai_fifo_segment_length;
1458 /* adjusts the size of hardware fifo (which determines block size for dma xfers) */
1459 static int set_ai_fifo_size(struct comedi_device *dev, unsigned int num_samples)
1461 const struct pcidas64_board *thisboard = comedi_board(dev);
1462 unsigned int num_fifo_entries;
1464 const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1466 num_fifo_entries = num_samples / fifo->sample_packing_ratio;
1468 retval = set_ai_fifo_segment_length(dev,
1470 fifo->num_segments);
1474 num_samples = retval * fifo->num_segments * fifo->sample_packing_ratio;
1476 DEBUG_PRINT("set hardware fifo size to %i\n", num_samples);
1481 /* query length of fifo */
1482 static unsigned int ai_fifo_size(struct comedi_device *dev)
1484 const struct pcidas64_board *thisboard = comedi_board(dev);
1485 struct pcidas64_private *devpriv = dev->private;
1487 return devpriv->ai_fifo_segment_length *
1488 thisboard->ai_fifo->num_segments *
1489 thisboard->ai_fifo->sample_packing_ratio;
1492 static void init_stc_registers(struct comedi_device *dev)
1494 const struct pcidas64_board *thisboard = comedi_board(dev);
1495 struct pcidas64_private *devpriv = dev->private;
1497 unsigned long flags;
1499 spin_lock_irqsave(&dev->spinlock, flags);
1501 /* bit should be set for 6025,
1502 * although docs say boards with <= 16 chans should be cleared XXX */
1504 devpriv->adc_control1_bits |= ADC_QUEUE_CONFIG_BIT;
1505 writew(devpriv->adc_control1_bits,
1506 devpriv->main_iobase + ADC_CONTROL1_REG);
1508 /* 6402/16 manual says this register must be initialized to 0xff? */
1509 writew(0xff, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1511 bits = SLOW_DAC_BIT | DMA_CH_SELECT_BIT;
1512 if (thisboard->layout == LAYOUT_4020)
1513 bits |= INTERNAL_CLOCK_4020_BITS;
1514 devpriv->hw_config_bits |= bits;
1515 writew(devpriv->hw_config_bits,
1516 devpriv->main_iobase + HW_CONFIG_REG);
1518 writew(0, devpriv->main_iobase + DAQ_SYNC_REG);
1519 writew(0, devpriv->main_iobase + CALIBRATION_REG);
1521 spin_unlock_irqrestore(&dev->spinlock, flags);
1523 /* set fifos to maximum size */
1524 devpriv->fifo_size_bits |= DAC_FIFO_BITS;
1525 set_ai_fifo_segment_length(dev,
1526 thisboard->ai_fifo->max_segment_length);
1528 devpriv->dac_control1_bits = DAC_OUTPUT_ENABLE_BIT;
1529 devpriv->intr_enable_bits =
1530 /* EN_DAC_INTR_SRC_BIT | DAC_INTR_QEMPTY_BITS | */
1531 EN_DAC_DONE_INTR_BIT | EN_DAC_UNDERRUN_BIT;
1532 writew(devpriv->intr_enable_bits,
1533 devpriv->main_iobase + INTR_ENABLE_REG);
1535 disable_ai_pacing(dev);
1538 static int alloc_and_init_dma_members(struct comedi_device *dev)
1540 const struct pcidas64_board *thisboard = comedi_board(dev);
1541 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1542 struct pcidas64_private *devpriv = dev->private;
1545 /* allocate pci dma buffers */
1546 for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
1547 devpriv->ai_buffer[i] =
1548 pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
1549 &devpriv->ai_buffer_bus_addr[i]);
1550 if (devpriv->ai_buffer[i] == NULL)
1554 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1555 if (ao_cmd_is_supported(thisboard)) {
1556 devpriv->ao_buffer[i] =
1557 pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
1559 ao_buffer_bus_addr[i]);
1560 if (devpriv->ao_buffer[i] == NULL)
1565 /* allocate dma descriptors */
1566 devpriv->ai_dma_desc =
1567 pci_alloc_consistent(pcidev, sizeof(struct plx_dma_desc) *
1568 ai_dma_ring_count(thisboard),
1569 &devpriv->ai_dma_desc_bus_addr);
1570 if (devpriv->ai_dma_desc == NULL)
1573 DEBUG_PRINT("ai dma descriptors start at bus addr 0x%llx\n",
1574 (unsigned long long)devpriv->ai_dma_desc_bus_addr);
1575 if (ao_cmd_is_supported(thisboard)) {
1576 devpriv->ao_dma_desc =
1577 pci_alloc_consistent(pcidev,
1578 sizeof(struct plx_dma_desc) *
1580 &devpriv->ao_dma_desc_bus_addr);
1581 if (devpriv->ao_dma_desc == NULL)
1584 DEBUG_PRINT("ao dma descriptors start at bus addr 0x%llx\n",
1585 (unsigned long long)devpriv->ao_dma_desc_bus_addr);
1587 /* initialize dma descriptors */
1588 for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
1589 devpriv->ai_dma_desc[i].pci_start_addr =
1590 cpu_to_le32(devpriv->ai_buffer_bus_addr[i]);
1591 if (thisboard->layout == LAYOUT_4020)
1592 devpriv->ai_dma_desc[i].local_start_addr =
1593 cpu_to_le32(devpriv->local1_iobase +
1596 devpriv->ai_dma_desc[i].local_start_addr =
1597 cpu_to_le32(devpriv->local0_iobase +
1599 devpriv->ai_dma_desc[i].transfer_size = cpu_to_le32(0);
1600 devpriv->ai_dma_desc[i].next =
1601 cpu_to_le32((devpriv->ai_dma_desc_bus_addr +
1602 ((i + 1) % ai_dma_ring_count(thisboard)) *
1603 sizeof(devpriv->ai_dma_desc[0])) |
1604 PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
1605 PLX_XFER_LOCAL_TO_PCI);
1607 if (ao_cmd_is_supported(thisboard)) {
1608 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1609 devpriv->ao_dma_desc[i].pci_start_addr =
1610 cpu_to_le32(devpriv->ao_buffer_bus_addr[i]);
1611 devpriv->ao_dma_desc[i].local_start_addr =
1612 cpu_to_le32(devpriv->local0_iobase +
1614 devpriv->ao_dma_desc[i].transfer_size = cpu_to_le32(0);
1615 devpriv->ao_dma_desc[i].next =
1616 cpu_to_le32((devpriv->ao_dma_desc_bus_addr +
1617 ((i + 1) % (AO_DMA_RING_COUNT)) *
1618 sizeof(devpriv->ao_dma_desc[0])) |
1619 PLX_DESC_IN_PCI_BIT |
1620 PLX_INTR_TERM_COUNT);
1626 static inline void warn_external_queue(struct comedi_device *dev)
1629 "AO command and AI external channel queue cannot be used simultaneously.");
1631 "Use internal AI channel queue (channels must be consecutive and use same range/aref)");
1634 /* Their i2c requires a huge delay on setting clock or data high for some reason */
1635 static const int i2c_high_udelay = 1000;
1636 static const int i2c_low_udelay = 10;
1638 /* set i2c data line high or low */
1639 static void i2c_set_sda(struct comedi_device *dev, int state)
1641 struct pcidas64_private *devpriv = dev->private;
1642 static const int data_bit = CTL_EE_W;
1643 void __iomem *plx_control_addr = devpriv->plx9080_iobase +
1647 /* set data line high */
1648 devpriv->plx_control_bits &= ~data_bit;
1649 writel(devpriv->plx_control_bits, plx_control_addr);
1650 udelay(i2c_high_udelay);
1651 } else { /* set data line low */
1653 devpriv->plx_control_bits |= data_bit;
1654 writel(devpriv->plx_control_bits, plx_control_addr);
1655 udelay(i2c_low_udelay);
1659 /* set i2c clock line high or low */
1660 static void i2c_set_scl(struct comedi_device *dev, int state)
1662 struct pcidas64_private *devpriv = dev->private;
1663 static const int clock_bit = CTL_USERO;
1664 void __iomem *plx_control_addr = devpriv->plx9080_iobase +
1668 /* set clock line high */
1669 devpriv->plx_control_bits &= ~clock_bit;
1670 writel(devpriv->plx_control_bits, plx_control_addr);
1671 udelay(i2c_high_udelay);
1672 } else { /* set clock line low */
1674 devpriv->plx_control_bits |= clock_bit;
1675 writel(devpriv->plx_control_bits, plx_control_addr);
1676 udelay(i2c_low_udelay);
1680 static void i2c_write_byte(struct comedi_device *dev, uint8_t byte)
1683 unsigned int num_bits = 8;
1685 DEBUG_PRINT("writing to i2c byte 0x%x\n", byte);
1687 for (bit = 1 << (num_bits - 1); bit; bit >>= 1) {
1688 i2c_set_scl(dev, 0);
1690 i2c_set_sda(dev, 1);
1692 i2c_set_sda(dev, 0);
1693 i2c_set_scl(dev, 1);
1697 /* we can't really read the lines, so fake it */
1698 static int i2c_read_ack(struct comedi_device *dev)
1700 i2c_set_scl(dev, 0);
1701 i2c_set_sda(dev, 1);
1702 i2c_set_scl(dev, 1);
1704 return 0; /* return fake acknowledge bit */
1707 /* send start bit */
1708 static void i2c_start(struct comedi_device *dev)
1710 i2c_set_scl(dev, 1);
1711 i2c_set_sda(dev, 1);
1712 i2c_set_sda(dev, 0);
1716 static void i2c_stop(struct comedi_device *dev)
1718 i2c_set_scl(dev, 0);
1719 i2c_set_sda(dev, 0);
1720 i2c_set_scl(dev, 1);
1721 i2c_set_sda(dev, 1);
1724 static void i2c_write(struct comedi_device *dev, unsigned int address,
1725 const uint8_t *data, unsigned int length)
1727 struct pcidas64_private *devpriv = dev->private;
1730 static const int read_bit = 0x1;
1732 /* XXX need mutex to prevent simultaneous attempts to access
1733 * eeprom and i2c bus */
1735 /* make sure we dont send anything to eeprom */
1736 devpriv->plx_control_bits &= ~CTL_EE_CS;
1741 /* send address and write bit */
1742 bitstream = (address << 1) & ~read_bit;
1743 i2c_write_byte(dev, bitstream);
1745 /* get acknowledge */
1746 if (i2c_read_ack(dev) != 0) {
1747 comedi_error(dev, "i2c write failed: no acknowledge");
1751 /* write data bytes */
1752 for (i = 0; i < length; i++) {
1753 i2c_write_byte(dev, data[i]);
1754 if (i2c_read_ack(dev) != 0) {
1755 comedi_error(dev, "i2c write failed: no acknowledge");
1763 static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1764 struct comedi_insn *insn, unsigned int *data)
1766 const struct pcidas64_board *thisboard = comedi_board(dev);
1767 struct pcidas64_private *devpriv = dev->private;
1768 unsigned int bits = 0, n, i;
1769 unsigned int channel, range, aref;
1770 unsigned long flags;
1771 static const int timeout = 100;
1773 DEBUG_PRINT("chanspec 0x%x\n", insn->chanspec);
1774 channel = CR_CHAN(insn->chanspec);
1775 range = CR_RANGE(insn->chanspec);
1776 aref = CR_AREF(insn->chanspec);
1778 /* disable card's analog input interrupt sources and pacing */
1779 /* 4020 generates dac done interrupts even though they are disabled */
1780 disable_ai_pacing(dev);
1782 spin_lock_irqsave(&dev->spinlock, flags);
1783 if (insn->chanspec & CR_ALT_FILTER)
1784 devpriv->adc_control1_bits |= ADC_DITHER_BIT;
1786 devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
1787 writew(devpriv->adc_control1_bits,
1788 devpriv->main_iobase + ADC_CONTROL1_REG);
1789 spin_unlock_irqrestore(&dev->spinlock, flags);
1791 if (thisboard->layout != LAYOUT_4020) {
1792 /* use internal queue */
1793 devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
1794 writew(devpriv->hw_config_bits,
1795 devpriv->main_iobase + HW_CONFIG_REG);
1797 /* ALT_SOURCE is internal calibration reference */
1798 if (insn->chanspec & CR_ALT_SOURCE) {
1799 unsigned int cal_en_bit;
1801 DEBUG_PRINT("reading calibration source\n");
1802 if (thisboard->layout == LAYOUT_60XX)
1803 cal_en_bit = CAL_EN_60XX_BIT;
1805 cal_en_bit = CAL_EN_64XX_BIT;
1806 /* select internal reference source to connect
1809 adc_src_bits(devpriv->calibration_source),
1810 devpriv->main_iobase + CALIBRATION_REG);
1812 /* make sure internal calibration source
1814 writew(0, devpriv->main_iobase + CALIBRATION_REG);
1816 /* load internal queue */
1819 bits |= ai_range_bits_6xxx(dev, CR_RANGE(insn->chanspec));
1820 /* set single-ended / differential */
1821 bits |= se_diff_bit_6xxx(dev, aref == AREF_DIFF);
1822 if (aref == AREF_COMMON)
1823 bits |= ADC_COMMON_BIT;
1824 bits |= adc_chan_bits(channel);
1825 /* set stop channel */
1826 writew(adc_chan_bits(channel),
1827 devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
1828 /* set start channel, and rest of settings */
1829 writew(bits, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
1831 uint8_t old_cal_range_bits = devpriv->i2c_cal_range_bits;
1833 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
1834 if (insn->chanspec & CR_ALT_SOURCE) {
1835 DEBUG_PRINT("reading calibration source\n");
1836 devpriv->i2c_cal_range_bits |=
1837 adc_src_4020_bits(devpriv->calibration_source);
1838 } else { /* select BNC inputs */
1839 devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
1843 devpriv->i2c_cal_range_bits |= attenuate_bit(channel);
1845 devpriv->i2c_cal_range_bits &= ~attenuate_bit(channel);
1846 /* update calibration/range i2c register only if necessary,
1847 * as it is very slow */
1848 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
1849 uint8_t i2c_data = devpriv->i2c_cal_range_bits;
1850 i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
1854 /* 4020 manual asks that sample interval register to be set
1855 * before writing to convert register.
1856 * Using somewhat arbitrary setting of 4 master clock ticks
1858 writew(0, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1859 writew(2, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
1862 for (n = 0; n < insn->n; n++) {
1864 /* clear adc buffer (inside loop for 4020 sake) */
1865 writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
1867 /* trigger conversion, bits sent only matter for 4020 */
1868 writew(adc_convert_chan_4020_bits(CR_CHAN(insn->chanspec)),
1869 devpriv->main_iobase + ADC_CONVERT_REG);
1872 for (i = 0; i < timeout; i++) {
1873 bits = readw(devpriv->main_iobase + HW_STATUS_REG);
1874 DEBUG_PRINT(" pipe bits 0x%x\n", pipe_full_bits(bits));
1875 if (thisboard->layout == LAYOUT_4020) {
1876 if (readw(devpriv->main_iobase +
1877 ADC_WRITE_PNTR_REG))
1880 if (pipe_full_bits(bits))
1885 DEBUG_PRINT(" looped %i times waiting for data\n", i);
1887 comedi_error(dev, " analog input read insn timed out");
1888 dev_info(dev->class_dev, "status 0x%x\n", bits);
1891 if (thisboard->layout == LAYOUT_4020)
1892 data[n] = readl(devpriv->dio_counter_iobase +
1893 ADC_FIFO_REG) & 0xffff;
1895 data[n] = readw(devpriv->main_iobase + PIPE1_READ_REG);
1901 static int ai_config_calibration_source(struct comedi_device *dev,
1904 const struct pcidas64_board *thisboard = comedi_board(dev);
1905 struct pcidas64_private *devpriv = dev->private;
1906 unsigned int source = data[1];
1907 int num_calibration_sources;
1909 if (thisboard->layout == LAYOUT_60XX)
1910 num_calibration_sources = 16;
1912 num_calibration_sources = 8;
1913 if (source >= num_calibration_sources) {
1914 dev_dbg(dev->class_dev, "invalid calibration source: %i\n",
1919 DEBUG_PRINT("setting calibration source to %i\n", source);
1920 devpriv->calibration_source = source;
1925 static int ai_config_block_size(struct comedi_device *dev, unsigned int *data)
1927 const struct pcidas64_board *thisboard = comedi_board(dev);
1929 const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1930 unsigned int block_size, requested_block_size;
1933 requested_block_size = data[1];
1935 if (requested_block_size) {
1936 fifo_size = requested_block_size * fifo->num_segments /
1939 retval = set_ai_fifo_size(dev, fifo_size);
1945 block_size = ai_fifo_size(dev) / fifo->num_segments * bytes_in_sample;
1947 data[1] = block_size;
1952 static int ai_config_master_clock_4020(struct comedi_device *dev,
1955 struct pcidas64_private *devpriv = dev->private;
1956 unsigned int divisor = data[4];
1965 case COMEDI_EV_SCAN_BEGIN:
1966 devpriv->ext_clock.divisor = divisor;
1967 devpriv->ext_clock.chanspec = data[2];
1976 return retval ? retval : 5;
1979 /* XXX could add support for 60xx series */
1980 static int ai_config_master_clock(struct comedi_device *dev, unsigned int *data)
1982 const struct pcidas64_board *thisboard = comedi_board(dev);
1984 switch (thisboard->layout) {
1986 return ai_config_master_clock_4020(dev, data);
1996 static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s,
1997 struct comedi_insn *insn, unsigned int *data)
2002 case INSN_CONFIG_ALT_SOURCE:
2003 return ai_config_calibration_source(dev, data);
2005 case INSN_CONFIG_BLOCK_SIZE:
2006 return ai_config_block_size(dev, data);
2008 case INSN_CONFIG_TIMER_1:
2009 return ai_config_master_clock(dev, data);
2018 /* Gets nearest achievable timing given master clock speed, does not
2019 * take into account possible minimum/maximum divisor values. Used
2020 * by other timing checking functions. */
2021 static unsigned int get_divisor(unsigned int ns, unsigned int flags)
2023 unsigned int divisor;
2025 switch (flags & TRIG_ROUND_MASK) {
2027 divisor = (ns + TIMER_BASE - 1) / TIMER_BASE;
2029 case TRIG_ROUND_DOWN:
2030 divisor = ns / TIMER_BASE;
2032 case TRIG_ROUND_NEAREST:
2034 divisor = (ns + TIMER_BASE / 2) / TIMER_BASE;
2040 /* utility function that rounds desired timing to an achievable time, and
2041 * sets cmd members appropriately.
2042 * adc paces conversions from master clock by dividing by (x + 3) where x is 24 bit number
2044 static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd)
2046 const struct pcidas64_board *thisboard = comedi_board(dev);
2047 unsigned int convert_divisor = 0, scan_divisor;
2048 static const int min_convert_divisor = 3;
2049 static const int max_convert_divisor =
2050 max_counter_value + min_convert_divisor;
2051 static const int min_scan_divisor_4020 = 2;
2052 unsigned long long max_scan_divisor, min_scan_divisor;
2054 if (cmd->convert_src == TRIG_TIMER) {
2055 if (thisboard->layout == LAYOUT_4020) {
2056 cmd->convert_arg = 0;
2058 convert_divisor = get_divisor(cmd->convert_arg,
2060 if (convert_divisor > max_convert_divisor)
2061 convert_divisor = max_convert_divisor;
2062 if (convert_divisor < min_convert_divisor)
2063 convert_divisor = min_convert_divisor;
2064 cmd->convert_arg = convert_divisor * TIMER_BASE;
2066 } else if (cmd->convert_src == TRIG_NOW) {
2067 cmd->convert_arg = 0;
2070 if (cmd->scan_begin_src == TRIG_TIMER) {
2071 scan_divisor = get_divisor(cmd->scan_begin_arg, cmd->flags);
2072 if (cmd->convert_src == TRIG_TIMER) {
2073 /* XXX check for integer overflows */
2074 min_scan_divisor = convert_divisor * cmd->chanlist_len;
2076 (convert_divisor * cmd->chanlist_len - 1) +
2079 min_scan_divisor = min_scan_divisor_4020;
2080 max_scan_divisor = max_counter_value + min_scan_divisor;
2082 if (scan_divisor > max_scan_divisor)
2083 scan_divisor = max_scan_divisor;
2084 if (scan_divisor < min_scan_divisor)
2085 scan_divisor = min_scan_divisor;
2086 cmd->scan_begin_arg = scan_divisor * TIMER_BASE;
2092 static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2093 struct comedi_cmd *cmd)
2095 const struct pcidas64_board *thisboard = comedi_board(dev);
2097 unsigned int tmp_arg, tmp_arg2;
2100 unsigned int triggers;
2102 /* Step 1 : check if triggers are trivially valid */
2104 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
2106 triggers = TRIG_TIMER;
2107 if (thisboard->layout == LAYOUT_4020)
2108 triggers |= TRIG_OTHER;
2110 triggers |= TRIG_FOLLOW;
2111 err |= cfc_check_trigger_src(&cmd->scan_begin_src, triggers);
2113 triggers = TRIG_TIMER;
2114 if (thisboard->layout == LAYOUT_4020)
2115 triggers |= TRIG_NOW;
2117 triggers |= TRIG_EXT;
2118 err |= cfc_check_trigger_src(&cmd->convert_src, triggers);
2119 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2120 err |= cfc_check_trigger_src(&cmd->stop_src,
2121 TRIG_COUNT | TRIG_EXT | TRIG_NONE);
2126 /* Step 2a : make sure trigger sources are unique */
2128 err |= cfc_check_trigger_is_unique(cmd->start_src);
2129 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2130 err |= cfc_check_trigger_is_unique(cmd->convert_src);
2131 err |= cfc_check_trigger_is_unique(cmd->stop_src);
2133 /* Step 2b : and mutually compatible */
2135 if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
2137 if (cmd->stop_src != TRIG_COUNT &&
2138 cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
2144 /* Step 3: check if arguments are trivially valid */
2146 if (cmd->convert_src == TRIG_TIMER) {
2147 if (thisboard->layout == LAYOUT_4020) {
2148 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2150 err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
2151 thisboard->ai_speed);
2152 /* if scans are timed faster than conversion rate allows */
2153 if (cmd->scan_begin_src == TRIG_TIMER)
2154 err |= cfc_check_trigger_arg_min(
2155 &cmd->scan_begin_arg,
2161 err |= cfc_check_trigger_arg_min(&cmd->chanlist_len, 1);
2162 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
2164 switch (cmd->stop_src) {
2168 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
2171 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
2180 /* step 4: fix up any arguments */
2182 if (cmd->convert_src == TRIG_TIMER) {
2183 tmp_arg = cmd->convert_arg;
2184 tmp_arg2 = cmd->scan_begin_arg;
2185 check_adc_timing(dev, cmd);
2186 if (tmp_arg != cmd->convert_arg)
2188 if (tmp_arg2 != cmd->scan_begin_arg)
2195 /* make sure user is doesn't change analog reference mid chanlist */
2196 if (cmd->chanlist) {
2197 aref = CR_AREF(cmd->chanlist[0]);
2198 for (i = 1; i < cmd->chanlist_len; i++) {
2199 if (aref != CR_AREF(cmd->chanlist[i])) {
2201 "all elements in chanlist must use the same analog reference");
2206 /* check 4020 chanlist */
2207 if (thisboard->layout == LAYOUT_4020) {
2208 unsigned int first_channel = CR_CHAN(cmd->chanlist[0]);
2209 for (i = 1; i < cmd->chanlist_len; i++) {
2210 if (CR_CHAN(cmd->chanlist[i]) !=
2211 first_channel + i) {
2213 "chanlist must use consecutive channels");
2218 if (cmd->chanlist_len == 3) {
2220 "chanlist cannot be 3 channels long, use 1, 2, or 4 channels");
2232 static int use_hw_sample_counter(struct comedi_cmd *cmd)
2234 /* disable for now until I work out a race */
2237 if (cmd->stop_src == TRIG_COUNT && cmd->stop_arg <= max_counter_value)
2243 static void setup_sample_counters(struct comedi_device *dev,
2244 struct comedi_cmd *cmd)
2246 struct pcidas64_private *devpriv = dev->private;
2248 if (cmd->stop_src == TRIG_COUNT) {
2249 /* set software count */
2250 devpriv->ai_count = cmd->stop_arg * cmd->chanlist_len;
2252 /* load hardware conversion counter */
2253 if (use_hw_sample_counter(cmd)) {
2254 writew(cmd->stop_arg & 0xffff,
2255 devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2256 writew((cmd->stop_arg >> 16) & 0xff,
2257 devpriv->main_iobase + ADC_COUNT_UPPER_REG);
2259 writew(1, devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2263 static inline unsigned int dma_transfer_size(struct comedi_device *dev)
2265 const struct pcidas64_board *thisboard = comedi_board(dev);
2266 struct pcidas64_private *devpriv = dev->private;
2267 unsigned int num_samples;
2269 num_samples = devpriv->ai_fifo_segment_length *
2270 thisboard->ai_fifo->sample_packing_ratio;
2271 if (num_samples > DMA_BUFFER_SIZE / sizeof(uint16_t))
2272 num_samples = DMA_BUFFER_SIZE / sizeof(uint16_t);
2277 static uint32_t ai_convert_counter_6xxx(const struct comedi_device *dev,
2278 const struct comedi_cmd *cmd)
2280 /* supposed to load counter with desired divisor minus 3 */
2281 return cmd->convert_arg / TIMER_BASE - 3;
2284 static uint32_t ai_scan_counter_6xxx(struct comedi_device *dev,
2285 struct comedi_cmd *cmd)
2289 /* figure out how long we need to delay at end of scan */
2290 switch (cmd->scan_begin_src) {
2292 count = (cmd->scan_begin_arg -
2293 (cmd->convert_arg * (cmd->chanlist_len - 1))) /
2297 count = cmd->convert_arg / TIMER_BASE;
2306 static uint32_t ai_convert_counter_4020(struct comedi_device *dev,
2307 struct comedi_cmd *cmd)
2309 struct pcidas64_private *devpriv = dev->private;
2310 unsigned int divisor;
2312 switch (cmd->scan_begin_src) {
2314 divisor = cmd->scan_begin_arg / TIMER_BASE;
2317 divisor = devpriv->ext_clock.divisor;
2319 default: /* should never happen */
2320 comedi_error(dev, "bug! failed to set ai pacing!");
2325 /* supposed to load counter with desired divisor minus 2 for 4020 */
2329 static void select_master_clock_4020(struct comedi_device *dev,
2330 const struct comedi_cmd *cmd)
2332 struct pcidas64_private *devpriv = dev->private;
2334 /* select internal/external master clock */
2335 devpriv->hw_config_bits &= ~MASTER_CLOCK_4020_MASK;
2336 if (cmd->scan_begin_src == TRIG_OTHER) {
2337 int chanspec = devpriv->ext_clock.chanspec;
2339 if (CR_CHAN(chanspec))
2340 devpriv->hw_config_bits |= BNC_CLOCK_4020_BITS;
2342 devpriv->hw_config_bits |= EXT_CLOCK_4020_BITS;
2344 devpriv->hw_config_bits |= INTERNAL_CLOCK_4020_BITS;
2346 writew(devpriv->hw_config_bits,
2347 devpriv->main_iobase + HW_CONFIG_REG);
2350 static void select_master_clock(struct comedi_device *dev,
2351 const struct comedi_cmd *cmd)
2353 const struct pcidas64_board *thisboard = comedi_board(dev);
2355 switch (thisboard->layout) {
2357 select_master_clock_4020(dev, cmd);
2364 static inline void dma_start_sync(struct comedi_device *dev,
2365 unsigned int channel)
2367 struct pcidas64_private *devpriv = dev->private;
2368 unsigned long flags;
2370 /* spinlock for plx dma control/status reg */
2371 spin_lock_irqsave(&dev->spinlock, flags);
2373 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2374 PLX_CLEAR_DMA_INTR_BIT,
2375 devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2377 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2378 PLX_CLEAR_DMA_INTR_BIT,
2379 devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2380 spin_unlock_irqrestore(&dev->spinlock, flags);
2383 static void set_ai_pacing(struct comedi_device *dev, struct comedi_cmd *cmd)
2385 const struct pcidas64_board *thisboard = comedi_board(dev);
2386 struct pcidas64_private *devpriv = dev->private;
2387 uint32_t convert_counter = 0, scan_counter = 0;
2389 check_adc_timing(dev, cmd);
2391 select_master_clock(dev, cmd);
2393 if (thisboard->layout == LAYOUT_4020) {
2394 convert_counter = ai_convert_counter_4020(dev, cmd);
2396 convert_counter = ai_convert_counter_6xxx(dev, cmd);
2397 scan_counter = ai_scan_counter_6xxx(dev, cmd);
2400 /* load lower 16 bits of convert interval */
2401 writew(convert_counter & 0xffff,
2402 devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
2403 DEBUG_PRINT("convert counter 0x%x\n", convert_counter);
2404 /* load upper 8 bits of convert interval */
2405 writew((convert_counter >> 16) & 0xff,
2406 devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
2407 /* load lower 16 bits of scan delay */
2408 writew(scan_counter & 0xffff,
2409 devpriv->main_iobase + ADC_DELAY_INTERVAL_LOWER_REG);
2410 /* load upper 8 bits of scan delay */
2411 writew((scan_counter >> 16) & 0xff,
2412 devpriv->main_iobase + ADC_DELAY_INTERVAL_UPPER_REG);
2413 DEBUG_PRINT("scan counter 0x%x\n", scan_counter);
2416 static int use_internal_queue_6xxx(const struct comedi_cmd *cmd)
2420 for (i = 0; i + 1 < cmd->chanlist_len; i++) {
2421 if (CR_CHAN(cmd->chanlist[i + 1]) !=
2422 CR_CHAN(cmd->chanlist[i]) + 1)
2424 if (CR_RANGE(cmd->chanlist[i + 1]) !=
2425 CR_RANGE(cmd->chanlist[i]))
2427 if (CR_AREF(cmd->chanlist[i + 1]) != CR_AREF(cmd->chanlist[i]))
2433 static int setup_channel_queue(struct comedi_device *dev,
2434 const struct comedi_cmd *cmd)
2436 const struct pcidas64_board *thisboard = comedi_board(dev);
2437 struct pcidas64_private *devpriv = dev->private;
2438 unsigned short bits;
2441 if (thisboard->layout != LAYOUT_4020) {
2442 if (use_internal_queue_6xxx(cmd)) {
2443 devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
2444 writew(devpriv->hw_config_bits,
2445 devpriv->main_iobase + HW_CONFIG_REG);
2448 bits |= adc_chan_bits(CR_CHAN(cmd->chanlist[0]));
2450 bits |= ai_range_bits_6xxx(dev,
2451 CR_RANGE(cmd->chanlist[0]));
2452 /* set single-ended / differential */
2453 bits |= se_diff_bit_6xxx(dev,
2454 CR_AREF(cmd->chanlist[0]) ==
2456 if (CR_AREF(cmd->chanlist[0]) == AREF_COMMON)
2457 bits |= ADC_COMMON_BIT;
2458 /* set stop channel */
2459 writew(adc_chan_bits
2460 (CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1])),
2461 devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
2462 /* set start channel, and rest of settings */
2464 devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2466 /* use external queue */
2467 if (dev->write_subdev && dev->write_subdev->busy) {
2468 warn_external_queue(dev);
2471 devpriv->hw_config_bits |= EXT_QUEUE_BIT;
2472 writew(devpriv->hw_config_bits,
2473 devpriv->main_iobase + HW_CONFIG_REG);
2474 /* clear DAC buffer to prevent weird interactions */
2476 devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
2477 /* clear queue pointer */
2478 writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2479 /* load external queue */
2480 for (i = 0; i < cmd->chanlist_len; i++) {
2483 bits |= adc_chan_bits(CR_CHAN(cmd->
2486 bits |= ai_range_bits_6xxx(dev,
2490 /* set single-ended / differential */
2491 bits |= se_diff_bit_6xxx(dev,
2495 if (CR_AREF(cmd->chanlist[i]) == AREF_COMMON)
2496 bits |= ADC_COMMON_BIT;
2497 /* mark end of queue */
2498 if (i == cmd->chanlist_len - 1)
2499 bits |= QUEUE_EOSCAN_BIT |
2502 devpriv->main_iobase +
2503 ADC_QUEUE_FIFO_REG);
2505 "wrote 0x%x to external channel queue\n",
2508 /* doing a queue clear is not specified in board docs,
2509 * but required for reliable operation */
2510 writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2511 /* prime queue holding register */
2512 writew(0, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2515 unsigned short old_cal_range_bits = devpriv->i2c_cal_range_bits;
2517 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
2518 /* select BNC inputs */
2519 devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
2521 for (i = 0; i < cmd->chanlist_len; i++) {
2522 unsigned int channel = CR_CHAN(cmd->chanlist[i]);
2523 unsigned int range = CR_RANGE(cmd->chanlist[i]);
2526 devpriv->i2c_cal_range_bits |=
2527 attenuate_bit(channel);
2529 devpriv->i2c_cal_range_bits &=
2530 ~attenuate_bit(channel);
2532 /* update calibration/range i2c register only if necessary,
2533 * as it is very slow */
2534 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
2535 uint8_t i2c_data = devpriv->i2c_cal_range_bits;
2536 i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
2543 static inline void load_first_dma_descriptor(struct comedi_device *dev,
2544 unsigned int dma_channel,
2545 unsigned int descriptor_bits)
2547 struct pcidas64_private *devpriv = dev->private;
2549 /* The transfer size, pci address, and local address registers
2550 * are supposedly unused during chained dma,
2551 * but I have found that left over values from last operation
2552 * occasionally cause problems with transfer of first dma
2553 * block. Initializing them to zero seems to fix the problem. */
2556 devpriv->plx9080_iobase + PLX_DMA1_TRANSFER_SIZE_REG);
2557 writel(0, devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG);
2559 devpriv->plx9080_iobase + PLX_DMA1_LOCAL_ADDRESS_REG);
2560 writel(descriptor_bits,
2561 devpriv->plx9080_iobase + PLX_DMA1_DESCRIPTOR_REG);
2564 devpriv->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG);
2565 writel(0, devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
2567 devpriv->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG);
2568 writel(descriptor_bits,
2569 devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
2573 static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2575 const struct pcidas64_board *thisboard = comedi_board(dev);
2576 struct pcidas64_private *devpriv = dev->private;
2577 struct comedi_async *async = s->async;
2578 struct comedi_cmd *cmd = &async->cmd;
2581 unsigned long flags;
2584 disable_ai_pacing(dev);
2587 retval = setup_channel_queue(dev, cmd);
2591 /* make sure internal calibration source is turned off */
2592 writew(0, devpriv->main_iobase + CALIBRATION_REG);
2594 set_ai_pacing(dev, cmd);
2596 setup_sample_counters(dev, cmd);
2598 enable_ai_interrupts(dev, cmd);
2600 spin_lock_irqsave(&dev->spinlock, flags);
2601 /* set mode, allow conversions through software gate */
2602 devpriv->adc_control1_bits |= ADC_SW_GATE_BIT;
2603 devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
2604 if (thisboard->layout != LAYOUT_4020) {
2605 devpriv->adc_control1_bits &= ~ADC_MODE_MASK;
2606 if (cmd->convert_src == TRIG_EXT)
2607 /* good old mode 13 */
2608 devpriv->adc_control1_bits |= adc_mode_bits(13);
2610 /* mode 8. What else could you need? */
2611 devpriv->adc_control1_bits |= adc_mode_bits(8);
2613 devpriv->adc_control1_bits &= ~CHANNEL_MODE_4020_MASK;
2614 if (cmd->chanlist_len == 4)
2615 devpriv->adc_control1_bits |= FOUR_CHANNEL_4020_BITS;
2616 else if (cmd->chanlist_len == 2)
2617 devpriv->adc_control1_bits |= TWO_CHANNEL_4020_BITS;
2618 devpriv->adc_control1_bits &= ~ADC_LO_CHANNEL_4020_MASK;
2619 devpriv->adc_control1_bits |=
2620 adc_lo_chan_4020_bits(CR_CHAN(cmd->chanlist[0]));
2621 devpriv->adc_control1_bits &= ~ADC_HI_CHANNEL_4020_MASK;
2622 devpriv->adc_control1_bits |=
2623 adc_hi_chan_4020_bits(CR_CHAN(cmd->chanlist
2624 [cmd->chanlist_len - 1]));
2626 writew(devpriv->adc_control1_bits,
2627 devpriv->main_iobase + ADC_CONTROL1_REG);
2628 DEBUG_PRINT("control1 bits 0x%x\n", devpriv->adc_control1_bits);
2629 spin_unlock_irqrestore(&dev->spinlock, flags);
2631 /* clear adc buffer */
2632 writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
2634 if ((cmd->flags & TRIG_WAKE_EOS) == 0 ||
2635 thisboard->layout == LAYOUT_4020) {
2636 devpriv->ai_dma_index = 0;
2638 /* set dma transfer size */
2639 for (i = 0; i < ai_dma_ring_count(thisboard); i++)
2640 devpriv->ai_dma_desc[i].transfer_size =
2641 cpu_to_le32(dma_transfer_size(dev) *
2644 /* give location of first dma descriptor */
2645 load_first_dma_descriptor(dev, 1,
2646 devpriv->ai_dma_desc_bus_addr |
2647 PLX_DESC_IN_PCI_BIT |
2648 PLX_INTR_TERM_COUNT |
2649 PLX_XFER_LOCAL_TO_PCI);
2651 dma_start_sync(dev, 1);
2654 if (thisboard->layout == LAYOUT_4020) {
2655 /* set source for external triggers */
2657 if (cmd->start_src == TRIG_EXT && CR_CHAN(cmd->start_arg))
2658 bits |= EXT_START_TRIG_BNC_BIT;
2659 if (cmd->stop_src == TRIG_EXT && CR_CHAN(cmd->stop_arg))
2660 bits |= EXT_STOP_TRIG_BNC_BIT;
2661 writew(bits, devpriv->main_iobase + DAQ_ATRIG_LOW_4020_REG);
2664 spin_lock_irqsave(&dev->spinlock, flags);
2666 /* enable pacing, triggering, etc */
2667 bits = ADC_ENABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT;
2668 if (cmd->flags & TRIG_WAKE_EOS)
2669 bits |= ADC_DMA_DISABLE_BIT;
2670 /* set start trigger */
2671 if (cmd->start_src == TRIG_EXT) {
2672 bits |= ADC_START_TRIG_EXT_BITS;
2673 if (cmd->start_arg & CR_INVERT)
2674 bits |= ADC_START_TRIG_FALLING_BIT;
2675 } else if (cmd->start_src == TRIG_NOW)
2676 bits |= ADC_START_TRIG_SOFT_BITS;
2677 if (use_hw_sample_counter(cmd))
2678 bits |= ADC_SAMPLE_COUNTER_EN_BIT;
2679 writew(bits, devpriv->main_iobase + ADC_CONTROL0_REG);
2680 DEBUG_PRINT("control0 bits 0x%x\n", bits);
2682 devpriv->ai_cmd_running = 1;
2684 spin_unlock_irqrestore(&dev->spinlock, flags);
2686 /* start acquisition */
2687 if (cmd->start_src == TRIG_NOW) {
2688 writew(0, devpriv->main_iobase + ADC_START_REG);
2689 DEBUG_PRINT("soft trig\n");
2695 /* read num_samples from 16 bit wide ai fifo */
2696 static void pio_drain_ai_fifo_16(struct comedi_device *dev)
2698 struct pcidas64_private *devpriv = dev->private;
2699 struct comedi_subdevice *s = dev->read_subdev;
2700 struct comedi_async *async = s->async;
2701 struct comedi_cmd *cmd = &async->cmd;
2703 uint16_t prepost_bits;
2704 int read_segment, read_index, write_segment, write_index;
2708 /* get least significant 15 bits */
2709 read_index = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) &
2711 write_index = readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) &
2713 /* Get most significant bits (grey code).
2714 * Different boards use different code so use a scheme
2715 * that doesn't depend on encoding. This read must
2716 * occur after reading least significant 15 bits to avoid race
2717 * with fifo switching to next segment. */
2718 prepost_bits = readw(devpriv->main_iobase + PREPOST_REG);
2720 /* if read and write pointers are not on the same fifo segment,
2721 * read to the end of the read segment */
2722 read_segment = adc_upper_read_ptr_code(prepost_bits);
2723 write_segment = adc_upper_write_ptr_code(prepost_bits);
2725 DEBUG_PRINT(" rd seg %i, wrt seg %i, rd idx %i, wrt idx %i\n",
2726 read_segment, write_segment, read_index,
2729 if (read_segment != write_segment)
2731 devpriv->ai_fifo_segment_length - read_index;
2733 num_samples = write_index - read_index;
2735 if (cmd->stop_src == TRIG_COUNT) {
2736 if (devpriv->ai_count == 0)
2738 if (num_samples > devpriv->ai_count)
2739 num_samples = devpriv->ai_count;
2741 devpriv->ai_count -= num_samples;
2744 if (num_samples < 0) {
2745 dev_err(dev->class_dev,
2746 "cb_pcidas64: bug! num_samples < 0\n");
2750 DEBUG_PRINT(" read %i samples from fifo\n", num_samples);
2752 for (i = 0; i < num_samples; i++) {
2753 cfc_write_to_buffer(s,
2754 readw(devpriv->main_iobase +
2758 } while (read_segment != write_segment);
2761 /* Read from 32 bit wide ai fifo of 4020 - deal with insane grey coding of
2762 * pointers. The pci-4020 hardware only supports dma transfers (it only
2763 * supports the use of pio for draining the last remaining points from the
2764 * fifo when a data acquisition operation has completed).
2766 static void pio_drain_ai_fifo_32(struct comedi_device *dev)
2768 struct pcidas64_private *devpriv = dev->private;
2769 struct comedi_subdevice *s = dev->read_subdev;
2770 struct comedi_async *async = s->async;
2771 struct comedi_cmd *cmd = &async->cmd;
2773 unsigned int max_transfer = 100000;
2776 readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff;
2778 readw(devpriv->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2780 if (cmd->stop_src == TRIG_COUNT) {
2781 if (max_transfer > devpriv->ai_count)
2782 max_transfer = devpriv->ai_count;
2785 for (i = 0; read_code != write_code && i < max_transfer;) {
2786 fifo_data = readl(devpriv->dio_counter_iobase + ADC_FIFO_REG);
2787 cfc_write_to_buffer(s, fifo_data & 0xffff);
2789 if (i < max_transfer) {
2790 cfc_write_to_buffer(s, (fifo_data >> 16) & 0xffff);
2793 read_code = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) &
2796 devpriv->ai_count -= i;
2800 static void pio_drain_ai_fifo(struct comedi_device *dev)
2802 const struct pcidas64_board *thisboard = comedi_board(dev);
2804 if (thisboard->layout == LAYOUT_4020)
2805 pio_drain_ai_fifo_32(dev);
2807 pio_drain_ai_fifo_16(dev);
2810 static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
2812 const struct pcidas64_board *thisboard = comedi_board(dev);
2813 struct pcidas64_private *devpriv = dev->private;
2814 struct comedi_async *async = dev->read_subdev->async;
2815 uint32_t next_transfer_addr;
2817 int num_samples = 0;
2818 void __iomem *pci_addr_reg;
2822 devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
2825 devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
2827 /* loop until we have read all the full buffers */
2828 for (j = 0, next_transfer_addr = readl(pci_addr_reg);
2829 (next_transfer_addr <
2830 devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] ||
2831 next_transfer_addr >=
2832 devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] +
2833 DMA_BUFFER_SIZE) && j < ai_dma_ring_count(thisboard); j++) {
2834 /* transfer data from dma buffer to comedi buffer */
2835 num_samples = dma_transfer_size(dev);
2836 if (async->cmd.stop_src == TRIG_COUNT) {
2837 if (num_samples > devpriv->ai_count)
2838 num_samples = devpriv->ai_count;
2839 devpriv->ai_count -= num_samples;
2841 cfc_write_array_to_buffer(dev->read_subdev,
2842 devpriv->ai_buffer[devpriv->
2844 num_samples * sizeof(uint16_t));
2845 devpriv->ai_dma_index = (devpriv->ai_dma_index + 1) %
2846 ai_dma_ring_count(thisboard);
2848 DEBUG_PRINT("next buffer addr 0x%lx\n",
2849 (unsigned long)devpriv->
2850 ai_buffer_bus_addr[devpriv->ai_dma_index]);
2851 DEBUG_PRINT("pci addr reg 0x%x\n", next_transfer_addr);
2853 /* XXX check for dma ring buffer overrun
2854 * (use end-of-chain bit to mark last unused buffer) */
2857 static void handle_ai_interrupt(struct comedi_device *dev,
2858 unsigned short status,
2859 unsigned int plx_status)
2861 const struct pcidas64_board *thisboard = comedi_board(dev);
2862 struct pcidas64_private *devpriv = dev->private;
2863 struct comedi_subdevice *s = dev->read_subdev;
2864 struct comedi_async *async = s->async;
2865 struct comedi_cmd *cmd = &async->cmd;
2866 uint8_t dma1_status;
2867 unsigned long flags;
2869 /* check for fifo overrun */
2870 if (status & ADC_OVERRUN_BIT) {
2871 comedi_error(dev, "fifo overrun");
2872 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
2874 /* spin lock makes sure no one else changes plx dma control reg */
2875 spin_lock_irqsave(&dev->spinlock, flags);
2876 dma1_status = readb(devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2877 if (plx_status & ICS_DMA1_A) { /* dma chan 1 interrupt */
2878 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
2879 devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2880 DEBUG_PRINT("dma1 status 0x%x\n", dma1_status);
2882 if (dma1_status & PLX_DMA_EN_BIT)
2883 drain_dma_buffers(dev, 1);
2885 DEBUG_PRINT(" cleared dma ch1 interrupt\n");
2887 spin_unlock_irqrestore(&dev->spinlock, flags);
2889 if (status & ADC_DONE_BIT)
2890 DEBUG_PRINT("adc done interrupt\n");
2892 /* drain fifo with pio */
2893 if ((status & ADC_DONE_BIT) ||
2894 ((cmd->flags & TRIG_WAKE_EOS) &&
2895 (status & ADC_INTR_PENDING_BIT) &&
2896 (thisboard->layout != LAYOUT_4020))) {
2897 DEBUG_PRINT("pio fifo drain\n");
2898 spin_lock_irqsave(&dev->spinlock, flags);
2899 if (devpriv->ai_cmd_running) {
2900 spin_unlock_irqrestore(&dev->spinlock, flags);
2901 pio_drain_ai_fifo(dev);
2903 spin_unlock_irqrestore(&dev->spinlock, flags);
2905 /* if we are have all the data, then quit */
2906 if ((cmd->stop_src == TRIG_COUNT && (int)devpriv->ai_count <= 0) ||
2907 (cmd->stop_src == TRIG_EXT && (status & ADC_STOP_BIT))) {
2908 async->events |= COMEDI_CB_EOA;
2911 cfc_handle_events(dev, s);
2914 static inline unsigned int prev_ao_dma_index(struct comedi_device *dev)
2916 struct pcidas64_private *devpriv = dev->private;
2917 unsigned int buffer_index;
2919 if (devpriv->ao_dma_index == 0)
2920 buffer_index = AO_DMA_RING_COUNT - 1;
2922 buffer_index = devpriv->ao_dma_index - 1;
2923 return buffer_index;
2926 static int last_ao_dma_load_completed(struct comedi_device *dev)
2928 struct pcidas64_private *devpriv = dev->private;
2929 unsigned int buffer_index;
2930 unsigned int transfer_address;
2931 unsigned short dma_status;
2933 buffer_index = prev_ao_dma_index(dev);
2934 dma_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2935 if ((dma_status & PLX_DMA_DONE_BIT) == 0)
2939 readl(devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
2940 if (transfer_address != devpriv->ao_buffer_bus_addr[buffer_index])
2946 static int ao_stopped_by_error(struct comedi_device *dev,
2947 const struct comedi_cmd *cmd)
2949 struct pcidas64_private *devpriv = dev->private;
2951 if (cmd->stop_src == TRIG_NONE)
2953 if (cmd->stop_src == TRIG_COUNT) {
2954 if (devpriv->ao_count)
2956 if (last_ao_dma_load_completed(dev) == 0)
2962 static inline int ao_dma_needs_restart(struct comedi_device *dev,
2963 unsigned short dma_status)
2965 if ((dma_status & PLX_DMA_DONE_BIT) == 0 ||
2966 (dma_status & PLX_DMA_EN_BIT) == 0)
2968 if (last_ao_dma_load_completed(dev))
2974 static void restart_ao_dma(struct comedi_device *dev)
2976 struct pcidas64_private *devpriv = dev->private;
2977 unsigned int dma_desc_bits;
2980 readl(devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
2981 dma_desc_bits &= ~PLX_END_OF_CHAIN_BIT;
2982 DEBUG_PRINT("restarting ao dma, descriptor reg 0x%x\n", dma_desc_bits);
2983 load_first_dma_descriptor(dev, 0, dma_desc_bits);
2985 dma_start_sync(dev, 0);
2988 static unsigned int load_ao_dma_buffer(struct comedi_device *dev,
2989 const struct comedi_cmd *cmd)
2991 struct pcidas64_private *devpriv = dev->private;
2992 unsigned int num_bytes, buffer_index, prev_buffer_index;
2993 unsigned int next_bits;
2995 buffer_index = devpriv->ao_dma_index;
2996 prev_buffer_index = prev_ao_dma_index(dev);
2998 DEBUG_PRINT("attempting to load ao buffer %i (0x%llx)\n", buffer_index,
2999 (unsigned long long)devpriv->ao_buffer_bus_addr[
3002 num_bytes = comedi_buf_read_n_available(dev->write_subdev->async);
3003 if (num_bytes > DMA_BUFFER_SIZE)
3004 num_bytes = DMA_BUFFER_SIZE;
3005 if (cmd->stop_src == TRIG_COUNT && num_bytes > devpriv->ao_count)
3006 num_bytes = devpriv->ao_count;
3007 num_bytes -= num_bytes % bytes_in_sample;
3012 DEBUG_PRINT("loading %i bytes\n", num_bytes);
3014 num_bytes = cfc_read_array_from_buffer(dev->write_subdev,
3016 ao_buffer[buffer_index],
3018 devpriv->ao_dma_desc[buffer_index].transfer_size =
3019 cpu_to_le32(num_bytes);
3020 /* set end of chain bit so we catch underruns */
3021 next_bits = le32_to_cpu(devpriv->ao_dma_desc[buffer_index].next);
3022 next_bits |= PLX_END_OF_CHAIN_BIT;
3023 devpriv->ao_dma_desc[buffer_index].next = cpu_to_le32(next_bits);
3024 /* clear end of chain bit on previous buffer now that we have set it
3025 * for the last buffer */
3026 next_bits = le32_to_cpu(devpriv->ao_dma_desc[prev_buffer_index].next);
3027 next_bits &= ~PLX_END_OF_CHAIN_BIT;
3028 devpriv->ao_dma_desc[prev_buffer_index].next = cpu_to_le32(next_bits);
3030 devpriv->ao_dma_index = (buffer_index + 1) % AO_DMA_RING_COUNT;
3031 devpriv->ao_count -= num_bytes;
3036 static void load_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3038 struct pcidas64_private *devpriv = dev->private;
3039 unsigned int num_bytes;
3040 unsigned int next_transfer_addr;
3041 void __iomem *pci_addr_reg =
3042 devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
3043 unsigned int buffer_index;
3046 buffer_index = devpriv->ao_dma_index;
3047 /* don't overwrite data that hasn't been transferred yet */
3048 next_transfer_addr = readl(pci_addr_reg);
3049 if (next_transfer_addr >=
3050 devpriv->ao_buffer_bus_addr[buffer_index] &&
3051 next_transfer_addr <
3052 devpriv->ao_buffer_bus_addr[buffer_index] +
3055 num_bytes = load_ao_dma_buffer(dev, cmd);
3056 } while (num_bytes >= DMA_BUFFER_SIZE);
3059 static void handle_ao_interrupt(struct comedi_device *dev,
3060 unsigned short status, unsigned int plx_status)
3062 struct pcidas64_private *devpriv = dev->private;
3063 struct comedi_subdevice *s = dev->write_subdev;
3064 struct comedi_async *async;
3065 struct comedi_cmd *cmd;
3066 uint8_t dma0_status;
3067 unsigned long flags;
3069 /* board might not support ao, in which case write_subdev is NULL */
3075 /* spin lock makes sure no one else changes plx dma control reg */
3076 spin_lock_irqsave(&dev->spinlock, flags);
3077 dma0_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
3078 if (plx_status & ICS_DMA0_A) { /* dma chan 0 interrupt */
3079 if ((dma0_status & PLX_DMA_EN_BIT) &&
3080 !(dma0_status & PLX_DMA_DONE_BIT))
3081 writeb(PLX_DMA_EN_BIT | PLX_CLEAR_DMA_INTR_BIT,
3082 devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
3084 writeb(PLX_CLEAR_DMA_INTR_BIT,
3085 devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
3086 spin_unlock_irqrestore(&dev->spinlock, flags);
3087 DEBUG_PRINT("dma0 status 0x%x\n", dma0_status);
3088 if (dma0_status & PLX_DMA_EN_BIT) {
3089 load_ao_dma(dev, cmd);
3090 /* try to recover from dma end-of-chain event */
3091 if (ao_dma_needs_restart(dev, dma0_status))
3092 restart_ao_dma(dev);
3094 DEBUG_PRINT(" cleared dma ch0 interrupt\n");
3096 spin_unlock_irqrestore(&dev->spinlock, flags);
3099 if ((status & DAC_DONE_BIT)) {
3100 async->events |= COMEDI_CB_EOA;
3101 if (ao_stopped_by_error(dev, cmd))
3102 async->events |= COMEDI_CB_ERROR;
3103 DEBUG_PRINT("plx dma0 desc reg 0x%x\n",
3104 readl(devpriv->plx9080_iobase +
3105 PLX_DMA0_DESCRIPTOR_REG));
3106 DEBUG_PRINT("plx dma0 address reg 0x%x\n",
3107 readl(devpriv->plx9080_iobase +
3108 PLX_DMA0_PCI_ADDRESS_REG));
3110 cfc_handle_events(dev, s);
3113 static irqreturn_t handle_interrupt(int irq, void *d)
3115 struct comedi_device *dev = d;
3116 struct pcidas64_private *devpriv = dev->private;
3117 unsigned short status;
3118 uint32_t plx_status;
3121 plx_status = readl(devpriv->plx9080_iobase + PLX_INTRCS_REG);
3122 status = readw(devpriv->main_iobase + HW_STATUS_REG);
3124 DEBUG_PRINT("hw status 0x%x, plx status 0x%x\n", status, plx_status);
3126 /* an interrupt before all the postconfig stuff gets done could
3127 * cause a NULL dereference if we continue through the
3128 * interrupt handler */
3129 if (!dev->attached) {
3130 DEBUG_PRINT("premature interrupt, ignoring\n");
3133 handle_ai_interrupt(dev, status, plx_status);
3134 handle_ao_interrupt(dev, status, plx_status);
3136 /* clear possible plx9080 interrupt sources */
3137 if (plx_status & ICS_LDIA) { /* clear local doorbell interrupt */
3138 plx_bits = readl(devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
3139 writel(plx_bits, devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
3140 DEBUG_PRINT(" cleared local doorbell bits 0x%x\n", plx_bits);
3143 DEBUG_PRINT("exiting handler\n");
3148 static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3150 struct pcidas64_private *devpriv = dev->private;
3151 unsigned long flags;
3153 spin_lock_irqsave(&dev->spinlock, flags);
3154 if (devpriv->ai_cmd_running == 0) {
3155 spin_unlock_irqrestore(&dev->spinlock, flags);
3158 devpriv->ai_cmd_running = 0;
3159 spin_unlock_irqrestore(&dev->spinlock, flags);
3161 disable_ai_pacing(dev);
3165 DEBUG_PRINT("ai canceled\n");
3169 static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
3170 struct comedi_insn *insn, unsigned int *data)
3172 const struct pcidas64_board *thisboard = comedi_board(dev);
3173 struct pcidas64_private *devpriv = dev->private;
3174 int chan = CR_CHAN(insn->chanspec);
3175 int range = CR_RANGE(insn->chanspec);
3177 /* do some initializing */
3178 writew(0, devpriv->main_iobase + DAC_CONTROL0_REG);
3181 set_dac_range_bits(dev, &devpriv->dac_control1_bits, chan, range);
3182 writew(devpriv->dac_control1_bits,
3183 devpriv->main_iobase + DAC_CONTROL1_REG);
3185 /* write to channel */
3186 if (thisboard->layout == LAYOUT_4020) {
3187 writew(data[0] & 0xff,
3188 devpriv->main_iobase + dac_lsb_4020_reg(chan));
3189 writew((data[0] >> 8) & 0xf,
3190 devpriv->main_iobase + dac_msb_4020_reg(chan));
3192 writew(data[0], devpriv->main_iobase + dac_convert_reg(chan));
3195 /* remember output value */
3196 devpriv->ao_value[chan] = data[0];
3201 static int ao_readback_insn(struct comedi_device *dev,
3202 struct comedi_subdevice *s,
3203 struct comedi_insn *insn, unsigned int *data)
3205 struct pcidas64_private *devpriv = dev->private;
3207 data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)];
3212 static void set_dac_control0_reg(struct comedi_device *dev,
3213 const struct comedi_cmd *cmd)
3215 struct pcidas64_private *devpriv = dev->private;
3216 unsigned int bits = DAC_ENABLE_BIT | WAVEFORM_GATE_LEVEL_BIT |
3217 WAVEFORM_GATE_ENABLE_BIT | WAVEFORM_GATE_SELECT_BIT;
3219 if (cmd->start_src == TRIG_EXT) {
3220 bits |= WAVEFORM_TRIG_EXT_BITS;
3221 if (cmd->start_arg & CR_INVERT)
3222 bits |= WAVEFORM_TRIG_FALLING_BIT;
3224 bits |= WAVEFORM_TRIG_SOFT_BITS;
3226 if (cmd->scan_begin_src == TRIG_EXT) {
3227 bits |= DAC_EXT_UPDATE_ENABLE_BIT;
3228 if (cmd->scan_begin_arg & CR_INVERT)
3229 bits |= DAC_EXT_UPDATE_FALLING_BIT;
3231 writew(bits, devpriv->main_iobase + DAC_CONTROL0_REG);
3234 static void set_dac_control1_reg(struct comedi_device *dev,
3235 const struct comedi_cmd *cmd)
3237 struct pcidas64_private *devpriv = dev->private;
3240 for (i = 0; i < cmd->chanlist_len; i++) {
3243 channel = CR_CHAN(cmd->chanlist[i]);
3244 range = CR_RANGE(cmd->chanlist[i]);
3245 set_dac_range_bits(dev, &devpriv->dac_control1_bits, channel,
3248 devpriv->dac_control1_bits |= DAC_SW_GATE_BIT;
3249 writew(devpriv->dac_control1_bits,
3250 devpriv->main_iobase + DAC_CONTROL1_REG);
3253 static void set_dac_select_reg(struct comedi_device *dev,
3254 const struct comedi_cmd *cmd)
3256 struct pcidas64_private *devpriv = dev->private;
3258 unsigned int first_channel, last_channel;
3260 first_channel = CR_CHAN(cmd->chanlist[0]);
3261 last_channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
3262 if (last_channel < first_channel)
3263 comedi_error(dev, "bug! last ao channel < first ao channel");
3265 bits = (first_channel & 0x7) | (last_channel & 0x7) << 3;
3267 writew(bits, devpriv->main_iobase + DAC_SELECT_REG);
3270 static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags)
3272 return get_divisor(ns, flags) - 2;
3275 static void set_dac_interval_regs(struct comedi_device *dev,
3276 const struct comedi_cmd *cmd)
3278 struct pcidas64_private *devpriv = dev->private;
3279 unsigned int divisor;
3281 if (cmd->scan_begin_src != TRIG_TIMER)
3284 divisor = get_ao_divisor(cmd->scan_begin_arg, cmd->flags);
3285 if (divisor > max_counter_value) {
3286 comedi_error(dev, "bug! ao divisor too big");
3287 divisor = max_counter_value;
3289 writew(divisor & 0xffff,
3290 devpriv->main_iobase + DAC_SAMPLE_INTERVAL_LOWER_REG);
3291 writew((divisor >> 16) & 0xff,
3292 devpriv->main_iobase + DAC_SAMPLE_INTERVAL_UPPER_REG);
3295 static int prep_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3297 struct pcidas64_private *devpriv = dev->private;
3298 unsigned int num_bytes;
3301 /* clear queue pointer too, since external queue has
3302 * weird interactions with ao fifo */
3303 writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
3304 writew(0, devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
3306 num_bytes = (DAC_FIFO_SIZE / 2) * bytes_in_sample;
3307 if (cmd->stop_src == TRIG_COUNT &&
3308 num_bytes / bytes_in_sample > devpriv->ao_count)
3309 num_bytes = devpriv->ao_count * bytes_in_sample;
3310 num_bytes = cfc_read_array_from_buffer(dev->write_subdev,
3311 devpriv->ao_bounce_buffer,
3313 for (i = 0; i < num_bytes / bytes_in_sample; i++) {
3314 writew(devpriv->ao_bounce_buffer[i],
3315 devpriv->main_iobase + DAC_FIFO_REG);
3317 devpriv->ao_count -= num_bytes / bytes_in_sample;
3318 if (cmd->stop_src == TRIG_COUNT && devpriv->ao_count == 0)
3320 num_bytes = load_ao_dma_buffer(dev, cmd);
3323 load_ao_dma(dev, cmd);
3325 dma_start_sync(dev, 0);
3330 static inline int external_ai_queue_in_use(struct comedi_device *dev)
3332 const struct pcidas64_board *thisboard = comedi_board(dev);
3334 if (dev->read_subdev->busy)
3336 if (thisboard->layout == LAYOUT_4020)
3338 else if (use_internal_queue_6xxx(&dev->read_subdev->async->cmd))
3343 static int ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3344 unsigned int trig_num)
3346 struct pcidas64_private *devpriv = dev->private;
3347 struct comedi_cmd *cmd = &s->async->cmd;
3353 retval = prep_ao_dma(dev, cmd);
3357 set_dac_control0_reg(dev, cmd);
3359 if (cmd->start_src == TRIG_INT)
3360 writew(0, devpriv->main_iobase + DAC_START_REG);
3362 s->async->inttrig = NULL;
3367 static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3369 struct pcidas64_private *devpriv = dev->private;
3370 struct comedi_cmd *cmd = &s->async->cmd;
3372 if (external_ai_queue_in_use(dev)) {
3373 warn_external_queue(dev);
3376 /* disable analog output system during setup */
3377 writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3379 devpriv->ao_dma_index = 0;
3380 devpriv->ao_count = cmd->stop_arg * cmd->chanlist_len;
3382 set_dac_select_reg(dev, cmd);
3383 set_dac_interval_regs(dev, cmd);
3384 load_first_dma_descriptor(dev, 0, devpriv->ao_dma_desc_bus_addr |
3385 PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT);
3387 set_dac_control1_reg(dev, cmd);
3388 s->async->inttrig = ao_inttrig;
3393 static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3394 struct comedi_cmd *cmd)
3396 const struct pcidas64_board *thisboard = comedi_board(dev);
3398 unsigned int tmp_arg;
3401 /* Step 1 : check if triggers are trivially valid */
3403 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3404 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
3405 TRIG_TIMER | TRIG_EXT);
3406 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3407 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3408 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3413 /* Step 2a : make sure trigger sources are unique */
3415 err |= cfc_check_trigger_is_unique(cmd->start_src);
3416 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
3418 /* Step 2b : and mutually compatible */
3420 if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
3422 if (cmd->stop_src != TRIG_COUNT &&
3423 cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
3429 /* Step 3: check if arguments are trivially valid */
3431 if (cmd->scan_begin_src == TRIG_TIMER) {
3432 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
3433 thisboard->ao_scan_speed);
3434 if (get_ao_divisor(cmd->scan_begin_arg, cmd->flags) >
3435 max_counter_value) {
3436 cmd->scan_begin_arg = (max_counter_value + 2) *
3442 err |= cfc_check_trigger_arg_min(&cmd->chanlist_len, 1);
3443 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3448 /* step 4: fix up any arguments */
3450 if (cmd->scan_begin_src == TRIG_TIMER) {
3451 tmp_arg = cmd->scan_begin_arg;
3452 cmd->scan_begin_arg = get_divisor(cmd->scan_begin_arg,
3453 cmd->flags) * TIMER_BASE;
3454 if (tmp_arg != cmd->scan_begin_arg)
3461 if (cmd->chanlist) {
3462 unsigned int first_channel = CR_CHAN(cmd->chanlist[0]);
3463 for (i = 1; i < cmd->chanlist_len; i++) {
3464 if (CR_CHAN(cmd->chanlist[i]) != first_channel + i) {
3466 "chanlist must use consecutive channels");
3479 static int ao_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3481 struct pcidas64_private *devpriv = dev->private;
3483 writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3488 static int dio_callback(int dir, int port, int data, unsigned long arg)
3490 void __iomem *iobase = (void __iomem *)arg;
3492 writeb(data, iobase + port);
3493 DEBUG_PRINT("wrote 0x%x to port %i\n", data, port);
3496 return readb(iobase + port);
3500 static int dio_callback_4020(int dir, int port, int data, unsigned long arg)
3502 void __iomem *iobase = (void __iomem *)arg;
3504 writew(data, iobase + 2 * port);
3507 return readw(iobase + 2 * port);
3511 static int di_rbits(struct comedi_device *dev, struct comedi_subdevice *s,
3512 struct comedi_insn *insn, unsigned int *data)
3514 struct pcidas64_private *devpriv = dev->private;
3517 bits = readb(devpriv->dio_counter_iobase + DI_REG);
3525 static int do_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
3526 struct comedi_insn *insn, unsigned int *data)
3528 struct pcidas64_private *devpriv = dev->private;
3531 /* zero bits we are going to change */
3532 s->state &= ~data[0];
3534 s->state |= data[0] & data[1];
3536 writeb(s->state, devpriv->dio_counter_iobase + DO_REG);
3543 static int dio_60xx_config_insn(struct comedi_device *dev,
3544 struct comedi_subdevice *s,
3545 struct comedi_insn *insn, unsigned int *data)
3547 struct pcidas64_private *devpriv = dev->private;
3550 mask = 1 << CR_CHAN(insn->chanspec);
3553 case INSN_CONFIG_DIO_INPUT:
3554 s->io_bits &= ~mask;
3556 case INSN_CONFIG_DIO_OUTPUT:
3559 case INSN_CONFIG_DIO_QUERY:
3560 data[1] = (s->io_bits & mask) ? COMEDI_OUTPUT : COMEDI_INPUT;
3567 devpriv->dio_counter_iobase + DIO_DIRECTION_60XX_REG);
3572 static int dio_60xx_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
3573 struct comedi_insn *insn, unsigned int *data)
3575 struct pcidas64_private *devpriv = dev->private;
3578 s->state &= ~data[0];
3579 s->state |= (data[0] & data[1]);
3581 devpriv->dio_counter_iobase + DIO_DATA_60XX_REG);
3584 data[1] = readb(devpriv->dio_counter_iobase + DIO_DATA_60XX_REG);
3589 /* pci-6025 8800 caldac:
3590 * address 0 == dac channel 0 offset
3591 * address 1 == dac channel 0 gain
3592 * address 2 == dac channel 1 offset
3593 * address 3 == dac channel 1 gain
3594 * address 4 == fine adc offset
3595 * address 5 == coarse adc offset
3596 * address 6 == coarse adc gain
3597 * address 7 == fine adc gain
3599 /* pci-6402/16 uses all 8 channels for dac:
3600 * address 0 == dac channel 0 fine gain
3601 * address 1 == dac channel 0 coarse gain
3602 * address 2 == dac channel 0 coarse offset
3603 * address 3 == dac channel 1 coarse offset
3604 * address 4 == dac channel 1 fine gain
3605 * address 5 == dac channel 1 coarse gain
3606 * address 6 == dac channel 0 fine offset
3607 * address 7 == dac channel 1 fine offset
3610 static int caldac_8800_write(struct comedi_device *dev, unsigned int address,
3613 struct pcidas64_private *devpriv = dev->private;
3614 static const int num_caldac_channels = 8;
3615 static const int bitstream_length = 11;
3616 unsigned int bitstream = ((address & 0x7) << 8) | value;
3617 unsigned int bit, register_bits;
3618 static const int caldac_8800_udelay = 1;
3620 if (address >= num_caldac_channels) {
3621 comedi_error(dev, "illegal caldac channel");
3624 for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3626 if (bitstream & bit)
3627 register_bits |= SERIAL_DATA_IN_BIT;
3628 udelay(caldac_8800_udelay);
3629 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3630 register_bits |= SERIAL_CLOCK_BIT;
3631 udelay(caldac_8800_udelay);
3632 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3634 udelay(caldac_8800_udelay);
3635 writew(SELECT_8800_BIT, devpriv->main_iobase + CALIBRATION_REG);
3636 udelay(caldac_8800_udelay);
3637 writew(0, devpriv->main_iobase + CALIBRATION_REG);
3638 udelay(caldac_8800_udelay);
3643 static int caldac_i2c_write(struct comedi_device *dev,
3644 unsigned int caldac_channel, unsigned int value)
3646 uint8_t serial_bytes[3];
3649 /* manual has gain and offset bits switched */
3656 NOT_CLEAR_REGISTERS = 0x20,
3659 switch (caldac_channel) {
3660 case 0: /* chan 0 offset */
3661 i2c_addr = CALDAC0_I2C_ADDR;
3662 serial_bytes[0] = OFFSET_0_2;
3664 case 1: /* chan 1 offset */
3665 i2c_addr = CALDAC0_I2C_ADDR;
3666 serial_bytes[0] = OFFSET_1_3;
3668 case 2: /* chan 2 offset */
3669 i2c_addr = CALDAC1_I2C_ADDR;
3670 serial_bytes[0] = OFFSET_0_2;
3672 case 3: /* chan 3 offset */
3673 i2c_addr = CALDAC1_I2C_ADDR;
3674 serial_bytes[0] = OFFSET_1_3;
3676 case 4: /* chan 0 gain */
3677 i2c_addr = CALDAC0_I2C_ADDR;
3678 serial_bytes[0] = GAIN_0_2;
3680 case 5: /* chan 1 gain */
3681 i2c_addr = CALDAC0_I2C_ADDR;
3682 serial_bytes[0] = GAIN_1_3;
3684 case 6: /* chan 2 gain */
3685 i2c_addr = CALDAC1_I2C_ADDR;
3686 serial_bytes[0] = GAIN_0_2;
3688 case 7: /* chan 3 gain */
3689 i2c_addr = CALDAC1_I2C_ADDR;
3690 serial_bytes[0] = GAIN_1_3;
3693 comedi_error(dev, "invalid caldac channel\n");
3697 serial_bytes[1] = NOT_CLEAR_REGISTERS | ((value >> 8) & 0xf);
3698 serial_bytes[2] = value & 0xff;
3699 i2c_write(dev, i2c_addr, serial_bytes, 3);
3703 static void caldac_write(struct comedi_device *dev, unsigned int channel,
3706 const struct pcidas64_board *thisboard = comedi_board(dev);
3707 struct pcidas64_private *devpriv = dev->private;
3709 devpriv->caldac_state[channel] = value;
3711 switch (thisboard->layout) {
3714 caldac_8800_write(dev, channel, value);
3717 caldac_i2c_write(dev, channel, value);
3724 static int calib_write_insn(struct comedi_device *dev,
3725 struct comedi_subdevice *s,
3726 struct comedi_insn *insn, unsigned int *data)
3728 struct pcidas64_private *devpriv = dev->private;
3729 int channel = CR_CHAN(insn->chanspec);
3731 /* return immediately if setting hasn't changed, since
3732 * programming these things is slow */
3733 if (devpriv->caldac_state[channel] == data[0])
3736 caldac_write(dev, channel, data[0]);
3741 static int calib_read_insn(struct comedi_device *dev,
3742 struct comedi_subdevice *s, struct comedi_insn *insn,
3745 struct pcidas64_private *devpriv = dev->private;
3746 unsigned int channel = CR_CHAN(insn->chanspec);
3748 data[0] = devpriv->caldac_state[channel];
3753 static void ad8402_write(struct comedi_device *dev, unsigned int channel,
3756 struct pcidas64_private *devpriv = dev->private;
3757 static const int bitstream_length = 10;
3758 unsigned int bit, register_bits;
3759 unsigned int bitstream = ((channel & 0x3) << 8) | (value & 0xff);
3760 static const int ad8402_udelay = 1;
3762 devpriv->ad8402_state[channel] = value;
3764 register_bits = SELECT_8402_64XX_BIT;
3765 udelay(ad8402_udelay);
3766 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3768 for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3769 if (bitstream & bit)
3770 register_bits |= SERIAL_DATA_IN_BIT;
3772 register_bits &= ~SERIAL_DATA_IN_BIT;
3773 udelay(ad8402_udelay);
3774 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3775 udelay(ad8402_udelay);
3776 writew(register_bits | SERIAL_CLOCK_BIT,
3777 devpriv->main_iobase + CALIBRATION_REG);
3780 udelay(ad8402_udelay);
3781 writew(0, devpriv->main_iobase + CALIBRATION_REG);
3784 /* for pci-das6402/16, channel 0 is analog input gain and channel 1 is offset */
3785 static int ad8402_write_insn(struct comedi_device *dev,
3786 struct comedi_subdevice *s,
3787 struct comedi_insn *insn, unsigned int *data)
3789 struct pcidas64_private *devpriv = dev->private;
3790 int channel = CR_CHAN(insn->chanspec);
3792 /* return immediately if setting hasn't changed, since
3793 * programming these things is slow */
3794 if (devpriv->ad8402_state[channel] == data[0])
3797 devpriv->ad8402_state[channel] = data[0];
3799 ad8402_write(dev, channel, data[0]);
3804 static int ad8402_read_insn(struct comedi_device *dev,
3805 struct comedi_subdevice *s,
3806 struct comedi_insn *insn, unsigned int *data)
3808 struct pcidas64_private *devpriv = dev->private;
3809 unsigned int channel = CR_CHAN(insn->chanspec);
3811 data[0] = devpriv->ad8402_state[channel];
3816 static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address)
3818 struct pcidas64_private *devpriv = dev->private;
3819 static const int bitstream_length = 11;
3820 static const int read_command = 0x6;
3821 unsigned int bitstream = (read_command << 8) | address;
3823 void __iomem * const plx_control_addr =
3824 devpriv->plx9080_iobase + PLX_CONTROL_REG;
3826 static const int value_length = 16;
3827 static const int eeprom_udelay = 1;
3829 udelay(eeprom_udelay);
3830 devpriv->plx_control_bits &= ~CTL_EE_CLK & ~CTL_EE_CS;
3831 /* make sure we don't send anything to the i2c bus on 4020 */
3832 devpriv->plx_control_bits |= CTL_USERO;
3833 writel(devpriv->plx_control_bits, plx_control_addr);
3834 /* activate serial eeprom */
3835 udelay(eeprom_udelay);
3836 devpriv->plx_control_bits |= CTL_EE_CS;
3837 writel(devpriv->plx_control_bits, plx_control_addr);
3839 /* write read command and desired memory address */
3840 for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3841 /* set bit to be written */
3842 udelay(eeprom_udelay);
3843 if (bitstream & bit)
3844 devpriv->plx_control_bits |= CTL_EE_W;
3846 devpriv->plx_control_bits &= ~CTL_EE_W;
3847 writel(devpriv->plx_control_bits, plx_control_addr);
3849 udelay(eeprom_udelay);
3850 devpriv->plx_control_bits |= CTL_EE_CLK;
3851 writel(devpriv->plx_control_bits, plx_control_addr);
3852 udelay(eeprom_udelay);
3853 devpriv->plx_control_bits &= ~CTL_EE_CLK;
3854 writel(devpriv->plx_control_bits, plx_control_addr);
3856 /* read back value from eeprom memory location */
3858 for (bit = 1 << (value_length - 1); bit; bit >>= 1) {
3860 udelay(eeprom_udelay);
3861 devpriv->plx_control_bits |= CTL_EE_CLK;
3862 writel(devpriv->plx_control_bits, plx_control_addr);
3863 udelay(eeprom_udelay);
3864 devpriv->plx_control_bits &= ~CTL_EE_CLK;
3865 writel(devpriv->plx_control_bits, plx_control_addr);
3866 udelay(eeprom_udelay);
3867 if (readl(plx_control_addr) & CTL_EE_R)
3871 /* deactivate eeprom serial input */
3872 udelay(eeprom_udelay);
3873 devpriv->plx_control_bits &= ~CTL_EE_CS;
3874 writel(devpriv->plx_control_bits, plx_control_addr);
3879 static int eeprom_read_insn(struct comedi_device *dev,
3880 struct comedi_subdevice *s,
3881 struct comedi_insn *insn, unsigned int *data)
3883 data[0] = read_eeprom(dev, CR_CHAN(insn->chanspec));
3888 /* Allocate and initialize the subdevice structures.
3890 static int setup_subdevices(struct comedi_device *dev)
3892 const struct pcidas64_board *thisboard = comedi_board(dev);
3893 struct pcidas64_private *devpriv = dev->private;
3894 struct comedi_subdevice *s;
3895 void __iomem *dio_8255_iobase;
3899 ret = comedi_alloc_subdevices(dev, 10);
3903 s = &dev->subdevices[0];
3904 /* analog input subdevice */
3905 dev->read_subdev = s;
3906 s->type = COMEDI_SUBD_AI;
3907 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DITHER | SDF_CMD_READ;
3908 if (thisboard->layout == LAYOUT_60XX)
3909 s->subdev_flags |= SDF_COMMON | SDF_DIFF;
3910 else if (thisboard->layout == LAYOUT_64XX)
3911 s->subdev_flags |= SDF_DIFF;
3912 /* XXX Number of inputs in differential mode is ignored */
3913 s->n_chan = thisboard->ai_se_chans;
3914 s->len_chanlist = 0x2000;
3915 s->maxdata = (1 << thisboard->ai_bits) - 1;
3916 s->range_table = thisboard->ai_range_table;
3917 s->insn_read = ai_rinsn;
3918 s->insn_config = ai_config_insn;
3920 s->do_cmdtest = ai_cmdtest;
3921 s->cancel = ai_cancel;
3922 if (thisboard->layout == LAYOUT_4020) {
3924 /* set adc to read from inputs
3925 * (not internal calibration sources) */
3926 devpriv->i2c_cal_range_bits = adc_src_4020_bits(4);
3927 /* set channels to +-5 volt input ranges */
3928 for (i = 0; i < s->n_chan; i++)
3929 devpriv->i2c_cal_range_bits |= attenuate_bit(i);
3930 data = devpriv->i2c_cal_range_bits;
3931 i2c_write(dev, RANGE_CAL_I2C_ADDR, &data, sizeof(data));
3934 /* analog output subdevice */
3935 s = &dev->subdevices[1];
3936 if (thisboard->ao_nchan) {
3937 s->type = COMEDI_SUBD_AO;
3938 s->subdev_flags = SDF_READABLE | SDF_WRITABLE |
3939 SDF_GROUND | SDF_CMD_WRITE;
3940 s->n_chan = thisboard->ao_nchan;
3941 s->maxdata = (1 << thisboard->ao_bits) - 1;
3942 s->range_table = thisboard->ao_range_table;
3943 s->insn_read = ao_readback_insn;
3944 s->insn_write = ao_winsn;
3945 if (ao_cmd_is_supported(thisboard)) {
3946 dev->write_subdev = s;
3947 s->do_cmdtest = ao_cmdtest;
3949 s->len_chanlist = thisboard->ao_nchan;
3950 s->cancel = ao_cancel;
3953 s->type = COMEDI_SUBD_UNUSED;
3957 s = &dev->subdevices[2];
3958 if (thisboard->layout == LAYOUT_64XX) {
3959 s->type = COMEDI_SUBD_DI;
3960 s->subdev_flags = SDF_READABLE;
3963 s->range_table = &range_digital;
3964 s->insn_bits = di_rbits;
3966 s->type = COMEDI_SUBD_UNUSED;
3968 /* digital output */
3969 if (thisboard->layout == LAYOUT_64XX) {
3970 s = &dev->subdevices[3];
3971 s->type = COMEDI_SUBD_DO;
3972 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
3975 s->range_table = &range_digital;
3976 s->insn_bits = do_wbits;
3978 s->type = COMEDI_SUBD_UNUSED;
3981 s = &dev->subdevices[4];
3982 if (thisboard->has_8255) {
3983 if (thisboard->layout == LAYOUT_4020) {
3984 dio_8255_iobase = devpriv->main_iobase + I8255_4020_REG;
3985 subdev_8255_init(dev, s, dio_callback_4020,
3986 (unsigned long)dio_8255_iobase);
3989 devpriv->dio_counter_iobase + DIO_8255_OFFSET;
3990 subdev_8255_init(dev, s, dio_callback,
3991 (unsigned long)dio_8255_iobase);
3994 s->type = COMEDI_SUBD_UNUSED;
3996 /* 8 channel dio for 60xx */
3997 s = &dev->subdevices[5];
3998 if (thisboard->layout == LAYOUT_60XX) {
3999 s->type = COMEDI_SUBD_DIO;
4000 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
4003 s->range_table = &range_digital;
4004 s->insn_config = dio_60xx_config_insn;
4005 s->insn_bits = dio_60xx_wbits;
4007 s->type = COMEDI_SUBD_UNUSED;
4010 s = &dev->subdevices[6];
4011 s->type = COMEDI_SUBD_CALIB;
4012 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4014 if (thisboard->layout == LAYOUT_4020)
4018 s->insn_read = calib_read_insn;
4019 s->insn_write = calib_write_insn;
4020 for (i = 0; i < s->n_chan; i++)
4021 caldac_write(dev, i, s->maxdata / 2);
4023 /* 2 channel ad8402 potentiometer */
4024 s = &dev->subdevices[7];
4025 if (thisboard->layout == LAYOUT_64XX) {
4026 s->type = COMEDI_SUBD_CALIB;
4027 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4029 s->insn_read = ad8402_read_insn;
4030 s->insn_write = ad8402_write_insn;
4032 for (i = 0; i < s->n_chan; i++)
4033 ad8402_write(dev, i, s->maxdata / 2);
4035 s->type = COMEDI_SUBD_UNUSED;
4037 /* serial EEPROM, if present */
4038 s = &dev->subdevices[8];
4039 if (readl(devpriv->plx9080_iobase + PLX_CONTROL_REG) & CTL_EECHK) {
4040 s->type = COMEDI_SUBD_MEMORY;
4041 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
4043 s->maxdata = 0xffff;
4044 s->insn_read = eeprom_read_insn;
4046 s->type = COMEDI_SUBD_UNUSED;
4048 /* user counter subd XXX */
4049 s = &dev->subdevices[9];
4050 s->type = COMEDI_SUBD_UNUSED;
4055 static int auto_attach(struct comedi_device *dev,
4056 unsigned long context)
4058 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
4059 const struct pcidas64_board *thisboard = NULL;
4060 struct pcidas64_private *devpriv;
4061 uint32_t local_range, local_decode;
4064 if (context < ARRAY_SIZE(pcidas64_boards))
4065 thisboard = &pcidas64_boards[context];
4068 dev->board_ptr = thisboard;
4070 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
4073 dev->private = devpriv;
4075 retval = comedi_pci_enable(dev);
4078 pci_set_master(pcidev);
4080 /* Initialize dev->board_name */
4081 dev->board_name = thisboard->name;
4083 devpriv->main_phys_iobase = pci_resource_start(pcidev, 2);
4084 devpriv->dio_counter_phys_iobase = pci_resource_start(pcidev, 3);
4086 devpriv->plx9080_iobase = pci_ioremap_bar(pcidev, 0);
4087 devpriv->main_iobase = pci_ioremap_bar(pcidev, 2);
4088 devpriv->dio_counter_iobase = pci_ioremap_bar(pcidev, 3);
4090 if (!devpriv->plx9080_iobase || !devpriv->main_iobase
4091 || !devpriv->dio_counter_iobase) {
4092 dev_warn(dev->class_dev, "failed to remap io memory\n");
4096 DEBUG_PRINT(" plx9080 remapped to 0x%p\n", devpriv->plx9080_iobase);
4097 DEBUG_PRINT(" main remapped to 0x%p\n", devpriv->main_iobase);
4098 DEBUG_PRINT(" diocounter remapped to 0x%p\n",
4099 devpriv->dio_counter_iobase);
4101 /* figure out what local addresses are */
4102 local_range = readl(devpriv->plx9080_iobase + PLX_LAS0RNG_REG) &
4104 local_decode = readl(devpriv->plx9080_iobase + PLX_LAS0MAP_REG) &
4105 local_range & LMAP_MEM_MASK;
4106 devpriv->local0_iobase = ((uint32_t)devpriv->main_phys_iobase &
4107 ~local_range) | local_decode;
4108 local_range = readl(devpriv->plx9080_iobase + PLX_LAS1RNG_REG) &
4110 local_decode = readl(devpriv->plx9080_iobase + PLX_LAS1MAP_REG) &
4111 local_range & LMAP_MEM_MASK;
4112 devpriv->local1_iobase = ((uint32_t)devpriv->dio_counter_phys_iobase &
4113 ~local_range) | local_decode;
4115 DEBUG_PRINT(" local 0 io addr 0x%x\n", devpriv->local0_iobase);
4116 DEBUG_PRINT(" local 1 io addr 0x%x\n", devpriv->local1_iobase);
4118 retval = alloc_and_init_dma_members(dev);
4122 devpriv->hw_revision =
4123 hw_revision(dev, readw(devpriv->main_iobase + HW_STATUS_REG));
4124 dev_dbg(dev->class_dev, "stc hardware revision %i\n",
4125 devpriv->hw_revision);
4127 init_stc_registers(dev);
4129 if (request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
4130 "cb_pcidas64", dev)) {
4131 dev_dbg(dev->class_dev, "unable to allocate irq %u\n",
4135 dev->irq = pcidev->irq;
4136 dev_dbg(dev->class_dev, "irq %u\n", dev->irq);
4138 retval = setup_subdevices(dev);
4145 static void detach(struct comedi_device *dev)
4147 const struct pcidas64_board *thisboard = comedi_board(dev);
4148 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
4149 struct pcidas64_private *devpriv = dev->private;
4153 free_irq(dev->irq, dev);
4156 if (devpriv->plx9080_iobase) {
4157 disable_plx_interrupts(dev);
4158 iounmap(devpriv->plx9080_iobase);
4160 if (devpriv->main_iobase)
4161 iounmap(devpriv->main_iobase);
4162 if (devpriv->dio_counter_iobase)
4163 iounmap(devpriv->dio_counter_iobase);
4164 /* free pci dma buffers */
4165 for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
4166 if (devpriv->ai_buffer[i])
4167 pci_free_consistent(pcidev,
4169 devpriv->ai_buffer[i],
4170 devpriv->ai_buffer_bus_addr[i]);
4172 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
4173 if (devpriv->ao_buffer[i])
4174 pci_free_consistent(pcidev,
4176 devpriv->ao_buffer[i],
4177 devpriv->ao_buffer_bus_addr[i]);
4179 /* free dma descriptors */
4180 if (devpriv->ai_dma_desc)
4181 pci_free_consistent(pcidev,
4182 sizeof(struct plx_dma_desc) *
4183 ai_dma_ring_count(thisboard),
4184 devpriv->ai_dma_desc,
4185 devpriv->ai_dma_desc_bus_addr);
4186 if (devpriv->ao_dma_desc)
4187 pci_free_consistent(pcidev,
4188 sizeof(struct plx_dma_desc) *
4190 devpriv->ao_dma_desc,
4191 devpriv->ao_dma_desc_bus_addr);
4194 comedi_spriv_free(dev, 4);
4195 comedi_pci_disable(dev);
4198 static struct comedi_driver cb_pcidas64_driver = {
4199 .driver_name = "cb_pcidas64",
4200 .module = THIS_MODULE,
4201 .auto_attach = auto_attach,
4205 static int cb_pcidas64_pci_probe(struct pci_dev *dev,
4206 const struct pci_device_id *id)
4208 return comedi_pci_auto_config(dev, &cb_pcidas64_driver,
4212 static DEFINE_PCI_DEVICE_TABLE(cb_pcidas64_pci_table) = {
4213 { PCI_VDEVICE(CB, 0x001d), BOARD_PCIDAS6402_16 },
4214 { PCI_VDEVICE(CB, 0x001e), BOARD_PCIDAS6402_12 },
4215 { PCI_VDEVICE(CB, 0x0035), BOARD_PCIDAS64_M1_16 },
4216 { PCI_VDEVICE(CB, 0x0036), BOARD_PCIDAS64_M2_16 },
4217 { PCI_VDEVICE(CB, 0x0037), BOARD_PCIDAS64_M3_16 },
4218 { PCI_VDEVICE(CB, 0x0052), BOARD_PCIDAS4020_12 },
4219 { PCI_VDEVICE(CB, 0x005d), BOARD_PCIDAS6023 },
4220 { PCI_VDEVICE(CB, 0x005e), BOARD_PCIDAS6025 },
4221 { PCI_VDEVICE(CB, 0x005f), BOARD_PCIDAS6030 },
4222 { PCI_VDEVICE(CB, 0x0060), BOARD_PCIDAS6031 },
4223 { PCI_VDEVICE(CB, 0x0061), BOARD_PCIDAS6032 },
4224 { PCI_VDEVICE(CB, 0x0062), BOARD_PCIDAS6033 },
4225 { PCI_VDEVICE(CB, 0x0063), BOARD_PCIDAS6034 },
4226 { PCI_VDEVICE(CB, 0x0064), BOARD_PCIDAS6035 },
4227 { PCI_VDEVICE(CB, 0x0065), BOARD_PCIDAS6040 },
4228 { PCI_VDEVICE(CB, 0x0066), BOARD_PCIDAS6052 },
4229 { PCI_VDEVICE(CB, 0x0067), BOARD_PCIDAS6070 },
4230 { PCI_VDEVICE(CB, 0x0068), BOARD_PCIDAS6071 },
4231 { PCI_VDEVICE(CB, 0x006f), BOARD_PCIDAS6036 },
4232 { PCI_VDEVICE(CB, 0x0078), BOARD_PCIDAS6013 },
4233 { PCI_VDEVICE(CB, 0x0079), BOARD_PCIDAS6014 },
4236 MODULE_DEVICE_TABLE(pci, cb_pcidas64_pci_table);
4238 static struct pci_driver cb_pcidas64_pci_driver = {
4239 .name = "cb_pcidas64",
4240 .id_table = cb_pcidas64_pci_table,
4241 .probe = cb_pcidas64_pci_probe,
4242 .remove = comedi_pci_auto_unconfig,
4244 module_comedi_pci_driver(cb_pcidas64_driver, cb_pcidas64_pci_driver);
4246 MODULE_AUTHOR("Comedi http://www.comedi.org");
4247 MODULE_DESCRIPTION("Comedi low-level driver");
4248 MODULE_LICENSE("GPL");