drivers/staging/comedi/drivers/cb_pcidas64.c

   1 /*
   2     comedi/drivers/cb_pcidas64.c
   3     This is a driver for the ComputerBoards/MeasurementComputing PCI-DAS
   4     64xx, 60xx, and 4020 cards.
   5
   6     Author:  Frank Mori Hess <fmhess@users.sourceforge.net>
   7     Copyright (C) 2001, 2002 Frank Mori Hess
   8
   9     Thanks also go to the following people:
  10
  11     Steve Rosenbluth, for providing the source code for
  12     his pci-das6402 driver, and source code for working QNX pci-6402
  13     drivers by Greg Laird and Mariusz Bogacz.  None of the code was
  14     used directly here, but it was useful as an additional source of
  15     documentation on how to program the boards.
  16
  17     John Sims, for much testing and feedback on pcidas-4020 support.
  18
  19     COMEDI - Linux Control and Measurement Device Interface
  20     Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
  21
  22     This program is free software; you can redistribute it and/or modify
  23     it under the terms of the GNU General Public License as published by
  24     the Free Software Foundation; either version 2 of the License, or
  25     (at your option) any later version.
  26
  27     This program is distributed in the hope that it will be useful,
  28     but WITHOUT ANY WARRANTY; without even the implied warranty of
  29     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  30     GNU General Public License for more details.
  31 */
  32
  33 /*
  34  * Driver: cb_pcidas64
  35  * Description: MeasurementComputing PCI-DAS64xx, 60XX, and 4020 series
  36  *   with the PLX 9080 PCI controller
  37  * Author: Frank Mori Hess <fmhess@users.sourceforge.net>
  38  * Status: works
  39  * Updated: Fri, 02 Nov 2012 18:58:55 +0000
  40  * Devices: [Measurement Computing] PCI-DAS6402/16 (cb_pcidas64),
  41  *   PCI-DAS6402/12, PCI-DAS64/M1/16, PCI-DAS64/M2/16,
  42  *   PCI-DAS64/M3/16, PCI-DAS6402/16/JR, PCI-DAS64/M1/16/JR,
  43  *   PCI-DAS64/M2/16/JR, PCI-DAS64/M3/16/JR, PCI-DAS64/M1/14,
  44  *   PCI-DAS64/M2/14, PCI-DAS64/M3/14, PCI-DAS6013, PCI-DAS6014,
  45  *   PCI-DAS6023, PCI-DAS6025, PCI-DAS6030,
  46  *   PCI-DAS6031, PCI-DAS6032, PCI-DAS6033, PCI-DAS6034,
  47  *   PCI-DAS6035, PCI-DAS6036, PCI-DAS6040, PCI-DAS6052,
  48  *   PCI-DAS6070, PCI-DAS6071, PCI-DAS4020/12
  49  *
  50  * Configuration options:
  51  *   None.
  52  *
  53  * Manual attachment of PCI cards with the comedi_config utility is not
  54  * supported by this driver; they are attached automatically.
  55  *
  56  * These boards may be autocalibrated with the comedi_calibrate utility.
  57  *
  58  * To select the bnc trigger input on the 4020 (instead of the dio input),
  59  * specify a nonzero channel in the chanspec.  If you wish to use an external
  60  * master clock on the 4020, you may do so by setting the scan_begin_src
  61  * to TRIG_OTHER, and using an INSN_CONFIG_TIMER_1 configuration insn
  62  * to configure the divisor to use for the external clock.
  63  *
  64  * Some devices are not identified because the PCI device IDs are not yet
  65  * known. If you have such a board, please let the maintainers know.
  66  */
  67
  68 /*
  69
  70 TODO:
  71         make it return error if user attempts an ai command that uses the
  72         external queue, and an ao command simultaneously user counter subdevice
  73         there are a number of boards this driver will support when they are
  74         fully released, but does not yet since the pci device id numbers
  75         are not yet available.
  76
  77         support prescaled 100khz clock for slow pacing (not available on 6000
  78         series?)
  79
  80         make ao fifo size adjustable like ai fifo
  81 */
  82
  83 #include <linux/module.h>
  84 #include <linux/delay.h>
  85 #include <linux/interrupt.h>
  86
  87 #include "../comedi_pci.h"
  88
  89 #include "8255.h"
  90 #include "plx9080.h"
  91
  92 #define TIMER_BASE 25           /*  40MHz master clock */
  93 /* 100kHz 'prescaled' clock for slow acquisition,
  94  * maybe I'll support this someday */
  95 #define PRESCALED_TIMER_BASE    10000
  96 #define DMA_BUFFER_SIZE 0x1000
  97
  98 /* maximum value that can be loaded into board's 24-bit counters*/
  99 static const int max_counter_value = 0xffffff;
 100
 101 /* PCI-DAS64xxx base addresses */
 102
 103 /* devpriv->main_iobase registers */
 104 enum write_only_registers {
 105         INTR_ENABLE_REG = 0x0,  /*  interrupt enable register */
 106         HW_CONFIG_REG = 0x2,    /*  hardware config register */
 107         DAQ_SYNC_REG = 0xc,
 108         DAQ_ATRIG_LOW_4020_REG = 0xc,
 109         ADC_CONTROL0_REG = 0x10,        /*  adc control register 0 */
 110         ADC_CONTROL1_REG = 0x12,        /*  adc control register 1 */
 111         CALIBRATION_REG = 0x14,
 112         /*  lower 16 bits of adc sample interval counter */
 113         ADC_SAMPLE_INTERVAL_LOWER_REG = 0x16,
 114         /*  upper 8 bits of adc sample interval counter */
 115         ADC_SAMPLE_INTERVAL_UPPER_REG = 0x18,
 116         /*  lower 16 bits of delay interval counter */
 117         ADC_DELAY_INTERVAL_LOWER_REG = 0x1a,
 118         /*  upper 8 bits of delay interval counter */
 119         ADC_DELAY_INTERVAL_UPPER_REG = 0x1c,
 120         /*  lower 16 bits of hardware conversion/scan counter */
 121         ADC_COUNT_LOWER_REG = 0x1e,
 122         /*  upper 8 bits of hardware conversion/scan counter */
 123         ADC_COUNT_UPPER_REG = 0x20,
 124         ADC_START_REG = 0x22,   /*  software trigger to start acquisition */
 125         ADC_CONVERT_REG = 0x24, /*  initiates single conversion */
 126         ADC_QUEUE_CLEAR_REG = 0x26,     /*  clears adc queue */
 127         ADC_QUEUE_LOAD_REG = 0x28,      /*  loads adc queue */
 128         ADC_BUFFER_CLEAR_REG = 0x2a,
 129         /*  high channel for internal queue, use adc_chan_bits() inline above */
 130         ADC_QUEUE_HIGH_REG = 0x2c,
 131         DAC_CONTROL0_REG = 0x50,        /*  dac control register 0 */
 132         DAC_CONTROL1_REG = 0x52,        /*  dac control register 0 */
 133         /*  lower 16 bits of dac sample interval counter */
 134         DAC_SAMPLE_INTERVAL_LOWER_REG = 0x54,
 135         /*  upper 8 bits of dac sample interval counter */
 136         DAC_SAMPLE_INTERVAL_UPPER_REG = 0x56,
 137         DAC_SELECT_REG = 0x60,
 138         DAC_START_REG = 0x64,
 139         DAC_BUFFER_CLEAR_REG = 0x66,    /*  clear dac buffer */
 140 };
 141
 142 static inline unsigned int dac_convert_reg(unsigned int channel)
 143 {
 144         return 0x70 + (2 * (channel & 0x1));
 145 }
 146
 147 static inline unsigned int dac_lsb_4020_reg(unsigned int channel)
 148 {
 149         return 0x70 + (4 * (channel & 0x1));
 150 }
 151
 152 static inline unsigned int dac_msb_4020_reg(unsigned int channel)
 153 {
 154         return 0x72 + (4 * (channel & 0x1));
 155 }
 156
 157 enum read_only_registers {
 158         /*
 159          * hardware status register,
 160          * reading this apparently clears pending interrupts as well
 161          */
 162         HW_STATUS_REG = 0x0,
 163         PIPE1_READ_REG = 0x4,
 164         ADC_READ_PNTR_REG = 0x8,
 165         LOWER_XFER_REG = 0x10,
 166         ADC_WRITE_PNTR_REG = 0xc,
 167         PREPOST_REG = 0x14,
 168 };
 169
 170 enum read_write_registers {
 171         I8255_4020_REG = 0x48,  /*  8255 offset, for 4020 only */
 172         /*  external channel/gain queue, uses same bits as ADC_QUEUE_LOAD_REG */
 173         ADC_QUEUE_FIFO_REG = 0x100,
 174         ADC_FIFO_REG = 0x200,   /* adc data fifo */
 175         /* dac data fifo, has weird interactions with external channel queue */
 176         DAC_FIFO_REG = 0x300,
 177 };
 178
 179 /* dev->mmio registers */
 180 enum dio_counter_registers {
 181         DIO_8255_OFFSET = 0x0,
 182         DO_REG = 0x20,
 183         DI_REG = 0x28,
 184         DIO_DIRECTION_60XX_REG = 0x40,
 185         DIO_DATA_60XX_REG = 0x48,
 186 };
 187
 188 /* bit definitions for write-only registers */
 189
 190 enum intr_enable_contents {
 191         ADC_INTR_SRC_MASK = 0x3,        /*  adc interrupt source mask */
 192         ADC_INTR_QFULL_BITS = 0x0,      /*  interrupt fifo quarter full */
 193         ADC_INTR_EOC_BITS = 0x1,        /*  interrupt end of conversion */
 194         ADC_INTR_EOSCAN_BITS = 0x2,     /*  interrupt end of scan */
 195         ADC_INTR_EOSEQ_BITS = 0x3,      /*  interrupt end of sequence mask */
 196         EN_ADC_INTR_SRC_BIT = 0x4,      /*  enable adc interrupt source */
 197         EN_ADC_DONE_INTR_BIT = 0x8,     /*  enable adc acquisition done intr */
 198         DAC_INTR_SRC_MASK = 0x30,
 199         DAC_INTR_QEMPTY_BITS = 0x0,
 200         DAC_INTR_HIGH_CHAN_BITS = 0x10,
 201         EN_DAC_INTR_SRC_BIT = 0x40,     /*  enable dac interrupt source */
 202         EN_DAC_DONE_INTR_BIT = 0x80,
 203         EN_ADC_ACTIVE_INTR_BIT = 0x200, /*  enable adc active interrupt */
 204         EN_ADC_STOP_INTR_BIT = 0x400,   /*  enable adc stop trigger interrupt */
 205         EN_DAC_ACTIVE_INTR_BIT = 0x800, /*  enable dac active interrupt */
 206         EN_DAC_UNDERRUN_BIT = 0x4000,   /*  enable dac underrun status bit */
 207         EN_ADC_OVERRUN_BIT = 0x8000,    /*  enable adc overrun status bit */
 208 };
 209
 210 enum hw_config_contents {
 211         MASTER_CLOCK_4020_MASK = 0x3,   /*  master clock source mask for 4020 */
 212         INTERNAL_CLOCK_4020_BITS = 0x1, /*  use 40 MHz internal master clock */
 213         BNC_CLOCK_4020_BITS = 0x2,      /*  use BNC input for master clock */
 214         EXT_CLOCK_4020_BITS = 0x3,      /*  use dio input for master clock */
 215         EXT_QUEUE_BIT = 0x200,          /*  use external channel/gain queue */
 216         /*  use 225 nanosec strobe when loading dac instead of 50 nanosec */
 217         SLOW_DAC_BIT = 0x400,
 218         /*  bit with unknown function yet given as default value in pci-das64
 219          *  manual */
 220         HW_CONFIG_DUMMY_BITS = 0x2000,
 221         /*  bit selects channels 1/0 for analog input/output, otherwise 0/1 */
 222         DMA_CH_SELECT_BIT = 0x8000,
 223         FIFO_SIZE_REG = 0x4,            /*  allows adjustment of fifo sizes */
 224         DAC_FIFO_SIZE_MASK = 0xff00,    /*  bits that set dac fifo size */
 225         DAC_FIFO_BITS = 0xf800,         /*  8k sample ao fifo */
 226 };
 227 #define DAC_FIFO_SIZE 0x2000
 228
 229 enum daq_atrig_low_4020_contents {
 230         /*  use trig/ext clk bnc input for analog gate signal */
 231         EXT_AGATE_BNC_BIT = 0x8000,
 232         /*  use trig/ext clk bnc input for external stop trigger signal */
 233         EXT_STOP_TRIG_BNC_BIT = 0x4000,
 234         /*  use trig/ext clk bnc input for external start trigger signal */
 235         EXT_START_TRIG_BNC_BIT = 0x2000,
 236 };
 237
 238 static inline uint16_t analog_trig_low_threshold_bits(uint16_t threshold)
 239 {
 240         return threshold & 0xfff;
 241 }
 242
 243 enum adc_control0_contents {
 244         ADC_GATE_SRC_MASK = 0x3,        /*  bits that select gate */
 245         ADC_SOFT_GATE_BITS = 0x1,       /*  software gate */
 246         ADC_EXT_GATE_BITS = 0x2,        /*  external digital gate */
 247         ADC_ANALOG_GATE_BITS = 0x3,     /*  analog level gate */
 248         /*  level-sensitive gate (for digital) */
 249         ADC_GATE_LEVEL_BIT = 0x4,
 250         ADC_GATE_POLARITY_BIT = 0x8,    /*  gate active low */
 251         ADC_START_TRIG_SOFT_BITS = 0x10,
 252         ADC_START_TRIG_EXT_BITS = 0x20,
 253         ADC_START_TRIG_ANALOG_BITS = 0x30,
 254         ADC_START_TRIG_MASK = 0x30,
 255         ADC_START_TRIG_FALLING_BIT = 0x40,      /*  trig 1 uses falling edge */
 256         /*  external pacing uses falling edge */
 257         ADC_EXT_CONV_FALLING_BIT = 0x800,
 258         /*  enable hardware scan counter */
 259         ADC_SAMPLE_COUNTER_EN_BIT = 0x1000,
 260         ADC_DMA_DISABLE_BIT = 0x4000,   /*  disables dma */
 261         ADC_ENABLE_BIT = 0x8000,        /*  master adc enable */
 262 };
 263
 264 enum adc_control1_contents {
 265         /*  should be set for boards with > 16 channels */
 266         ADC_QUEUE_CONFIG_BIT = 0x1,
 267         CONVERT_POLARITY_BIT = 0x10,
 268         EOC_POLARITY_BIT = 0x20,
 269         ADC_SW_GATE_BIT = 0x40, /*  software gate of adc */
 270         ADC_DITHER_BIT = 0x200, /*  turn on extra noise for dithering */
 271         RETRIGGER_BIT = 0x800,
 272         ADC_LO_CHANNEL_4020_MASK = 0x300,
 273         ADC_HI_CHANNEL_4020_MASK = 0xc00,
 274         TWO_CHANNEL_4020_BITS = 0x1000, /*  two channel mode for 4020 */
 275         FOUR_CHANNEL_4020_BITS = 0x2000, /*  four channel mode for 4020 */
 276         CHANNEL_MODE_4020_MASK = 0x3000,
 277         ADC_MODE_MASK = 0xf000,
 278 };
 279
 280 static inline uint16_t adc_lo_chan_4020_bits(unsigned int channel)
 281 {
 282         return (channel & 0x3) << 8;
 283 };
 284
 285 static inline uint16_t adc_hi_chan_4020_bits(unsigned int channel)
 286 {
 287         return (channel & 0x3) << 10;
 288 };
 289
 290 static inline uint16_t adc_mode_bits(unsigned int mode)
 291 {
 292         return (mode & 0xf) << 12;
 293 };
 294
 295 enum calibration_contents {
 296         SELECT_8800_BIT = 0x1,
 297         SELECT_8402_64XX_BIT = 0x2,
 298         SELECT_1590_60XX_BIT = 0x2,
 299         CAL_EN_64XX_BIT = 0x40, /*  calibration enable for 64xx series */
 300         SERIAL_DATA_IN_BIT = 0x80,
 301         SERIAL_CLOCK_BIT = 0x100,
 302         CAL_EN_60XX_BIT = 0x200, /*  calibration enable for 60xx series */
 303         CAL_GAIN_BIT = 0x800,
 304 };
 305
 306 /*
 307  * calibration sources for 6025 are:
 308  *  0 : ground
 309  *  1 : 10V
 310  *  2 : 5V
 311  *  3 : 0.5V
 312  *  4 : 0.05V
 313  *  5 : ground
 314  *  6 : dac channel 0
 315  *  7 : dac channel 1
 316  */
 317
 318 static inline uint16_t adc_src_bits(unsigned int source)
 319 {
 320         return (source & 0xf) << 3;
 321 };
 322
 323 static inline uint16_t adc_convert_chan_4020_bits(unsigned int channel)
 324 {
 325         return (channel & 0x3) << 8;
 326 };
 327
 328 enum adc_queue_load_contents {
 329         UNIP_BIT = 0x800,       /*  unipolar/bipolar bit */
 330         ADC_SE_DIFF_BIT = 0x1000,       /*  single-ended/ differential bit */
 331         /*  non-referenced single-ended (common-mode input) */
 332         ADC_COMMON_BIT = 0x2000,
 333         QUEUE_EOSEQ_BIT = 0x4000,       /*  queue end of sequence */
 334         QUEUE_EOSCAN_BIT = 0x8000,      /*  queue end of scan */
 335 };
 336
 337 static inline uint16_t adc_chan_bits(unsigned int channel)
 338 {
 339         return channel & 0x3f;
 340 };
 341
 342 enum dac_control0_contents {
 343         DAC_ENABLE_BIT = 0x8000,        /*  dac controller enable bit */
 344         DAC_CYCLIC_STOP_BIT = 0x4000,
 345         DAC_WAVEFORM_MODE_BIT = 0x100,
 346         DAC_EXT_UPDATE_FALLING_BIT = 0x80,
 347         DAC_EXT_UPDATE_ENABLE_BIT = 0x40,
 348         WAVEFORM_TRIG_MASK = 0x30,
 349         WAVEFORM_TRIG_DISABLED_BITS = 0x0,
 350         WAVEFORM_TRIG_SOFT_BITS = 0x10,
 351         WAVEFORM_TRIG_EXT_BITS = 0x20,
 352         WAVEFORM_TRIG_ADC1_BITS = 0x30,
 353         WAVEFORM_TRIG_FALLING_BIT = 0x8,
 354         WAVEFORM_GATE_LEVEL_BIT = 0x4,
 355         WAVEFORM_GATE_ENABLE_BIT = 0x2,
 356         WAVEFORM_GATE_SELECT_BIT = 0x1,
 357 };
 358
 359 enum dac_control1_contents {
 360         DAC_WRITE_POLARITY_BIT = 0x800, /* board-dependent setting */
 361         DAC1_EXT_REF_BIT = 0x200,
 362         DAC0_EXT_REF_BIT = 0x100,
 363         DAC_OUTPUT_ENABLE_BIT = 0x80,   /*  dac output enable bit */
 364         DAC_UPDATE_POLARITY_BIT = 0x40, /* board-dependent setting */
 365         DAC_SW_GATE_BIT = 0x20,
 366         DAC1_UNIPOLAR_BIT = 0x8,
 367         DAC0_UNIPOLAR_BIT = 0x2,
 368 };
 369
 370 /* bit definitions for read-only registers */
 371 enum hw_status_contents {
 372         DAC_UNDERRUN_BIT = 0x1,
 373         ADC_OVERRUN_BIT = 0x2,
 374         DAC_ACTIVE_BIT = 0x4,
 375         ADC_ACTIVE_BIT = 0x8,
 376         DAC_INTR_PENDING_BIT = 0x10,
 377         ADC_INTR_PENDING_BIT = 0x20,
 378         DAC_DONE_BIT = 0x40,
 379         ADC_DONE_BIT = 0x80,
 380         EXT_INTR_PENDING_BIT = 0x100,
 381         ADC_STOP_BIT = 0x200,
 382 };
 383
 384 static inline uint16_t pipe_full_bits(uint16_t hw_status_bits)
 385 {
 386         return (hw_status_bits >> 10) & 0x3;
 387 };
 388
 389 static inline unsigned int dma_chain_flag_bits(uint16_t prepost_bits)
 390 {
 391         return (prepost_bits >> 6) & 0x3;
 392 }
 393
 394 static inline unsigned int adc_upper_read_ptr_code(uint16_t prepost_bits)
 395 {
 396         return (prepost_bits >> 12) & 0x3;
 397 }
 398
 399 static inline unsigned int adc_upper_write_ptr_code(uint16_t prepost_bits)
 400 {
 401         return (prepost_bits >> 14) & 0x3;
 402 }
 403
 404 /* I2C addresses for 4020 */
 405 enum i2c_addresses {
 406         RANGE_CAL_I2C_ADDR = 0x20,
 407         CALDAC0_I2C_ADDR = 0xc,
 408         CALDAC1_I2C_ADDR = 0xd,
 409 };
 410
 411 enum range_cal_i2c_contents {
 412         /*  bits that set what source the adc converter measures */
 413         ADC_SRC_4020_MASK = 0x70,
 414         /*  make bnc trig/ext clock threshold 0V instead of 2.5V */
 415         BNC_TRIG_THRESHOLD_0V_BIT = 0x80,
 416 };
 417
 418 static inline uint8_t adc_src_4020_bits(unsigned int source)
 419 {
 420         return (source << 4) & ADC_SRC_4020_MASK;
 421 };
 422
 423 static inline uint8_t attenuate_bit(unsigned int channel)
 424 {
 425         /*  attenuate channel (+-5V input range) */
 426         return 1 << (channel & 0x3);
 427 };
 428
 429 /* analog input ranges for 64xx boards */
 430 static const struct comedi_lrange ai_ranges_64xx = {
 431         8, {
 432                 BIP_RANGE(10),
 433                 BIP_RANGE(5),
 434                 BIP_RANGE(2.5),
 435                 BIP_RANGE(1.25),
 436                 UNI_RANGE(10),
 437                 UNI_RANGE(5),
 438                 UNI_RANGE(2.5),
 439                 UNI_RANGE(1.25)
 440         }
 441 };
 442
 443 static const uint8_t ai_range_code_64xx[8] = {
 444         0x0, 0x1, 0x2, 0x3,     /* bipolar 10, 5, 2,5, 1.25 */
 445         0x8, 0x9, 0xa, 0xb      /* unipolar 10, 5, 2.5, 1.25 */
 446 };
 447
 448 /* analog input ranges for 64-Mx boards */
 449 static const struct comedi_lrange ai_ranges_64_mx = {
 450         7, {
 451                 BIP_RANGE(5),
 452                 BIP_RANGE(2.5),
 453                 BIP_RANGE(1.25),
 454                 BIP_RANGE(0.625),
 455                 UNI_RANGE(5),
 456                 UNI_RANGE(2.5),
 457                 UNI_RANGE(1.25)
 458         }
 459 };
 460
 461 static const uint8_t ai_range_code_64_mx[7] = {
 462         0x0, 0x1, 0x2, 0x3,     /* bipolar 5, 2.5, 1.25, 0.625 */
 463         0x9, 0xa, 0xb           /* unipolar 5, 2.5, 1.25 */
 464 };
 465
 466 /* analog input ranges for 60xx boards */
 467 static const struct comedi_lrange ai_ranges_60xx = {
 468         4, {
 469                 BIP_RANGE(10),
 470                 BIP_RANGE(5),
 471                 BIP_RANGE(0.5),
 472                 BIP_RANGE(0.05)
 473         }
 474 };
 475
 476 static const uint8_t ai_range_code_60xx[4] = {
 477         0x0, 0x1, 0x4, 0x7      /* bipolar 10, 5, 0.5, 0.05 */
 478 };
 479
 480 /* analog input ranges for 6030, etc boards */
 481 static const struct comedi_lrange ai_ranges_6030 = {
 482         14, {
 483                 BIP_RANGE(10),
 484                 BIP_RANGE(5),
 485                 BIP_RANGE(2),
 486                 BIP_RANGE(1),
 487                 BIP_RANGE(0.5),
 488                 BIP_RANGE(0.2),
 489                 BIP_RANGE(0.1),
 490                 UNI_RANGE(10),
 491                 UNI_RANGE(5),
 492                 UNI_RANGE(2),
 493                 UNI_RANGE(1),
 494                 UNI_RANGE(0.5),
 495                 UNI_RANGE(0.2),
 496                 UNI_RANGE(0.1)
 497         }
 498 };
 499
 500 static const uint8_t ai_range_code_6030[14] = {
 501         0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, /* bip 10, 5, 2, 1, 0.5, 0.2, 0.1 */
 502         0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf  /* uni 10, 5, 2, 1, 0.5, 0.2, 0.1 */
 503 };
 504
 505 /* analog input ranges for 6052, etc boards */
 506 static const struct comedi_lrange ai_ranges_6052 = {
 507         15, {
 508                 BIP_RANGE(10),
 509                 BIP_RANGE(5),
 510                 BIP_RANGE(2.5),
 511                 BIP_RANGE(1),
 512                 BIP_RANGE(0.5),
 513                 BIP_RANGE(0.25),
 514                 BIP_RANGE(0.1),
 515                 BIP_RANGE(0.05),
 516                 UNI_RANGE(10),
 517                 UNI_RANGE(5),
 518                 UNI_RANGE(2),
 519                 UNI_RANGE(1),
 520                 UNI_RANGE(0.5),
 521                 UNI_RANGE(0.2),
 522                 UNI_RANGE(0.1)
 523         }
 524 };
 525
 526 static const uint8_t ai_range_code_6052[15] = {
 527         0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, /* bipolar 10 ... 0.05 */
 528         0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf       /* unipolar 10 ... 0.1 */
 529 };
 530
 531 /* analog input ranges for 4020 board */
 532 static const struct comedi_lrange ai_ranges_4020 = {
 533         2, {
 534                 BIP_RANGE(5),
 535                 BIP_RANGE(1)
 536         }
 537 };
 538
 539 /* analog output ranges */
 540 static const struct comedi_lrange ao_ranges_64xx = {
 541         4, {
 542                 BIP_RANGE(5),
 543                 BIP_RANGE(10),
 544                 UNI_RANGE(5),
 545                 UNI_RANGE(10)
 546         }
 547 };
 548
 549 static const int ao_range_code_64xx[] = {
 550         0x0,
 551         0x1,
 552         0x2,
 553         0x3,
 554 };
 555
 556 static const int ao_range_code_60xx[] = {
 557         0x0,
 558 };
 559
 560 static const struct comedi_lrange ao_ranges_6030 = {
 561         2, {
 562                 BIP_RANGE(10),
 563                 UNI_RANGE(10)
 564         }
 565 };
 566
 567 static const int ao_range_code_6030[] = {
 568         0x0,
 569         0x2,
 570 };
 571
 572 static const struct comedi_lrange ao_ranges_4020 = {
 573         2, {
 574                 BIP_RANGE(5),
 575                 BIP_RANGE(10)
 576         }
 577 };
 578
 579 static const int ao_range_code_4020[] = {
 580         0x1,
 581         0x0,
 582 };
 583
 584 enum register_layout {
 585         LAYOUT_60XX,
 586         LAYOUT_64XX,
 587         LAYOUT_4020,
 588 };
 589
 590 struct hw_fifo_info {
 591         unsigned int num_segments;
 592         unsigned int max_segment_length;
 593         unsigned int sample_packing_ratio;
 594         uint16_t fifo_size_reg_mask;
 595 };
 596
 597 enum pcidas64_boardid {
 598         BOARD_PCIDAS6402_16,
 599         BOARD_PCIDAS6402_12,
 600         BOARD_PCIDAS64_M1_16,
 601         BOARD_PCIDAS64_M2_16,
 602         BOARD_PCIDAS64_M3_16,
 603         BOARD_PCIDAS6013,
 604         BOARD_PCIDAS6014,
 605         BOARD_PCIDAS6023,
 606         BOARD_PCIDAS6025,
 607         BOARD_PCIDAS6030,
 608         BOARD_PCIDAS6031,
 609         BOARD_PCIDAS6032,
 610         BOARD_PCIDAS6033,
 611         BOARD_PCIDAS6034,
 612         BOARD_PCIDAS6035,
 613         BOARD_PCIDAS6036,
 614         BOARD_PCIDAS6040,
 615         BOARD_PCIDAS6052,
 616         BOARD_PCIDAS6070,
 617         BOARD_PCIDAS6071,
 618         BOARD_PCIDAS4020_12,
 619         BOARD_PCIDAS6402_16_JR,
 620         BOARD_PCIDAS64_M1_16_JR,
 621         BOARD_PCIDAS64_M2_16_JR,
 622         BOARD_PCIDAS64_M3_16_JR,
 623         BOARD_PCIDAS64_M1_14,
 624         BOARD_PCIDAS64_M2_14,
 625         BOARD_PCIDAS64_M3_14,
 626 };
 627
 628 struct pcidas64_board {
 629         const char *name;
 630         int ai_se_chans;        /*  number of ai inputs in single-ended mode */
 631         int ai_bits;            /*  analog input resolution */
 632         int ai_speed;           /*  fastest conversion period in ns */
 633         const struct comedi_lrange *ai_range_table;
 634         const uint8_t *ai_range_code;
 635         int ao_nchan;           /*  number of analog out channels */
 636         int ao_bits;            /*  analog output resolution */
 637         int ao_scan_speed;      /*  analog output scan speed */
 638         const struct comedi_lrange *ao_range_table;
 639         const int *ao_range_code;
 640         const struct hw_fifo_info *const ai_fifo;
 641         /*  different board families have slightly different registers */
 642         enum register_layout layout;
 643         unsigned has_8255:1;
 644 };
 645
 646 static const struct hw_fifo_info ai_fifo_4020 = {
 647         .num_segments = 2,
 648         .max_segment_length = 0x8000,
 649         .sample_packing_ratio = 2,
 650         .fifo_size_reg_mask = 0x7f,
 651 };
 652
 653 static const struct hw_fifo_info ai_fifo_64xx = {
 654         .num_segments = 4,
 655         .max_segment_length = 0x800,
 656         .sample_packing_ratio = 1,
 657         .fifo_size_reg_mask = 0x3f,
 658 };
 659
 660 static const struct hw_fifo_info ai_fifo_60xx = {
 661         .num_segments = 4,
 662         .max_segment_length = 0x800,
 663         .sample_packing_ratio = 1,
 664         .fifo_size_reg_mask = 0x7f,
 665 };
 666
 667 /*
 668  * maximum number of dma transfers we will chain together into a ring
 669  * (and the maximum number of dma buffers we maintain)
 670  */
 671 #define MAX_AI_DMA_RING_COUNT (0x80000 / DMA_BUFFER_SIZE)
 672 #define MIN_AI_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
 673 #define AO_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
 674 static inline unsigned int ai_dma_ring_count(const struct pcidas64_board *board)
 675 {
 676         if (board->layout == LAYOUT_4020)
 677                 return MAX_AI_DMA_RING_COUNT;
 678
 679         return MIN_AI_DMA_RING_COUNT;
 680 }
 681
 682 static const int bytes_in_sample = 2;
 683
 684 static const struct pcidas64_board pcidas64_boards[] = {
 685         [BOARD_PCIDAS6402_16] = {
 686                 .name           = "pci-das6402/16",
 687                 .ai_se_chans    = 64,
 688                 .ai_bits        = 16,
 689                 .ai_speed       = 5000,
 690                 .ao_nchan       = 2,
 691                 .ao_bits        = 16,
 692                 .ao_scan_speed  = 10000,
 693                 .layout         = LAYOUT_64XX,
 694                 .ai_range_table = &ai_ranges_64xx,
 695                 .ai_range_code  = ai_range_code_64xx,
 696                 .ao_range_table = &ao_ranges_64xx,
 697                 .ao_range_code  = ao_range_code_64xx,
 698                 .ai_fifo        = &ai_fifo_64xx,
 699                 .has_8255       = 1,
 700         },
 701         [BOARD_PCIDAS6402_12] = {
 702                 .name           = "pci-das6402/12",     /*  XXX check */
 703                 .ai_se_chans    = 64,
 704                 .ai_bits        = 12,
 705                 .ai_speed       = 5000,
 706                 .ao_nchan       = 2,
 707                 .ao_bits        = 12,
 708                 .ao_scan_speed  = 10000,
 709                 .layout         = LAYOUT_64XX,
 710                 .ai_range_table = &ai_ranges_64xx,
 711                 .ai_range_code  = ai_range_code_64xx,
 712                 .ao_range_table = &ao_ranges_64xx,
 713                 .ao_range_code  = ao_range_code_64xx,
 714                 .ai_fifo        = &ai_fifo_64xx,
 715                 .has_8255       = 1,
 716         },
 717         [BOARD_PCIDAS64_M1_16] = {
 718                 .name           = "pci-das64/m1/16",
 719                 .ai_se_chans    = 64,
 720                 .ai_bits        = 16,
 721                 .ai_speed       = 1000,
 722                 .ao_nchan       = 2,
 723                 .ao_bits        = 16,
 724                 .ao_scan_speed  = 10000,
 725                 .layout         = LAYOUT_64XX,
 726                 .ai_range_table = &ai_ranges_64_mx,
 727                 .ai_range_code  = ai_range_code_64_mx,
 728                 .ao_range_table = &ao_ranges_64xx,
 729                 .ao_range_code  = ao_range_code_64xx,
 730                 .ai_fifo        = &ai_fifo_64xx,
 731                 .has_8255       = 1,
 732         },
 733         [BOARD_PCIDAS64_M2_16] = {
 734                 .name = "pci-das64/m2/16",
 735                 .ai_se_chans    = 64,
 736                 .ai_bits        = 16,
 737                 .ai_speed       = 500,
 738                 .ao_nchan       = 2,
 739                 .ao_bits        = 16,
 740                 .ao_scan_speed  = 10000,
 741                 .layout         = LAYOUT_64XX,
 742                 .ai_range_table = &ai_ranges_64_mx,
 743                 .ai_range_code  = ai_range_code_64_mx,
 744                 .ao_range_table = &ao_ranges_64xx,
 745                 .ao_range_code  = ao_range_code_64xx,
 746                 .ai_fifo        = &ai_fifo_64xx,
 747                 .has_8255       = 1,
 748         },
 749         [BOARD_PCIDAS64_M3_16] = {
 750                 .name           = "pci-das64/m3/16",
 751                 .ai_se_chans    = 64,
 752                 .ai_bits        = 16,
 753                 .ai_speed       = 333,
 754                 .ao_nchan       = 2,
 755                 .ao_bits        = 16,
 756                 .ao_scan_speed  = 10000,
 757                 .layout         = LAYOUT_64XX,
 758                 .ai_range_table = &ai_ranges_64_mx,
 759                 .ai_range_code  = ai_range_code_64_mx,
 760                 .ao_range_table = &ao_ranges_64xx,
 761                 .ao_range_code  = ao_range_code_64xx,
 762                 .ai_fifo        = &ai_fifo_64xx,
 763                 .has_8255       = 1,
 764         },
 765         [BOARD_PCIDAS6013] = {
 766                 .name           = "pci-das6013",
 767                 .ai_se_chans    = 16,
 768                 .ai_bits        = 16,
 769                 .ai_speed       = 5000,
 770                 .ao_nchan       = 0,
 771                 .ao_bits        = 16,
 772                 .layout         = LAYOUT_60XX,
 773                 .ai_range_table = &ai_ranges_60xx,
 774                 .ai_range_code  = ai_range_code_60xx,
 775                 .ao_range_table = &range_bipolar10,
 776                 .ao_range_code  = ao_range_code_60xx,
 777                 .ai_fifo        = &ai_fifo_60xx,
 778                 .has_8255       = 0,
 779         },
 780         [BOARD_PCIDAS6014] = {
 781                 .name           = "pci-das6014",
 782                 .ai_se_chans    = 16,
 783                 .ai_bits        = 16,
 784                 .ai_speed       = 5000,
 785                 .ao_nchan       = 2,
 786                 .ao_bits        = 16,
 787                 .ao_scan_speed  = 100000,
 788                 .layout         = LAYOUT_60XX,
 789                 .ai_range_table = &ai_ranges_60xx,
 790                 .ai_range_code  = ai_range_code_60xx,
 791                 .ao_range_table = &range_bipolar10,
 792                 .ao_range_code  = ao_range_code_60xx,
 793                 .ai_fifo        = &ai_fifo_60xx,
 794                 .has_8255       = 0,
 795         },
 796         [BOARD_PCIDAS6023] = {
 797                 .name           = "pci-das6023",
 798                 .ai_se_chans    = 16,
 799                 .ai_bits        = 12,
 800                 .ai_speed       = 5000,
 801                 .ao_nchan       = 0,
 802                 .ao_scan_speed  = 100000,
 803                 .layout         = LAYOUT_60XX,
 804                 .ai_range_table = &ai_ranges_60xx,
 805                 .ai_range_code  = ai_range_code_60xx,
 806                 .ao_range_table = &range_bipolar10,
 807                 .ao_range_code  = ao_range_code_60xx,
 808                 .ai_fifo        = &ai_fifo_60xx,
 809                 .has_8255       = 1,
 810         },
 811         [BOARD_PCIDAS6025] = {
 812                 .name           = "pci-das6025",
 813                 .ai_se_chans    = 16,
 814                 .ai_bits        = 12,
 815                 .ai_speed       = 5000,
 816                 .ao_nchan       = 2,
 817                 .ao_bits        = 12,
 818                 .ao_scan_speed  = 100000,
 819                 .layout         = LAYOUT_60XX,
 820                 .ai_range_table = &ai_ranges_60xx,
 821                 .ai_range_code  = ai_range_code_60xx,
 822                 .ao_range_table = &range_bipolar10,
 823                 .ao_range_code  = ao_range_code_60xx,
 824                 .ai_fifo        = &ai_fifo_60xx,
 825                 .has_8255       = 1,
 826         },
 827         [BOARD_PCIDAS6030] = {
 828                 .name           = "pci-das6030",
 829                 .ai_se_chans    = 16,
 830                 .ai_bits        = 16,
 831                 .ai_speed       = 10000,
 832                 .ao_nchan       = 2,
 833                 .ao_bits        = 16,
 834                 .ao_scan_speed  = 10000,
 835                 .layout         = LAYOUT_60XX,
 836                 .ai_range_table = &ai_ranges_6030,
 837                 .ai_range_code  = ai_range_code_6030,
 838                 .ao_range_table = &ao_ranges_6030,
 839                 .ao_range_code  = ao_range_code_6030,
 840                 .ai_fifo        = &ai_fifo_60xx,
 841                 .has_8255       = 0,
 842         },
 843         [BOARD_PCIDAS6031] = {
 844                 .name           = "pci-das6031",
 845                 .ai_se_chans    = 64,
 846                 .ai_bits        = 16,
 847                 .ai_speed       = 10000,
 848                 .ao_nchan       = 2,
 849                 .ao_bits        = 16,
 850                 .ao_scan_speed  = 10000,
 851                 .layout         = LAYOUT_60XX,
 852                 .ai_range_table = &ai_ranges_6030,
 853                 .ai_range_code  = ai_range_code_6030,
 854                 .ao_range_table = &ao_ranges_6030,
 855                 .ao_range_code  = ao_range_code_6030,
 856                 .ai_fifo        = &ai_fifo_60xx,
 857                 .has_8255       = 0,
 858         },
 859         [BOARD_PCIDAS6032] = {
 860                 .name           = "pci-das6032",
 861                 .ai_se_chans    = 16,
 862                 .ai_bits        = 16,
 863                 .ai_speed       = 10000,
 864                 .ao_nchan       = 0,
 865                 .layout         = LAYOUT_60XX,
 866                 .ai_range_table = &ai_ranges_6030,
 867                 .ai_range_code  = ai_range_code_6030,
 868                 .ai_fifo        = &ai_fifo_60xx,
 869                 .has_8255       = 0,
 870         },
 871         [BOARD_PCIDAS6033] = {
 872                 .name           = "pci-das6033",
 873                 .ai_se_chans    = 64,
 874                 .ai_bits        = 16,
 875                 .ai_speed       = 10000,
 876                 .ao_nchan       = 0,
 877                 .layout         = LAYOUT_60XX,
 878                 .ai_range_table = &ai_ranges_6030,
 879                 .ai_range_code  = ai_range_code_6030,
 880                 .ai_fifo        = &ai_fifo_60xx,
 881                 .has_8255       = 0,
 882         },
 883         [BOARD_PCIDAS6034] = {
 884                 .name           = "pci-das6034",
 885                 .ai_se_chans    = 16,
 886                 .ai_bits        = 16,
 887                 .ai_speed       = 5000,
 888                 .ao_nchan       = 0,
 889                 .ao_scan_speed  = 0,
 890                 .layout         = LAYOUT_60XX,
 891                 .ai_range_table = &ai_ranges_60xx,
 892                 .ai_range_code  = ai_range_code_60xx,
 893                 .ai_fifo        = &ai_fifo_60xx,
 894                 .has_8255       = 0,
 895         },
 896         [BOARD_PCIDAS6035] = {
 897                 .name           = "pci-das6035",
 898                 .ai_se_chans    = 16,
 899                 .ai_bits        = 16,
 900                 .ai_speed       = 5000,
 901                 .ao_nchan       = 2,
 902                 .ao_bits        = 12,
 903                 .ao_scan_speed  = 100000,
 904                 .layout         = LAYOUT_60XX,
 905                 .ai_range_table = &ai_ranges_60xx,
 906                 .ai_range_code  = ai_range_code_60xx,
 907                 .ao_range_table = &range_bipolar10,
 908                 .ao_range_code  = ao_range_code_60xx,
 909                 .ai_fifo        = &ai_fifo_60xx,
 910                 .has_8255       = 0,
 911         },
 912         [BOARD_PCIDAS6036] = {
 913                 .name           = "pci-das6036",
 914                 .ai_se_chans    = 16,
 915                 .ai_bits        = 16,
 916                 .ai_speed       = 5000,
 917                 .ao_nchan       = 2,
 918                 .ao_bits        = 16,
 919                 .ao_scan_speed  = 100000,
 920                 .layout         = LAYOUT_60XX,
 921                 .ai_range_table = &ai_ranges_60xx,
 922                 .ai_range_code  = ai_range_code_60xx,
 923                 .ao_range_table = &range_bipolar10,
 924                 .ao_range_code  = ao_range_code_60xx,
 925                 .ai_fifo        = &ai_fifo_60xx,
 926                 .has_8255       = 0,
 927         },
 928         [BOARD_PCIDAS6040] = {
 929                 .name           = "pci-das6040",
 930                 .ai_se_chans    = 16,
 931                 .ai_bits        = 12,
 932                 .ai_speed       = 2000,
 933                 .ao_nchan       = 2,
 934                 .ao_bits        = 12,
 935                 .ao_scan_speed  = 1000,
 936                 .layout         = LAYOUT_60XX,
 937                 .ai_range_table = &ai_ranges_6052,
 938                 .ai_range_code  = ai_range_code_6052,
 939                 .ao_range_table = &ao_ranges_6030,
 940                 .ao_range_code  = ao_range_code_6030,
 941                 .ai_fifo        = &ai_fifo_60xx,
 942                 .has_8255       = 0,
 943         },
 944         [BOARD_PCIDAS6052] = {
 945                 .name           = "pci-das6052",
 946                 .ai_se_chans    = 16,
 947                 .ai_bits        = 16,
 948                 .ai_speed       = 3333,
 949                 .ao_nchan       = 2,
 950                 .ao_bits        = 16,
 951                 .ao_scan_speed  = 3333,
 952                 .layout         = LAYOUT_60XX,
 953                 .ai_range_table = &ai_ranges_6052,
 954                 .ai_range_code  = ai_range_code_6052,
 955                 .ao_range_table = &ao_ranges_6030,
 956                 .ao_range_code  = ao_range_code_6030,
 957                 .ai_fifo        = &ai_fifo_60xx,
 958                 .has_8255       = 0,
 959         },
 960         [BOARD_PCIDAS6070] = {
 961                 .name           = "pci-das6070",
 962                 .ai_se_chans    = 16,
 963                 .ai_bits        = 12,
 964                 .ai_speed       = 800,
 965                 .ao_nchan       = 2,
 966                 .ao_bits        = 12,
 967                 .ao_scan_speed  = 1000,
 968                 .layout         = LAYOUT_60XX,
 969                 .ai_range_table = &ai_ranges_6052,
 970                 .ai_range_code  = ai_range_code_6052,
 971                 .ao_range_table = &ao_ranges_6030,
 972                 .ao_range_code  = ao_range_code_6030,
 973                 .ai_fifo        = &ai_fifo_60xx,
 974                 .has_8255       = 0,
 975         },
 976         [BOARD_PCIDAS6071] = {
 977                 .name           = "pci-das6071",
 978                 .ai_se_chans    = 64,
 979                 .ai_bits        = 12,
 980                 .ai_speed       = 800,
 981                 .ao_nchan       = 2,
 982                 .ao_bits        = 12,
 983                 .ao_scan_speed  = 1000,
 984                 .layout         = LAYOUT_60XX,
 985                 .ai_range_table = &ai_ranges_6052,
 986                 .ai_range_code  = ai_range_code_6052,
 987                 .ao_range_table = &ao_ranges_6030,
 988                 .ao_range_code  = ao_range_code_6030,
 989                 .ai_fifo        = &ai_fifo_60xx,
 990                 .has_8255       = 0,
 991         },
 992         [BOARD_PCIDAS4020_12] = {
 993                 .name           = "pci-das4020/12",
 994                 .ai_se_chans    = 4,
 995                 .ai_bits        = 12,
 996                 .ai_speed       = 50,
 997                 .ao_bits        = 12,
 998                 .ao_nchan       = 2,
 999                 .ao_scan_speed  = 0,    /*  no hardware pacing on ao */
1000                 .layout         = LAYOUT_4020,
1001                 .ai_range_table = &ai_ranges_4020,
1002                 .ao_range_table = &ao_ranges_4020,
1003                 .ao_range_code  = ao_range_code_4020,
1004                 .ai_fifo        = &ai_fifo_4020,
1005                 .has_8255       = 1,
1006         },
1007 #if 0
1008         /*
1009          * The device id for these boards is unknown
1010          */
1011
1012         [BOARD_PCIDAS6402_16_JR] = {
1013                 .name           = "pci-das6402/16/jr",
1014                 .ai_se_chans    = 64,
1015                 .ai_bits        = 16,
1016                 .ai_speed       = 5000,
1017                 .ao_nchan       = 0,
1018                 .ao_scan_speed  = 10000,
1019                 .layout         = LAYOUT_64XX,
1020                 .ai_range_table = &ai_ranges_64xx,
1021                 .ai_range_code  = ai_range_code_64xx,
1022                 .ai_fifo        = ai_fifo_64xx,
1023                 .has_8255       = 1,
1024         },
1025         [BOARD_PCIDAS64_M1_16_JR] = {
1026                 .name           = "pci-das64/m1/16/jr",
1027                 .ai_se_chans    = 64,
1028                 .ai_bits        = 16,
1029                 .ai_speed       = 1000,
1030                 .ao_nchan       = 0,
1031                 .ao_scan_speed  = 10000,
1032                 .layout         = LAYOUT_64XX,
1033                 .ai_range_table = &ai_ranges_64_mx,
1034                 .ai_range_code  = ai_range_code_64_mx,
1035                 .ai_fifo        = ai_fifo_64xx,
1036                 .has_8255       = 1,
1037         },
1038         [BOARD_PCIDAS64_M2_16_JR] = {
1039                 .name = "pci-das64/m2/16/jr",
1040                 .ai_se_chans    = 64,
1041                 .ai_bits        = 16,
1042                 .ai_speed       = 500,
1043                 .ao_nchan       = 0,
1044                 .ao_scan_speed  = 10000,
1045                 .layout         = LAYOUT_64XX,
1046                 .ai_range_table = &ai_ranges_64_mx,
1047                 .ai_range_code  = ai_range_code_64_mx,
1048                 .ai_fifo        = ai_fifo_64xx,
1049                 .has_8255       = 1,
1050         },
1051         [BOARD_PCIDAS64_M3_16_JR] = {
1052                 .name           = "pci-das64/m3/16/jr",
1053                 .ai_se_chans    = 64,
1054                 .ai_bits        = 16,
1055                 .ai_speed       = 333,
1056                 .ao_nchan       = 0,
1057                 .ao_scan_speed  = 10000,
1058                 .layout         = LAYOUT_64XX,
1059                 .ai_range_table = &ai_ranges_64_mx,
1060                 .ai_range_code  = ai_range_code_64_mx,
1061                 .ai_fifo        = ai_fifo_64xx,
1062                 .has_8255       = 1,
1063         },
1064         [BOARD_PCIDAS64_M1_14] = {
1065                 .name           = "pci-das64/m1/14",
1066                 .ai_se_chans    = 64,
1067                 .ai_bits        = 14,
1068                 .ai_speed       = 1000,
1069                 .ao_nchan       = 2,
1070                 .ao_scan_speed  = 10000,
1071                 .layout         = LAYOUT_64XX,
1072                 .ai_range_table = &ai_ranges_64_mx,
1073                 .ai_range_code  = ai_range_code_64_mx,
1074                 .ai_fifo        = ai_fifo_64xx,
1075                 .has_8255       = 1,
1076         },
1077         [BOARD_PCIDAS64_M2_14] = {
1078                 .name           = "pci-das64/m2/14",
1079                 .ai_se_chans    = 64,
1080                 .ai_bits        = 14,
1081                 .ai_speed       = 500,
1082                 .ao_nchan       = 2,
1083                 .ao_scan_speed  = 10000,
1084                 .layout         = LAYOUT_64XX,
1085                 .ai_range_table = &ai_ranges_64_mx,
1086                 .ai_range_code  = ai_range_code_64_mx,
1087                 .ai_fifo        = ai_fifo_64xx,
1088                 .has_8255       = 1,
1089         },
1090         [BOARD_PCIDAS64_M3_14] = {
1091                 .name           = "pci-das64/m3/14",
1092                 .ai_se_chans    = 64,
1093                 .ai_bits        = 14,
1094                 .ai_speed       = 333,
1095                 .ao_nchan       = 2,
1096                 .ao_scan_speed  = 10000,
1097                 .layout         = LAYOUT_64XX,
1098                 .ai_range_table = &ai_ranges_64_mx,
1099                 .ai_range_code  = ai_range_code_64_mx,
1100                 .ai_fifo        = ai_fifo_64xx,
1101                 .has_8255       = 1,
1102         },
1103 #endif
1104 };
1105
1106 static inline unsigned short se_diff_bit_6xxx(struct comedi_device *dev,
1107                                               int use_differential)
1108 {
1109         const struct pcidas64_board *thisboard = dev->board_ptr;
1110
1111         if ((thisboard->layout == LAYOUT_64XX && !use_differential) ||
1112             (thisboard->layout == LAYOUT_60XX && use_differential))
1113                 return ADC_SE_DIFF_BIT;
1114
1115         return 0;
1116 }
1117
1118 struct ext_clock_info {
1119         /*  master clock divisor to use for scans with external master clock */
1120         unsigned int divisor;
1121         /*  chanspec for master clock input when used as scan begin src */
1122         unsigned int chanspec;
1123 };
1124
1125 /* this structure is for data unique to this hardware driver. */
1126 struct pcidas64_private {
1127         /*  base addresses (physical) */
1128         resource_size_t main_phys_iobase;
1129         resource_size_t dio_counter_phys_iobase;
1130         /*  base addresses (ioremapped) */
1131         void __iomem *plx9080_iobase;
1132         void __iomem *main_iobase;
1133         /*  local address (used by dma controller) */
1134         uint32_t local0_iobase;
1135         uint32_t local1_iobase;
1136         /*  dma buffers for analog input */
1137         uint16_t *ai_buffer[MAX_AI_DMA_RING_COUNT];
1138         /*  physical addresses of ai dma buffers */
1139         dma_addr_t ai_buffer_bus_addr[MAX_AI_DMA_RING_COUNT];
1140         /*  array of ai dma descriptors read by plx9080,
1141          *  allocated to get proper alignment */
1142         struct plx_dma_desc *ai_dma_desc;
1143         /*  physical address of ai dma descriptor array */
1144         dma_addr_t ai_dma_desc_bus_addr;
1145         /*  index of the ai dma descriptor/buffer
1146          *  that is currently being used */
1147         unsigned int ai_dma_index;
1148         /*  dma buffers for analog output */
1149         uint16_t *ao_buffer[AO_DMA_RING_COUNT];
1150         /*  physical addresses of ao dma buffers */
1151         dma_addr_t ao_buffer_bus_addr[AO_DMA_RING_COUNT];
1152         struct plx_dma_desc *ao_dma_desc;
1153         dma_addr_t ao_dma_desc_bus_addr;
1154         /*  keeps track of buffer where the next ao sample should go */
1155         unsigned int ao_dma_index;
1156         unsigned int hw_revision;       /*  stc chip hardware revision number */
1157         /*  last bits sent to INTR_ENABLE_REG register */
1158         unsigned int intr_enable_bits;
1159         /*  last bits sent to ADC_CONTROL1_REG register */
1160         uint16_t adc_control1_bits;
1161         /*  last bits sent to FIFO_SIZE_REG register */
1162         uint16_t fifo_size_bits;
1163         /*  last bits sent to HW_CONFIG_REG register */
1164         uint16_t hw_config_bits;
1165         uint16_t dac_control1_bits;
1166         /*  last bits written to plx9080 control register */
1167         uint32_t plx_control_bits;
1168         /*  last bits written to plx interrupt control and status register */
1169         uint32_t plx_intcsr_bits;
1170         /*  index of calibration source readable through ai ch0 */
1171         int calibration_source;
1172         /*  bits written to i2c calibration/range register */
1173         uint8_t i2c_cal_range_bits;
1174         /*  configure digital triggers to trigger on falling edge */
1175         unsigned int ext_trig_falling;
1176         short ai_cmd_running;
1177         unsigned int ai_fifo_segment_length;
1178         struct ext_clock_info ext_clock;
1179         unsigned short ao_bounce_buffer[DAC_FIFO_SIZE];
1180 };
1181
1182 static unsigned int ai_range_bits_6xxx(const struct comedi_device *dev,
1183                                        unsigned int range_index)
1184 {
1185         const struct pcidas64_board *thisboard = dev->board_ptr;
1186
1187         return thisboard->ai_range_code[range_index] << 8;
1188 }
1189
1190 static unsigned int hw_revision(const struct comedi_device *dev,
1191                                 uint16_t hw_status_bits)
1192 {
1193         const struct pcidas64_board *thisboard = dev->board_ptr;
1194
1195         if (thisboard->layout == LAYOUT_4020)
1196                 return (hw_status_bits >> 13) & 0x7;
1197
1198         return (hw_status_bits >> 12) & 0xf;
1199 }
1200
1201 static void set_dac_range_bits(struct comedi_device *dev,
1202                                uint16_t *bits, unsigned int channel,
1203                                unsigned int range)
1204 {
1205         const struct pcidas64_board *thisboard = dev->board_ptr;
1206         unsigned int code = thisboard->ao_range_code[range];
1207
1208         if (channel > 1)
1209                 dev_err(dev->class_dev, "bug! bad channel?\n");
1210         if (code & ~0x3)
1211                 dev_err(dev->class_dev, "bug! bad range code?\n");
1212
1213         *bits &= ~(0x3 << (2 * channel));
1214         *bits |= code << (2 * channel);
1215 };
1216
1217 static inline int ao_cmd_is_supported(const struct pcidas64_board *board)
1218 {
1219         return board->ao_nchan && board->layout != LAYOUT_4020;
1220 }
1221
1222 static void abort_dma(struct comedi_device *dev, unsigned int channel)
1223 {
1224         struct pcidas64_private *devpriv = dev->private;
1225         unsigned long flags;
1226
1227         /*  spinlock for plx dma control/status reg */
1228         spin_lock_irqsave(&dev->spinlock, flags);
1229
1230         plx9080_abort_dma(devpriv->plx9080_iobase, channel);
1231
1232         spin_unlock_irqrestore(&dev->spinlock, flags);
1233 }
1234
1235 static void disable_plx_interrupts(struct comedi_device *dev)
1236 {
1237         struct pcidas64_private *devpriv = dev->private;
1238
1239         devpriv->plx_intcsr_bits = 0;
1240         writel(devpriv->plx_intcsr_bits,
1241                devpriv->plx9080_iobase + PLX_INTRCS_REG);
1242 }
1243
1244 static void disable_ai_interrupts(struct comedi_device *dev)
1245 {
1246         struct pcidas64_private *devpriv = dev->private;
1247         unsigned long flags;
1248
1249         spin_lock_irqsave(&dev->spinlock, flags);
1250         devpriv->intr_enable_bits &=
1251                 ~EN_ADC_INTR_SRC_BIT & ~EN_ADC_DONE_INTR_BIT &
1252                 ~EN_ADC_ACTIVE_INTR_BIT & ~EN_ADC_STOP_INTR_BIT &
1253                 ~EN_ADC_OVERRUN_BIT & ~ADC_INTR_SRC_MASK;
1254         writew(devpriv->intr_enable_bits,
1255                devpriv->main_iobase + INTR_ENABLE_REG);
1256         spin_unlock_irqrestore(&dev->spinlock, flags);
1257 }
1258
1259 static void enable_ai_interrupts(struct comedi_device *dev,
1260                                  const struct comedi_cmd *cmd)
1261 {
1262         const struct pcidas64_board *thisboard = dev->board_ptr;
1263         struct pcidas64_private *devpriv = dev->private;
1264         uint32_t bits;
1265         unsigned long flags;
1266
1267         bits = EN_ADC_OVERRUN_BIT | EN_ADC_DONE_INTR_BIT |
1268                EN_ADC_ACTIVE_INTR_BIT | EN_ADC_STOP_INTR_BIT;
1269         /*
1270          * Use pio transfer and interrupt on end of conversion
1271          * if CMDF_WAKE_EOS flag is set.
1272          */
1273         if (cmd->flags & CMDF_WAKE_EOS) {
1274                 /*  4020 doesn't support pio transfers except for fifo dregs */
1275                 if (thisboard->layout != LAYOUT_4020)
1276                         bits |= ADC_INTR_EOSCAN_BITS | EN_ADC_INTR_SRC_BIT;
1277         }
1278         spin_lock_irqsave(&dev->spinlock, flags);
1279         devpriv->intr_enable_bits |= bits;
1280         writew(devpriv->intr_enable_bits,
1281                devpriv->main_iobase + INTR_ENABLE_REG);
1282         spin_unlock_irqrestore(&dev->spinlock, flags);
1283 }
1284
1285 /* initialize plx9080 chip */
1286 static void init_plx9080(struct comedi_device *dev)
1287 {
1288         const struct pcidas64_board *thisboard = dev->board_ptr;
1289         struct pcidas64_private *devpriv = dev->private;
1290         uint32_t bits;
1291         void __iomem *plx_iobase = devpriv->plx9080_iobase;
1292
1293         devpriv->plx_control_bits =
1294                 readl(devpriv->plx9080_iobase + PLX_CONTROL_REG);
1295
1296 #ifdef __BIG_ENDIAN
1297         bits = BIGEND_DMA0 | BIGEND_DMA1;
1298 #else
1299         bits = 0;
1300 #endif
1301         writel(bits, devpriv->plx9080_iobase + PLX_BIGEND_REG);
1302
1303         disable_plx_interrupts(dev);
1304
1305         abort_dma(dev, 0);
1306         abort_dma(dev, 1);
1307
1308         /*  configure dma0 mode */
1309         bits = 0;
1310         /*  enable ready input, not sure if this is necessary */
1311         bits |= PLX_DMA_EN_READYIN_BIT;
1312         /*  enable bterm, not sure if this is necessary */
1313         bits |= PLX_EN_BTERM_BIT;
1314         /*  enable dma chaining */
1315         bits |= PLX_EN_CHAIN_BIT;
1316         /*  enable interrupt on dma done
1317          *  (probably don't need this, since chain never finishes) */
1318         bits |= PLX_EN_DMA_DONE_INTR_BIT;
1319         /*  don't increment local address during transfers
1320          *  (we are transferring from a fixed fifo register) */
1321         bits |= PLX_LOCAL_ADDR_CONST_BIT;
1322         /*  route dma interrupt to pci bus */
1323         bits |= PLX_DMA_INTR_PCI_BIT;
1324         /*  enable demand mode */
1325         bits |= PLX_DEMAND_MODE_BIT;
1326         /*  enable local burst mode */
1327         bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
1328         /*  4020 uses 32 bit dma */
1329         if (thisboard->layout == LAYOUT_4020)
1330                 bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
1331         else            /*  localspace0 bus is 16 bits wide */
1332                 bits |= PLX_LOCAL_BUS_16_WIDE_BITS;
1333         writel(bits, plx_iobase + PLX_DMA1_MODE_REG);
1334         if (ao_cmd_is_supported(thisboard))
1335                 writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
1336
1337         /*  enable interrupts on plx 9080 */
1338         devpriv->plx_intcsr_bits |=
1339             ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
1340             ICS_DMA0_E | ICS_DMA1_E;
1341         writel(devpriv->plx_intcsr_bits,
1342                devpriv->plx9080_iobase + PLX_INTRCS_REG);
1343 }
1344
1345 static void disable_ai_pacing(struct comedi_device *dev)
1346 {
1347         struct pcidas64_private *devpriv = dev->private;
1348         unsigned long flags;
1349
1350         disable_ai_interrupts(dev);
1351
1352         spin_lock_irqsave(&dev->spinlock, flags);
1353         devpriv->adc_control1_bits &= ~ADC_SW_GATE_BIT;
1354         writew(devpriv->adc_control1_bits,
1355                devpriv->main_iobase + ADC_CONTROL1_REG);
1356         spin_unlock_irqrestore(&dev->spinlock, flags);
1357
1358         /* disable pacing, triggering, etc */
1359         writew(ADC_DMA_DISABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT,
1360                devpriv->main_iobase + ADC_CONTROL0_REG);
1361 }
1362
1363 static int set_ai_fifo_segment_length(struct comedi_device *dev,
1364                                       unsigned int num_entries)
1365 {
1366         const struct pcidas64_board *thisboard = dev->board_ptr;
1367         struct pcidas64_private *devpriv = dev->private;
1368         static const int increment_size = 0x100;
1369         const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1370         unsigned int num_increments;
1371         uint16_t bits;
1372
1373         if (num_entries < increment_size)
1374                 num_entries = increment_size;
1375         if (num_entries > fifo->max_segment_length)
1376                 num_entries = fifo->max_segment_length;
1377
1378         /*  1 == 256 entries, 2 == 512 entries, etc */
1379         num_increments = (num_entries + increment_size / 2) / increment_size;
1380
1381         bits = (~(num_increments - 1)) & fifo->fifo_size_reg_mask;
1382         devpriv->fifo_size_bits &= ~fifo->fifo_size_reg_mask;
1383         devpriv->fifo_size_bits |= bits;
1384         writew(devpriv->fifo_size_bits,
1385                devpriv->main_iobase + FIFO_SIZE_REG);
1386
1387         devpriv->ai_fifo_segment_length = num_increments * increment_size;
1388
1389         return devpriv->ai_fifo_segment_length;
1390 }
1391
1392 /*
1393  * adjusts the size of hardware fifo (which determines block size for dma xfers)
1394  */
1395 static int set_ai_fifo_size(struct comedi_device *dev, unsigned int num_samples)
1396 {
1397         const struct pcidas64_board *thisboard = dev->board_ptr;
1398         unsigned int num_fifo_entries;
1399         int retval;
1400         const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1401
1402         num_fifo_entries = num_samples / fifo->sample_packing_ratio;
1403
1404         retval = set_ai_fifo_segment_length(dev,
1405                                             num_fifo_entries /
1406                                             fifo->num_segments);
1407         if (retval < 0)
1408                 return retval;
1409
1410         num_samples = retval * fifo->num_segments * fifo->sample_packing_ratio;
1411
1412         return num_samples;
1413 }
1414
1415 /* query length of fifo */
1416 static unsigned int ai_fifo_size(struct comedi_device *dev)
1417 {
1418         const struct pcidas64_board *thisboard = dev->board_ptr;
1419         struct pcidas64_private *devpriv = dev->private;
1420
1421         return devpriv->ai_fifo_segment_length *
1422                thisboard->ai_fifo->num_segments *
1423                thisboard->ai_fifo->sample_packing_ratio;
1424 }
1425
1426 static void init_stc_registers(struct comedi_device *dev)
1427 {
1428         const struct pcidas64_board *thisboard = dev->board_ptr;
1429         struct pcidas64_private *devpriv = dev->private;
1430         uint16_t bits;
1431         unsigned long flags;
1432
1433         spin_lock_irqsave(&dev->spinlock, flags);
1434
1435         /*
1436          * bit should be set for 6025,
1437          * although docs say boards with <= 16 chans should be cleared XXX
1438          */
1439         if (1)
1440                 devpriv->adc_control1_bits |= ADC_QUEUE_CONFIG_BIT;
1441         writew(devpriv->adc_control1_bits,
1442                devpriv->main_iobase + ADC_CONTROL1_REG);
1443
1444         /*  6402/16 manual says this register must be initialized to 0xff? */
1445         writew(0xff, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1446
1447         bits = SLOW_DAC_BIT | DMA_CH_SELECT_BIT;
1448         if (thisboard->layout == LAYOUT_4020)
1449                 bits |= INTERNAL_CLOCK_4020_BITS;
1450         devpriv->hw_config_bits |= bits;
1451         writew(devpriv->hw_config_bits,
1452                devpriv->main_iobase + HW_CONFIG_REG);
1453
1454         writew(0, devpriv->main_iobase + DAQ_SYNC_REG);
1455         writew(0, devpriv->main_iobase + CALIBRATION_REG);
1456
1457         spin_unlock_irqrestore(&dev->spinlock, flags);
1458
1459         /*  set fifos to maximum size */
1460         devpriv->fifo_size_bits |= DAC_FIFO_BITS;
1461         set_ai_fifo_segment_length(dev,
1462                                    thisboard->ai_fifo->max_segment_length);
1463
1464         devpriv->dac_control1_bits = DAC_OUTPUT_ENABLE_BIT;
1465         devpriv->intr_enable_bits =
1466                 /* EN_DAC_INTR_SRC_BIT | DAC_INTR_QEMPTY_BITS | */
1467                 EN_DAC_DONE_INTR_BIT | EN_DAC_UNDERRUN_BIT;
1468         writew(devpriv->intr_enable_bits,
1469                devpriv->main_iobase + INTR_ENABLE_REG);
1470
1471         disable_ai_pacing(dev);
1472 };
1473
1474 static int alloc_and_init_dma_members(struct comedi_device *dev)
1475 {
1476         const struct pcidas64_board *thisboard = dev->board_ptr;
1477         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1478         struct pcidas64_private *devpriv = dev->private;
1479         int i;
1480
1481         /*  allocate pci dma buffers */
1482         for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
1483                 devpriv->ai_buffer[i] =
1484                         pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
1485                                              &devpriv->ai_buffer_bus_addr[i]);
1486                 if (!devpriv->ai_buffer[i])
1487                         return -ENOMEM;
1488         }
1489         for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1490                 if (ao_cmd_is_supported(thisboard)) {
1491                         devpriv->ao_buffer[i] =
1492                                 pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
1493                                                      &devpriv->
1494                                                       ao_buffer_bus_addr[i]);
1495                         if (!devpriv->ao_buffer[i])
1496                                 return -ENOMEM;
1497                 }
1498         }
1499         /*  allocate dma descriptors */
1500         devpriv->ai_dma_desc =
1501                 pci_alloc_consistent(pcidev, sizeof(struct plx_dma_desc) *
1502                                      ai_dma_ring_count(thisboard),
1503                                      &devpriv->ai_dma_desc_bus_addr);
1504         if (!devpriv->ai_dma_desc)
1505                 return -ENOMEM;
1506
1507         if (ao_cmd_is_supported(thisboard)) {
1508                 devpriv->ao_dma_desc =
1509                         pci_alloc_consistent(pcidev,
1510                                              sizeof(struct plx_dma_desc) *
1511                                              AO_DMA_RING_COUNT,
1512                                              &devpriv->ao_dma_desc_bus_addr);
1513                 if (!devpriv->ao_dma_desc)
1514                         return -ENOMEM;
1515         }
1516         /*  initialize dma descriptors */
1517         for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
1518                 devpriv->ai_dma_desc[i].pci_start_addr =
1519                         cpu_to_le32(devpriv->ai_buffer_bus_addr[i]);
1520                 if (thisboard->layout == LAYOUT_4020)
1521                         devpriv->ai_dma_desc[i].local_start_addr =
1522                                 cpu_to_le32(devpriv->local1_iobase +
1523                                             ADC_FIFO_REG);
1524                 else
1525                         devpriv->ai_dma_desc[i].local_start_addr =
1526                                 cpu_to_le32(devpriv->local0_iobase +
1527                                             ADC_FIFO_REG);
1528                 devpriv->ai_dma_desc[i].transfer_size = cpu_to_le32(0);
1529                 devpriv->ai_dma_desc[i].next =
1530                         cpu_to_le32((devpriv->ai_dma_desc_bus_addr +
1531                                      ((i + 1) % ai_dma_ring_count(thisboard)) *
1532                                      sizeof(devpriv->ai_dma_desc[0])) |
1533                                     PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
1534                                     PLX_XFER_LOCAL_TO_PCI);
1535         }
1536         if (ao_cmd_is_supported(thisboard)) {
1537                 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1538                         devpriv->ao_dma_desc[i].pci_start_addr =
1539                                 cpu_to_le32(devpriv->ao_buffer_bus_addr[i]);
1540                         devpriv->ao_dma_desc[i].local_start_addr =
1541                                 cpu_to_le32(devpriv->local0_iobase +
1542                                             DAC_FIFO_REG);
1543                         devpriv->ao_dma_desc[i].transfer_size = cpu_to_le32(0);
1544                         devpriv->ao_dma_desc[i].next =
1545                                 cpu_to_le32((devpriv->ao_dma_desc_bus_addr +
1546                                              ((i + 1) % (AO_DMA_RING_COUNT)) *
1547                                              sizeof(devpriv->ao_dma_desc[0])) |
1548                                             PLX_DESC_IN_PCI_BIT |
1549                                             PLX_INTR_TERM_COUNT);
1550                 }
1551         }
1552         return 0;
1553 }
1554
1555 static void cb_pcidas64_free_dma(struct comedi_device *dev)
1556 {
1557         const struct pcidas64_board *thisboard = dev->board_ptr;
1558         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1559         struct pcidas64_private *devpriv = dev->private;
1560         int i;
1561
1562         if (!devpriv)
1563                 return;
1564
1565         /* free pci dma buffers */
1566         for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
1567                 if (devpriv->ai_buffer[i])
1568                         pci_free_consistent(pcidev,
1569                                             DMA_BUFFER_SIZE,
1570                                             devpriv->ai_buffer[i],
1571                                             devpriv->ai_buffer_bus_addr[i]);
1572         }
1573         for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1574                 if (devpriv->ao_buffer[i])
1575                         pci_free_consistent(pcidev,
1576                                             DMA_BUFFER_SIZE,
1577                                             devpriv->ao_buffer[i],
1578                                             devpriv->ao_buffer_bus_addr[i]);
1579         }
1580         /* free dma descriptors */
1581         if (devpriv->ai_dma_desc)
1582                 pci_free_consistent(pcidev,
1583                                     sizeof(struct plx_dma_desc) *
1584                                     ai_dma_ring_count(thisboard),
1585                                     devpriv->ai_dma_desc,
1586                                     devpriv->ai_dma_desc_bus_addr);
1587         if (devpriv->ao_dma_desc)
1588                 pci_free_consistent(pcidev,
1589                                     sizeof(struct plx_dma_desc) *
1590                                     AO_DMA_RING_COUNT,
1591                                     devpriv->ao_dma_desc,
1592                                     devpriv->ao_dma_desc_bus_addr);
1593 }
1594
1595 static inline void warn_external_queue(struct comedi_device *dev)
1596 {
1597         dev_err(dev->class_dev,
1598                 "AO command and AI external channel queue cannot be used simultaneously\n");
1599         dev_err(dev->class_dev,
1600                 "Use internal AI channel queue (channels must be consecutive and use same range/aref)\n");
1601 }
1602
1603 /*
1604  * their i2c requires a huge delay on setting clock or data high for some reason
1605  */
1606 static const int i2c_high_udelay = 1000;
1607 static const int i2c_low_udelay = 10;
1608
1609 /* set i2c data line high or low */
1610 static void i2c_set_sda(struct comedi_device *dev, int state)
1611 {
1612         struct pcidas64_private *devpriv = dev->private;
1613         static const int data_bit = CTL_EE_W;
1614         void __iomem *plx_control_addr = devpriv->plx9080_iobase +
1615                                          PLX_CONTROL_REG;
1616
1617         if (state) {
1618                 /*  set data line high */
1619                 devpriv->plx_control_bits &= ~data_bit;
1620                 writel(devpriv->plx_control_bits, plx_control_addr);
1621                 udelay(i2c_high_udelay);
1622         } else {                /*  set data line low */
1623
1624                 devpriv->plx_control_bits |= data_bit;
1625                 writel(devpriv->plx_control_bits, plx_control_addr);
1626                 udelay(i2c_low_udelay);
1627         }
1628 }
1629
1630 /* set i2c clock line high or low */
1631 static void i2c_set_scl(struct comedi_device *dev, int state)
1632 {
1633         struct pcidas64_private *devpriv = dev->private;
1634         static const int clock_bit = CTL_USERO;
1635         void __iomem *plx_control_addr = devpriv->plx9080_iobase +
1636                                          PLX_CONTROL_REG;
1637
1638         if (state) {
1639                 /*  set clock line high */
1640                 devpriv->plx_control_bits &= ~clock_bit;
1641                 writel(devpriv->plx_control_bits, plx_control_addr);
1642                 udelay(i2c_high_udelay);
1643         } else {                /*  set clock line low */
1644
1645                 devpriv->plx_control_bits |= clock_bit;
1646                 writel(devpriv->plx_control_bits, plx_control_addr);
1647                 udelay(i2c_low_udelay);
1648         }
1649 }
1650
1651 static void i2c_write_byte(struct comedi_device *dev, uint8_t byte)
1652 {
1653         uint8_t bit;
1654         unsigned int num_bits = 8;
1655
1656         for (bit = 1 << (num_bits - 1); bit; bit >>= 1) {
1657                 i2c_set_scl(dev, 0);
1658                 if ((byte & bit))
1659                         i2c_set_sda(dev, 1);
1660                 else
1661                         i2c_set_sda(dev, 0);
1662                 i2c_set_scl(dev, 1);
1663         }
1664 }
1665
1666 /* we can't really read the lines, so fake it */
1667 static int i2c_read_ack(struct comedi_device *dev)
1668 {
1669         i2c_set_scl(dev, 0);
1670         i2c_set_sda(dev, 1);
1671         i2c_set_scl(dev, 1);
1672
1673         return 0;               /*  return fake acknowledge bit */
1674 }
1675
1676 /* send start bit */
1677 static void i2c_start(struct comedi_device *dev)
1678 {
1679         i2c_set_scl(dev, 1);
1680         i2c_set_sda(dev, 1);
1681         i2c_set_sda(dev, 0);
1682 }
1683
1684 /* send stop bit */
1685 static void i2c_stop(struct comedi_device *dev)
1686 {
1687         i2c_set_scl(dev, 0);
1688         i2c_set_sda(dev, 0);
1689         i2c_set_scl(dev, 1);
1690         i2c_set_sda(dev, 1);
1691 }
1692
1693 static void i2c_write(struct comedi_device *dev, unsigned int address,
1694                       const uint8_t *data, unsigned int length)
1695 {
1696         struct pcidas64_private *devpriv = dev->private;
1697         unsigned int i;
1698         uint8_t bitstream;
1699         static const int read_bit = 0x1;
1700
1701         /*
1702          * XXX need mutex to prevent simultaneous attempts to access
1703          * eeprom and i2c bus
1704          */
1705
1706         /*  make sure we dont send anything to eeprom */
1707         devpriv->plx_control_bits &= ~CTL_EE_CS;
1708
1709         i2c_stop(dev);
1710         i2c_start(dev);
1711
1712         /*  send address and write bit */
1713         bitstream = (address << 1) & ~read_bit;
1714         i2c_write_byte(dev, bitstream);
1715
1716         /*  get acknowledge */
1717         if (i2c_read_ack(dev) != 0) {
1718                 dev_err(dev->class_dev, "failed: no acknowledge\n");
1719                 i2c_stop(dev);
1720                 return;
1721         }
1722         /*  write data bytes */
1723         for (i = 0; i < length; i++) {
1724                 i2c_write_byte(dev, data[i]);
1725                 if (i2c_read_ack(dev) != 0) {
1726                         dev_err(dev->class_dev, "failed: no acknowledge\n");
1727                         i2c_stop(dev);
1728                         return;
1729                 }
1730         }
1731         i2c_stop(dev);
1732 }
1733
1734 static int cb_pcidas64_ai_eoc(struct comedi_device *dev,
1735                               struct comedi_subdevice *s,
1736                               struct comedi_insn *insn,
1737                               unsigned long context)
1738 {
1739         const struct pcidas64_board *thisboard = dev->board_ptr;
1740         struct pcidas64_private *devpriv = dev->private;
1741         unsigned int status;
1742
1743         status = readw(devpriv->main_iobase + HW_STATUS_REG);
1744         if (thisboard->layout == LAYOUT_4020) {
1745                 status = readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG);
1746                 if (status)
1747                         return 0;
1748         } else {
1749                 if (pipe_full_bits(status))
1750                         return 0;
1751         }
1752         return -EBUSY;
1753 }
1754
1755 static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1756                     struct comedi_insn *insn, unsigned int *data)
1757 {
1758         const struct pcidas64_board *thisboard = dev->board_ptr;
1759         struct pcidas64_private *devpriv = dev->private;
1760         unsigned int bits = 0, n;
1761         unsigned int channel, range, aref;
1762         unsigned long flags;
1763         int ret;
1764
1765         channel = CR_CHAN(insn->chanspec);
1766         range = CR_RANGE(insn->chanspec);
1767         aref = CR_AREF(insn->chanspec);
1768
1769         /*  disable card's analog input interrupt sources and pacing */
1770         /*  4020 generates dac done interrupts even though they are disabled */
1771         disable_ai_pacing(dev);
1772
1773         spin_lock_irqsave(&dev->spinlock, flags);
1774         if (insn->chanspec & CR_ALT_FILTER)
1775                 devpriv->adc_control1_bits |= ADC_DITHER_BIT;
1776         else
1777                 devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
1778         writew(devpriv->adc_control1_bits,
1779                devpriv->main_iobase + ADC_CONTROL1_REG);
1780         spin_unlock_irqrestore(&dev->spinlock, flags);
1781
1782         if (thisboard->layout != LAYOUT_4020) {
1783                 /*  use internal queue */
1784                 devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
1785                 writew(devpriv->hw_config_bits,
1786                        devpriv->main_iobase + HW_CONFIG_REG);
1787
1788                 /*  ALT_SOURCE is internal calibration reference */
1789                 if (insn->chanspec & CR_ALT_SOURCE) {
1790                         unsigned int cal_en_bit;
1791
1792                         if (thisboard->layout == LAYOUT_60XX)
1793                                 cal_en_bit = CAL_EN_60XX_BIT;
1794                         else
1795                                 cal_en_bit = CAL_EN_64XX_BIT;
1796                         /*
1797                          * select internal reference source to connect
1798                          * to channel 0
1799                          */
1800                         writew(cal_en_bit |
1801                                adc_src_bits(devpriv->calibration_source),
1802                                devpriv->main_iobase + CALIBRATION_REG);
1803                 } else {
1804                         /*
1805                          * make sure internal calibration source
1806                          * is turned off
1807                          */
1808                         writew(0, devpriv->main_iobase + CALIBRATION_REG);
1809                 }
1810                 /*  load internal queue */
1811                 bits = 0;
1812                 /*  set gain */
1813                 bits |= ai_range_bits_6xxx(dev, CR_RANGE(insn->chanspec));
1814                 /*  set single-ended / differential */
1815                 bits |= se_diff_bit_6xxx(dev, aref == AREF_DIFF);
1816                 if (aref == AREF_COMMON)
1817                         bits |= ADC_COMMON_BIT;
1818                 bits |= adc_chan_bits(channel);
1819                 /*  set stop channel */
1820                 writew(adc_chan_bits(channel),
1821                        devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
1822                 /*  set start channel, and rest of settings */
1823                 writew(bits, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
1824         } else {
1825                 uint8_t old_cal_range_bits = devpriv->i2c_cal_range_bits;
1826
1827                 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
1828                 if (insn->chanspec & CR_ALT_SOURCE) {
1829                         devpriv->i2c_cal_range_bits |=
1830                                 adc_src_4020_bits(devpriv->calibration_source);
1831                 } else {        /* select BNC inputs */
1832                         devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
1833                 }
1834                 /*  select range */
1835                 if (range == 0)
1836                         devpriv->i2c_cal_range_bits |= attenuate_bit(channel);
1837                 else
1838                         devpriv->i2c_cal_range_bits &= ~attenuate_bit(channel);
1839                 /*
1840                  * update calibration/range i2c register only if necessary,
1841                  * as it is very slow
1842                  */
1843                 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
1844                         uint8_t i2c_data = devpriv->i2c_cal_range_bits;
1845
1846                         i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
1847                                   sizeof(i2c_data));
1848                 }
1849
1850                 /*
1851                  * 4020 manual asks that sample interval register to be set
1852                  * before writing to convert register.
1853                  * Using somewhat arbitrary setting of 4 master clock ticks
1854                  * = 0.1 usec
1855                  */
1856                 writew(0, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1857                 writew(2, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
1858         }
1859
1860         for (n = 0; n < insn->n; n++) {
1861                 /*  clear adc buffer (inside loop for 4020 sake) */
1862                 writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
1863
1864                 /* trigger conversion, bits sent only matter for 4020 */
1865                 writew(adc_convert_chan_4020_bits(CR_CHAN(insn->chanspec)),
1866                        devpriv->main_iobase + ADC_CONVERT_REG);
1867
1868                 /*  wait for data */
1869                 ret = comedi_timeout(dev, s, insn, cb_pcidas64_ai_eoc, 0);
1870                 if (ret)
1871                         return ret;
1872
1873                 if (thisboard->layout == LAYOUT_4020)
1874                         data[n] = readl(dev->mmio + ADC_FIFO_REG) & 0xffff;
1875                 else
1876                         data[n] = readw(devpriv->main_iobase + PIPE1_READ_REG);
1877         }
1878
1879         return n;
1880 }
1881
1882 static int ai_config_calibration_source(struct comedi_device *dev,
1883                                         unsigned int *data)
1884 {
1885         const struct pcidas64_board *thisboard = dev->board_ptr;
1886         struct pcidas64_private *devpriv = dev->private;
1887         unsigned int source = data[1];
1888         int num_calibration_sources;
1889
1890         if (thisboard->layout == LAYOUT_60XX)
1891                 num_calibration_sources = 16;
1892         else
1893                 num_calibration_sources = 8;
1894         if (source >= num_calibration_sources) {
1895                 dev_dbg(dev->class_dev, "invalid calibration source: %i\n",
1896                         source);
1897                 return -EINVAL;
1898         }
1899
1900         devpriv->calibration_source = source;
1901
1902         return 2;
1903 }
1904
1905 static int ai_config_block_size(struct comedi_device *dev, unsigned int *data)
1906 {
1907         const struct pcidas64_board *thisboard = dev->board_ptr;
1908         int fifo_size;
1909         const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1910         unsigned int block_size, requested_block_size;
1911         int retval;
1912
1913         requested_block_size = data[1];
1914
1915         if (requested_block_size) {
1916                 fifo_size = requested_block_size * fifo->num_segments /
1917                             bytes_in_sample;
1918
1919                 retval = set_ai_fifo_size(dev, fifo_size);
1920                 if (retval < 0)
1921                         return retval;
1922         }
1923
1924         block_size = ai_fifo_size(dev) / fifo->num_segments * bytes_in_sample;
1925
1926         data[1] = block_size;
1927
1928         return 2;
1929 }
1930
1931 static int ai_config_master_clock_4020(struct comedi_device *dev,
1932                                        unsigned int *data)
1933 {
1934         struct pcidas64_private *devpriv = dev->private;
1935         unsigned int divisor = data[4];
1936         int retval = 0;
1937
1938         if (divisor < 2) {
1939                 divisor = 2;
1940                 retval = -EAGAIN;
1941         }
1942
1943         switch (data[1]) {
1944         case COMEDI_EV_SCAN_BEGIN:
1945                 devpriv->ext_clock.divisor = divisor;
1946                 devpriv->ext_clock.chanspec = data[2];
1947                 break;
1948         default:
1949                 return -EINVAL;
1950         }
1951
1952         data[4] = divisor;
1953
1954         return retval ? retval : 5;
1955 }
1956
1957 /* XXX could add support for 60xx series */
1958 static int ai_config_master_clock(struct comedi_device *dev, unsigned int *data)
1959 {
1960         const struct pcidas64_board *thisboard = dev->board_ptr;
1961
1962         switch (thisboard->layout) {
1963         case LAYOUT_4020:
1964                 return ai_config_master_clock_4020(dev, data);
1965         default:
1966                 return -EINVAL;
1967         }
1968
1969         return -EINVAL;
1970 }
1971
1972 static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s,
1973                           struct comedi_insn *insn, unsigned int *data)
1974 {
1975         int id = data[0];
1976
1977         switch (id) {
1978         case INSN_CONFIG_ALT_SOURCE:
1979                 return ai_config_calibration_source(dev, data);
1980         case INSN_CONFIG_BLOCK_SIZE:
1981                 return ai_config_block_size(dev, data);
1982         case INSN_CONFIG_TIMER_1:
1983                 return ai_config_master_clock(dev, data);
1984         default:
1985                 return -EINVAL;
1986         }
1987         return -EINVAL;
1988 }
1989
1990 /*
1991  * Gets nearest achievable timing given master clock speed, does not
1992  * take into account possible minimum/maximum divisor values.  Used
1993  * by other timing checking functions.
1994  */
1995 static unsigned int get_divisor(unsigned int ns, unsigned int flags)
1996 {
1997         unsigned int divisor;
1998
1999         switch (flags & CMDF_ROUND_MASK) {
2000         case CMDF_ROUND_UP:
2001                 divisor = (ns + TIMER_BASE - 1) / TIMER_BASE;
2002                 break;
2003         case CMDF_ROUND_DOWN:
2004                 divisor = ns / TIMER_BASE;
2005                 break;
2006         case CMDF_ROUND_NEAREST:
2007         default:
2008                 divisor = (ns + TIMER_BASE / 2) / TIMER_BASE;
2009                 break;
2010         }
2011         return divisor;
2012 }
2013
2014 /*
2015  * utility function that rounds desired timing to an achievable time, and
2016  * sets cmd members appropriately.
2017  * adc paces conversions from master clock by dividing by (x + 3) where x is
2018  * 24 bit number
2019  */
2020 static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd)
2021 {
2022         const struct pcidas64_board *thisboard = dev->board_ptr;
2023         unsigned long long convert_divisor = 0;
2024         unsigned int scan_divisor;
2025         static const int min_convert_divisor = 3;
2026         static const int max_convert_divisor =
2027                 max_counter_value + min_convert_divisor;
2028         static const int min_scan_divisor_4020 = 2;
2029         unsigned long long max_scan_divisor, min_scan_divisor;
2030
2031         if (cmd->convert_src == TRIG_TIMER) {
2032                 if (thisboard->layout == LAYOUT_4020) {
2033                         cmd->convert_arg = 0;
2034                 } else {
2035                         convert_divisor = get_divisor(cmd->convert_arg,
2036                                                       cmd->flags);
2037                         if (convert_divisor > max_convert_divisor)
2038                                 convert_divisor = max_convert_divisor;
2039                         if (convert_divisor < min_convert_divisor)
2040                                 convert_divisor = min_convert_divisor;
2041                         cmd->convert_arg = convert_divisor * TIMER_BASE;
2042                 }
2043         } else if (cmd->convert_src == TRIG_NOW) {
2044                 cmd->convert_arg = 0;
2045         }
2046
2047         if (cmd->scan_begin_src == TRIG_TIMER) {
2048                 scan_divisor = get_divisor(cmd->scan_begin_arg, cmd->flags);
2049                 if (cmd->convert_src == TRIG_TIMER) {
2050                         min_scan_divisor = convert_divisor * cmd->chanlist_len;
2051                         max_scan_divisor =
2052                                 (convert_divisor * cmd->chanlist_len - 1) +
2053                                 max_counter_value;
2054                 } else {
2055                         min_scan_divisor = min_scan_divisor_4020;
2056                         max_scan_divisor = max_counter_value + min_scan_divisor;
2057                 }
2058                 if (scan_divisor > max_scan_divisor)
2059                         scan_divisor = max_scan_divisor;
2060                 if (scan_divisor < min_scan_divisor)
2061                         scan_divisor = min_scan_divisor;
2062                 cmd->scan_begin_arg = scan_divisor * TIMER_BASE;
2063         }
2064 }
2065
2066 static int cb_pcidas64_ai_check_chanlist(struct comedi_device *dev,
2067                                          struct comedi_subdevice *s,
2068                                          struct comedi_cmd *cmd)
2069 {
2070         const struct pcidas64_board *board = dev->board_ptr;
2071         unsigned int aref0 = CR_AREF(cmd->chanlist[0]);
2072         int i;
2073
2074         for (i = 1; i < cmd->chanlist_len; i++) {
2075                 unsigned int aref = CR_AREF(cmd->chanlist[i]);
2076
2077                 if (aref != aref0) {
2078                         dev_dbg(dev->class_dev,
2079                                 "all elements in chanlist must use the same analog reference\n");
2080                         return -EINVAL;
2081                 }
2082         }
2083
2084         if (board->layout == LAYOUT_4020) {
2085                 unsigned int chan0 = CR_CHAN(cmd->chanlist[0]);
2086
2087                 for (i = 1; i < cmd->chanlist_len; i++) {
2088                         unsigned int chan = CR_CHAN(cmd->chanlist[i]);
2089
2090                         if (chan != (chan0 + i)) {
2091                                 dev_dbg(dev->class_dev,
2092                                         "chanlist must use consecutive channels\n");
2093                                 return -EINVAL;
2094                         }
2095                 }
2096                 if (cmd->chanlist_len == 3) {
2097                         dev_dbg(dev->class_dev,
2098                                 "chanlist cannot be 3 channels long, use 1, 2, or 4 channels\n");
2099                         return -EINVAL;
2100                 }
2101         }
2102
2103         return 0;
2104 }
2105
2106 static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2107                       struct comedi_cmd *cmd)
2108 {
2109         const struct pcidas64_board *thisboard = dev->board_ptr;
2110         int err = 0;
2111         unsigned int tmp_arg, tmp_arg2;
2112         unsigned int triggers;
2113
2114         /* Step 1 : check if triggers are trivially valid */
2115
2116         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
2117
2118         triggers = TRIG_TIMER;
2119         if (thisboard->layout == LAYOUT_4020)
2120                 triggers |= TRIG_OTHER;
2121         else
2122                 triggers |= TRIG_FOLLOW;
2123         err |= comedi_check_trigger_src(&cmd->scan_begin_src, triggers);
2124
2125         triggers = TRIG_TIMER;
2126         if (thisboard->layout == LAYOUT_4020)
2127                 triggers |= TRIG_NOW;
2128         else
2129                 triggers |= TRIG_EXT;
2130         err |= comedi_check_trigger_src(&cmd->convert_src, triggers);
2131         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2132         err |= comedi_check_trigger_src(&cmd->stop_src,
2133                                         TRIG_COUNT | TRIG_EXT | TRIG_NONE);
2134
2135         if (err)
2136                 return 1;
2137
2138         /* Step 2a : make sure trigger sources are unique */
2139
2140         err |= comedi_check_trigger_is_unique(cmd->start_src);
2141         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
2142         err |= comedi_check_trigger_is_unique(cmd->convert_src);
2143         err |= comedi_check_trigger_is_unique(cmd->stop_src);
2144
2145         /* Step 2b : and mutually compatible */
2146
2147         if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
2148                 err |= -EINVAL;
2149
2150         if (err)
2151                 return 2;
2152
2153         /* Step 3: check if arguments are trivially valid */
2154
2155         switch (cmd->start_src) {
2156         case TRIG_NOW:
2157                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
2158                 break;
2159         case TRIG_EXT:
2160                 /*
2161                  * start_arg is the CR_CHAN | CR_INVERT of the
2162                  * external trigger.
2163                  */
2164                 break;
2165         }
2166
2167         if (cmd->convert_src == TRIG_TIMER) {
2168                 if (thisboard->layout == LAYOUT_4020) {
2169                         err |= comedi_check_trigger_arg_is(&cmd->convert_arg,
2170                                                            0);
2171                 } else {
2172                         err |= comedi_check_trigger_arg_min(&cmd->convert_arg,
2173                                                             thisboard->
2174                                                             ai_speed);
2175                         /*
2176                          * if scans are timed faster than conversion rate
2177                          * allows
2178                          */
2179                         if (cmd->scan_begin_src == TRIG_TIMER) {
2180                                 err |= comedi_check_trigger_arg_min(
2181                                                 &cmd->scan_begin_arg,
2182                                                 cmd->convert_arg *
2183                                                 cmd->chanlist_len);
2184                         }
2185                 }
2186         }
2187
2188         err |= comedi_check_trigger_arg_min(&cmd->chanlist_len, 1);
2189         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
2190                                            cmd->chanlist_len);
2191
2192         switch (cmd->stop_src) {
2193         case TRIG_EXT:
2194                 break;
2195         case TRIG_COUNT:
2196                 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
2197                 break;
2198         case TRIG_NONE:
2199                 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
2200                 break;
2201         default:
2202                 break;
2203         }
2204
2205         if (err)
2206                 return 3;
2207
2208         /* step 4: fix up any arguments */
2209
2210         if (cmd->convert_src == TRIG_TIMER) {
2211                 tmp_arg = cmd->convert_arg;
2212                 tmp_arg2 = cmd->scan_begin_arg;
2213                 check_adc_timing(dev, cmd);
2214                 if (tmp_arg != cmd->convert_arg)
2215                         err++;
2216                 if (tmp_arg2 != cmd->scan_begin_arg)
2217                         err++;
2218         }
2219
2220         if (err)
2221                 return 4;
2222
2223         /* Step 5: check channel list if it exists */
2224         if (cmd->chanlist && cmd->chanlist_len > 0)
2225                 err |= cb_pcidas64_ai_check_chanlist(dev, s, cmd);
2226
2227         if (err)
2228                 return 5;
2229
2230         return 0;
2231 }
2232
2233 static int use_hw_sample_counter(struct comedi_cmd *cmd)
2234 {
2235 /* disable for now until I work out a race */
2236         return 0;
2237
2238         if (cmd->stop_src == TRIG_COUNT && cmd->stop_arg <= max_counter_value)
2239                 return 1;
2240
2241         return 0;
2242 }
2243
2244 static void setup_sample_counters(struct comedi_device *dev,
2245                                   struct comedi_cmd *cmd)
2246 {
2247         struct pcidas64_private *devpriv = dev->private;
2248
2249         /*  load hardware conversion counter */
2250         if (use_hw_sample_counter(cmd)) {
2251                 writew(cmd->stop_arg & 0xffff,
2252                        devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2253                 writew((cmd->stop_arg >> 16) & 0xff,
2254                        devpriv->main_iobase + ADC_COUNT_UPPER_REG);
2255         } else {
2256                 writew(1, devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2257         }
2258 }
2259
2260 static inline unsigned int dma_transfer_size(struct comedi_device *dev)
2261 {
2262         const struct pcidas64_board *thisboard = dev->board_ptr;
2263         struct pcidas64_private *devpriv = dev->private;
2264         unsigned int num_samples;
2265
2266         num_samples = devpriv->ai_fifo_segment_length *
2267                       thisboard->ai_fifo->sample_packing_ratio;
2268         if (num_samples > DMA_BUFFER_SIZE / sizeof(uint16_t))
2269                 num_samples = DMA_BUFFER_SIZE / sizeof(uint16_t);
2270
2271         return num_samples;
2272 }
2273
2274 static uint32_t ai_convert_counter_6xxx(const struct comedi_device *dev,
2275                                         const struct comedi_cmd *cmd)
2276 {
2277         /*  supposed to load counter with desired divisor minus 3 */
2278         return cmd->convert_arg / TIMER_BASE - 3;
2279 }
2280
2281 static uint32_t ai_scan_counter_6xxx(struct comedi_device *dev,
2282                                      struct comedi_cmd *cmd)
2283 {
2284         uint32_t count;
2285
2286         /*  figure out how long we need to delay at end of scan */
2287         switch (cmd->scan_begin_src) {
2288         case TRIG_TIMER:
2289                 count = (cmd->scan_begin_arg -
2290                          (cmd->convert_arg * (cmd->chanlist_len - 1))) /
2291                         TIMER_BASE;
2292                 break;
2293         case TRIG_FOLLOW:
2294                 count = cmd->convert_arg / TIMER_BASE;
2295                 break;
2296         default:
2297                 return 0;
2298         }
2299         return count - 3;
2300 }
2301
2302 static uint32_t ai_convert_counter_4020(struct comedi_device *dev,
2303                                         struct comedi_cmd *cmd)
2304 {
2305         struct pcidas64_private *devpriv = dev->private;
2306         unsigned int divisor;
2307
2308         switch (cmd->scan_begin_src) {
2309         case TRIG_TIMER:
2310                 divisor = cmd->scan_begin_arg / TIMER_BASE;
2311                 break;
2312         case TRIG_OTHER:
2313                 divisor = devpriv->ext_clock.divisor;
2314                 break;
2315         default:                /*  should never happen */
2316                 dev_err(dev->class_dev, "bug! failed to set ai pacing!\n");
2317                 divisor = 1000;
2318                 break;
2319         }
2320
2321         /*  supposed to load counter with desired divisor minus 2 for 4020 */
2322         return divisor - 2;
2323 }
2324
2325 static void select_master_clock_4020(struct comedi_device *dev,
2326                                      const struct comedi_cmd *cmd)
2327 {
2328         struct pcidas64_private *devpriv = dev->private;
2329
2330         /*  select internal/external master clock */
2331         devpriv->hw_config_bits &= ~MASTER_CLOCK_4020_MASK;
2332         if (cmd->scan_begin_src == TRIG_OTHER) {
2333                 int chanspec = devpriv->ext_clock.chanspec;
2334
2335                 if (CR_CHAN(chanspec))
2336                         devpriv->hw_config_bits |= BNC_CLOCK_4020_BITS;
2337                 else
2338                         devpriv->hw_config_bits |= EXT_CLOCK_4020_BITS;
2339         } else {
2340                 devpriv->hw_config_bits |= INTERNAL_CLOCK_4020_BITS;
2341         }
2342         writew(devpriv->hw_config_bits,
2343                devpriv->main_iobase + HW_CONFIG_REG);
2344 }
2345
2346 static void select_master_clock(struct comedi_device *dev,
2347                                 const struct comedi_cmd *cmd)
2348 {
2349         const struct pcidas64_board *thisboard = dev->board_ptr;
2350
2351         switch (thisboard->layout) {
2352         case LAYOUT_4020:
2353                 select_master_clock_4020(dev, cmd);
2354                 break;
2355         default:
2356                 break;
2357         }
2358 }
2359
2360 static inline void dma_start_sync(struct comedi_device *dev,
2361                                   unsigned int channel)
2362 {
2363         struct pcidas64_private *devpriv = dev->private;
2364         unsigned long flags;
2365
2366         /*  spinlock for plx dma control/status reg */
2367         spin_lock_irqsave(&dev->spinlock, flags);
2368         if (channel)
2369                 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2370                        PLX_CLEAR_DMA_INTR_BIT,
2371                        devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2372         else
2373                 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2374                        PLX_CLEAR_DMA_INTR_BIT,
2375                        devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2376         spin_unlock_irqrestore(&dev->spinlock, flags);
2377 }
2378
2379 static void set_ai_pacing(struct comedi_device *dev, struct comedi_cmd *cmd)
2380 {
2381         const struct pcidas64_board *thisboard = dev->board_ptr;
2382         struct pcidas64_private *devpriv = dev->private;
2383         uint32_t convert_counter = 0, scan_counter = 0;
2384
2385         check_adc_timing(dev, cmd);
2386
2387         select_master_clock(dev, cmd);
2388
2389         if (thisboard->layout == LAYOUT_4020) {
2390                 convert_counter = ai_convert_counter_4020(dev, cmd);
2391         } else {
2392                 convert_counter = ai_convert_counter_6xxx(dev, cmd);
2393                 scan_counter = ai_scan_counter_6xxx(dev, cmd);
2394         }
2395
2396         /*  load lower 16 bits of convert interval */
2397         writew(convert_counter & 0xffff,
2398                devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
2399         /*  load upper 8 bits of convert interval */
2400         writew((convert_counter >> 16) & 0xff,
2401                devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
2402         /*  load lower 16 bits of scan delay */
2403         writew(scan_counter & 0xffff,
2404                devpriv->main_iobase + ADC_DELAY_INTERVAL_LOWER_REG);
2405         /*  load upper 8 bits of scan delay */
2406         writew((scan_counter >> 16) & 0xff,
2407                devpriv->main_iobase + ADC_DELAY_INTERVAL_UPPER_REG);
2408 }
2409
2410 static int use_internal_queue_6xxx(const struct comedi_cmd *cmd)
2411 {
2412         int i;
2413
2414         for (i = 0; i + 1 < cmd->chanlist_len; i++) {
2415                 if (CR_CHAN(cmd->chanlist[i + 1]) !=
2416                     CR_CHAN(cmd->chanlist[i]) + 1)
2417                         return 0;
2418                 if (CR_RANGE(cmd->chanlist[i + 1]) !=
2419                     CR_RANGE(cmd->chanlist[i]))
2420                         return 0;
2421                 if (CR_AREF(cmd->chanlist[i + 1]) != CR_AREF(cmd->chanlist[i]))
2422                         return 0;
2423         }
2424         return 1;
2425 }
2426
2427 static int setup_channel_queue(struct comedi_device *dev,
2428                                const struct comedi_cmd *cmd)
2429 {
2430         const struct pcidas64_board *thisboard = dev->board_ptr;
2431         struct pcidas64_private *devpriv = dev->private;
2432         unsigned short bits;
2433         int i;
2434
2435         if (thisboard->layout != LAYOUT_4020) {
2436                 if (use_internal_queue_6xxx(cmd)) {
2437                         devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
2438                         writew(devpriv->hw_config_bits,
2439                                devpriv->main_iobase + HW_CONFIG_REG);
2440                         bits = 0;
2441                         /*  set channel */
2442                         bits |= adc_chan_bits(CR_CHAN(cmd->chanlist[0]));
2443                         /*  set gain */
2444                         bits |= ai_range_bits_6xxx(dev,
2445                                                    CR_RANGE(cmd->chanlist[0]));
2446                         /*  set single-ended / differential */
2447                         bits |= se_diff_bit_6xxx(dev,
2448                                                  CR_AREF(cmd->chanlist[0]) ==
2449                                                  AREF_DIFF);
2450                         if (CR_AREF(cmd->chanlist[0]) == AREF_COMMON)
2451                                 bits |= ADC_COMMON_BIT;
2452                         /*  set stop channel */
2453                         writew(adc_chan_bits
2454                                (CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1])),
2455                                devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
2456                         /*  set start channel, and rest of settings */
2457                         writew(bits,
2458                                devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2459                 } else {
2460                         /*  use external queue */
2461                         if (dev->write_subdev && dev->write_subdev->busy) {
2462                                 warn_external_queue(dev);
2463                                 return -EBUSY;
2464                         }
2465                         devpriv->hw_config_bits |= EXT_QUEUE_BIT;
2466                         writew(devpriv->hw_config_bits,
2467                                devpriv->main_iobase + HW_CONFIG_REG);
2468                         /*  clear DAC buffer to prevent weird interactions */
2469                         writew(0,
2470                                devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
2471                         /*  clear queue pointer */
2472                         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2473                         /*  load external queue */
2474                         for (i = 0; i < cmd->chanlist_len; i++) {
2475                                 bits = 0;
2476                                 /*  set channel */
2477                                 bits |= adc_chan_bits(CR_CHAN(cmd->
2478                                                               chanlist[i]));
2479                                 /*  set gain */
2480                                 bits |= ai_range_bits_6xxx(dev,
2481                                                            CR_RANGE(cmd->
2482                                                                     chanlist
2483                                                                     [i]));
2484                                 /*  set single-ended / differential */
2485                                 bits |= se_diff_bit_6xxx(dev,
2486                                                          CR_AREF(cmd->
2487                                                                  chanlist[i]) ==
2488                                                          AREF_DIFF);
2489                                 if (CR_AREF(cmd->chanlist[i]) == AREF_COMMON)
2490                                         bits |= ADC_COMMON_BIT;
2491                                 /*  mark end of queue */
2492                                 if (i == cmd->chanlist_len - 1)
2493                                         bits |= QUEUE_EOSCAN_BIT |
2494                                                 QUEUE_EOSEQ_BIT;
2495                                 writew(bits,
2496                                        devpriv->main_iobase +
2497                                        ADC_QUEUE_FIFO_REG);
2498                         }
2499                         /*
2500                          * doing a queue clear is not specified in board docs,
2501                          * but required for reliable operation
2502                          */
2503                         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2504                         /*  prime queue holding register */
2505                         writew(0, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2506                 }
2507         } else {
2508                 unsigned short old_cal_range_bits = devpriv->i2c_cal_range_bits;
2509
2510                 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
2511                 /* select BNC inputs */
2512                 devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
2513                 /*  select ranges */
2514                 for (i = 0; i < cmd->chanlist_len; i++) {
2515                         unsigned int channel = CR_CHAN(cmd->chanlist[i]);
2516                         unsigned int range = CR_RANGE(cmd->chanlist[i]);
2517
2518                         if (range == 0)
2519                                 devpriv->i2c_cal_range_bits |=
2520                                         attenuate_bit(channel);
2521                         else
2522                                 devpriv->i2c_cal_range_bits &=
2523                                         ~attenuate_bit(channel);
2524                 }
2525                 /*
2526                  * update calibration/range i2c register only if necessary,
2527                  * as it is very slow
2528                  */
2529                 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
2530                         uint8_t i2c_data = devpriv->i2c_cal_range_bits;
2531
2532                         i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
2533                                   sizeof(i2c_data));
2534                 }
2535         }
2536         return 0;
2537 }
2538
2539 static inline void load_first_dma_descriptor(struct comedi_device *dev,
2540                                              unsigned int dma_channel,
2541                                              unsigned int descriptor_bits)
2542 {
2543         struct pcidas64_private *devpriv = dev->private;
2544
2545         /*
2546          * The transfer size, pci address, and local address registers
2547          * are supposedly unused during chained dma,
2548          * but I have found that left over values from last operation
2549          * occasionally cause problems with transfer of first dma
2550          * block.  Initializing them to zero seems to fix the problem.
2551          */
2552         if (dma_channel) {
2553                 writel(0,
2554                        devpriv->plx9080_iobase + PLX_DMA1_TRANSFER_SIZE_REG);
2555                 writel(0, devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG);
2556                 writel(0,
2557                        devpriv->plx9080_iobase + PLX_DMA1_LOCAL_ADDRESS_REG);
2558                 writel(descriptor_bits,
2559                        devpriv->plx9080_iobase + PLX_DMA1_DESCRIPTOR_REG);
2560         } else {
2561                 writel(0,
2562                        devpriv->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG);
2563                 writel(0, devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
2564                 writel(0,
2565                        devpriv->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG);
2566                 writel(descriptor_bits,
2567                        devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
2568         }
2569 }
2570
2571 static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2572 {
2573         const struct pcidas64_board *thisboard = dev->board_ptr;
2574         struct pcidas64_private *devpriv = dev->private;
2575         struct comedi_async *async = s->async;
2576         struct comedi_cmd *cmd = &async->cmd;
2577         uint32_t bits;
2578         unsigned int i;
2579         unsigned long flags;
2580         int retval;
2581
2582         disable_ai_pacing(dev);
2583         abort_dma(dev, 1);
2584
2585         retval = setup_channel_queue(dev, cmd);
2586         if (retval < 0)
2587                 return retval;
2588
2589         /*  make sure internal calibration source is turned off */
2590         writew(0, devpriv->main_iobase + CALIBRATION_REG);
2591
2592         set_ai_pacing(dev, cmd);
2593
2594         setup_sample_counters(dev, cmd);
2595
2596         enable_ai_interrupts(dev, cmd);
2597
2598         spin_lock_irqsave(&dev->spinlock, flags);
2599         /* set mode, allow conversions through software gate */
2600         devpriv->adc_control1_bits |= ADC_SW_GATE_BIT;
2601         devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
2602         if (thisboard->layout != LAYOUT_4020) {
2603                 devpriv->adc_control1_bits &= ~ADC_MODE_MASK;
2604                 if (cmd->convert_src == TRIG_EXT)
2605                         /*  good old mode 13 */
2606                         devpriv->adc_control1_bits |= adc_mode_bits(13);
2607                 else
2608                         /*  mode 8.  What else could you need? */
2609                         devpriv->adc_control1_bits |= adc_mode_bits(8);
2610         } else {
2611                 devpriv->adc_control1_bits &= ~CHANNEL_MODE_4020_MASK;
2612                 if (cmd->chanlist_len == 4)
2613                         devpriv->adc_control1_bits |= FOUR_CHANNEL_4020_BITS;
2614                 else if (cmd->chanlist_len == 2)
2615                         devpriv->adc_control1_bits |= TWO_CHANNEL_4020_BITS;
2616                 devpriv->adc_control1_bits &= ~ADC_LO_CHANNEL_4020_MASK;
2617                 devpriv->adc_control1_bits |=
2618                         adc_lo_chan_4020_bits(CR_CHAN(cmd->chanlist[0]));
2619                 devpriv->adc_control1_bits &= ~ADC_HI_CHANNEL_4020_MASK;
2620                 devpriv->adc_control1_bits |=
2621                         adc_hi_chan_4020_bits(CR_CHAN(cmd->chanlist
2622                                                       [cmd->chanlist_len - 1]));
2623         }
2624         writew(devpriv->adc_control1_bits,
2625                devpriv->main_iobase + ADC_CONTROL1_REG);
2626         spin_unlock_irqrestore(&dev->spinlock, flags);
2627
2628         /*  clear adc buffer */
2629         writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
2630
2631         if ((cmd->flags & CMDF_WAKE_EOS) == 0 ||
2632             thisboard->layout == LAYOUT_4020) {
2633                 devpriv->ai_dma_index = 0;
2634
2635                 /*  set dma transfer size */
2636                 for (i = 0; i < ai_dma_ring_count(thisboard); i++)
2637                         devpriv->ai_dma_desc[i].transfer_size =
2638                                 cpu_to_le32(dma_transfer_size(dev) *
2639                                             sizeof(uint16_t));
2640
2641                 /*  give location of first dma descriptor */
2642                 load_first_dma_descriptor(dev, 1,
2643                                           devpriv->ai_dma_desc_bus_addr |
2644                                           PLX_DESC_IN_PCI_BIT |
2645                                           PLX_INTR_TERM_COUNT |
2646                                           PLX_XFER_LOCAL_TO_PCI);
2647
2648                 dma_start_sync(dev, 1);
2649         }
2650
2651         if (thisboard->layout == LAYOUT_4020) {
2652                 /* set source for external triggers */
2653                 bits = 0;
2654                 if (cmd->start_src == TRIG_EXT && CR_CHAN(cmd->start_arg))
2655                         bits |= EXT_START_TRIG_BNC_BIT;
2656                 if (cmd->stop_src == TRIG_EXT && CR_CHAN(cmd->stop_arg))
2657                         bits |= EXT_STOP_TRIG_BNC_BIT;
2658                 writew(bits, devpriv->main_iobase + DAQ_ATRIG_LOW_4020_REG);
2659         }
2660
2661         spin_lock_irqsave(&dev->spinlock, flags);
2662
2663         /* enable pacing, triggering, etc */
2664         bits = ADC_ENABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT;
2665         if (cmd->flags & CMDF_WAKE_EOS)
2666                 bits |= ADC_DMA_DISABLE_BIT;
2667         /*  set start trigger */
2668         if (cmd->start_src == TRIG_EXT) {
2669                 bits |= ADC_START_TRIG_EXT_BITS;
2670                 if (cmd->start_arg & CR_INVERT)
2671                         bits |= ADC_START_TRIG_FALLING_BIT;
2672         } else if (cmd->start_src == TRIG_NOW) {
2673                 bits |= ADC_START_TRIG_SOFT_BITS;
2674         }
2675         if (use_hw_sample_counter(cmd))
2676                 bits |= ADC_SAMPLE_COUNTER_EN_BIT;
2677         writew(bits, devpriv->main_iobase + ADC_CONTROL0_REG);
2678
2679         devpriv->ai_cmd_running = 1;
2680
2681         spin_unlock_irqrestore(&dev->spinlock, flags);
2682
2683         /*  start acquisition */
2684         if (cmd->start_src == TRIG_NOW)
2685                 writew(0, devpriv->main_iobase + ADC_START_REG);
2686
2687         return 0;
2688 }
2689
2690 /* read num_samples from 16 bit wide ai fifo */
2691 static void pio_drain_ai_fifo_16(struct comedi_device *dev)
2692 {
2693         struct pcidas64_private *devpriv = dev->private;
2694         struct comedi_subdevice *s = dev->read_subdev;
2695         unsigned int i;
2696         uint16_t prepost_bits;
2697         int read_segment, read_index, write_segment, write_index;
2698         int num_samples;
2699
2700         do {
2701                 /*  get least significant 15 bits */
2702                 read_index = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) &
2703                              0x7fff;
2704                 write_index = readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) &
2705                               0x7fff;
2706                 /*
2707                  * Get most significant bits (grey code).
2708                  * Different boards use different code so use a scheme
2709                  * that doesn't depend on encoding.  This read must
2710                  * occur after reading least significant 15 bits to avoid race
2711                  * with fifo switching to next segment.
2712                  */
2713                 prepost_bits = readw(devpriv->main_iobase + PREPOST_REG);
2714
2715                 /*
2716                  * if read and write pointers are not on the same fifo segment,
2717                  * read to the end of the read segment
2718                  */
2719                 read_segment = adc_upper_read_ptr_code(prepost_bits);
2720                 write_segment = adc_upper_write_ptr_code(prepost_bits);
2721
2722                 if (read_segment != write_segment)
2723                         num_samples =
2724                                 devpriv->ai_fifo_segment_length - read_index;
2725                 else
2726                         num_samples = write_index - read_index;
2727                 if (num_samples < 0) {
2728                         dev_err(dev->class_dev,
2729                                 "cb_pcidas64: bug! num_samples < 0\n");
2730                         break;
2731                 }
2732
2733                 num_samples = comedi_nsamples_left(s, num_samples);
2734                 if (num_samples == 0)
2735                         break;
2736
2737                 for (i = 0; i < num_samples; i++) {
2738                         unsigned short val;
2739
2740                         val = readw(devpriv->main_iobase + ADC_FIFO_REG);
2741                         comedi_buf_write_samples(s, &val, 1);
2742                 }
2743
2744         } while (read_segment != write_segment);
2745 }
2746
2747 /*
2748  * Read from 32 bit wide ai fifo of 4020 - deal with insane grey coding of
2749  * pointers.  The pci-4020 hardware only supports dma transfers (it only
2750  * supports the use of pio for draining the last remaining points from the
2751  * fifo when a data acquisition operation has completed).
2752  */
2753 static void pio_drain_ai_fifo_32(struct comedi_device *dev)
2754 {
2755         struct pcidas64_private *devpriv = dev->private;
2756         struct comedi_subdevice *s = dev->read_subdev;
2757         unsigned int nsamples;
2758         unsigned int i;
2759         uint32_t fifo_data;
2760         int write_code =
2761                 readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff;
2762         int read_code =
2763                 readw(devpriv->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2764
2765         nsamples = comedi_nsamples_left(s, 100000);
2766         for (i = 0; read_code != write_code && i < nsamples;) {
2767                 unsigned short val;
2768
2769                 fifo_data = readl(dev->mmio + ADC_FIFO_REG);
2770                 val = fifo_data & 0xffff;
2771                 comedi_buf_write_samples(s, &val, 1);
2772                 i++;
2773                 if (i < nsamples) {
2774                         val = (fifo_data >> 16) & 0xffff;
2775                         comedi_buf_write_samples(s, &val, 1);
2776                         i++;
2777                 }
2778                 read_code = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) &
2779                             0x7fff;
2780         }
2781 }
2782
2783 /* empty fifo */
2784 static void pio_drain_ai_fifo(struct comedi_device *dev)
2785 {
2786         const struct pcidas64_board *thisboard = dev->board_ptr;
2787
2788         if (thisboard->layout == LAYOUT_4020)
2789                 pio_drain_ai_fifo_32(dev);
2790         else
2791                 pio_drain_ai_fifo_16(dev);
2792 }
2793
2794 static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
2795 {
2796         const struct pcidas64_board *thisboard = dev->board_ptr;
2797         struct pcidas64_private *devpriv = dev->private;
2798         struct comedi_subdevice *s = dev->read_subdev;
2799         uint32_t next_transfer_addr;
2800         int j;
2801         int num_samples = 0;
2802         void __iomem *pci_addr_reg;
2803
2804         if (channel)
2805                 pci_addr_reg =
2806                     devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
2807         else
2808                 pci_addr_reg =
2809                     devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
2810
2811         /*  loop until we have read all the full buffers */
2812         for (j = 0, next_transfer_addr = readl(pci_addr_reg);
2813              (next_transfer_addr <
2814               devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] ||
2815               next_transfer_addr >=
2816               devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] +
2817               DMA_BUFFER_SIZE) && j < ai_dma_ring_count(thisboard); j++) {
2818                 /*  transfer data from dma buffer to comedi buffer */
2819                 num_samples = comedi_nsamples_left(s, dma_transfer_size(dev));
2820                 comedi_buf_write_samples(s,
2821                                 devpriv->ai_buffer[devpriv->ai_dma_index],
2822                                 num_samples);
2823                 devpriv->ai_dma_index = (devpriv->ai_dma_index + 1) %
2824                                         ai_dma_ring_count(thisboard);
2825         }
2826         /*
2827          * XXX check for dma ring buffer overrun
2828          * (use end-of-chain bit to mark last unused buffer)
2829          */
2830 }
2831
2832 static void handle_ai_interrupt(struct comedi_device *dev,
2833                                 unsigned short status,
2834                                 unsigned int plx_status)
2835 {
2836         const struct pcidas64_board *thisboard = dev->board_ptr;
2837         struct pcidas64_private *devpriv = dev->private;
2838         struct comedi_subdevice *s = dev->read_subdev;
2839         struct comedi_async *async = s->async;
2840         struct comedi_cmd *cmd = &async->cmd;
2841         uint8_t dma1_status;
2842         unsigned long flags;
2843
2844         /*  check for fifo overrun */
2845         if (status & ADC_OVERRUN_BIT) {
2846                 dev_err(dev->class_dev, "fifo overrun\n");
2847                 async->events |= COMEDI_CB_ERROR;
2848         }
2849         /*  spin lock makes sure no one else changes plx dma control reg */
2850         spin_lock_irqsave(&dev->spinlock, flags);
2851         dma1_status = readb(devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2852         if (plx_status & ICS_DMA1_A) {  /*  dma chan 1 interrupt */
2853                 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
2854                        devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2855
2856                 if (dma1_status & PLX_DMA_EN_BIT)
2857                         drain_dma_buffers(dev, 1);
2858         }
2859         spin_unlock_irqrestore(&dev->spinlock, flags);
2860
2861         /*  drain fifo with pio */
2862         if ((status & ADC_DONE_BIT) ||
2863             ((cmd->flags & CMDF_WAKE_EOS) &&
2864              (status & ADC_INTR_PENDING_BIT) &&
2865              (thisboard->layout != LAYOUT_4020))) {
2866                 spin_lock_irqsave(&dev->spinlock, flags);
2867                 if (devpriv->ai_cmd_running) {
2868                         spin_unlock_irqrestore(&dev->spinlock, flags);
2869                         pio_drain_ai_fifo(dev);
2870                 } else {
2871                         spin_unlock_irqrestore(&dev->spinlock, flags);
2872                 }
2873         }
2874         /*  if we are have all the data, then quit */
2875         if ((cmd->stop_src == TRIG_COUNT &&
2876              async->scans_done >= cmd->stop_arg) ||
2877             (cmd->stop_src == TRIG_EXT && (status & ADC_STOP_BIT)))
2878                 async->events |= COMEDI_CB_EOA;
2879
2880         comedi_handle_events(dev, s);
2881 }
2882
2883 static inline unsigned int prev_ao_dma_index(struct comedi_device *dev)
2884 {
2885         struct pcidas64_private *devpriv = dev->private;
2886         unsigned int buffer_index;
2887
2888         if (devpriv->ao_dma_index == 0)
2889                 buffer_index = AO_DMA_RING_COUNT - 1;
2890         else
2891                 buffer_index = devpriv->ao_dma_index - 1;
2892         return buffer_index;
2893 }
2894
2895 static int last_ao_dma_load_completed(struct comedi_device *dev)
2896 {
2897         struct pcidas64_private *devpriv = dev->private;
2898         unsigned int buffer_index;
2899         unsigned int transfer_address;
2900         unsigned short dma_status;
2901
2902         buffer_index = prev_ao_dma_index(dev);
2903         dma_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2904         if ((dma_status & PLX_DMA_DONE_BIT) == 0)
2905                 return 0;
2906
2907         transfer_address =
2908                 readl(devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
2909         if (transfer_address != devpriv->ao_buffer_bus_addr[buffer_index])
2910                 return 0;
2911
2912         return 1;
2913 }
2914
2915 static inline int ao_dma_needs_restart(struct comedi_device *dev,
2916                                        unsigned short dma_status)
2917 {
2918         if ((dma_status & PLX_DMA_DONE_BIT) == 0 ||
2919             (dma_status & PLX_DMA_EN_BIT) == 0)
2920                 return 0;
2921         if (last_ao_dma_load_completed(dev))
2922                 return 0;
2923
2924         return 1;
2925 }
2926
2927 static void restart_ao_dma(struct comedi_device *dev)
2928 {
2929         struct pcidas64_private *devpriv = dev->private;
2930         unsigned int dma_desc_bits;
2931
2932         dma_desc_bits =
2933                 readl(devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
2934         dma_desc_bits &= ~PLX_END_OF_CHAIN_BIT;
2935         load_first_dma_descriptor(dev, 0, dma_desc_bits);
2936
2937         dma_start_sync(dev, 0);
2938 }
2939
2940 static unsigned int cb_pcidas64_ao_fill_buffer(struct comedi_device *dev,
2941                                                struct comedi_subdevice *s,
2942                                                unsigned short *dest,
2943                                                unsigned int max_bytes)
2944 {
2945         unsigned int nsamples = comedi_bytes_to_samples(s, max_bytes);
2946         unsigned int actual_bytes;
2947
2948         nsamples = comedi_nsamples_left(s, nsamples);
2949         actual_bytes = comedi_buf_read_samples(s, dest, nsamples);
2950
2951         return comedi_bytes_to_samples(s, actual_bytes);
2952 }
2953
2954 static unsigned int load_ao_dma_buffer(struct comedi_device *dev,
2955                                        const struct comedi_cmd *cmd)
2956 {
2957         struct pcidas64_private *devpriv = dev->private;
2958         struct comedi_subdevice *s = dev->write_subdev;
2959         unsigned int buffer_index = devpriv->ao_dma_index;
2960         unsigned int prev_buffer_index = prev_ao_dma_index(dev);
2961         unsigned int nsamples;
2962         unsigned int nbytes;
2963         unsigned int next_bits;
2964
2965         nsamples = cb_pcidas64_ao_fill_buffer(dev, s,
2966                                               devpriv->ao_buffer[buffer_index],
2967                                               DMA_BUFFER_SIZE);
2968         if (nsamples == 0)
2969                 return 0;
2970
2971         nbytes = comedi_samples_to_bytes(s, nsamples);
2972         devpriv->ao_dma_desc[buffer_index].transfer_size = cpu_to_le32(nbytes);
2973         /* set end of chain bit so we catch underruns */
2974         next_bits = le32_to_cpu(devpriv->ao_dma_desc[buffer_index].next);
2975         next_bits |= PLX_END_OF_CHAIN_BIT;
2976         devpriv->ao_dma_desc[buffer_index].next = cpu_to_le32(next_bits);
2977         /*
2978          * clear end of chain bit on previous buffer now that we have set it
2979          * for the last buffer
2980          */
2981         next_bits = le32_to_cpu(devpriv->ao_dma_desc[prev_buffer_index].next);
2982         next_bits &= ~PLX_END_OF_CHAIN_BIT;
2983         devpriv->ao_dma_desc[prev_buffer_index].next = cpu_to_le32(next_bits);
2984
2985         devpriv->ao_dma_index = (buffer_index + 1) % AO_DMA_RING_COUNT;
2986
2987         return nbytes;
2988 }
2989
2990 static void load_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
2991 {
2992         struct pcidas64_private *devpriv = dev->private;
2993         unsigned int num_bytes;
2994         unsigned int next_transfer_addr;
2995         void __iomem *pci_addr_reg =
2996                 devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
2997         unsigned int buffer_index;
2998
2999         do {
3000                 buffer_index = devpriv->ao_dma_index;
3001                 /* don't overwrite data that hasn't been transferred yet */
3002                 next_transfer_addr = readl(pci_addr_reg);
3003                 if (next_transfer_addr >=
3004                     devpriv->ao_buffer_bus_addr[buffer_index] &&
3005                     next_transfer_addr <
3006                     devpriv->ao_buffer_bus_addr[buffer_index] +
3007                     DMA_BUFFER_SIZE)
3008                         return;
3009                 num_bytes = load_ao_dma_buffer(dev, cmd);
3010         } while (num_bytes >= DMA_BUFFER_SIZE);
3011 }
3012
3013 static void handle_ao_interrupt(struct comedi_device *dev,
3014                                 unsigned short status, unsigned int plx_status)
3015 {
3016         struct pcidas64_private *devpriv = dev->private;
3017         struct comedi_subdevice *s = dev->write_subdev;
3018         struct comedi_async *async;
3019         struct comedi_cmd *cmd;
3020         uint8_t dma0_status;
3021         unsigned long flags;
3022
3023         /* board might not support ao, in which case write_subdev is NULL */
3024         if (!s)
3025                 return;
3026         async = s->async;
3027         cmd = &async->cmd;
3028
3029         /*  spin lock makes sure no one else changes plx dma control reg */
3030         spin_lock_irqsave(&dev->spinlock, flags);
3031         dma0_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
3032         if (plx_status & ICS_DMA0_A) {  /*  dma chan 0 interrupt */
3033                 if ((dma0_status & PLX_DMA_EN_BIT) &&
3034                     !(dma0_status & PLX_DMA_DONE_BIT))
3035                         writeb(PLX_DMA_EN_BIT | PLX_CLEAR_DMA_INTR_BIT,
3036                                devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
3037                 else
3038                         writeb(PLX_CLEAR_DMA_INTR_BIT,
3039                                devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
3040                 spin_unlock_irqrestore(&dev->spinlock, flags);
3041                 if (dma0_status & PLX_DMA_EN_BIT) {
3042                         load_ao_dma(dev, cmd);
3043                         /* try to recover from dma end-of-chain event */
3044                         if (ao_dma_needs_restart(dev, dma0_status))
3045                                 restart_ao_dma(dev);
3046                 }
3047         } else {
3048                 spin_unlock_irqrestore(&dev->spinlock, flags);
3049         }
3050
3051         if ((status & DAC_DONE_BIT)) {
3052                 if ((cmd->stop_src == TRIG_COUNT &&
3053                      async->scans_done >= cmd->stop_arg) ||
3054                     last_ao_dma_load_completed(dev))
3055                         async->events |= COMEDI_CB_EOA;
3056                 else
3057                         async->events |= COMEDI_CB_ERROR;
3058         }
3059         comedi_handle_events(dev, s);
3060 }
3061
3062 static irqreturn_t handle_interrupt(int irq, void *d)
3063 {
3064         struct comedi_device *dev = d;
3065         struct pcidas64_private *devpriv = dev->private;
3066         unsigned short status;
3067         uint32_t plx_status;
3068         uint32_t plx_bits;
3069
3070         plx_status = readl(devpriv->plx9080_iobase + PLX_INTRCS_REG);
3071         status = readw(devpriv->main_iobase + HW_STATUS_REG);
3072
3073         /*
3074          * an interrupt before all the postconfig stuff gets done could
3075          * cause a NULL dereference if we continue through the
3076          * interrupt handler
3077          */
3078         if (!dev->attached)
3079                 return IRQ_HANDLED;
3080
3081         handle_ai_interrupt(dev, status, plx_status);
3082         handle_ao_interrupt(dev, status, plx_status);
3083
3084         /*  clear possible plx9080 interrupt sources */
3085         if (plx_status & ICS_LDIA) {    /*  clear local doorbell interrupt */
3086                 plx_bits = readl(devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
3087                 writel(plx_bits, devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
3088         }
3089
3090         return IRQ_HANDLED;
3091 }
3092
3093 static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3094 {
3095         struct pcidas64_private *devpriv = dev->private;
3096         unsigned long flags;
3097
3098         spin_lock_irqsave(&dev->spinlock, flags);
3099         if (devpriv->ai_cmd_running == 0) {
3100                 spin_unlock_irqrestore(&dev->spinlock, flags);
3101                 return 0;
3102         }
3103         devpriv->ai_cmd_running = 0;
3104         spin_unlock_irqrestore(&dev->spinlock, flags);
3105
3106         disable_ai_pacing(dev);
3107
3108         abort_dma(dev, 1);
3109
3110         return 0;
3111 }
3112
3113 static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
3114                     struct comedi_insn *insn, unsigned int *data)
3115 {
3116         const struct pcidas64_board *thisboard = dev->board_ptr;
3117         struct pcidas64_private *devpriv = dev->private;
3118         int chan = CR_CHAN(insn->chanspec);
3119         int range = CR_RANGE(insn->chanspec);
3120
3121         /*  do some initializing */
3122         writew(0, devpriv->main_iobase + DAC_CONTROL0_REG);
3123
3124         /*  set range */
3125         set_dac_range_bits(dev, &devpriv->dac_control1_bits, chan, range);
3126         writew(devpriv->dac_control1_bits,
3127                devpriv->main_iobase + DAC_CONTROL1_REG);
3128
3129         /*  write to channel */
3130         if (thisboard->layout == LAYOUT_4020) {
3131                 writew(data[0] & 0xff,
3132                        devpriv->main_iobase + dac_lsb_4020_reg(chan));
3133                 writew((data[0] >> 8) & 0xf,
3134                        devpriv->main_iobase + dac_msb_4020_reg(chan));
3135         } else {
3136                 writew(data[0], devpriv->main_iobase + dac_convert_reg(chan));
3137         }
3138
3139         /*  remember output value */
3140         s->readback[chan] = data[0];
3141
3142         return 1;
3143 }
3144
3145 static void set_dac_control0_reg(struct comedi_device *dev,
3146                                  const struct comedi_cmd *cmd)
3147 {
3148         struct pcidas64_private *devpriv = dev->private;
3149         unsigned int bits = DAC_ENABLE_BIT | WAVEFORM_GATE_LEVEL_BIT |
3150                             WAVEFORM_GATE_ENABLE_BIT | WAVEFORM_GATE_SELECT_BIT;
3151
3152         if (cmd->start_src == TRIG_EXT) {
3153                 bits |= WAVEFORM_TRIG_EXT_BITS;
3154                 if (cmd->start_arg & CR_INVERT)
3155                         bits |= WAVEFORM_TRIG_FALLING_BIT;
3156         } else {
3157                 bits |= WAVEFORM_TRIG_SOFT_BITS;
3158         }
3159         if (cmd->scan_begin_src == TRIG_EXT) {
3160                 bits |= DAC_EXT_UPDATE_ENABLE_BIT;
3161                 if (cmd->scan_begin_arg & CR_INVERT)
3162                         bits |= DAC_EXT_UPDATE_FALLING_BIT;
3163         }
3164         writew(bits, devpriv->main_iobase + DAC_CONTROL0_REG);
3165 }
3166
3167 static void set_dac_control1_reg(struct comedi_device *dev,
3168                                  const struct comedi_cmd *cmd)
3169 {
3170         struct pcidas64_private *devpriv = dev->private;
3171         int i;
3172
3173         for (i = 0; i < cmd->chanlist_len; i++) {
3174                 int channel, range;
3175
3176                 channel = CR_CHAN(cmd->chanlist[i]);
3177                 range = CR_RANGE(cmd->chanlist[i]);
3178                 set_dac_range_bits(dev, &devpriv->dac_control1_bits, channel,
3179                                    range);
3180         }
3181         devpriv->dac_control1_bits |= DAC_SW_GATE_BIT;
3182         writew(devpriv->dac_control1_bits,
3183                devpriv->main_iobase + DAC_CONTROL1_REG);
3184 }
3185
3186 static void set_dac_select_reg(struct comedi_device *dev,
3187                                const struct comedi_cmd *cmd)
3188 {
3189         struct pcidas64_private *devpriv = dev->private;
3190         uint16_t bits;
3191         unsigned int first_channel, last_channel;
3192
3193         first_channel = CR_CHAN(cmd->chanlist[0]);
3194         last_channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
3195         if (last_channel < first_channel)
3196                 dev_err(dev->class_dev,
3197                         "bug! last ao channel < first ao channel\n");
3198
3199         bits = (first_channel & 0x7) | (last_channel & 0x7) << 3;
3200
3201         writew(bits, devpriv->main_iobase + DAC_SELECT_REG);
3202 }
3203
3204 static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags)
3205 {
3206         return get_divisor(ns, flags) - 2;
3207 }
3208
3209 static void set_dac_interval_regs(struct comedi_device *dev,
3210                                   const struct comedi_cmd *cmd)
3211 {
3212         struct pcidas64_private *devpriv = dev->private;
3213         unsigned int divisor;
3214
3215         if (cmd->scan_begin_src != TRIG_TIMER)
3216                 return;
3217
3218         divisor = get_ao_divisor(cmd->scan_begin_arg, cmd->flags);
3219         if (divisor > max_counter_value) {
3220                 dev_err(dev->class_dev, "bug! ao divisor too big\n");
3221                 divisor = max_counter_value;
3222         }
3223         writew(divisor & 0xffff,
3224                devpriv->main_iobase + DAC_SAMPLE_INTERVAL_LOWER_REG);
3225         writew((divisor >> 16) & 0xff,
3226                devpriv->main_iobase + DAC_SAMPLE_INTERVAL_UPPER_REG);
3227 }
3228
3229 static int prep_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3230 {
3231         struct pcidas64_private *devpriv = dev->private;
3232         struct comedi_subdevice *s = dev->write_subdev;
3233         unsigned int nsamples;
3234         unsigned int nbytes;
3235         int i;
3236
3237         /*
3238          * clear queue pointer too, since external queue has
3239          * weird interactions with ao fifo
3240          */
3241         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
3242         writew(0, devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
3243
3244         nsamples = cb_pcidas64_ao_fill_buffer(dev, s,
3245                                               devpriv->ao_bounce_buffer,
3246                                               DAC_FIFO_SIZE);
3247         if (nsamples == 0)
3248                 return -1;
3249
3250         for (i = 0; i < nsamples; i++) {
3251                 writew(devpriv->ao_bounce_buffer[i],
3252                        devpriv->main_iobase + DAC_FIFO_REG);
3253         }
3254
3255         if (cmd->stop_src == TRIG_COUNT &&
3256             s->async->scans_done >= cmd->stop_arg)
3257                 return 0;
3258
3259         nbytes = load_ao_dma_buffer(dev, cmd);
3260         if (nbytes == 0)
3261                 return -1;
3262         load_ao_dma(dev, cmd);
3263
3264         dma_start_sync(dev, 0);
3265
3266         return 0;
3267 }
3268
3269 static inline int external_ai_queue_in_use(struct comedi_device *dev,
3270                                            struct comedi_subdevice *s,
3271                                            struct comedi_cmd *cmd)
3272 {
3273         const struct pcidas64_board *thisboard = dev->board_ptr;
3274
3275         if (s->busy)
3276                 return 0;
3277         if (thisboard->layout == LAYOUT_4020)
3278                 return 0;
3279         else if (use_internal_queue_6xxx(cmd))
3280                 return 0;
3281         return 1;
3282 }
3283
3284 static int ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3285                       unsigned int trig_num)
3286 {
3287         struct pcidas64_private *devpriv = dev->private;
3288         struct comedi_cmd *cmd = &s->async->cmd;
3289         int retval;
3290
3291         if (trig_num != cmd->start_arg)
3292                 return -EINVAL;
3293
3294         retval = prep_ao_dma(dev, cmd);
3295         if (retval < 0)
3296                 return -EPIPE;
3297
3298         set_dac_control0_reg(dev, cmd);
3299
3300         if (cmd->start_src == TRIG_INT)
3301                 writew(0, devpriv->main_iobase + DAC_START_REG);
3302
3303         s->async->inttrig = NULL;
3304
3305         return 0;
3306 }
3307
3308 static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3309 {
3310         struct pcidas64_private *devpriv = dev->private;
3311         struct comedi_cmd *cmd = &s->async->cmd;
3312
3313         if (external_ai_queue_in_use(dev, s, cmd)) {
3314                 warn_external_queue(dev);
3315                 return -EBUSY;
3316         }
3317         /* disable analog output system during setup */
3318         writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3319
3320         devpriv->ao_dma_index = 0;
3321
3322         set_dac_select_reg(dev, cmd);
3323         set_dac_interval_regs(dev, cmd);
3324         load_first_dma_descriptor(dev, 0, devpriv->ao_dma_desc_bus_addr |
3325                                   PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT);
3326
3327         set_dac_control1_reg(dev, cmd);
3328         s->async->inttrig = ao_inttrig;
3329
3330         return 0;
3331 }
3332
3333 static int cb_pcidas64_ao_check_chanlist(struct comedi_device *dev,
3334                                          struct comedi_subdevice *s,
3335                                          struct comedi_cmd *cmd)
3336 {
3337         unsigned int chan0 = CR_CHAN(cmd->chanlist[0]);
3338         int i;
3339
3340         for (i = 1; i < cmd->chanlist_len; i++) {
3341                 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3342
3343                 if (chan != (chan0 + i)) {
3344                         dev_dbg(dev->class_dev,
3345                                 "chanlist must use consecutive channels\n");
3346                         return -EINVAL;
3347                 }
3348         }
3349
3350         return 0;
3351 }
3352
3353 static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3354                       struct comedi_cmd *cmd)
3355 {
3356         const struct pcidas64_board *thisboard = dev->board_ptr;
3357         int err = 0;
3358         unsigned int tmp_arg;
3359
3360         /* Step 1 : check if triggers are trivially valid */
3361
3362         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3363         err |= comedi_check_trigger_src(&cmd->scan_begin_src,
3364                                         TRIG_TIMER | TRIG_EXT);
3365         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3366         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3367         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3368
3369         if (err)
3370                 return 1;
3371
3372         /* Step 2a : make sure trigger sources are unique */
3373
3374         err |= comedi_check_trigger_is_unique(cmd->start_src);
3375         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
3376
3377         /* Step 2b : and mutually compatible */
3378
3379         if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
3380                 err |= -EINVAL;
3381         if (cmd->stop_src != TRIG_COUNT &&
3382             cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
3383                 err |= -EINVAL;
3384
3385         if (err)
3386                 return 2;
3387
3388         /* Step 3: check if arguments are trivially valid */
3389
3390         err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3391
3392         if (cmd->scan_begin_src == TRIG_TIMER) {
3393                 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
3394                                                     thisboard->ao_scan_speed);
3395                 if (get_ao_divisor(cmd->scan_begin_arg, cmd->flags) >
3396                     max_counter_value) {
3397                         cmd->scan_begin_arg = (max_counter_value + 2) *
3398                                               TIMER_BASE;
3399                         err |= -EINVAL;
3400                 }
3401         }
3402
3403         err |= comedi_check_trigger_arg_min(&cmd->chanlist_len, 1);
3404         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3405                                            cmd->chanlist_len);
3406
3407         if (err)
3408                 return 3;
3409
3410         /* step 4: fix up any arguments */
3411
3412         if (cmd->scan_begin_src == TRIG_TIMER) {
3413                 tmp_arg = cmd->scan_begin_arg;
3414                 cmd->scan_begin_arg = get_divisor(cmd->scan_begin_arg,
3415                                                   cmd->flags) * TIMER_BASE;
3416                 if (tmp_arg != cmd->scan_begin_arg)
3417                         err++;
3418         }
3419
3420         if (err)
3421                 return 4;
3422
3423         /* Step 5: check channel list if it exists */
3424         if (cmd->chanlist && cmd->chanlist_len > 0)
3425                 err |= cb_pcidas64_ao_check_chanlist(dev, s, cmd);
3426
3427         if (err)
3428                 return 5;
3429
3430         return 0;
3431 }
3432
3433 static int ao_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3434 {
3435         struct pcidas64_private *devpriv = dev->private;
3436
3437         writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3438         abort_dma(dev, 0);
3439         return 0;
3440 }
3441
3442 static int dio_callback_4020(struct comedi_device *dev,
3443                              int dir, int port, int data, unsigned long iobase)
3444 {
3445         struct pcidas64_private *devpriv = dev->private;
3446
3447         if (dir) {
3448                 writew(data, devpriv->main_iobase + iobase + 2 * port);
3449                 return 0;
3450         }
3451         return readw(devpriv->main_iobase + iobase + 2 * port);
3452 }
3453
3454 static int di_rbits(struct comedi_device *dev, struct comedi_subdevice *s,
3455                     struct comedi_insn *insn, unsigned int *data)
3456 {
3457         unsigned int bits;
3458
3459         bits = readb(dev->mmio + DI_REG);
3460         bits &= 0xf;
3461         data[1] = bits;
3462         data[0] = 0;
3463
3464         return insn->n;
3465 }
3466
3467 static int do_wbits(struct comedi_device *dev,
3468                     struct comedi_subdevice *s,
3469                     struct comedi_insn *insn,
3470                     unsigned int *data)
3471 {
3472         if (comedi_dio_update_state(s, data))
3473                 writeb(s->state, dev->mmio + DO_REG);
3474
3475         data[1] = s->state;
3476
3477         return insn->n;
3478 }
3479
3480 static int dio_60xx_config_insn(struct comedi_device *dev,
3481                                 struct comedi_subdevice *s,
3482                                 struct comedi_insn *insn,
3483                                 unsigned int *data)
3484 {
3485         int ret;
3486
3487         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3488         if (ret)
3489                 return ret;
3490
3491         writeb(s->io_bits, dev->mmio + DIO_DIRECTION_60XX_REG);
3492
3493         return insn->n;
3494 }
3495
3496 static int dio_60xx_wbits(struct comedi_device *dev,
3497                           struct comedi_subdevice *s,
3498                           struct comedi_insn *insn,
3499                           unsigned int *data)
3500 {
3501         if (comedi_dio_update_state(s, data))
3502                 writeb(s->state, dev->mmio + DIO_DATA_60XX_REG);
3503
3504         data[1] = readb(dev->mmio + DIO_DATA_60XX_REG);
3505
3506         return insn->n;
3507 }
3508
3509 /*
3510  * pci-6025 8800 caldac:
3511  * address 0 == dac channel 0 offset
3512  * address 1 == dac channel 0 gain
3513  * address 2 == dac channel 1 offset
3514  * address 3 == dac channel 1 gain
3515  * address 4 == fine adc offset
3516  * address 5 == coarse adc offset
3517  * address 6 == coarse adc gain
3518  * address 7 == fine adc gain
3519  */
3520 /*
3521  * pci-6402/16 uses all 8 channels for dac:
3522  * address 0 == dac channel 0 fine gain
3523  * address 1 == dac channel 0 coarse gain
3524  * address 2 == dac channel 0 coarse offset
3525  * address 3 == dac channel 1 coarse offset
3526  * address 4 == dac channel 1 fine gain
3527  * address 5 == dac channel 1 coarse gain
3528  * address 6 == dac channel 0 fine offset
3529  * address 7 == dac channel 1 fine offset
3530  */
3531
3532 static int caldac_8800_write(struct comedi_device *dev, unsigned int address,
3533                              uint8_t value)
3534 {
3535         struct pcidas64_private *devpriv = dev->private;
3536         static const int num_caldac_channels = 8;
3537         static const int bitstream_length = 11;
3538         unsigned int bitstream = ((address & 0x7) << 8) | value;
3539         unsigned int bit, register_bits;
3540         static const int caldac_8800_udelay = 1;
3541
3542         if (address >= num_caldac_channels) {
3543                 dev_err(dev->class_dev, "illegal caldac channel\n");
3544                 return -1;
3545         }
3546         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3547                 register_bits = 0;
3548                 if (bitstream & bit)
3549                         register_bits |= SERIAL_DATA_IN_BIT;
3550                 udelay(caldac_8800_udelay);
3551                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3552                 register_bits |= SERIAL_CLOCK_BIT;
3553                 udelay(caldac_8800_udelay);
3554                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3555         }
3556         udelay(caldac_8800_udelay);
3557         writew(SELECT_8800_BIT, devpriv->main_iobase + CALIBRATION_REG);
3558         udelay(caldac_8800_udelay);
3559         writew(0, devpriv->main_iobase + CALIBRATION_REG);
3560         udelay(caldac_8800_udelay);
3561         return 0;
3562 }
3563
3564 /* 4020 caldacs */
3565 static int caldac_i2c_write(struct comedi_device *dev,
3566                             unsigned int caldac_channel, unsigned int value)
3567 {
3568         uint8_t serial_bytes[3];
3569         uint8_t i2c_addr;
3570         enum pointer_bits {
3571                 /*  manual has gain and offset bits switched */
3572                 OFFSET_0_2 = 0x1,
3573                 GAIN_0_2 = 0x2,
3574                 OFFSET_1_3 = 0x4,
3575                 GAIN_1_3 = 0x8,
3576         };
3577         enum data_bits {
3578                 NOT_CLEAR_REGISTERS = 0x20,
3579         };
3580
3581         switch (caldac_channel) {
3582         case 0:         /*  chan 0 offset */
3583                 i2c_addr = CALDAC0_I2C_ADDR;
3584                 serial_bytes[0] = OFFSET_0_2;
3585                 break;
3586         case 1:         /*  chan 1 offset */
3587                 i2c_addr = CALDAC0_I2C_ADDR;
3588                 serial_bytes[0] = OFFSET_1_3;
3589                 break;
3590         case 2:         /*  chan 2 offset */
3591                 i2c_addr = CALDAC1_I2C_ADDR;
3592                 serial_bytes[0] = OFFSET_0_2;
3593                 break;
3594         case 3:         /*  chan 3 offset */
3595                 i2c_addr = CALDAC1_I2C_ADDR;
3596                 serial_bytes[0] = OFFSET_1_3;
3597                 break;
3598         case 4:         /*  chan 0 gain */
3599                 i2c_addr = CALDAC0_I2C_ADDR;
3600                 serial_bytes[0] = GAIN_0_2;
3601                 break;
3602         case 5:         /*  chan 1 gain */
3603                 i2c_addr = CALDAC0_I2C_ADDR;
3604                 serial_bytes[0] = GAIN_1_3;
3605                 break;
3606         case 6:         /*  chan 2 gain */
3607                 i2c_addr = CALDAC1_I2C_ADDR;
3608                 serial_bytes[0] = GAIN_0_2;
3609                 break;
3610         case 7:         /*  chan 3 gain */
3611                 i2c_addr = CALDAC1_I2C_ADDR;
3612                 serial_bytes[0] = GAIN_1_3;
3613                 break;
3614         default:
3615                 dev_err(dev->class_dev, "invalid caldac channel\n");
3616                 return -1;
3617         }
3618         serial_bytes[1] = NOT_CLEAR_REGISTERS | ((value >> 8) & 0xf);
3619         serial_bytes[2] = value & 0xff;
3620         i2c_write(dev, i2c_addr, serial_bytes, 3);
3621         return 0;
3622 }
3623
3624 static void caldac_write(struct comedi_device *dev, unsigned int channel,
3625                          unsigned int value)
3626 {
3627         const struct pcidas64_board *thisboard = dev->board_ptr;
3628
3629         switch (thisboard->layout) {
3630         case LAYOUT_60XX:
3631         case LAYOUT_64XX:
3632                 caldac_8800_write(dev, channel, value);
3633                 break;
3634         case LAYOUT_4020:
3635                 caldac_i2c_write(dev, channel, value);
3636                 break;
3637         default:
3638                 break;
3639         }
3640 }
3641
3642 static int cb_pcidas64_calib_insn_write(struct comedi_device *dev,
3643                                         struct comedi_subdevice *s,
3644                                         struct comedi_insn *insn,
3645                                         unsigned int *data)
3646 {
3647         unsigned int chan = CR_CHAN(insn->chanspec);
3648
3649         /*
3650          * Programming the calib device is slow. Only write the
3651          * last data value if the value has changed.
3652          */
3653         if (insn->n) {
3654                 unsigned int val = data[insn->n - 1];
3655
3656                 if (s->readback[chan] != val) {
3657                         caldac_write(dev, chan, val);
3658                         s->readback[chan] = val;
3659                 }
3660         }
3661
3662         return insn->n;
3663 }
3664
3665 static void ad8402_write(struct comedi_device *dev, unsigned int channel,
3666                          unsigned int value)
3667 {
3668         struct pcidas64_private *devpriv = dev->private;
3669         static const int bitstream_length = 10;
3670         unsigned int bit, register_bits;
3671         unsigned int bitstream = ((channel & 0x3) << 8) | (value & 0xff);
3672         static const int ad8402_udelay = 1;
3673
3674         register_bits = SELECT_8402_64XX_BIT;
3675         udelay(ad8402_udelay);
3676         writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3677
3678         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3679                 if (bitstream & bit)
3680                         register_bits |= SERIAL_DATA_IN_BIT;
3681                 else
3682                         register_bits &= ~SERIAL_DATA_IN_BIT;
3683                 udelay(ad8402_udelay);
3684                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3685                 udelay(ad8402_udelay);
3686                 writew(register_bits | SERIAL_CLOCK_BIT,
3687                        devpriv->main_iobase + CALIBRATION_REG);
3688         }
3689
3690         udelay(ad8402_udelay);
3691         writew(0, devpriv->main_iobase + CALIBRATION_REG);
3692 }
3693
3694 /* for pci-das6402/16, channel 0 is analog input gain and channel 1 is offset */
3695 static int cb_pcidas64_ad8402_insn_write(struct comedi_device *dev,
3696                                          struct comedi_subdevice *s,
3697                                          struct comedi_insn *insn,
3698                                          unsigned int *data)
3699 {
3700         unsigned int chan = CR_CHAN(insn->chanspec);
3701
3702         /*
3703          * Programming the calib device is slow. Only write the
3704          * last data value if the value has changed.
3705          */
3706         if (insn->n) {
3707                 unsigned int val = data[insn->n - 1];
3708
3709                 if (s->readback[chan] != val) {
3710                         ad8402_write(dev, chan, val);
3711                         s->readback[chan] = val;
3712                 }
3713         }
3714
3715         return insn->n;
3716 }
3717
3718 static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address)
3719 {
3720         struct pcidas64_private *devpriv = dev->private;
3721         static const int bitstream_length = 11;
3722         static const int read_command = 0x6;
3723         unsigned int bitstream = (read_command << 8) | address;
3724         unsigned int bit;
3725         void __iomem * const plx_control_addr =
3726                 devpriv->plx9080_iobase + PLX_CONTROL_REG;
3727         uint16_t value;
3728         static const int value_length = 16;
3729         static const int eeprom_udelay = 1;
3730
3731         udelay(eeprom_udelay);
3732         devpriv->plx_control_bits &= ~CTL_EE_CLK & ~CTL_EE_CS;
3733         /*  make sure we don't send anything to the i2c bus on 4020 */
3734         devpriv->plx_control_bits |= CTL_USERO;
3735         writel(devpriv->plx_control_bits, plx_control_addr);
3736         /*  activate serial eeprom */
3737         udelay(eeprom_udelay);
3738         devpriv->plx_control_bits |= CTL_EE_CS;
3739         writel(devpriv->plx_control_bits, plx_control_addr);
3740
3741         /*  write read command and desired memory address */
3742         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3743                 /*  set bit to be written */
3744                 udelay(eeprom_udelay);
3745                 if (bitstream & bit)
3746                         devpriv->plx_control_bits |= CTL_EE_W;
3747                 else
3748                         devpriv->plx_control_bits &= ~CTL_EE_W;
3749                 writel(devpriv->plx_control_bits, plx_control_addr);
3750                 /*  clock in bit */
3751                 udelay(eeprom_udelay);
3752                 devpriv->plx_control_bits |= CTL_EE_CLK;
3753                 writel(devpriv->plx_control_bits, plx_control_addr);
3754                 udelay(eeprom_udelay);
3755                 devpriv->plx_control_bits &= ~CTL_EE_CLK;
3756                 writel(devpriv->plx_control_bits, plx_control_addr);
3757         }
3758         /*  read back value from eeprom memory location */
3759         value = 0;
3760         for (bit = 1 << (value_length - 1); bit; bit >>= 1) {
3761                 /*  clock out bit */
3762                 udelay(eeprom_udelay);
3763                 devpriv->plx_control_bits |= CTL_EE_CLK;
3764                 writel(devpriv->plx_control_bits, plx_control_addr);
3765                 udelay(eeprom_udelay);
3766                 devpriv->plx_control_bits &= ~CTL_EE_CLK;
3767                 writel(devpriv->plx_control_bits, plx_control_addr);
3768                 udelay(eeprom_udelay);
3769                 if (readl(plx_control_addr) & CTL_EE_R)
3770                         value |= bit;
3771         }
3772
3773         /*  deactivate eeprom serial input */
3774         udelay(eeprom_udelay);
3775         devpriv->plx_control_bits &= ~CTL_EE_CS;
3776         writel(devpriv->plx_control_bits, plx_control_addr);
3777
3778         return value;
3779 }
3780
3781 static int eeprom_read_insn(struct comedi_device *dev,
3782                             struct comedi_subdevice *s,
3783                             struct comedi_insn *insn, unsigned int *data)
3784 {
3785         data[0] = read_eeprom(dev, CR_CHAN(insn->chanspec));
3786
3787         return 1;
3788 }
3789
3790 /*
3791  * Allocate and initialize the subdevice structures.
3792  */
3793 static int setup_subdevices(struct comedi_device *dev)
3794 {
3795         const struct pcidas64_board *thisboard = dev->board_ptr;
3796         struct pcidas64_private *devpriv = dev->private;
3797         struct comedi_subdevice *s;
3798         int i;
3799         int ret;
3800
3801         ret = comedi_alloc_subdevices(dev, 10);
3802         if (ret)
3803                 return ret;
3804
3805         s = &dev->subdevices[0];
3806         /* analog input subdevice */
3807         dev->read_subdev = s;
3808         s->type = COMEDI_SUBD_AI;
3809         s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DITHER | SDF_CMD_READ;
3810         if (thisboard->layout == LAYOUT_60XX)
3811                 s->subdev_flags |= SDF_COMMON | SDF_DIFF;
3812         else if (thisboard->layout == LAYOUT_64XX)
3813                 s->subdev_flags |= SDF_DIFF;
3814         /* XXX Number of inputs in differential mode is ignored */
3815         s->n_chan = thisboard->ai_se_chans;
3816         s->len_chanlist = 0x2000;
3817         s->maxdata = (1 << thisboard->ai_bits) - 1;
3818         s->range_table = thisboard->ai_range_table;
3819         s->insn_read = ai_rinsn;
3820         s->insn_config = ai_config_insn;
3821         s->do_cmd = ai_cmd;
3822         s->do_cmdtest = ai_cmdtest;
3823         s->cancel = ai_cancel;
3824         if (thisboard->layout == LAYOUT_4020) {
3825                 uint8_t data;
3826                 /*
3827                  * set adc to read from inputs
3828                  * (not internal calibration sources)
3829                  */
3830                 devpriv->i2c_cal_range_bits = adc_src_4020_bits(4);
3831                 /*  set channels to +-5 volt input ranges */
3832                 for (i = 0; i < s->n_chan; i++)
3833                         devpriv->i2c_cal_range_bits |= attenuate_bit(i);
3834                 data = devpriv->i2c_cal_range_bits;
3835                 i2c_write(dev, RANGE_CAL_I2C_ADDR, &data, sizeof(data));
3836         }
3837
3838         /* analog output subdevice */
3839         s = &dev->subdevices[1];
3840         if (thisboard->ao_nchan) {
3841                 s->type = COMEDI_SUBD_AO;
3842                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE |
3843                                   SDF_GROUND | SDF_CMD_WRITE;
3844                 s->n_chan = thisboard->ao_nchan;
3845                 s->maxdata = (1 << thisboard->ao_bits) - 1;
3846                 s->range_table = thisboard->ao_range_table;
3847                 s->insn_write = ao_winsn;
3848
3849                 ret = comedi_alloc_subdev_readback(s);
3850                 if (ret)
3851                         return ret;
3852
3853                 if (ao_cmd_is_supported(thisboard)) {
3854                         dev->write_subdev = s;
3855                         s->do_cmdtest = ao_cmdtest;
3856                         s->do_cmd = ao_cmd;
3857                         s->len_chanlist = thisboard->ao_nchan;
3858                         s->cancel = ao_cancel;
3859                 }
3860         } else {
3861                 s->type = COMEDI_SUBD_UNUSED;
3862         }
3863
3864         /*  digital input */
3865         s = &dev->subdevices[2];
3866         if (thisboard->layout == LAYOUT_64XX) {
3867                 s->type = COMEDI_SUBD_DI;
3868                 s->subdev_flags = SDF_READABLE;
3869                 s->n_chan = 4;
3870                 s->maxdata = 1;
3871                 s->range_table = &range_digital;
3872                 s->insn_bits = di_rbits;
3873         } else {
3874                 s->type = COMEDI_SUBD_UNUSED;
3875         }
3876
3877         /*  digital output */
3878         if (thisboard->layout == LAYOUT_64XX) {
3879                 s = &dev->subdevices[3];
3880                 s->type = COMEDI_SUBD_DO;
3881                 s->subdev_flags = SDF_WRITABLE;
3882                 s->n_chan = 4;
3883                 s->maxdata = 1;
3884                 s->range_table = &range_digital;
3885                 s->insn_bits = do_wbits;
3886         } else {
3887                 s->type = COMEDI_SUBD_UNUSED;
3888         }
3889
3890         /* 8255 */
3891         s = &dev->subdevices[4];
3892         if (thisboard->has_8255) {
3893                 if (thisboard->layout == LAYOUT_4020) {
3894                         ret = subdev_8255_init(dev, s, dio_callback_4020,
3895                                                I8255_4020_REG);
3896                 } else {
3897                         ret = subdev_8255_mm_init(dev, s, NULL,
3898                                                   DIO_8255_OFFSET);
3899                 }
3900                 if (ret)
3901                         return ret;
3902         } else {
3903                 s->type = COMEDI_SUBD_UNUSED;
3904         }
3905
3906         /*  8 channel dio for 60xx */
3907         s = &dev->subdevices[5];
3908         if (thisboard->layout == LAYOUT_60XX) {
3909                 s->type = COMEDI_SUBD_DIO;
3910                 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
3911                 s->n_chan = 8;
3912                 s->maxdata = 1;
3913                 s->range_table = &range_digital;
3914                 s->insn_config = dio_60xx_config_insn;
3915                 s->insn_bits = dio_60xx_wbits;
3916         } else {
3917                 s->type = COMEDI_SUBD_UNUSED;
3918         }
3919
3920         /*  caldac */
3921         s = &dev->subdevices[6];
3922         s->type = COMEDI_SUBD_CALIB;
3923         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3924         s->n_chan = 8;
3925         if (thisboard->layout == LAYOUT_4020)
3926                 s->maxdata = 0xfff;
3927         else
3928                 s->maxdata = 0xff;
3929         s->insn_write = cb_pcidas64_calib_insn_write;
3930
3931         ret = comedi_alloc_subdev_readback(s);
3932         if (ret)
3933                 return ret;
3934
3935         for (i = 0; i < s->n_chan; i++) {
3936                 caldac_write(dev, i, s->maxdata / 2);
3937                 s->readback[i] = s->maxdata / 2;
3938         }
3939
3940         /*  2 channel ad8402 potentiometer */
3941         s = &dev->subdevices[7];
3942         if (thisboard->layout == LAYOUT_64XX) {
3943                 s->type = COMEDI_SUBD_CALIB;
3944                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3945                 s->n_chan = 2;
3946                 s->maxdata = 0xff;
3947                 s->insn_write = cb_pcidas64_ad8402_insn_write;
3948
3949                 ret = comedi_alloc_subdev_readback(s);
3950                 if (ret)
3951                         return ret;
3952
3953                 for (i = 0; i < s->n_chan; i++) {
3954                         ad8402_write(dev, i, s->maxdata / 2);
3955                         s->readback[i] = s->maxdata / 2;
3956                 }
3957         } else {
3958                 s->type = COMEDI_SUBD_UNUSED;
3959         }
3960
3961         /* serial EEPROM, if present */
3962         s = &dev->subdevices[8];
3963         if (readl(devpriv->plx9080_iobase + PLX_CONTROL_REG) & CTL_EECHK) {
3964                 s->type = COMEDI_SUBD_MEMORY;
3965                 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
3966                 s->n_chan = 128;
3967                 s->maxdata = 0xffff;
3968                 s->insn_read = eeprom_read_insn;
3969         } else {
3970                 s->type = COMEDI_SUBD_UNUSED;
3971         }
3972
3973         /*  user counter subd XXX */
3974         s = &dev->subdevices[9];
3975         s->type = COMEDI_SUBD_UNUSED;
3976
3977         return 0;
3978 }
3979
3980 static int auto_attach(struct comedi_device *dev,
3981                        unsigned long context)
3982 {
3983         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
3984         const struct pcidas64_board *thisboard = NULL;
3985         struct pcidas64_private *devpriv;
3986         uint32_t local_range, local_decode;
3987         int retval;
3988
3989         if (context < ARRAY_SIZE(pcidas64_boards))
3990                 thisboard = &pcidas64_boards[context];
3991         if (!thisboard)
3992                 return -ENODEV;
3993         dev->board_ptr = thisboard;
3994
3995         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
3996         if (!devpriv)
3997                 return -ENOMEM;
3998
3999         retval = comedi_pci_enable(dev);
4000         if (retval)
4001                 return retval;
4002         pci_set_master(pcidev);
4003
4004         /* Initialize dev->board_name */
4005         dev->board_name = thisboard->name;
4006
4007         devpriv->main_phys_iobase = pci_resource_start(pcidev, 2);
4008         devpriv->dio_counter_phys_iobase = pci_resource_start(pcidev, 3);
4009
4010         devpriv->plx9080_iobase = pci_ioremap_bar(pcidev, 0);
4011         devpriv->main_iobase = pci_ioremap_bar(pcidev, 2);
4012         dev->mmio = pci_ioremap_bar(pcidev, 3);
4013
4014         if (!devpriv->plx9080_iobase || !devpriv->main_iobase || !dev->mmio) {
4015                 dev_warn(dev->class_dev, "failed to remap io memory\n");
4016                 return -ENOMEM;
4017         }
4018
4019         /*  figure out what local addresses are */
4020         local_range = readl(devpriv->plx9080_iobase + PLX_LAS0RNG_REG) &
4021                       LRNG_MEM_MASK;
4022         local_decode = readl(devpriv->plx9080_iobase + PLX_LAS0MAP_REG) &
4023                        local_range & LMAP_MEM_MASK;
4024         devpriv->local0_iobase = ((uint32_t)devpriv->main_phys_iobase &
4025                                   ~local_range) | local_decode;
4026         local_range = readl(devpriv->plx9080_iobase + PLX_LAS1RNG_REG) &
4027                       LRNG_MEM_MASK;
4028         local_decode = readl(devpriv->plx9080_iobase + PLX_LAS1MAP_REG) &
4029                        local_range & LMAP_MEM_MASK;
4030         devpriv->local1_iobase = ((uint32_t)devpriv->dio_counter_phys_iobase &
4031                                   ~local_range) | local_decode;
4032
4033         retval = alloc_and_init_dma_members(dev);
4034         if (retval < 0)
4035                 return retval;
4036
4037         devpriv->hw_revision =
4038                 hw_revision(dev, readw(devpriv->main_iobase + HW_STATUS_REG));
4039         dev_dbg(dev->class_dev, "stc hardware revision %i\n",
4040                 devpriv->hw_revision);
4041         init_plx9080(dev);
4042         init_stc_registers(dev);
4043
4044         retval = request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
4045                              dev->board_name, dev);
4046         if (retval) {
4047                 dev_dbg(dev->class_dev, "unable to allocate irq %u\n",
4048                         pcidev->irq);
4049                 return retval;
4050         }
4051         dev->irq = pcidev->irq;
4052         dev_dbg(dev->class_dev, "irq %u\n", dev->irq);
4053
4054         retval = setup_subdevices(dev);
4055         if (retval < 0)
4056                 return retval;
4057
4058         return 0;
4059 }
4060
4061 static void detach(struct comedi_device *dev)
4062 {
4063         struct pcidas64_private *devpriv = dev->private;
4064
4065         if (dev->irq)
4066                 free_irq(dev->irq, dev);
4067         if (devpriv) {
4068                 if (devpriv->plx9080_iobase) {
4069                         disable_plx_interrupts(dev);
4070                         iounmap(devpriv->plx9080_iobase);
4071                 }
4072                 if (devpriv->main_iobase)
4073                         iounmap(devpriv->main_iobase);
4074                 if (dev->mmio)
4075                         iounmap(dev->mmio);
4076         }
4077         comedi_pci_disable(dev);
4078         cb_pcidas64_free_dma(dev);
4079 }
4080
4081 static struct comedi_driver cb_pcidas64_driver = {
4082         .driver_name    = "cb_pcidas64",
4083         .module         = THIS_MODULE,
4084         .auto_attach    = auto_attach,
4085         .detach         = detach,
4086 };
4087
4088 static int cb_pcidas64_pci_probe(struct pci_dev *dev,
4089                                  const struct pci_device_id *id)
4090 {
4091         return comedi_pci_auto_config(dev, &cb_pcidas64_driver,
4092                                       id->driver_data);
4093 }
4094
4095 static const struct pci_device_id cb_pcidas64_pci_table[] = {
4096         { PCI_VDEVICE(CB, 0x001d), BOARD_PCIDAS6402_16 },
4097         { PCI_VDEVICE(CB, 0x001e), BOARD_PCIDAS6402_12 },
4098         { PCI_VDEVICE(CB, 0x0035), BOARD_PCIDAS64_M1_16 },
4099         { PCI_VDEVICE(CB, 0x0036), BOARD_PCIDAS64_M2_16 },
4100         { PCI_VDEVICE(CB, 0x0037), BOARD_PCIDAS64_M3_16 },
4101         { PCI_VDEVICE(CB, 0x0052), BOARD_PCIDAS4020_12 },
4102         { PCI_VDEVICE(CB, 0x005d), BOARD_PCIDAS6023 },
4103         { PCI_VDEVICE(CB, 0x005e), BOARD_PCIDAS6025 },
4104         { PCI_VDEVICE(CB, 0x005f), BOARD_PCIDAS6030 },
4105         { PCI_VDEVICE(CB, 0x0060), BOARD_PCIDAS6031 },
4106         { PCI_VDEVICE(CB, 0x0061), BOARD_PCIDAS6032 },
4107         { PCI_VDEVICE(CB, 0x0062), BOARD_PCIDAS6033 },
4108         { PCI_VDEVICE(CB, 0x0063), BOARD_PCIDAS6034 },
4109         { PCI_VDEVICE(CB, 0x0064), BOARD_PCIDAS6035 },
4110         { PCI_VDEVICE(CB, 0x0065), BOARD_PCIDAS6040 },
4111         { PCI_VDEVICE(CB, 0x0066), BOARD_PCIDAS6052 },
4112         { PCI_VDEVICE(CB, 0x0067), BOARD_PCIDAS6070 },
4113         { PCI_VDEVICE(CB, 0x0068), BOARD_PCIDAS6071 },
4114         { PCI_VDEVICE(CB, 0x006f), BOARD_PCIDAS6036 },
4115         { PCI_VDEVICE(CB, 0x0078), BOARD_PCIDAS6013 },
4116         { PCI_VDEVICE(CB, 0x0079), BOARD_PCIDAS6014 },
4117         { 0 }
4118 };
4119 MODULE_DEVICE_TABLE(pci, cb_pcidas64_pci_table);
4120
4121 static struct pci_driver cb_pcidas64_pci_driver = {
4122         .name           = "cb_pcidas64",
4123         .id_table       = cb_pcidas64_pci_table,
4124         .probe          = cb_pcidas64_pci_probe,
4125         .remove         = comedi_pci_auto_unconfig,
4126 };
4127 module_comedi_pci_driver(cb_pcidas64_driver, cb_pcidas64_pci_driver);
4128
4129 MODULE_AUTHOR("Comedi http://www.comedi.org");
4130 MODULE_DESCRIPTION("Comedi low-level driver");
4131 MODULE_LICENSE("GPL");