2 comedi/drivers/gsc_hpdi.c
3 This is a driver for the General Standards Corporation High
4 Speed Parallel Digital Interface rs485 boards.
6 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
7 Copyright (C) 2003 Coherent Imaging Systems
9 COMEDI - Linux Control and Measurement Device Interface
10 Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 ************************************************************************/
30 * Description: General Standards Corporation High
31 * Speed Parallel Digital Interface rs485 boards
32 * Author: Frank Mori Hess <fmhess@users.sourceforge.net>
33 * Status: only receive mode works, transmit not supported
34 * Updated: Thu, 01 Nov 2012 16:17:38 +0000
35 * Devices: [General Standards Corporation] PCI-HPDI32 (gsc_hpdi),
38 * Configuration options:
41 * Manual configuration of supported devices is not supported; they are
42 * configured automatically.
44 * There are some additional hpdi models available from GSC for which
45 * support could be added to this driver.
48 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
50 #include <linux/interrupt.h>
51 #include "../comedidev.h"
52 #include <linux/delay.h>
55 #include "comedi_fc.h"
57 static void abort_dma(struct comedi_device *dev, unsigned int channel);
58 static int hpdi_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
59 static int hpdi_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s,
60 struct comedi_cmd *cmd);
61 static int hpdi_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
62 static irqreturn_t handle_interrupt(int irq, void *d);
63 static int dio_config_block_size(struct comedi_device *dev, unsigned int *data);
65 #undef HPDI_DEBUG /* disable debugging messages */
66 /* #define HPDI_DEBUG enable debugging code */
69 #define DEBUG_PRINT(format, args...) pr_debug(format , ## args)
71 #define DEBUG_PRINT(format, args...) no_printk(pr_fmt(format), ## args)
74 #define TIMER_BASE 50 /* 20MHz master clock */
75 #define DMA_BUFFER_SIZE 0x10000
76 #define NUM_DMA_BUFFERS 4
77 #define NUM_DMA_DESCRIPTORS 256
79 /* indices of base address regions */
80 enum base_address_regions {
81 PLX9080_BADDRINDEX = 0,
86 FIRMWARE_REV_REG = 0x0,
87 BOARD_CONTROL_REG = 0x4,
88 BOARD_STATUS_REG = 0x8,
89 TX_PROG_ALMOST_REG = 0xc,
90 RX_PROG_ALMOST_REG = 0x10,
93 TX_STATUS_COUNT_REG = 0x1c,
94 TX_LINE_VALID_COUNT_REG = 0x20,
95 TX_LINE_INVALID_COUNT_REG = 0x24,
96 RX_STATUS_COUNT_REG = 0x28,
97 RX_LINE_COUNT_REG = 0x2c,
98 INTERRUPT_CONTROL_REG = 0x30,
99 INTERRUPT_STATUS_REG = 0x34,
100 TX_CLOCK_DIVIDER_REG = 0x38,
101 TX_FIFO_SIZE_REG = 0x40,
102 RX_FIFO_SIZE_REG = 0x44,
103 TX_FIFO_WORDS_REG = 0x48,
104 RX_FIFO_WORDS_REG = 0x4c,
105 INTERRUPT_EDGE_LEVEL_REG = 0x50,
106 INTERRUPT_POLARITY_REG = 0x54,
109 /* bit definitions */
111 enum firmware_revision_bits {
112 FEATURES_REG_PRESENT_BIT = 0x8000,
115 enum board_control_bits {
116 BOARD_RESET_BIT = 0x1, /* wait 10usec before accessing fifos */
117 TX_FIFO_RESET_BIT = 0x2,
118 RX_FIFO_RESET_BIT = 0x4,
119 TX_ENABLE_BIT = 0x10,
120 RX_ENABLE_BIT = 0x20,
121 DEMAND_DMA_DIRECTION_TX_BIT = 0x40,
122 /* for ch 0, ch 1 can only transmit (when present) */
123 LINE_VALID_ON_STATUS_VALID_BIT = 0x80,
125 CABLE_THROTTLE_ENABLE_BIT = 0x20,
126 TEST_MODE_ENABLE_BIT = 0x80000000,
129 enum board_status_bits {
130 COMMAND_LINE_STATUS_MASK = 0x7f,
131 TX_IN_PROGRESS_BIT = 0x80,
132 TX_NOT_EMPTY_BIT = 0x100,
133 TX_NOT_ALMOST_EMPTY_BIT = 0x200,
134 TX_NOT_ALMOST_FULL_BIT = 0x400,
135 TX_NOT_FULL_BIT = 0x800,
136 RX_NOT_EMPTY_BIT = 0x1000,
137 RX_NOT_ALMOST_EMPTY_BIT = 0x2000,
138 RX_NOT_ALMOST_FULL_BIT = 0x4000,
139 RX_NOT_FULL_BIT = 0x8000,
140 BOARD_JUMPER0_INSTALLED_BIT = 0x10000,
141 BOARD_JUMPER1_INSTALLED_BIT = 0x20000,
142 TX_OVERRUN_BIT = 0x200000,
143 RX_UNDERRUN_BIT = 0x400000,
144 RX_OVERRUN_BIT = 0x800000,
147 static uint32_t almost_full_bits(unsigned int num_words)
149 /* XXX need to add or subtract one? */
150 return (num_words << 16) & 0xff0000;
153 static uint32_t almost_empty_bits(unsigned int num_words)
155 return num_words & 0xffff;
159 FIFO_SIZE_PRESENT_BIT = 0x1,
160 FIFO_WORDS_PRESENT_BIT = 0x2,
161 LEVEL_EDGE_INTERRUPTS_PRESENT_BIT = 0x4,
162 GPIO_SUPPORTED_BIT = 0x8,
163 PLX_DMA_CH1_SUPPORTED_BIT = 0x10,
164 OVERRUN_UNDERRUN_SUPPORTED_BIT = 0x20,
167 enum interrupt_sources {
168 FRAME_VALID_START_INTR = 0,
169 FRAME_VALID_END_INTR = 1,
170 TX_FIFO_EMPTY_INTR = 8,
171 TX_FIFO_ALMOST_EMPTY_INTR = 9,
172 TX_FIFO_ALMOST_FULL_INTR = 10,
173 TX_FIFO_FULL_INTR = 11,
175 RX_ALMOST_EMPTY_INTR = 13,
176 RX_ALMOST_FULL_INTR = 14,
180 static uint32_t intr_bit(int interrupt_source)
182 return 0x1 << interrupt_source;
185 static unsigned int fifo_size(uint32_t fifo_size_bits)
187 return fifo_size_bits & 0xfffff;
191 const char *name; /* board name */
192 int device_id; /* pci device id */
193 int subdevice_id; /* pci subdevice id */
196 static const struct hpdi_board hpdi_boards[] = {
198 .name = "pci-hpdi32",
199 .device_id = PCI_DEVICE_ID_PLX_9080,
200 .subdevice_id = 0x2400,
204 .name = "pxi-hpdi32",
206 .subdevice_id = 0x2705,
211 struct hpdi_private {
212 /* base addresses (ioremapped) */
213 void __iomem *plx9080_iobase;
214 void __iomem *hpdi_iobase;
215 uint32_t *dio_buffer[NUM_DMA_BUFFERS]; /* dma buffers */
216 /* physical addresses of dma buffers */
217 dma_addr_t dio_buffer_phys_addr[NUM_DMA_BUFFERS];
218 /* array of dma descriptors read by plx9080, allocated to get proper
220 struct plx_dma_desc *dma_desc;
221 /* physical address of dma descriptor array */
222 dma_addr_t dma_desc_phys_addr;
223 unsigned int num_dma_descriptors;
224 /* pointer to start of buffers indexed by descriptor */
225 uint32_t *desc_dio_buffer[NUM_DMA_DESCRIPTORS];
226 /* index of the dma descriptor that is currently being used */
227 volatile unsigned int dma_desc_index;
228 unsigned int tx_fifo_size;
229 unsigned int rx_fifo_size;
230 volatile unsigned long dio_count;
231 /* software copies of values written to hpdi registers */
232 volatile uint32_t bits[24];
233 /* number of bytes at which to generate COMEDI_CB_BLOCK events */
234 volatile unsigned int block_size;
235 unsigned dio_config_output:1;
238 static int dio_config_insn(struct comedi_device *dev,
239 struct comedi_subdevice *s, struct comedi_insn *insn,
242 struct hpdi_private *devpriv = dev->private;
245 case INSN_CONFIG_DIO_OUTPUT:
246 devpriv->dio_config_output = 1;
249 case INSN_CONFIG_DIO_INPUT:
250 devpriv->dio_config_output = 0;
253 case INSN_CONFIG_DIO_QUERY:
255 devpriv->dio_config_output ? COMEDI_OUTPUT : COMEDI_INPUT;
258 case INSN_CONFIG_BLOCK_SIZE:
259 return dio_config_block_size(dev, data);
268 static void disable_plx_interrupts(struct comedi_device *dev)
270 struct hpdi_private *devpriv = dev->private;
272 writel(0, devpriv->plx9080_iobase + PLX_INTRCS_REG);
275 /* initialize plx9080 chip */
276 static void init_plx9080(struct comedi_device *dev)
278 struct hpdi_private *devpriv = dev->private;
280 void __iomem *plx_iobase = devpriv->plx9080_iobase;
283 DEBUG_PRINT(" plx interrupt status 0x%x\n",
284 readl(plx_iobase + PLX_INTRCS_REG));
285 DEBUG_PRINT(" plx id bits 0x%x\n", readl(plx_iobase + PLX_ID_REG));
286 DEBUG_PRINT(" plx control reg 0x%x\n",
287 readl(devpriv->plx9080_iobase + PLX_CONTROL_REG));
289 DEBUG_PRINT(" plx revision 0x%x\n",
290 readl(plx_iobase + PLX_REVISION_REG));
291 DEBUG_PRINT(" plx dma channel 0 mode 0x%x\n",
292 readl(plx_iobase + PLX_DMA0_MODE_REG));
293 DEBUG_PRINT(" plx dma channel 1 mode 0x%x\n",
294 readl(plx_iobase + PLX_DMA1_MODE_REG));
295 DEBUG_PRINT(" plx dma channel 0 pci address 0x%x\n",
296 readl(plx_iobase + PLX_DMA0_PCI_ADDRESS_REG));
297 DEBUG_PRINT(" plx dma channel 0 local address 0x%x\n",
298 readl(plx_iobase + PLX_DMA0_LOCAL_ADDRESS_REG));
299 DEBUG_PRINT(" plx dma channel 0 transfer size 0x%x\n",
300 readl(plx_iobase + PLX_DMA0_TRANSFER_SIZE_REG));
301 DEBUG_PRINT(" plx dma channel 0 descriptor 0x%x\n",
302 readl(plx_iobase + PLX_DMA0_DESCRIPTOR_REG));
303 DEBUG_PRINT(" plx dma channel 0 command status 0x%x\n",
304 readb(plx_iobase + PLX_DMA0_CS_REG));
305 DEBUG_PRINT(" plx dma channel 0 threshold 0x%x\n",
306 readl(plx_iobase + PLX_DMA0_THRESHOLD_REG));
307 DEBUG_PRINT(" plx bigend 0x%x\n", readl(plx_iobase + PLX_BIGEND_REG));
309 bits = BIGEND_DMA0 | BIGEND_DMA1;
313 writel(bits, devpriv->plx9080_iobase + PLX_BIGEND_REG);
315 disable_plx_interrupts(dev);
320 /* configure dma0 mode */
322 /* enable ready input */
323 bits |= PLX_DMA_EN_READYIN_BIT;
324 /* enable dma chaining */
325 bits |= PLX_EN_CHAIN_BIT;
326 /* enable interrupt on dma done
327 * (probably don't need this, since chain never finishes) */
328 bits |= PLX_EN_DMA_DONE_INTR_BIT;
329 /* don't increment local address during transfers
330 * (we are transferring from a fixed fifo register) */
331 bits |= PLX_LOCAL_ADDR_CONST_BIT;
332 /* route dma interrupt to pci bus */
333 bits |= PLX_DMA_INTR_PCI_BIT;
334 /* enable demand mode */
335 bits |= PLX_DEMAND_MODE_BIT;
336 /* enable local burst mode */
337 bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
338 bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
339 writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
342 /* Allocate and initialize the subdevice structures.
344 static int setup_subdevices(struct comedi_device *dev)
346 struct comedi_subdevice *s;
349 ret = comedi_alloc_subdevices(dev, 1);
353 s = &dev->subdevices[0];
354 /* analog input subdevice */
355 dev->read_subdev = s;
356 /* dev->write_subdev = s; */
357 s->type = COMEDI_SUBD_DIO;
359 SDF_READABLE | SDF_WRITEABLE | SDF_LSAMPL | SDF_CMD_READ;
361 s->len_chanlist = 32;
363 s->range_table = &range_digital;
364 s->insn_config = dio_config_insn;
365 s->do_cmd = hpdi_cmd;
366 s->do_cmdtest = hpdi_cmd_test;
367 s->cancel = hpdi_cancel;
372 static int init_hpdi(struct comedi_device *dev)
374 struct hpdi_private *devpriv = dev->private;
375 uint32_t plx_intcsr_bits;
377 writel(BOARD_RESET_BIT, devpriv->hpdi_iobase + BOARD_CONTROL_REG);
380 writel(almost_empty_bits(32) | almost_full_bits(32),
381 devpriv->hpdi_iobase + RX_PROG_ALMOST_REG);
382 writel(almost_empty_bits(32) | almost_full_bits(32),
383 devpriv->hpdi_iobase + TX_PROG_ALMOST_REG);
385 devpriv->tx_fifo_size = fifo_size(readl(devpriv->hpdi_iobase +
387 devpriv->rx_fifo_size = fifo_size(readl(devpriv->hpdi_iobase +
390 writel(0, devpriv->hpdi_iobase + INTERRUPT_CONTROL_REG);
392 /* enable interrupts */
394 ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
396 writel(plx_intcsr_bits, devpriv->plx9080_iobase + PLX_INTRCS_REG);
401 /* setup dma descriptors so a link completes every 'transfer_size' bytes */
402 static int setup_dma_descriptors(struct comedi_device *dev,
403 unsigned int transfer_size)
405 struct hpdi_private *devpriv = dev->private;
406 unsigned int buffer_index, buffer_offset;
407 uint32_t next_bits = PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
408 PLX_XFER_LOCAL_TO_PCI;
411 if (transfer_size > DMA_BUFFER_SIZE)
412 transfer_size = DMA_BUFFER_SIZE;
413 transfer_size -= transfer_size % sizeof(uint32_t);
414 if (transfer_size == 0)
417 DEBUG_PRINT(" transfer_size %i\n", transfer_size);
418 DEBUG_PRINT(" descriptors at 0x%lx\n",
419 (unsigned long)devpriv->dma_desc_phys_addr);
423 for (i = 0; i < NUM_DMA_DESCRIPTORS &&
424 buffer_index < NUM_DMA_BUFFERS; i++) {
425 devpriv->dma_desc[i].pci_start_addr =
426 cpu_to_le32(devpriv->dio_buffer_phys_addr[buffer_index] +
428 devpriv->dma_desc[i].local_start_addr = cpu_to_le32(FIFO_REG);
429 devpriv->dma_desc[i].transfer_size =
430 cpu_to_le32(transfer_size);
431 devpriv->dma_desc[i].next =
432 cpu_to_le32((devpriv->dma_desc_phys_addr + (i +
434 sizeof(devpriv->dma_desc[0])) | next_bits);
436 devpriv->desc_dio_buffer[i] =
437 devpriv->dio_buffer[buffer_index] +
438 (buffer_offset / sizeof(uint32_t));
440 buffer_offset += transfer_size;
441 if (transfer_size + buffer_offset > DMA_BUFFER_SIZE) {
446 DEBUG_PRINT(" desc %i\n", i);
447 DEBUG_PRINT(" start addr virt 0x%p, phys 0x%lx\n",
448 devpriv->desc_dio_buffer[i],
449 (unsigned long)devpriv->dma_desc[i].
451 DEBUG_PRINT(" next 0x%lx\n",
452 (unsigned long)devpriv->dma_desc[i].next);
454 devpriv->num_dma_descriptors = i;
455 /* fix last descriptor to point back to first */
456 devpriv->dma_desc[i - 1].next =
457 cpu_to_le32(devpriv->dma_desc_phys_addr | next_bits);
458 DEBUG_PRINT(" desc %i next fixup 0x%lx\n", i - 1,
459 (unsigned long)devpriv->dma_desc[i - 1].next);
461 devpriv->block_size = transfer_size;
463 return transfer_size;
466 static const struct hpdi_board *hpdi_find_board(struct pci_dev *pcidev)
470 for (i = 0; i < ARRAY_SIZE(hpdi_boards); i++)
471 if (pcidev->device == hpdi_boards[i].device_id &&
472 pcidev->subsystem_device == hpdi_boards[i].subdevice_id)
473 return &hpdi_boards[i];
477 static int hpdi_auto_attach(struct comedi_device *dev,
478 unsigned long context_unused)
480 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
481 const struct hpdi_board *thisboard;
482 struct hpdi_private *devpriv;
486 thisboard = hpdi_find_board(pcidev);
488 dev_err(dev->class_dev, "gsc_hpdi: pci %s not supported\n",
492 dev->board_ptr = thisboard;
493 dev->board_name = thisboard->name;
495 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
498 dev->private = devpriv;
500 if (comedi_pci_enable(pcidev, dev->board_name)) {
501 dev_warn(dev->class_dev,
502 "failed enable PCI device and request regions\n");
505 dev->iobase = 1; /* the "detach" needs this */
506 pci_set_master(pcidev);
508 devpriv->plx9080_iobase =
509 ioremap(pci_resource_start(pcidev, PLX9080_BADDRINDEX),
510 pci_resource_len(pcidev, PLX9080_BADDRINDEX));
511 devpriv->hpdi_iobase =
512 ioremap(pci_resource_start(pcidev, HPDI_BADDRINDEX),
513 pci_resource_len(pcidev, HPDI_BADDRINDEX));
514 if (!devpriv->plx9080_iobase || !devpriv->hpdi_iobase) {
515 dev_warn(dev->class_dev, "failed to remap io memory\n");
519 DEBUG_PRINT(" plx9080 remapped to 0x%p\n", devpriv->plx9080_iobase);
520 DEBUG_PRINT(" hpdi remapped to 0x%p\n", devpriv->hpdi_iobase);
525 if (request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
526 dev->board_name, dev)) {
527 dev_warn(dev->class_dev,
528 "unable to allocate irq %u\n", pcidev->irq);
531 dev->irq = pcidev->irq;
533 dev_dbg(dev->class_dev, " irq %u\n", dev->irq);
535 /* allocate pci dma buffers */
536 for (i = 0; i < NUM_DMA_BUFFERS; i++) {
537 devpriv->dio_buffer[i] =
538 pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
539 &devpriv->dio_buffer_phys_addr[i]);
540 DEBUG_PRINT("dio_buffer at virt 0x%p, phys 0x%lx\n",
541 devpriv->dio_buffer[i],
542 (unsigned long)devpriv->dio_buffer_phys_addr[i]);
544 /* allocate dma descriptors */
545 devpriv->dma_desc = pci_alloc_consistent(pcidev,
546 sizeof(struct plx_dma_desc) *
548 &devpriv->dma_desc_phys_addr);
549 if (devpriv->dma_desc_phys_addr & 0xf) {
550 dev_warn(dev->class_dev,
551 " dma descriptors not quad-word aligned (bug)\n");
555 retval = setup_dma_descriptors(dev, 0x1000);
559 retval = setup_subdevices(dev);
563 return init_hpdi(dev);
566 static void hpdi_detach(struct comedi_device *dev)
568 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
569 struct hpdi_private *devpriv = dev->private;
573 free_irq(dev->irq, dev);
575 if (devpriv->plx9080_iobase) {
576 disable_plx_interrupts(dev);
577 iounmap(devpriv->plx9080_iobase);
579 if (devpriv->hpdi_iobase)
580 iounmap(devpriv->hpdi_iobase);
581 /* free pci dma buffers */
582 for (i = 0; i < NUM_DMA_BUFFERS; i++) {
583 if (devpriv->dio_buffer[i])
584 pci_free_consistent(pcidev,
586 devpriv->dio_buffer[i],
588 dio_buffer_phys_addr[i]);
590 /* free dma descriptors */
591 if (devpriv->dma_desc)
592 pci_free_consistent(pcidev,
593 sizeof(struct plx_dma_desc) *
596 devpriv->dma_desc_phys_addr);
598 comedi_pci_disable(pcidev);
602 static int dio_config_block_size(struct comedi_device *dev, unsigned int *data)
604 unsigned int requested_block_size;
607 requested_block_size = data[1];
609 retval = setup_dma_descriptors(dev, requested_block_size);
618 static int di_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s,
619 struct comedi_cmd *cmd)
624 /* Step 1 : check if triggers are trivially valid */
626 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
627 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
628 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
629 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
630 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
635 /* Step 2a : make sure trigger sources are unique */
637 err |= cfc_check_trigger_is_unique(cmd->stop_src);
639 /* Step 2b : and mutually compatible */
644 /* Step 3: check if arguments are trivially valid */
646 if (!cmd->chanlist_len) {
647 cmd->chanlist_len = 32;
650 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
652 switch (cmd->stop_src) {
654 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
657 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
666 /* step 4: fix up any arguments */
674 for (i = 1; i < cmd->chanlist_len; i++) {
675 if (CR_CHAN(cmd->chanlist[i]) != i) {
676 /* XXX could support 8 or 16 channels */
678 "chanlist must be ch 0 to 31 in order");
690 static int hpdi_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s,
691 struct comedi_cmd *cmd)
693 struct hpdi_private *devpriv = dev->private;
695 if (devpriv->dio_config_output)
698 return di_cmd_test(dev, s, cmd);
701 static inline void hpdi_writel(struct comedi_device *dev, uint32_t bits,
704 struct hpdi_private *devpriv = dev->private;
706 writel(bits | devpriv->bits[offset / sizeof(uint32_t)],
707 devpriv->hpdi_iobase + offset);
710 static int di_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
712 struct hpdi_private *devpriv = dev->private;
715 struct comedi_async *async = s->async;
716 struct comedi_cmd *cmd = &async->cmd;
718 hpdi_writel(dev, RX_FIFO_RESET_BIT, BOARD_CONTROL_REG);
720 DEBUG_PRINT("hpdi: in di_cmd\n");
724 devpriv->dma_desc_index = 0;
726 /* These register are supposedly unused during chained dma,
727 * but I have found that left over values from last operation
728 * occasionally cause problems with transfer of first dma
729 * block. Initializing them to zero seems to fix the problem. */
730 writel(0, devpriv->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG);
731 writel(0, devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
732 writel(0, devpriv->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG);
733 /* give location of first dma descriptor */
735 devpriv->dma_desc_phys_addr | PLX_DESC_IN_PCI_BIT |
736 PLX_INTR_TERM_COUNT | PLX_XFER_LOCAL_TO_PCI;
737 writel(bits, devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
739 /* spinlock for plx dma control/status reg */
740 spin_lock_irqsave(&dev->spinlock, flags);
741 /* enable dma transfer */
742 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT | PLX_CLEAR_DMA_INTR_BIT,
743 devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
744 spin_unlock_irqrestore(&dev->spinlock, flags);
746 if (cmd->stop_src == TRIG_COUNT)
747 devpriv->dio_count = cmd->stop_arg;
749 devpriv->dio_count = 1;
751 /* clear over/under run status flags */
752 writel(RX_UNDERRUN_BIT | RX_OVERRUN_BIT,
753 devpriv->hpdi_iobase + BOARD_STATUS_REG);
754 /* enable interrupts */
755 writel(intr_bit(RX_FULL_INTR),
756 devpriv->hpdi_iobase + INTERRUPT_CONTROL_REG);
758 DEBUG_PRINT("hpdi: starting rx\n");
759 hpdi_writel(dev, RX_ENABLE_BIT, BOARD_CONTROL_REG);
764 static int hpdi_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
766 struct hpdi_private *devpriv = dev->private;
768 if (devpriv->dio_config_output)
771 return di_cmd(dev, s);
774 static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
776 struct hpdi_private *devpriv = dev->private;
777 struct comedi_async *async = dev->read_subdev->async;
778 uint32_t next_transfer_addr;
781 void __iomem *pci_addr_reg;
785 devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
788 devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
790 /* loop until we have read all the full buffers */
792 for (next_transfer_addr = readl(pci_addr_reg);
793 (next_transfer_addr <
794 le32_to_cpu(devpriv->dma_desc[devpriv->dma_desc_index].
796 || next_transfer_addr >=
797 le32_to_cpu(devpriv->dma_desc[devpriv->dma_desc_index].
798 pci_start_addr) + devpriv->block_size)
799 && j < devpriv->num_dma_descriptors; j++) {
800 /* transfer data from dma buffer to comedi buffer */
801 num_samples = devpriv->block_size / sizeof(uint32_t);
802 if (async->cmd.stop_src == TRIG_COUNT) {
803 if (num_samples > devpriv->dio_count)
804 num_samples = devpriv->dio_count;
805 devpriv->dio_count -= num_samples;
807 cfc_write_array_to_buffer(dev->read_subdev,
808 devpriv->desc_dio_buffer[devpriv->
810 num_samples * sizeof(uint32_t));
811 devpriv->dma_desc_index++;
812 devpriv->dma_desc_index %= devpriv->num_dma_descriptors;
814 DEBUG_PRINT("next desc addr 0x%lx\n", (unsigned long)
815 devpriv->dma_desc[devpriv->dma_desc_index].
817 DEBUG_PRINT("pci addr reg 0x%x\n", next_transfer_addr);
819 /* XXX check for buffer overrun somehow */
822 static irqreturn_t handle_interrupt(int irq, void *d)
824 struct comedi_device *dev = d;
825 struct hpdi_private *devpriv = dev->private;
826 struct comedi_subdevice *s = dev->read_subdev;
827 struct comedi_async *async = s->async;
828 uint32_t hpdi_intr_status, hpdi_board_status;
831 uint8_t dma0_status, dma1_status;
837 plx_status = readl(devpriv->plx9080_iobase + PLX_INTRCS_REG);
838 if ((plx_status & (ICS_DMA0_A | ICS_DMA1_A | ICS_LIA)) == 0)
841 hpdi_intr_status = readl(devpriv->hpdi_iobase + INTERRUPT_STATUS_REG);
842 hpdi_board_status = readl(devpriv->hpdi_iobase + BOARD_STATUS_REG);
846 if (hpdi_intr_status) {
847 DEBUG_PRINT("hpdi: intr status 0x%x, ", hpdi_intr_status);
848 writel(hpdi_intr_status,
849 devpriv->hpdi_iobase + INTERRUPT_STATUS_REG);
851 /* spin lock makes sure no one else changes plx dma control reg */
852 spin_lock_irqsave(&dev->spinlock, flags);
853 dma0_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
854 if (plx_status & ICS_DMA0_A) { /* dma chan 0 interrupt */
855 writeb((dma0_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
856 devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
858 DEBUG_PRINT("dma0 status 0x%x\n", dma0_status);
859 if (dma0_status & PLX_DMA_EN_BIT)
860 drain_dma_buffers(dev, 0);
861 DEBUG_PRINT(" cleared dma ch0 interrupt\n");
863 spin_unlock_irqrestore(&dev->spinlock, flags);
865 /* spin lock makes sure no one else changes plx dma control reg */
866 spin_lock_irqsave(&dev->spinlock, flags);
867 dma1_status = readb(devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
868 if (plx_status & ICS_DMA1_A) { /* XXX *//* dma chan 1 interrupt */
869 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
870 devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
871 DEBUG_PRINT("dma1 status 0x%x\n", dma1_status);
873 DEBUG_PRINT(" cleared dma ch1 interrupt\n");
875 spin_unlock_irqrestore(&dev->spinlock, flags);
877 /* clear possible plx9080 interrupt sources */
878 if (plx_status & ICS_LDIA) { /* clear local doorbell interrupt */
879 plx_bits = readl(devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
880 writel(plx_bits, devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
881 DEBUG_PRINT(" cleared local doorbell bits 0x%x\n", plx_bits);
884 if (hpdi_board_status & RX_OVERRUN_BIT) {
885 comedi_error(dev, "rx fifo overrun");
886 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
887 DEBUG_PRINT("dma0_status 0x%x\n",
888 (int)readb(devpriv->plx9080_iobase +
892 if (hpdi_board_status & RX_UNDERRUN_BIT) {
893 comedi_error(dev, "rx fifo underrun");
894 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
897 if (devpriv->dio_count == 0)
898 async->events |= COMEDI_CB_EOA;
900 DEBUG_PRINT("board status 0x%x, ", hpdi_board_status);
901 DEBUG_PRINT("plx status 0x%x\n", plx_status);
903 DEBUG_PRINT(" events 0x%x\n", async->events);
905 cfc_handle_events(dev, s);
910 static void abort_dma(struct comedi_device *dev, unsigned int channel)
912 struct hpdi_private *devpriv = dev->private;
915 /* spinlock for plx dma control/status reg */
916 spin_lock_irqsave(&dev->spinlock, flags);
918 plx9080_abort_dma(devpriv->plx9080_iobase, channel);
920 spin_unlock_irqrestore(&dev->spinlock, flags);
923 static int hpdi_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
925 struct hpdi_private *devpriv = dev->private;
927 hpdi_writel(dev, 0, BOARD_CONTROL_REG);
929 writel(0, devpriv->hpdi_iobase + INTERRUPT_CONTROL_REG);
936 static struct comedi_driver gsc_hpdi_driver = {
937 .driver_name = "gsc_hpdi",
938 .module = THIS_MODULE,
939 .auto_attach = hpdi_auto_attach,
940 .detach = hpdi_detach,
943 static int gsc_hpdi_pci_probe(struct pci_dev *dev,
944 const struct pci_device_id *ent)
946 return comedi_pci_auto_config(dev, &gsc_hpdi_driver);
949 static void gsc_hpdi_pci_remove(struct pci_dev *dev)
951 comedi_pci_auto_unconfig(dev);
954 static DEFINE_PCI_DEVICE_TABLE(gsc_hpdi_pci_table) = {
955 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9080, PCI_VENDOR_ID_PLX,
959 MODULE_DEVICE_TABLE(pci, gsc_hpdi_pci_table);
961 static struct pci_driver gsc_hpdi_pci_driver = {
963 .id_table = gsc_hpdi_pci_table,
964 .probe = gsc_hpdi_pci_probe,
965 .remove = gsc_hpdi_pci_remove
967 module_comedi_pci_driver(gsc_hpdi_driver, gsc_hpdi_pci_driver);
969 MODULE_AUTHOR("Comedi http://www.comedi.org");
970 MODULE_DESCRIPTION("Comedi low-level driver");
971 MODULE_LICENSE("GPL");