2 comedi/drivers/gsc_hpdi.c
3 This is a driver for the General Standards Corporation High
4 Speed Parallel Digital Interface rs485 boards.
6 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
7 Copyright (C) 2003 Coherent Imaging Systems
9 COMEDI - Linux Control and Measurement Device Interface
10 Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
25 * Description: General Standards Corporation High
26 * Speed Parallel Digital Interface rs485 boards
27 * Author: Frank Mori Hess <fmhess@users.sourceforge.net>
28 * Status: only receive mode works, transmit not supported
29 * Updated: Thu, 01 Nov 2012 16:17:38 +0000
30 * Devices: [General Standards Corporation] PCI-HPDI32 (gsc_hpdi),
33 * Configuration options:
36 * Manual configuration of supported devices is not supported; they are
37 * configured automatically.
39 * There are some additional hpdi models available from GSC for which
40 * support could be added to this driver.
43 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
45 #include <linux/module.h>
46 #include <linux/pci.h>
47 #include <linux/delay.h>
48 #include <linux/interrupt.h>
50 #include "../comedidev.h"
53 #include "comedi_fc.h"
55 static void abort_dma(struct comedi_device *dev, unsigned int channel);
56 static int hpdi_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
57 static int hpdi_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s,
58 struct comedi_cmd *cmd);
59 static int hpdi_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
60 static irqreturn_t handle_interrupt(int irq, void *d);
61 static int dio_config_block_size(struct comedi_device *dev, unsigned int *data);
63 #undef HPDI_DEBUG /* disable debugging messages */
64 /* #define HPDI_DEBUG enable debugging code */
67 #define DEBUG_PRINT(format, args...) pr_debug(format , ## args)
69 #define DEBUG_PRINT(format, args...) no_printk(pr_fmt(format), ## args)
72 #define TIMER_BASE 50 /* 20MHz master clock */
73 #define DMA_BUFFER_SIZE 0x10000
74 #define NUM_DMA_BUFFERS 4
75 #define NUM_DMA_DESCRIPTORS 256
78 FIRMWARE_REV_REG = 0x0,
79 BOARD_CONTROL_REG = 0x4,
80 BOARD_STATUS_REG = 0x8,
81 TX_PROG_ALMOST_REG = 0xc,
82 RX_PROG_ALMOST_REG = 0x10,
85 TX_STATUS_COUNT_REG = 0x1c,
86 TX_LINE_VALID_COUNT_REG = 0x20,
87 TX_LINE_INVALID_COUNT_REG = 0x24,
88 RX_STATUS_COUNT_REG = 0x28,
89 RX_LINE_COUNT_REG = 0x2c,
90 INTERRUPT_CONTROL_REG = 0x30,
91 INTERRUPT_STATUS_REG = 0x34,
92 TX_CLOCK_DIVIDER_REG = 0x38,
93 TX_FIFO_SIZE_REG = 0x40,
94 RX_FIFO_SIZE_REG = 0x44,
95 TX_FIFO_WORDS_REG = 0x48,
96 RX_FIFO_WORDS_REG = 0x4c,
97 INTERRUPT_EDGE_LEVEL_REG = 0x50,
98 INTERRUPT_POLARITY_REG = 0x54,
101 /* bit definitions */
103 enum firmware_revision_bits {
104 FEATURES_REG_PRESENT_BIT = 0x8000,
107 enum board_control_bits {
108 BOARD_RESET_BIT = 0x1, /* wait 10usec before accessing fifos */
109 TX_FIFO_RESET_BIT = 0x2,
110 RX_FIFO_RESET_BIT = 0x4,
111 TX_ENABLE_BIT = 0x10,
112 RX_ENABLE_BIT = 0x20,
113 DEMAND_DMA_DIRECTION_TX_BIT = 0x40,
114 /* for ch 0, ch 1 can only transmit (when present) */
115 LINE_VALID_ON_STATUS_VALID_BIT = 0x80,
117 CABLE_THROTTLE_ENABLE_BIT = 0x20,
118 TEST_MODE_ENABLE_BIT = 0x80000000,
121 enum board_status_bits {
122 COMMAND_LINE_STATUS_MASK = 0x7f,
123 TX_IN_PROGRESS_BIT = 0x80,
124 TX_NOT_EMPTY_BIT = 0x100,
125 TX_NOT_ALMOST_EMPTY_BIT = 0x200,
126 TX_NOT_ALMOST_FULL_BIT = 0x400,
127 TX_NOT_FULL_BIT = 0x800,
128 RX_NOT_EMPTY_BIT = 0x1000,
129 RX_NOT_ALMOST_EMPTY_BIT = 0x2000,
130 RX_NOT_ALMOST_FULL_BIT = 0x4000,
131 RX_NOT_FULL_BIT = 0x8000,
132 BOARD_JUMPER0_INSTALLED_BIT = 0x10000,
133 BOARD_JUMPER1_INSTALLED_BIT = 0x20000,
134 TX_OVERRUN_BIT = 0x200000,
135 RX_UNDERRUN_BIT = 0x400000,
136 RX_OVERRUN_BIT = 0x800000,
139 static uint32_t almost_full_bits(unsigned int num_words)
141 /* XXX need to add or subtract one? */
142 return (num_words << 16) & 0xff0000;
145 static uint32_t almost_empty_bits(unsigned int num_words)
147 return num_words & 0xffff;
151 FIFO_SIZE_PRESENT_BIT = 0x1,
152 FIFO_WORDS_PRESENT_BIT = 0x2,
153 LEVEL_EDGE_INTERRUPTS_PRESENT_BIT = 0x4,
154 GPIO_SUPPORTED_BIT = 0x8,
155 PLX_DMA_CH1_SUPPORTED_BIT = 0x10,
156 OVERRUN_UNDERRUN_SUPPORTED_BIT = 0x20,
159 enum interrupt_sources {
160 FRAME_VALID_START_INTR = 0,
161 FRAME_VALID_END_INTR = 1,
162 TX_FIFO_EMPTY_INTR = 8,
163 TX_FIFO_ALMOST_EMPTY_INTR = 9,
164 TX_FIFO_ALMOST_FULL_INTR = 10,
165 TX_FIFO_FULL_INTR = 11,
167 RX_ALMOST_EMPTY_INTR = 13,
168 RX_ALMOST_FULL_INTR = 14,
172 static uint32_t intr_bit(int interrupt_source)
174 return 0x1 << interrupt_source;
177 static unsigned int fifo_size(uint32_t fifo_size_bits)
179 return fifo_size_bits & 0xfffff;
183 const char *name; /* board name */
184 int device_id; /* pci device id */
185 int subdevice_id; /* pci subdevice id */
188 static const struct hpdi_board hpdi_boards[] = {
190 .name = "pci-hpdi32",
191 .device_id = PCI_DEVICE_ID_PLX_9080,
192 .subdevice_id = 0x2400,
196 .name = "pxi-hpdi32",
198 .subdevice_id = 0x2705,
203 struct hpdi_private {
204 /* base addresses (ioremapped) */
205 void __iomem *plx9080_iobase;
206 void __iomem *hpdi_iobase;
207 uint32_t *dio_buffer[NUM_DMA_BUFFERS]; /* dma buffers */
208 /* physical addresses of dma buffers */
209 dma_addr_t dio_buffer_phys_addr[NUM_DMA_BUFFERS];
210 /* array of dma descriptors read by plx9080, allocated to get proper
212 struct plx_dma_desc *dma_desc;
213 /* physical address of dma descriptor array */
214 dma_addr_t dma_desc_phys_addr;
215 unsigned int num_dma_descriptors;
216 /* pointer to start of buffers indexed by descriptor */
217 uint32_t *desc_dio_buffer[NUM_DMA_DESCRIPTORS];
218 /* index of the dma descriptor that is currently being used */
219 volatile unsigned int dma_desc_index;
220 unsigned int tx_fifo_size;
221 unsigned int rx_fifo_size;
222 volatile unsigned long dio_count;
223 /* software copies of values written to hpdi registers */
224 volatile uint32_t bits[24];
225 /* number of bytes at which to generate COMEDI_CB_BLOCK events */
226 volatile unsigned int block_size;
227 unsigned dio_config_output:1;
230 static int dio_config_insn(struct comedi_device *dev,
231 struct comedi_subdevice *s, struct comedi_insn *insn,
234 struct hpdi_private *devpriv = dev->private;
237 case INSN_CONFIG_DIO_OUTPUT:
238 devpriv->dio_config_output = 1;
241 case INSN_CONFIG_DIO_INPUT:
242 devpriv->dio_config_output = 0;
245 case INSN_CONFIG_DIO_QUERY:
247 devpriv->dio_config_output ? COMEDI_OUTPUT : COMEDI_INPUT;
250 case INSN_CONFIG_BLOCK_SIZE:
251 return dio_config_block_size(dev, data);
260 static void disable_plx_interrupts(struct comedi_device *dev)
262 struct hpdi_private *devpriv = dev->private;
264 writel(0, devpriv->plx9080_iobase + PLX_INTRCS_REG);
267 /* initialize plx9080 chip */
268 static void init_plx9080(struct comedi_device *dev)
270 struct hpdi_private *devpriv = dev->private;
272 void __iomem *plx_iobase = devpriv->plx9080_iobase;
275 DEBUG_PRINT(" plx interrupt status 0x%x\n",
276 readl(plx_iobase + PLX_INTRCS_REG));
277 DEBUG_PRINT(" plx id bits 0x%x\n", readl(plx_iobase + PLX_ID_REG));
278 DEBUG_PRINT(" plx control reg 0x%x\n",
279 readl(devpriv->plx9080_iobase + PLX_CONTROL_REG));
281 DEBUG_PRINT(" plx revision 0x%x\n",
282 readl(plx_iobase + PLX_REVISION_REG));
283 DEBUG_PRINT(" plx dma channel 0 mode 0x%x\n",
284 readl(plx_iobase + PLX_DMA0_MODE_REG));
285 DEBUG_PRINT(" plx dma channel 1 mode 0x%x\n",
286 readl(plx_iobase + PLX_DMA1_MODE_REG));
287 DEBUG_PRINT(" plx dma channel 0 pci address 0x%x\n",
288 readl(plx_iobase + PLX_DMA0_PCI_ADDRESS_REG));
289 DEBUG_PRINT(" plx dma channel 0 local address 0x%x\n",
290 readl(plx_iobase + PLX_DMA0_LOCAL_ADDRESS_REG));
291 DEBUG_PRINT(" plx dma channel 0 transfer size 0x%x\n",
292 readl(plx_iobase + PLX_DMA0_TRANSFER_SIZE_REG));
293 DEBUG_PRINT(" plx dma channel 0 descriptor 0x%x\n",
294 readl(plx_iobase + PLX_DMA0_DESCRIPTOR_REG));
295 DEBUG_PRINT(" plx dma channel 0 command status 0x%x\n",
296 readb(plx_iobase + PLX_DMA0_CS_REG));
297 DEBUG_PRINT(" plx dma channel 0 threshold 0x%x\n",
298 readl(plx_iobase + PLX_DMA0_THRESHOLD_REG));
299 DEBUG_PRINT(" plx bigend 0x%x\n", readl(plx_iobase + PLX_BIGEND_REG));
301 bits = BIGEND_DMA0 | BIGEND_DMA1;
305 writel(bits, devpriv->plx9080_iobase + PLX_BIGEND_REG);
307 disable_plx_interrupts(dev);
312 /* configure dma0 mode */
314 /* enable ready input */
315 bits |= PLX_DMA_EN_READYIN_BIT;
316 /* enable dma chaining */
317 bits |= PLX_EN_CHAIN_BIT;
318 /* enable interrupt on dma done
319 * (probably don't need this, since chain never finishes) */
320 bits |= PLX_EN_DMA_DONE_INTR_BIT;
321 /* don't increment local address during transfers
322 * (we are transferring from a fixed fifo register) */
323 bits |= PLX_LOCAL_ADDR_CONST_BIT;
324 /* route dma interrupt to pci bus */
325 bits |= PLX_DMA_INTR_PCI_BIT;
326 /* enable demand mode */
327 bits |= PLX_DEMAND_MODE_BIT;
328 /* enable local burst mode */
329 bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
330 bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
331 writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
334 /* Allocate and initialize the subdevice structures.
336 static int setup_subdevices(struct comedi_device *dev)
338 struct comedi_subdevice *s;
341 ret = comedi_alloc_subdevices(dev, 1);
345 s = &dev->subdevices[0];
346 /* analog input subdevice */
347 dev->read_subdev = s;
348 /* dev->write_subdev = s; */
349 s->type = COMEDI_SUBD_DIO;
351 SDF_READABLE | SDF_WRITEABLE | SDF_LSAMPL | SDF_CMD_READ;
353 s->len_chanlist = 32;
355 s->range_table = &range_digital;
356 s->insn_config = dio_config_insn;
357 s->do_cmd = hpdi_cmd;
358 s->do_cmdtest = hpdi_cmd_test;
359 s->cancel = hpdi_cancel;
364 static int init_hpdi(struct comedi_device *dev)
366 struct hpdi_private *devpriv = dev->private;
367 uint32_t plx_intcsr_bits;
369 writel(BOARD_RESET_BIT, devpriv->hpdi_iobase + BOARD_CONTROL_REG);
372 writel(almost_empty_bits(32) | almost_full_bits(32),
373 devpriv->hpdi_iobase + RX_PROG_ALMOST_REG);
374 writel(almost_empty_bits(32) | almost_full_bits(32),
375 devpriv->hpdi_iobase + TX_PROG_ALMOST_REG);
377 devpriv->tx_fifo_size = fifo_size(readl(devpriv->hpdi_iobase +
379 devpriv->rx_fifo_size = fifo_size(readl(devpriv->hpdi_iobase +
382 writel(0, devpriv->hpdi_iobase + INTERRUPT_CONTROL_REG);
384 /* enable interrupts */
386 ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
388 writel(plx_intcsr_bits, devpriv->plx9080_iobase + PLX_INTRCS_REG);
393 /* setup dma descriptors so a link completes every 'transfer_size' bytes */
394 static int setup_dma_descriptors(struct comedi_device *dev,
395 unsigned int transfer_size)
397 struct hpdi_private *devpriv = dev->private;
398 unsigned int buffer_index, buffer_offset;
399 uint32_t next_bits = PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
400 PLX_XFER_LOCAL_TO_PCI;
403 if (transfer_size > DMA_BUFFER_SIZE)
404 transfer_size = DMA_BUFFER_SIZE;
405 transfer_size -= transfer_size % sizeof(uint32_t);
406 if (transfer_size == 0)
409 DEBUG_PRINT(" transfer_size %i\n", transfer_size);
410 DEBUG_PRINT(" descriptors at 0x%lx\n",
411 (unsigned long)devpriv->dma_desc_phys_addr);
415 for (i = 0; i < NUM_DMA_DESCRIPTORS &&
416 buffer_index < NUM_DMA_BUFFERS; i++) {
417 devpriv->dma_desc[i].pci_start_addr =
418 cpu_to_le32(devpriv->dio_buffer_phys_addr[buffer_index] +
420 devpriv->dma_desc[i].local_start_addr = cpu_to_le32(FIFO_REG);
421 devpriv->dma_desc[i].transfer_size =
422 cpu_to_le32(transfer_size);
423 devpriv->dma_desc[i].next =
424 cpu_to_le32((devpriv->dma_desc_phys_addr + (i +
426 sizeof(devpriv->dma_desc[0])) | next_bits);
428 devpriv->desc_dio_buffer[i] =
429 devpriv->dio_buffer[buffer_index] +
430 (buffer_offset / sizeof(uint32_t));
432 buffer_offset += transfer_size;
433 if (transfer_size + buffer_offset > DMA_BUFFER_SIZE) {
438 DEBUG_PRINT(" desc %i\n", i);
439 DEBUG_PRINT(" start addr virt 0x%p, phys 0x%lx\n",
440 devpriv->desc_dio_buffer[i],
441 (unsigned long)devpriv->dma_desc[i].
443 DEBUG_PRINT(" next 0x%lx\n",
444 (unsigned long)devpriv->dma_desc[i].next);
446 devpriv->num_dma_descriptors = i;
447 /* fix last descriptor to point back to first */
448 devpriv->dma_desc[i - 1].next =
449 cpu_to_le32(devpriv->dma_desc_phys_addr | next_bits);
450 DEBUG_PRINT(" desc %i next fixup 0x%lx\n", i - 1,
451 (unsigned long)devpriv->dma_desc[i - 1].next);
453 devpriv->block_size = transfer_size;
455 return transfer_size;
458 static const struct hpdi_board *hpdi_find_board(struct pci_dev *pcidev)
462 for (i = 0; i < ARRAY_SIZE(hpdi_boards); i++)
463 if (pcidev->device == hpdi_boards[i].device_id &&
464 pcidev->subsystem_device == hpdi_boards[i].subdevice_id)
465 return &hpdi_boards[i];
469 static int hpdi_auto_attach(struct comedi_device *dev,
470 unsigned long context_unused)
472 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
473 const struct hpdi_board *thisboard;
474 struct hpdi_private *devpriv;
478 thisboard = hpdi_find_board(pcidev);
480 dev_err(dev->class_dev, "gsc_hpdi: pci %s not supported\n",
484 dev->board_ptr = thisboard;
485 dev->board_name = thisboard->name;
487 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
491 retval = comedi_pci_enable(dev);
494 pci_set_master(pcidev);
496 devpriv->plx9080_iobase = pci_ioremap_bar(pcidev, 0);
497 devpriv->hpdi_iobase = pci_ioremap_bar(pcidev, 2);
498 if (!devpriv->plx9080_iobase || !devpriv->hpdi_iobase) {
499 dev_warn(dev->class_dev, "failed to remap io memory\n");
503 DEBUG_PRINT(" plx9080 remapped to 0x%p\n", devpriv->plx9080_iobase);
504 DEBUG_PRINT(" hpdi remapped to 0x%p\n", devpriv->hpdi_iobase);
509 if (request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
510 dev->board_name, dev)) {
511 dev_warn(dev->class_dev,
512 "unable to allocate irq %u\n", pcidev->irq);
515 dev->irq = pcidev->irq;
517 dev_dbg(dev->class_dev, " irq %u\n", dev->irq);
519 /* allocate pci dma buffers */
520 for (i = 0; i < NUM_DMA_BUFFERS; i++) {
521 devpriv->dio_buffer[i] =
522 pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
523 &devpriv->dio_buffer_phys_addr[i]);
524 DEBUG_PRINT("dio_buffer at virt 0x%p, phys 0x%lx\n",
525 devpriv->dio_buffer[i],
526 (unsigned long)devpriv->dio_buffer_phys_addr[i]);
528 /* allocate dma descriptors */
529 devpriv->dma_desc = pci_alloc_consistent(pcidev,
530 sizeof(struct plx_dma_desc) *
532 &devpriv->dma_desc_phys_addr);
533 if (devpriv->dma_desc_phys_addr & 0xf) {
534 dev_warn(dev->class_dev,
535 " dma descriptors not quad-word aligned (bug)\n");
539 retval = setup_dma_descriptors(dev, 0x1000);
543 retval = setup_subdevices(dev);
547 return init_hpdi(dev);
550 static void hpdi_detach(struct comedi_device *dev)
552 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
553 struct hpdi_private *devpriv = dev->private;
557 free_irq(dev->irq, dev);
559 if (devpriv->plx9080_iobase) {
560 disable_plx_interrupts(dev);
561 iounmap(devpriv->plx9080_iobase);
563 if (devpriv->hpdi_iobase)
564 iounmap(devpriv->hpdi_iobase);
565 /* free pci dma buffers */
566 for (i = 0; i < NUM_DMA_BUFFERS; i++) {
567 if (devpriv->dio_buffer[i])
568 pci_free_consistent(pcidev,
570 devpriv->dio_buffer[i],
572 dio_buffer_phys_addr[i]);
574 /* free dma descriptors */
575 if (devpriv->dma_desc)
576 pci_free_consistent(pcidev,
577 sizeof(struct plx_dma_desc) *
580 devpriv->dma_desc_phys_addr);
582 comedi_pci_disable(dev);
585 static int dio_config_block_size(struct comedi_device *dev, unsigned int *data)
587 unsigned int requested_block_size;
590 requested_block_size = data[1];
592 retval = setup_dma_descriptors(dev, requested_block_size);
601 static int di_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s,
602 struct comedi_cmd *cmd)
607 /* Step 1 : check if triggers are trivially valid */
609 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
610 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
611 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
612 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
613 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
618 /* Step 2a : make sure trigger sources are unique */
620 err |= cfc_check_trigger_is_unique(cmd->stop_src);
622 /* Step 2b : and mutually compatible */
627 /* Step 3: check if arguments are trivially valid */
629 if (!cmd->chanlist_len) {
630 cmd->chanlist_len = 32;
633 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
635 switch (cmd->stop_src) {
637 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
640 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
649 /* step 4: fix up any arguments */
657 for (i = 1; i < cmd->chanlist_len; i++) {
658 if (CR_CHAN(cmd->chanlist[i]) != i) {
659 /* XXX could support 8 or 16 channels */
661 "chanlist must be ch 0 to 31 in order");
673 static int hpdi_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s,
674 struct comedi_cmd *cmd)
676 struct hpdi_private *devpriv = dev->private;
678 if (devpriv->dio_config_output)
681 return di_cmd_test(dev, s, cmd);
684 static inline void hpdi_writel(struct comedi_device *dev, uint32_t bits,
687 struct hpdi_private *devpriv = dev->private;
689 writel(bits | devpriv->bits[offset / sizeof(uint32_t)],
690 devpriv->hpdi_iobase + offset);
693 static int di_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
695 struct hpdi_private *devpriv = dev->private;
698 struct comedi_async *async = s->async;
699 struct comedi_cmd *cmd = &async->cmd;
701 hpdi_writel(dev, RX_FIFO_RESET_BIT, BOARD_CONTROL_REG);
703 DEBUG_PRINT("hpdi: in di_cmd\n");
707 devpriv->dma_desc_index = 0;
709 /* These register are supposedly unused during chained dma,
710 * but I have found that left over values from last operation
711 * occasionally cause problems with transfer of first dma
712 * block. Initializing them to zero seems to fix the problem. */
713 writel(0, devpriv->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG);
714 writel(0, devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
715 writel(0, devpriv->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG);
716 /* give location of first dma descriptor */
718 devpriv->dma_desc_phys_addr | PLX_DESC_IN_PCI_BIT |
719 PLX_INTR_TERM_COUNT | PLX_XFER_LOCAL_TO_PCI;
720 writel(bits, devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
722 /* spinlock for plx dma control/status reg */
723 spin_lock_irqsave(&dev->spinlock, flags);
724 /* enable dma transfer */
725 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT | PLX_CLEAR_DMA_INTR_BIT,
726 devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
727 spin_unlock_irqrestore(&dev->spinlock, flags);
729 if (cmd->stop_src == TRIG_COUNT)
730 devpriv->dio_count = cmd->stop_arg;
732 devpriv->dio_count = 1;
734 /* clear over/under run status flags */
735 writel(RX_UNDERRUN_BIT | RX_OVERRUN_BIT,
736 devpriv->hpdi_iobase + BOARD_STATUS_REG);
737 /* enable interrupts */
738 writel(intr_bit(RX_FULL_INTR),
739 devpriv->hpdi_iobase + INTERRUPT_CONTROL_REG);
741 DEBUG_PRINT("hpdi: starting rx\n");
742 hpdi_writel(dev, RX_ENABLE_BIT, BOARD_CONTROL_REG);
747 static int hpdi_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
749 struct hpdi_private *devpriv = dev->private;
751 if (devpriv->dio_config_output)
754 return di_cmd(dev, s);
757 static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
759 struct hpdi_private *devpriv = dev->private;
760 struct comedi_async *async = dev->read_subdev->async;
761 uint32_t next_transfer_addr;
764 void __iomem *pci_addr_reg;
768 devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
771 devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
773 /* loop until we have read all the full buffers */
775 for (next_transfer_addr = readl(pci_addr_reg);
776 (next_transfer_addr <
777 le32_to_cpu(devpriv->dma_desc[devpriv->dma_desc_index].
779 || next_transfer_addr >=
780 le32_to_cpu(devpriv->dma_desc[devpriv->dma_desc_index].
781 pci_start_addr) + devpriv->block_size)
782 && j < devpriv->num_dma_descriptors; j++) {
783 /* transfer data from dma buffer to comedi buffer */
784 num_samples = devpriv->block_size / sizeof(uint32_t);
785 if (async->cmd.stop_src == TRIG_COUNT) {
786 if (num_samples > devpriv->dio_count)
787 num_samples = devpriv->dio_count;
788 devpriv->dio_count -= num_samples;
790 cfc_write_array_to_buffer(dev->read_subdev,
791 devpriv->desc_dio_buffer[devpriv->
793 num_samples * sizeof(uint32_t));
794 devpriv->dma_desc_index++;
795 devpriv->dma_desc_index %= devpriv->num_dma_descriptors;
797 DEBUG_PRINT("next desc addr 0x%lx\n", (unsigned long)
798 devpriv->dma_desc[devpriv->dma_desc_index].
800 DEBUG_PRINT("pci addr reg 0x%x\n", next_transfer_addr);
802 /* XXX check for buffer overrun somehow */
805 static irqreturn_t handle_interrupt(int irq, void *d)
807 struct comedi_device *dev = d;
808 struct hpdi_private *devpriv = dev->private;
809 struct comedi_subdevice *s = dev->read_subdev;
810 struct comedi_async *async = s->async;
811 uint32_t hpdi_intr_status, hpdi_board_status;
814 uint8_t dma0_status, dma1_status;
820 plx_status = readl(devpriv->plx9080_iobase + PLX_INTRCS_REG);
821 if ((plx_status & (ICS_DMA0_A | ICS_DMA1_A | ICS_LIA)) == 0)
824 hpdi_intr_status = readl(devpriv->hpdi_iobase + INTERRUPT_STATUS_REG);
825 hpdi_board_status = readl(devpriv->hpdi_iobase + BOARD_STATUS_REG);
829 if (hpdi_intr_status) {
830 DEBUG_PRINT("hpdi: intr status 0x%x, ", hpdi_intr_status);
831 writel(hpdi_intr_status,
832 devpriv->hpdi_iobase + INTERRUPT_STATUS_REG);
834 /* spin lock makes sure no one else changes plx dma control reg */
835 spin_lock_irqsave(&dev->spinlock, flags);
836 dma0_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
837 if (plx_status & ICS_DMA0_A) { /* dma chan 0 interrupt */
838 writeb((dma0_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
839 devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
841 DEBUG_PRINT("dma0 status 0x%x\n", dma0_status);
842 if (dma0_status & PLX_DMA_EN_BIT)
843 drain_dma_buffers(dev, 0);
844 DEBUG_PRINT(" cleared dma ch0 interrupt\n");
846 spin_unlock_irqrestore(&dev->spinlock, flags);
848 /* spin lock makes sure no one else changes plx dma control reg */
849 spin_lock_irqsave(&dev->spinlock, flags);
850 dma1_status = readb(devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
851 if (plx_status & ICS_DMA1_A) { /* XXX *//* dma chan 1 interrupt */
852 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
853 devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
854 DEBUG_PRINT("dma1 status 0x%x\n", dma1_status);
856 DEBUG_PRINT(" cleared dma ch1 interrupt\n");
858 spin_unlock_irqrestore(&dev->spinlock, flags);
860 /* clear possible plx9080 interrupt sources */
861 if (plx_status & ICS_LDIA) { /* clear local doorbell interrupt */
862 plx_bits = readl(devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
863 writel(plx_bits, devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
864 DEBUG_PRINT(" cleared local doorbell bits 0x%x\n", plx_bits);
867 if (hpdi_board_status & RX_OVERRUN_BIT) {
868 comedi_error(dev, "rx fifo overrun");
869 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
870 DEBUG_PRINT("dma0_status 0x%x\n",
871 (int)readb(devpriv->plx9080_iobase +
875 if (hpdi_board_status & RX_UNDERRUN_BIT) {
876 comedi_error(dev, "rx fifo underrun");
877 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
880 if (devpriv->dio_count == 0)
881 async->events |= COMEDI_CB_EOA;
883 DEBUG_PRINT("board status 0x%x, ", hpdi_board_status);
884 DEBUG_PRINT("plx status 0x%x\n", plx_status);
886 DEBUG_PRINT(" events 0x%x\n", async->events);
888 cfc_handle_events(dev, s);
893 static void abort_dma(struct comedi_device *dev, unsigned int channel)
895 struct hpdi_private *devpriv = dev->private;
898 /* spinlock for plx dma control/status reg */
899 spin_lock_irqsave(&dev->spinlock, flags);
901 plx9080_abort_dma(devpriv->plx9080_iobase, channel);
903 spin_unlock_irqrestore(&dev->spinlock, flags);
906 static int hpdi_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
908 struct hpdi_private *devpriv = dev->private;
910 hpdi_writel(dev, 0, BOARD_CONTROL_REG);
912 writel(0, devpriv->hpdi_iobase + INTERRUPT_CONTROL_REG);
919 static struct comedi_driver gsc_hpdi_driver = {
920 .driver_name = "gsc_hpdi",
921 .module = THIS_MODULE,
922 .auto_attach = hpdi_auto_attach,
923 .detach = hpdi_detach,
926 static int gsc_hpdi_pci_probe(struct pci_dev *dev,
927 const struct pci_device_id *id)
929 return comedi_pci_auto_config(dev, &gsc_hpdi_driver, id->driver_data);
932 static DEFINE_PCI_DEVICE_TABLE(gsc_hpdi_pci_table) = {
933 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9080, PCI_VENDOR_ID_PLX,
937 MODULE_DEVICE_TABLE(pci, gsc_hpdi_pci_table);
939 static struct pci_driver gsc_hpdi_pci_driver = {
941 .id_table = gsc_hpdi_pci_table,
942 .probe = gsc_hpdi_pci_probe,
943 .remove = comedi_pci_auto_unconfig,
945 module_comedi_pci_driver(gsc_hpdi_driver, gsc_hpdi_pci_driver);
947 MODULE_AUTHOR("Comedi http://www.comedi.org");
948 MODULE_DESCRIPTION("Comedi low-level driver");
949 MODULE_LICENSE("GPL");