2 comedi/drivers/me4000.c
3 Source code for the Meilhaus ME-4000 board family.
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 2000 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 Description: Meilhaus ME-4000 series boards
26 Devices: [Meilhaus] ME-4650 (me4000), ME-4670i, ME-4680, ME-4680i, ME-4680is
27 Author: gg (Guenter Gebhardt <g.gebhardt@meilhaus.com>)
28 Updated: Mon, 18 Mar 2002 15:34:01 -0800
29 Status: broken (no support for loading firmware)
38 Configuration Options: not applicable, uses PCI auto config
40 The firmware required by these boards is available in the
41 comedi_nonfree_firmware tarball available from
42 http://www.comedi.org. However, the driver's support for
43 loading the firmware through comedi_config is currently
48 #include <linux/interrupt.h>
49 #include "../comedidev.h"
51 #include <linux/delay.h>
52 #include <linux/list.h>
53 #include <linux/spinlock.h>
55 #include "comedi_fc.h"
59 /* file removed due to GPL incompatibility */
60 #include "me4000_fw.h"
63 #define PCI_DEVICE_ID_MEILHAUS_ME4650 0x4650
64 #define PCI_DEVICE_ID_MEILHAUS_ME4660 0x4660
65 #define PCI_DEVICE_ID_MEILHAUS_ME4660I 0x4661
66 #define PCI_DEVICE_ID_MEILHAUS_ME4660S 0x4662
67 #define PCI_DEVICE_ID_MEILHAUS_ME4660IS 0x4663
68 #define PCI_DEVICE_ID_MEILHAUS_ME4670 0x4670
69 #define PCI_DEVICE_ID_MEILHAUS_ME4670I 0x4671
70 #define PCI_DEVICE_ID_MEILHAUS_ME4670S 0x4672
71 #define PCI_DEVICE_ID_MEILHAUS_ME4670IS 0x4673
72 #define PCI_DEVICE_ID_MEILHAUS_ME4680 0x4680
73 #define PCI_DEVICE_ID_MEILHAUS_ME4680I 0x4681
74 #define PCI_DEVICE_ID_MEILHAUS_ME4680S 0x4682
75 #define PCI_DEVICE_ID_MEILHAUS_ME4680IS 0x4683
78 * ME4000 Register map and bit defines
80 #define ME4000_AO_CHAN(x) ((x) * 0x18)
82 #define ME4000_AO_CTRL_REG(x) (0x00 + ME4000_AO_CHAN(x))
83 #define ME4000_AO_CTRL_BIT_MODE_0 (1 << 0)
84 #define ME4000_AO_CTRL_BIT_MODE_1 (1 << 1)
85 #define ME4000_AO_CTRL_MASK_MODE (3 << 0)
86 #define ME4000_AO_CTRL_BIT_STOP (1 << 2)
87 #define ME4000_AO_CTRL_BIT_ENABLE_FIFO (1 << 3)
88 #define ME4000_AO_CTRL_BIT_ENABLE_EX_TRIG (1 << 4)
89 #define ME4000_AO_CTRL_BIT_EX_TRIG_EDGE (1 << 5)
90 #define ME4000_AO_CTRL_BIT_IMMEDIATE_STOP (1 << 7)
91 #define ME4000_AO_CTRL_BIT_ENABLE_DO (1 << 8)
92 #define ME4000_AO_CTRL_BIT_ENABLE_IRQ (1 << 9)
93 #define ME4000_AO_CTRL_BIT_RESET_IRQ (1 << 10)
94 #define ME4000_AO_STATUS_REG(x) (0x04 + ME4000_AO_CHAN(x))
95 #define ME4000_AO_STATUS_BIT_FSM (1 << 0)
96 #define ME4000_AO_STATUS_BIT_FF (1 << 1)
97 #define ME4000_AO_STATUS_BIT_HF (1 << 2)
98 #define ME4000_AO_STATUS_BIT_EF (1 << 3)
99 #define ME4000_AO_FIFO_REG(x) (0x08 + ME4000_AO_CHAN(x))
100 #define ME4000_AO_SINGLE_REG(x) (0x0c + ME4000_AO_CHAN(x))
101 #define ME4000_AO_TIMER_REG(x) (0x10 + ME4000_AO_CHAN(x))
102 #define ME4000_AI_CTRL_REG 0x74
103 #define ME4000_AI_STATUS_REG 0x74
104 #define ME4000_AI_CTRL_BIT_MODE_0 (1 << 0)
105 #define ME4000_AI_CTRL_BIT_MODE_1 (1 << 1)
106 #define ME4000_AI_CTRL_BIT_MODE_2 (1 << 2)
107 #define ME4000_AI_CTRL_BIT_SAMPLE_HOLD (1 << 3)
108 #define ME4000_AI_CTRL_BIT_IMMEDIATE_STOP (1 << 4)
109 #define ME4000_AI_CTRL_BIT_STOP (1 << 5)
110 #define ME4000_AI_CTRL_BIT_CHANNEL_FIFO (1 << 6)
111 #define ME4000_AI_CTRL_BIT_DATA_FIFO (1 << 7)
112 #define ME4000_AI_CTRL_BIT_FULLSCALE (1 << 8)
113 #define ME4000_AI_CTRL_BIT_OFFSET (1 << 9)
114 #define ME4000_AI_CTRL_BIT_EX_TRIG_ANALOG (1 << 10)
115 #define ME4000_AI_CTRL_BIT_EX_TRIG (1 << 11)
116 #define ME4000_AI_CTRL_BIT_EX_TRIG_FALLING (1 << 12)
117 #define ME4000_AI_CTRL_BIT_EX_IRQ (1 << 13)
118 #define ME4000_AI_CTRL_BIT_EX_IRQ_RESET (1 << 14)
119 #define ME4000_AI_CTRL_BIT_LE_IRQ (1 << 15)
120 #define ME4000_AI_CTRL_BIT_LE_IRQ_RESET (1 << 16)
121 #define ME4000_AI_CTRL_BIT_HF_IRQ (1 << 17)
122 #define ME4000_AI_CTRL_BIT_HF_IRQ_RESET (1 << 18)
123 #define ME4000_AI_CTRL_BIT_SC_IRQ (1 << 19)
124 #define ME4000_AI_CTRL_BIT_SC_IRQ_RESET (1 << 20)
125 #define ME4000_AI_CTRL_BIT_SC_RELOAD (1 << 21)
126 #define ME4000_AI_STATUS_BIT_EF_CHANNEL (1 << 22)
127 #define ME4000_AI_STATUS_BIT_HF_CHANNEL (1 << 23)
128 #define ME4000_AI_STATUS_BIT_FF_CHANNEL (1 << 24)
129 #define ME4000_AI_STATUS_BIT_EF_DATA (1 << 25)
130 #define ME4000_AI_STATUS_BIT_HF_DATA (1 << 26)
131 #define ME4000_AI_STATUS_BIT_FF_DATA (1 << 27)
132 #define ME4000_AI_STATUS_BIT_LE (1 << 28)
133 #define ME4000_AI_STATUS_BIT_FSM (1 << 29)
134 #define ME4000_AI_CTRL_BIT_EX_TRIG_BOTH (1 << 31)
135 #define ME4000_AI_CHANNEL_LIST_REG 0x78
136 #define ME4000_AI_LIST_INPUT_SINGLE_ENDED (0 << 5)
137 #define ME4000_AI_LIST_INPUT_DIFFERENTIAL (1 << 5)
138 #define ME4000_AI_LIST_RANGE_BIPOLAR_10 (0 << 6)
139 #define ME4000_AI_LIST_RANGE_BIPOLAR_2_5 (1 << 6)
140 #define ME4000_AI_LIST_RANGE_UNIPOLAR_10 (2 << 6)
141 #define ME4000_AI_LIST_RANGE_UNIPOLAR_2_5 (3 << 6)
142 #define ME4000_AI_LIST_LAST_ENTRY (1 << 8)
143 #define ME4000_AI_DATA_REG 0x7c
144 #define ME4000_AI_CHAN_TIMER_REG 0x80
145 #define ME4000_AI_CHAN_PRE_TIMER_REG 0x84
146 #define ME4000_AI_SCAN_TIMER_LOW_REG 0x88
147 #define ME4000_AI_SCAN_TIMER_HIGH_REG 0x8c
148 #define ME4000_AI_SCAN_PRE_TIMER_LOW_REG 0x90
149 #define ME4000_AI_SCAN_PRE_TIMER_HIGH_REG 0x94
150 #define ME4000_AI_START_REG 0x98
151 #define ME4000_IRQ_STATUS_REG 0x9c
152 #define ME4000_IRQ_STATUS_BIT_EX (1 << 0)
153 #define ME4000_IRQ_STATUS_BIT_LE (1 << 1)
154 #define ME4000_IRQ_STATUS_BIT_AI_HF (1 << 2)
155 #define ME4000_IRQ_STATUS_BIT_AO_0_HF (1 << 3)
156 #define ME4000_IRQ_STATUS_BIT_AO_1_HF (1 << 4)
157 #define ME4000_IRQ_STATUS_BIT_AO_2_HF (1 << 5)
158 #define ME4000_IRQ_STATUS_BIT_AO_3_HF (1 << 6)
159 #define ME4000_IRQ_STATUS_BIT_SC (1 << 7)
160 #define ME4000_DIO_PORT_0_REG 0xa0
161 #define ME4000_DIO_PORT_1_REG 0xa4
162 #define ME4000_DIO_PORT_2_REG 0xa8
163 #define ME4000_DIO_PORT_3_REG 0xac
164 #define ME4000_DIO_DIR_REG 0xb0
165 #define ME4000_AO_LOADSETREG_XX 0xb4
166 #define ME4000_DIO_CTRL_REG 0xb8
167 #define ME4000_DIO_CTRL_BIT_MODE_0 (1 << 0)
168 #define ME4000_DIO_CTRL_BIT_MODE_1 (1 << 1)
169 #define ME4000_DIO_CTRL_BIT_MODE_2 (1 << 2)
170 #define ME4000_DIO_CTRL_BIT_MODE_3 (1 << 3)
171 #define ME4000_DIO_CTRL_BIT_MODE_4 (1 << 4)
172 #define ME4000_DIO_CTRL_BIT_MODE_5 (1 << 5)
173 #define ME4000_DIO_CTRL_BIT_MODE_6 (1 << 6)
174 #define ME4000_DIO_CTRL_BIT_MODE_7 (1 << 7)
175 #define ME4000_DIO_CTRL_BIT_FUNCTION_0 (1 << 8)
176 #define ME4000_DIO_CTRL_BIT_FUNCTION_1 (1 << 9)
177 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_0 (1 << 10)
178 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_1 (1 << 11)
179 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_2 (1 << 12)
180 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_3 (1 << 13)
181 #define ME4000_AO_DEMUX_ADJUST_REG 0xbc
182 #define ME4000_AO_DEMUX_ADJUST_VALUE 0x4c
183 #define ME4000_AI_SAMPLE_COUNTER_REG 0xc0
186 * PLX Register map and bit defines
188 #define PLX_INTCSR 0x4c
189 #define PLX_INTCSR_LOCAL_INT1_EN (1 << 0)
190 #define PLX_INTCSR_LOCAL_INT1_POL (1 << 1)
191 #define PLX_INTCSR_LOCAL_INT1_STATE (1 << 2)
192 #define PLX_INTCSR_LOCAL_INT2_EN (1 << 3)
193 #define PLX_INTCSR_LOCAL_INT2_POL (1 << 4)
194 #define PLX_INTCSR_LOCAL_INT2_STATE (1 << 5)
195 #define PLX_INTCSR_PCI_INT_EN (1 << 6)
196 #define PLX_INTCSR_SOFT_INT (1 << 7)
198 #define PLX_ICR_BIT_EEPROM_CLOCK_SET (1 << 24)
199 #define PLX_ICR_BIT_EEPROM_CHIP_SELECT (1 << 25)
200 #define PLX_ICR_BIT_EEPROM_WRITE (1 << 26)
201 #define PLX_ICR_BIT_EEPROM_READ (1 << 27)
202 #define PLX_ICR_BIT_EEPROM_VALID (1 << 28)
203 #define PLX_ICR_MASK_EEPROM (0x1f << 24)
205 #define EEPROM_DELAY 1
207 #define ME4000_AI_FIFO_COUNT 2048
209 #define ME4000_AI_MIN_TICKS 66
210 #define ME4000_AI_MIN_SAMPLE_TIME 2000
211 #define ME4000_AI_BASE_FREQUENCY (unsigned int) 33E6
213 #define ME4000_AI_CHANNEL_LIST_COUNT 1024
216 unsigned long plx_regbase;
217 unsigned long timer_regbase;
219 unsigned int ao_readback[4];
222 struct me4000_board {
224 unsigned short device_id;
235 static const struct me4000_board me4000_boards[] = {
238 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4650,
243 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4660,
250 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4660I,
257 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4660S,
265 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4660IS,
273 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4670,
282 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4670I,
291 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4670S,
301 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4670IS,
311 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4680,
321 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4680I,
331 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4680S,
342 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4680IS,
354 static const struct comedi_lrange me4000_ai_range = {
364 #define FIRMWARE_NOT_AVAILABLE 1
365 #if FIRMWARE_NOT_AVAILABLE
366 extern unsigned char *xilinx_firm;
369 static int xilinx_download(struct comedi_device *dev)
371 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
372 struct me4000_info *info = dev->private;
373 unsigned long xilinx_iobase = pci_resource_start(pcidev, 5);
375 wait_queue_head_t queue;
382 init_waitqueue_head(&queue);
385 * Set PLX local interrupt 2 polarity to high.
386 * Interrupt is thrown by init pin of xilinx.
388 outl(0x10, info->plx_regbase + PLX_INTCSR);
390 /* Set /CS and /WRITE of the Xilinx */
391 value = inl(info->plx_regbase + PLX_ICR);
393 outl(value, info->plx_regbase + PLX_ICR);
395 /* Init Xilinx with CS1 */
396 inb(xilinx_iobase + 0xC8);
398 /* Wait until /INIT pin is set */
400 if (!(inl(info->plx_regbase + PLX_INTCSR) & 0x20)) {
401 dev_err(dev->class_dev, "Can't init Xilinx\n");
405 /* Reset /CS and /WRITE of the Xilinx */
406 value = inl(info->plx_regbase + PLX_ICR);
408 outl(value, info->plx_regbase + PLX_ICR);
409 if (FIRMWARE_NOT_AVAILABLE) {
410 dev_err(dev->class_dev,
411 "xilinx firmware unavailable due to licensing, aborting");
414 /* Download Xilinx firmware */
415 size = (xilinx_firm[0] << 24) + (xilinx_firm[1] << 16) +
416 (xilinx_firm[2] << 8) + xilinx_firm[3];
419 for (idx = 0; idx < size; idx++) {
420 outb(xilinx_firm[16 + idx], xilinx_iobase);
423 /* Check if BUSY flag is low */
424 if (inl(info->plx_regbase + PLX_ICR) & 0x20) {
425 dev_err(dev->class_dev,
426 "Xilinx is still busy (idx = %d)\n",
433 /* If done flag is high download was successful */
434 if (inl(info->plx_regbase + PLX_ICR) & 0x4) {
436 dev_err(dev->class_dev, "DONE flag is not set\n");
437 dev_err(dev->class_dev, "Download not successful\n");
441 /* Set /CS and /WRITE */
442 value = inl(info->plx_regbase + PLX_ICR);
444 outl(value, info->plx_regbase + PLX_ICR);
449 static void me4000_reset(struct comedi_device *dev)
451 struct me4000_info *info = dev->private;
455 /* Make a hardware reset */
456 val = inl(info->plx_regbase + PLX_ICR);
458 outl(val, info->plx_regbase + PLX_ICR);
460 outl(val , info->plx_regbase + PLX_ICR);
462 /* 0x8000 to the DACs means an output voltage of 0V */
463 for (chan = 0; chan < 4; chan++)
464 outl(0x8000, dev->iobase + ME4000_AO_SINGLE_REG(chan));
466 /* Set both stop bits in the analog input control register */
467 outl(ME4000_AI_CTRL_BIT_IMMEDIATE_STOP | ME4000_AI_CTRL_BIT_STOP,
468 dev->iobase + ME4000_AI_CTRL_REG);
470 /* Set both stop bits in the analog output control register */
471 val = ME4000_AO_CTRL_BIT_IMMEDIATE_STOP | ME4000_AO_CTRL_BIT_STOP;
472 for (chan = 0; chan < 4; chan++)
473 outl(val, dev->iobase + ME4000_AO_CTRL_REG(chan));
475 /* Enable interrupts on the PLX */
476 outl(0x43, info->plx_regbase + PLX_INTCSR);
478 /* Set the adustment register for AO demux */
479 outl(ME4000_AO_DEMUX_ADJUST_VALUE,
480 dev->iobase + ME4000_AO_DEMUX_ADJUST_REG);
483 * Set digital I/O direction for port 0
484 * to output on isolated versions
486 if (!(inl(dev->iobase + ME4000_DIO_DIR_REG) & 0x1))
487 outl(0x1, dev->iobase + ME4000_DIO_CTRL_REG);
490 /*=============================================================================
492 ===========================================================================*/
494 static int me4000_ai_insn_read(struct comedi_device *dev,
495 struct comedi_subdevice *subdevice,
496 struct comedi_insn *insn, unsigned int *data)
498 const struct me4000_board *thisboard = comedi_board(dev);
499 int chan = CR_CHAN(insn->chanspec);
500 int rang = CR_RANGE(insn->chanspec);
501 int aref = CR_AREF(insn->chanspec);
503 unsigned long entry = 0;
509 } else if (insn->n > 1) {
510 dev_err(dev->class_dev, "Invalid instruction length %d\n",
517 entry |= ME4000_AI_LIST_RANGE_UNIPOLAR_2_5;
520 entry |= ME4000_AI_LIST_RANGE_UNIPOLAR_10;
523 entry |= ME4000_AI_LIST_RANGE_BIPOLAR_2_5;
526 entry |= ME4000_AI_LIST_RANGE_BIPOLAR_10;
529 dev_err(dev->class_dev, "Invalid range specified\n");
536 if (chan >= thisboard->ai_nchan) {
537 dev_err(dev->class_dev,
538 "Analog input is not available\n");
541 entry |= ME4000_AI_LIST_INPUT_SINGLE_ENDED | chan;
545 if (rang == 0 || rang == 1) {
546 dev_err(dev->class_dev,
547 "Range must be bipolar when aref = diff\n");
551 if (chan >= thisboard->ai_diff_nchan) {
552 dev_err(dev->class_dev,
553 "Analog input is not available\n");
556 entry |= ME4000_AI_LIST_INPUT_DIFFERENTIAL | chan;
559 dev_err(dev->class_dev, "Invalid aref specified\n");
563 entry |= ME4000_AI_LIST_LAST_ENTRY;
565 /* Clear channel list, data fifo and both stop bits */
566 tmp = inl(dev->iobase + ME4000_AI_CTRL_REG);
567 tmp &= ~(ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
568 ME4000_AI_CTRL_BIT_DATA_FIFO |
569 ME4000_AI_CTRL_BIT_STOP | ME4000_AI_CTRL_BIT_IMMEDIATE_STOP);
570 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
572 /* Set the acquisition mode to single */
573 tmp &= ~(ME4000_AI_CTRL_BIT_MODE_0 | ME4000_AI_CTRL_BIT_MODE_1 |
574 ME4000_AI_CTRL_BIT_MODE_2);
575 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
577 /* Enable channel list and data fifo */
578 tmp |= ME4000_AI_CTRL_BIT_CHANNEL_FIFO | ME4000_AI_CTRL_BIT_DATA_FIFO;
579 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
581 /* Generate channel list entry */
582 outl(entry, dev->iobase + ME4000_AI_CHANNEL_LIST_REG);
584 /* Set the timer to maximum sample rate */
585 outl(ME4000_AI_MIN_TICKS, dev->iobase + ME4000_AI_CHAN_TIMER_REG);
586 outl(ME4000_AI_MIN_TICKS, dev->iobase + ME4000_AI_CHAN_PRE_TIMER_REG);
588 /* Start conversion by dummy read */
589 inl(dev->iobase + ME4000_AI_START_REG);
591 /* Wait until ready */
593 if (!(inl(dev->iobase + ME4000_AI_STATUS_REG) &
594 ME4000_AI_STATUS_BIT_EF_DATA)) {
595 dev_err(dev->class_dev, "Value not available after wait\n");
599 /* Read value from data fifo */
600 lval = inl(dev->iobase + ME4000_AI_DATA_REG) & 0xFFFF;
601 data[0] = lval ^ 0x8000;
606 static int me4000_ai_cancel(struct comedi_device *dev,
607 struct comedi_subdevice *s)
611 /* Stop any running conversion */
612 tmp = inl(dev->iobase + ME4000_AI_CTRL_REG);
613 tmp &= ~(ME4000_AI_CTRL_BIT_STOP | ME4000_AI_CTRL_BIT_IMMEDIATE_STOP);
614 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
616 /* Clear the control register */
617 outl(0x0, dev->iobase + ME4000_AI_CTRL_REG);
622 static int ai_check_chanlist(struct comedi_device *dev,
623 struct comedi_subdevice *s, struct comedi_cmd *cmd)
625 const struct me4000_board *thisboard = comedi_board(dev);
629 /* Check whether a channel list is available */
630 if (!cmd->chanlist_len) {
631 dev_err(dev->class_dev, "No channel list available\n");
635 /* Check the channel list size */
636 if (cmd->chanlist_len > ME4000_AI_CHANNEL_LIST_COUNT) {
637 dev_err(dev->class_dev, "Channel list is to large\n");
641 /* Check the pointer */
642 if (!cmd->chanlist) {
643 dev_err(dev->class_dev, "NULL pointer to channel list\n");
647 /* Check whether aref is equal for all entries */
648 aref = CR_AREF(cmd->chanlist[0]);
649 for (i = 0; i < cmd->chanlist_len; i++) {
650 if (CR_AREF(cmd->chanlist[i]) != aref) {
651 dev_err(dev->class_dev,
652 "Mode is not equal for all entries\n");
657 /* Check whether channels are available for this ending */
658 if (aref == SDF_DIFF) {
659 for (i = 0; i < cmd->chanlist_len; i++) {
660 if (CR_CHAN(cmd->chanlist[i]) >=
661 thisboard->ai_diff_nchan) {
662 dev_err(dev->class_dev,
663 "Channel number to high\n");
668 for (i = 0; i < cmd->chanlist_len; i++) {
669 if (CR_CHAN(cmd->chanlist[i]) >= thisboard->ai_nchan) {
670 dev_err(dev->class_dev,
671 "Channel number to high\n");
677 /* Check if bipolar is set for all entries when in differential mode */
678 if (aref == SDF_DIFF) {
679 for (i = 0; i < cmd->chanlist_len; i++) {
680 if (CR_RANGE(cmd->chanlist[i]) != 1 &&
681 CR_RANGE(cmd->chanlist[i]) != 2) {
682 dev_err(dev->class_dev,
683 "Bipolar is not selected in differential mode\n");
692 static int ai_round_cmd_args(struct comedi_device *dev,
693 struct comedi_subdevice *s,
694 struct comedi_cmd *cmd,
695 unsigned int *init_ticks,
696 unsigned int *scan_ticks, unsigned int *chan_ticks)
705 if (cmd->start_arg) {
706 *init_ticks = (cmd->start_arg * 33) / 1000;
707 rest = (cmd->start_arg * 33) % 1000;
709 if ((cmd->flags & TRIG_ROUND_MASK) == TRIG_ROUND_NEAREST) {
712 } else if ((cmd->flags & TRIG_ROUND_MASK) == TRIG_ROUND_UP) {
718 if (cmd->scan_begin_arg) {
719 *scan_ticks = (cmd->scan_begin_arg * 33) / 1000;
720 rest = (cmd->scan_begin_arg * 33) % 1000;
722 if ((cmd->flags & TRIG_ROUND_MASK) == TRIG_ROUND_NEAREST) {
725 } else if ((cmd->flags & TRIG_ROUND_MASK) == TRIG_ROUND_UP) {
731 if (cmd->convert_arg) {
732 *chan_ticks = (cmd->convert_arg * 33) / 1000;
733 rest = (cmd->convert_arg * 33) % 1000;
735 if ((cmd->flags & TRIG_ROUND_MASK) == TRIG_ROUND_NEAREST) {
738 } else if ((cmd->flags & TRIG_ROUND_MASK) == TRIG_ROUND_UP) {
747 static void ai_write_timer(struct comedi_device *dev,
748 unsigned int init_ticks,
749 unsigned int scan_ticks, unsigned int chan_ticks)
751 outl(init_ticks - 1, dev->iobase + ME4000_AI_SCAN_PRE_TIMER_LOW_REG);
752 outl(0x0, dev->iobase + ME4000_AI_SCAN_PRE_TIMER_HIGH_REG);
755 outl(scan_ticks - 1, dev->iobase + ME4000_AI_SCAN_TIMER_LOW_REG);
756 outl(0x0, dev->iobase + ME4000_AI_SCAN_TIMER_HIGH_REG);
759 outl(chan_ticks - 1, dev->iobase + ME4000_AI_CHAN_PRE_TIMER_REG);
760 outl(chan_ticks - 1, dev->iobase + ME4000_AI_CHAN_TIMER_REG);
763 static int ai_write_chanlist(struct comedi_device *dev,
764 struct comedi_subdevice *s, struct comedi_cmd *cmd)
772 for (i = 0; i < cmd->chanlist_len; i++) {
773 chan = CR_CHAN(cmd->chanlist[i]);
774 rang = CR_RANGE(cmd->chanlist[i]);
775 aref = CR_AREF(cmd->chanlist[i]);
780 entry |= ME4000_AI_LIST_RANGE_UNIPOLAR_2_5;
782 entry |= ME4000_AI_LIST_RANGE_UNIPOLAR_10;
784 entry |= ME4000_AI_LIST_RANGE_BIPOLAR_2_5;
786 entry |= ME4000_AI_LIST_RANGE_BIPOLAR_10;
788 if (aref == SDF_DIFF)
789 entry |= ME4000_AI_LIST_INPUT_DIFFERENTIAL;
791 entry |= ME4000_AI_LIST_INPUT_SINGLE_ENDED;
793 outl(entry, dev->iobase + ME4000_AI_CHANNEL_LIST_REG);
799 static int ai_prepare(struct comedi_device *dev,
800 struct comedi_subdevice *s,
801 struct comedi_cmd *cmd,
802 unsigned int init_ticks,
803 unsigned int scan_ticks, unsigned int chan_ticks)
806 unsigned long tmp = 0;
808 /* Write timer arguments */
809 ai_write_timer(dev, init_ticks, scan_ticks, chan_ticks);
811 /* Reset control register */
812 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
815 if ((cmd->start_src == TRIG_EXT &&
816 cmd->scan_begin_src == TRIG_TIMER &&
817 cmd->convert_src == TRIG_TIMER) ||
818 (cmd->start_src == TRIG_EXT &&
819 cmd->scan_begin_src == TRIG_FOLLOW &&
820 cmd->convert_src == TRIG_TIMER)) {
821 tmp = ME4000_AI_CTRL_BIT_MODE_1 |
822 ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
823 ME4000_AI_CTRL_BIT_DATA_FIFO;
824 } else if (cmd->start_src == TRIG_EXT &&
825 cmd->scan_begin_src == TRIG_EXT &&
826 cmd->convert_src == TRIG_TIMER) {
827 tmp = ME4000_AI_CTRL_BIT_MODE_2 |
828 ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
829 ME4000_AI_CTRL_BIT_DATA_FIFO;
830 } else if (cmd->start_src == TRIG_EXT &&
831 cmd->scan_begin_src == TRIG_EXT &&
832 cmd->convert_src == TRIG_EXT) {
833 tmp = ME4000_AI_CTRL_BIT_MODE_0 |
834 ME4000_AI_CTRL_BIT_MODE_1 |
835 ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
836 ME4000_AI_CTRL_BIT_DATA_FIFO;
838 tmp = ME4000_AI_CTRL_BIT_MODE_0 |
839 ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
840 ME4000_AI_CTRL_BIT_DATA_FIFO;
844 if (cmd->stop_src == TRIG_COUNT) {
845 outl(cmd->chanlist_len * cmd->stop_arg,
846 dev->iobase + ME4000_AI_SAMPLE_COUNTER_REG);
847 tmp |= ME4000_AI_CTRL_BIT_HF_IRQ | ME4000_AI_CTRL_BIT_SC_IRQ;
848 } else if (cmd->stop_src == TRIG_NONE &&
849 cmd->scan_end_src == TRIG_COUNT) {
850 outl(cmd->scan_end_arg,
851 dev->iobase + ME4000_AI_SAMPLE_COUNTER_REG);
852 tmp |= ME4000_AI_CTRL_BIT_HF_IRQ | ME4000_AI_CTRL_BIT_SC_IRQ;
854 tmp |= ME4000_AI_CTRL_BIT_HF_IRQ;
857 /* Write the setup to the control register */
858 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
860 /* Write the channel list */
861 ai_write_chanlist(dev, s, cmd);
866 static int me4000_ai_do_cmd(struct comedi_device *dev,
867 struct comedi_subdevice *s)
870 unsigned int init_ticks = 0;
871 unsigned int scan_ticks = 0;
872 unsigned int chan_ticks = 0;
873 struct comedi_cmd *cmd = &s->async->cmd;
875 /* Reset the analog input */
876 err = me4000_ai_cancel(dev, s);
880 /* Round the timer arguments */
881 err = ai_round_cmd_args(dev,
882 s, cmd, &init_ticks, &scan_ticks, &chan_ticks);
886 /* Prepare the AI for acquisition */
887 err = ai_prepare(dev, s, cmd, init_ticks, scan_ticks, chan_ticks);
891 /* Start acquistion by dummy read */
892 inl(dev->iobase + ME4000_AI_START_REG);
897 static int me4000_ai_do_cmd_test(struct comedi_device *dev,
898 struct comedi_subdevice *s,
899 struct comedi_cmd *cmd)
902 unsigned int init_ticks;
903 unsigned int chan_ticks;
904 unsigned int scan_ticks;
907 /* Only rounding flags are implemented */
908 cmd->flags &= TRIG_ROUND_NEAREST | TRIG_ROUND_UP | TRIG_ROUND_DOWN;
910 /* Round the timer arguments */
911 ai_round_cmd_args(dev, s, cmd, &init_ticks, &scan_ticks, &chan_ticks);
913 /* Step 1 : check if triggers are trivially valid */
915 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
916 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
917 TRIG_FOLLOW | TRIG_TIMER | TRIG_EXT);
918 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_TIMER | TRIG_EXT);
919 err |= cfc_check_trigger_src(&cmd->scan_end_src,
920 TRIG_NONE | TRIG_COUNT);
921 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE | TRIG_COUNT);
926 /* Step 2a : make sure trigger sources are unique */
928 err |= cfc_check_trigger_is_unique(cmd->start_src);
929 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
930 err |= cfc_check_trigger_is_unique(cmd->convert_src);
931 err |= cfc_check_trigger_is_unique(cmd->scan_end_src);
932 err |= cfc_check_trigger_is_unique(cmd->stop_src);
934 /* Step 2b : and mutually compatible */
936 if (cmd->start_src == TRIG_NOW &&
937 cmd->scan_begin_src == TRIG_TIMER &&
938 cmd->convert_src == TRIG_TIMER) {
939 } else if (cmd->start_src == TRIG_NOW &&
940 cmd->scan_begin_src == TRIG_FOLLOW &&
941 cmd->convert_src == TRIG_TIMER) {
942 } else if (cmd->start_src == TRIG_EXT &&
943 cmd->scan_begin_src == TRIG_TIMER &&
944 cmd->convert_src == TRIG_TIMER) {
945 } else if (cmd->start_src == TRIG_EXT &&
946 cmd->scan_begin_src == TRIG_FOLLOW &&
947 cmd->convert_src == TRIG_TIMER) {
948 } else if (cmd->start_src == TRIG_EXT &&
949 cmd->scan_begin_src == TRIG_EXT &&
950 cmd->convert_src == TRIG_TIMER) {
951 } else if (cmd->start_src == TRIG_EXT &&
952 cmd->scan_begin_src == TRIG_EXT &&
953 cmd->convert_src == TRIG_EXT) {
958 if (cmd->stop_src == TRIG_NONE && cmd->scan_end_src == TRIG_NONE) {
959 } else if (cmd->stop_src == TRIG_COUNT &&
960 cmd->scan_end_src == TRIG_NONE) {
961 } else if (cmd->stop_src == TRIG_NONE &&
962 cmd->scan_end_src == TRIG_COUNT) {
963 } else if (cmd->stop_src == TRIG_COUNT &&
964 cmd->scan_end_src == TRIG_COUNT) {
972 /* Step 3: check if arguments are trivially valid */
974 if (cmd->chanlist_len < 1) {
975 cmd->chanlist_len = 1;
978 if (init_ticks < 66) {
979 cmd->start_arg = 2000;
982 if (scan_ticks && scan_ticks < 67) {
983 cmd->scan_begin_arg = 2031;
986 if (chan_ticks < 66) {
987 cmd->convert_arg = 2000;
995 * Stage 4. Check for argument conflicts.
997 if (cmd->start_src == TRIG_NOW &&
998 cmd->scan_begin_src == TRIG_TIMER &&
999 cmd->convert_src == TRIG_TIMER) {
1001 /* Check timer arguments */
1002 if (init_ticks < ME4000_AI_MIN_TICKS) {
1003 dev_err(dev->class_dev, "Invalid start arg\n");
1004 cmd->start_arg = 2000; /* 66 ticks at least */
1007 if (chan_ticks < ME4000_AI_MIN_TICKS) {
1008 dev_err(dev->class_dev, "Invalid convert arg\n");
1009 cmd->convert_arg = 2000; /* 66 ticks at least */
1012 if (scan_ticks <= cmd->chanlist_len * chan_ticks) {
1013 dev_err(dev->class_dev, "Invalid scan end arg\n");
1015 /* At least one tick more */
1016 cmd->scan_end_arg = 2000 * cmd->chanlist_len + 31;
1019 } else if (cmd->start_src == TRIG_NOW &&
1020 cmd->scan_begin_src == TRIG_FOLLOW &&
1021 cmd->convert_src == TRIG_TIMER) {
1023 /* Check timer arguments */
1024 if (init_ticks < ME4000_AI_MIN_TICKS) {
1025 dev_err(dev->class_dev, "Invalid start arg\n");
1026 cmd->start_arg = 2000; /* 66 ticks at least */
1029 if (chan_ticks < ME4000_AI_MIN_TICKS) {
1030 dev_err(dev->class_dev, "Invalid convert arg\n");
1031 cmd->convert_arg = 2000; /* 66 ticks at least */
1034 } else if (cmd->start_src == TRIG_EXT &&
1035 cmd->scan_begin_src == TRIG_TIMER &&
1036 cmd->convert_src == TRIG_TIMER) {
1038 /* Check timer arguments */
1039 if (init_ticks < ME4000_AI_MIN_TICKS) {
1040 dev_err(dev->class_dev, "Invalid start arg\n");
1041 cmd->start_arg = 2000; /* 66 ticks at least */
1044 if (chan_ticks < ME4000_AI_MIN_TICKS) {
1045 dev_err(dev->class_dev, "Invalid convert arg\n");
1046 cmd->convert_arg = 2000; /* 66 ticks at least */
1049 if (scan_ticks <= cmd->chanlist_len * chan_ticks) {
1050 dev_err(dev->class_dev, "Invalid scan end arg\n");
1052 /* At least one tick more */
1053 cmd->scan_end_arg = 2000 * cmd->chanlist_len + 31;
1056 } else if (cmd->start_src == TRIG_EXT &&
1057 cmd->scan_begin_src == TRIG_FOLLOW &&
1058 cmd->convert_src == TRIG_TIMER) {
1060 /* Check timer arguments */
1061 if (init_ticks < ME4000_AI_MIN_TICKS) {
1062 dev_err(dev->class_dev, "Invalid start arg\n");
1063 cmd->start_arg = 2000; /* 66 ticks at least */
1066 if (chan_ticks < ME4000_AI_MIN_TICKS) {
1067 dev_err(dev->class_dev, "Invalid convert arg\n");
1068 cmd->convert_arg = 2000; /* 66 ticks at least */
1071 } else if (cmd->start_src == TRIG_EXT &&
1072 cmd->scan_begin_src == TRIG_EXT &&
1073 cmd->convert_src == TRIG_TIMER) {
1075 /* Check timer arguments */
1076 if (init_ticks < ME4000_AI_MIN_TICKS) {
1077 dev_err(dev->class_dev, "Invalid start arg\n");
1078 cmd->start_arg = 2000; /* 66 ticks at least */
1081 if (chan_ticks < ME4000_AI_MIN_TICKS) {
1082 dev_err(dev->class_dev, "Invalid convert arg\n");
1083 cmd->convert_arg = 2000; /* 66 ticks at least */
1086 } else if (cmd->start_src == TRIG_EXT &&
1087 cmd->scan_begin_src == TRIG_EXT &&
1088 cmd->convert_src == TRIG_EXT) {
1090 /* Check timer arguments */
1091 if (init_ticks < ME4000_AI_MIN_TICKS) {
1092 dev_err(dev->class_dev, "Invalid start arg\n");
1093 cmd->start_arg = 2000; /* 66 ticks at least */
1097 if (cmd->stop_src == TRIG_COUNT) {
1098 if (cmd->stop_arg == 0) {
1099 dev_err(dev->class_dev, "Invalid stop arg\n");
1104 if (cmd->scan_end_src == TRIG_COUNT) {
1105 if (cmd->scan_end_arg == 0) {
1106 dev_err(dev->class_dev, "Invalid scan end arg\n");
1107 cmd->scan_end_arg = 1;
1116 * Stage 5. Check the channel list.
1118 if (ai_check_chanlist(dev, s, cmd))
1124 static irqreturn_t me4000_ai_isr(int irq, void *dev_id)
1127 struct comedi_device *dev = dev_id;
1128 struct comedi_subdevice *s = &dev->subdevices[0];
1136 /* Reset all events */
1137 s->async->events = 0;
1139 /* Check if irq number is right */
1140 if (irq != dev->irq) {
1141 dev_err(dev->class_dev, "Incorrect interrupt num: %d\n", irq);
1145 if (inl(dev->iobase + ME4000_IRQ_STATUS_REG) &
1146 ME4000_IRQ_STATUS_BIT_AI_HF) {
1147 /* Read status register to find out what happened */
1148 tmp = inl(dev->iobase + ME4000_AI_CTRL_REG);
1150 if (!(tmp & ME4000_AI_STATUS_BIT_FF_DATA) &&
1151 !(tmp & ME4000_AI_STATUS_BIT_HF_DATA) &&
1152 (tmp & ME4000_AI_STATUS_BIT_EF_DATA)) {
1153 c = ME4000_AI_FIFO_COUNT;
1156 * FIFO overflow, so stop conversion
1157 * and disable all interrupts
1159 tmp |= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP;
1160 tmp &= ~(ME4000_AI_CTRL_BIT_HF_IRQ |
1161 ME4000_AI_CTRL_BIT_SC_IRQ);
1162 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1164 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1166 dev_err(dev->class_dev, "FIFO overflow\n");
1167 } else if ((tmp & ME4000_AI_STATUS_BIT_FF_DATA)
1168 && !(tmp & ME4000_AI_STATUS_BIT_HF_DATA)
1169 && (tmp & ME4000_AI_STATUS_BIT_EF_DATA)) {
1170 s->async->events |= COMEDI_CB_BLOCK;
1172 c = ME4000_AI_FIFO_COUNT / 2;
1174 dev_err(dev->class_dev,
1175 "Can't determine state of fifo\n");
1179 * Undefined state, so stop conversion
1180 * and disable all interrupts
1182 tmp |= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP;
1183 tmp &= ~(ME4000_AI_CTRL_BIT_HF_IRQ |
1184 ME4000_AI_CTRL_BIT_SC_IRQ);
1185 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1187 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1189 dev_err(dev->class_dev, "Undefined FIFO state\n");
1192 for (i = 0; i < c; i++) {
1193 /* Read value from data fifo */
1194 lval = inl(dev->iobase + ME4000_AI_DATA_REG) & 0xFFFF;
1197 if (!comedi_buf_put(s->async, lval)) {
1199 * Buffer overflow, so stop conversion
1200 * and disable all interrupts
1202 tmp |= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP;
1203 tmp &= ~(ME4000_AI_CTRL_BIT_HF_IRQ |
1204 ME4000_AI_CTRL_BIT_SC_IRQ);
1205 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1207 s->async->events |= COMEDI_CB_OVERFLOW;
1209 dev_err(dev->class_dev, "Buffer overflow\n");
1215 /* Work is done, so reset the interrupt */
1216 tmp |= ME4000_AI_CTRL_BIT_HF_IRQ_RESET;
1217 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1218 tmp &= ~ME4000_AI_CTRL_BIT_HF_IRQ_RESET;
1219 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1222 if (inl(dev->iobase + ME4000_IRQ_STATUS_REG) &
1223 ME4000_IRQ_STATUS_BIT_SC) {
1224 s->async->events |= COMEDI_CB_BLOCK | COMEDI_CB_EOA;
1227 * Acquisition is complete, so stop
1228 * conversion and disable all interrupts
1230 tmp = inl(dev->iobase + ME4000_AI_CTRL_REG);
1231 tmp |= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP;
1232 tmp &= ~(ME4000_AI_CTRL_BIT_HF_IRQ | ME4000_AI_CTRL_BIT_SC_IRQ);
1233 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1235 /* Poll data until fifo empty */
1236 while (inl(dev->iobase + ME4000_AI_CTRL_REG) &
1237 ME4000_AI_STATUS_BIT_EF_DATA) {
1238 /* Read value from data fifo */
1239 lval = inl(dev->iobase + ME4000_AI_DATA_REG) & 0xFFFF;
1242 if (!comedi_buf_put(s->async, lval)) {
1243 dev_err(dev->class_dev, "Buffer overflow\n");
1244 s->async->events |= COMEDI_CB_OVERFLOW;
1249 /* Work is done, so reset the interrupt */
1250 tmp |= ME4000_AI_CTRL_BIT_SC_IRQ_RESET;
1251 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1252 tmp &= ~ME4000_AI_CTRL_BIT_SC_IRQ_RESET;
1253 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1256 if (s->async->events)
1257 comedi_event(dev, s);
1262 /*=============================================================================
1263 Analog output section
1264 ===========================================================================*/
1266 static int me4000_ao_insn_write(struct comedi_device *dev,
1267 struct comedi_subdevice *s,
1268 struct comedi_insn *insn, unsigned int *data)
1270 const struct me4000_board *thisboard = comedi_board(dev);
1271 struct me4000_info *info = dev->private;
1272 int chan = CR_CHAN(insn->chanspec);
1273 int rang = CR_RANGE(insn->chanspec);
1274 int aref = CR_AREF(insn->chanspec);
1279 } else if (insn->n > 1) {
1280 dev_err(dev->class_dev, "Invalid instruction length %d\n",
1285 if (chan >= thisboard->ao_nchan) {
1286 dev_err(dev->class_dev, "Invalid channel %d\n", insn->n);
1291 dev_err(dev->class_dev, "Invalid range %d\n", insn->n);
1295 if (aref != AREF_GROUND && aref != AREF_COMMON) {
1296 dev_err(dev->class_dev, "Invalid aref %d\n", insn->n);
1300 /* Stop any running conversion */
1301 tmp = inl(dev->iobase + ME4000_AO_CTRL_REG(chan));
1302 tmp |= ME4000_AO_CTRL_BIT_IMMEDIATE_STOP;
1303 outl(tmp, dev->iobase + ME4000_AO_CTRL_REG(chan));
1305 /* Clear control register and set to single mode */
1306 outl(0x0, dev->iobase + ME4000_AO_CTRL_REG(chan));
1308 /* Write data value */
1309 outl(data[0], dev->iobase + ME4000_AO_SINGLE_REG(chan));
1311 /* Store in the mirror */
1312 info->ao_readback[chan] = data[0];
1317 static int me4000_ao_insn_read(struct comedi_device *dev,
1318 struct comedi_subdevice *s,
1319 struct comedi_insn *insn, unsigned int *data)
1321 struct me4000_info *info = dev->private;
1322 int chan = CR_CHAN(insn->chanspec);
1326 } else if (insn->n > 1) {
1327 dev_err(dev->class_dev, "Invalid instruction length\n");
1331 data[0] = info->ao_readback[chan];
1336 /*=============================================================================
1338 ===========================================================================*/
1340 static int me4000_dio_insn_bits(struct comedi_device *dev,
1341 struct comedi_subdevice *s,
1342 struct comedi_insn *insn, unsigned int *data)
1345 * The insn data consists of a mask in data[0] and the new data
1346 * in data[1]. The mask defines which bits we are concerning about.
1347 * The new data must be anded with the mask.
1348 * Each channel corresponds to a bit.
1351 /* Check if requested ports are configured for output */
1352 if ((s->io_bits & data[0]) != data[0])
1355 s->state &= ~data[0];
1356 s->state |= data[0] & data[1];
1358 /* Write out the new digital output lines */
1359 outl((s->state >> 0) & 0xFF,
1360 dev->iobase + ME4000_DIO_PORT_0_REG);
1361 outl((s->state >> 8) & 0xFF,
1362 dev->iobase + ME4000_DIO_PORT_1_REG);
1363 outl((s->state >> 16) & 0xFF,
1364 dev->iobase + ME4000_DIO_PORT_2_REG);
1365 outl((s->state >> 24) & 0xFF,
1366 dev->iobase + ME4000_DIO_PORT_3_REG);
1369 /* On return, data[1] contains the value of
1370 the digital input and output lines. */
1371 data[1] = ((inl(dev->iobase + ME4000_DIO_PORT_0_REG) & 0xFF) << 0) |
1372 ((inl(dev->iobase + ME4000_DIO_PORT_1_REG) & 0xFF) << 8) |
1373 ((inl(dev->iobase + ME4000_DIO_PORT_2_REG) & 0xFF) << 16) |
1374 ((inl(dev->iobase + ME4000_DIO_PORT_3_REG) & 0xFF) << 24);
1379 static int me4000_dio_insn_config(struct comedi_device *dev,
1380 struct comedi_subdevice *s,
1381 struct comedi_insn *insn, unsigned int *data)
1384 int chan = CR_CHAN(insn->chanspec);
1389 case INSN_CONFIG_DIO_QUERY:
1391 (s->io_bits & (1 << chan)) ? COMEDI_OUTPUT : COMEDI_INPUT;
1393 case INSN_CONFIG_DIO_INPUT:
1394 case INSN_CONFIG_DIO_OUTPUT:
1399 * The input or output configuration of each digital line is
1400 * configured by a special insn_config instruction. chanspec
1401 * contains the channel to be changed, and data[0] contains the
1402 * value INSN_CONFIG_DIO_INPUT or INSN_CONFIG_DIO_OUTPUT.
1403 * On the ME-4000 it is only possible to switch port wise (8 bit)
1406 tmp = inl(dev->iobase + ME4000_DIO_CTRL_REG);
1408 if (data[0] == INSN_CONFIG_DIO_OUTPUT) {
1411 tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_0 |
1412 ME4000_DIO_CTRL_BIT_MODE_1);
1413 tmp |= ME4000_DIO_CTRL_BIT_MODE_0;
1414 } else if (chan < 16) {
1416 * Chech for optoisolated ME-4000 version.
1417 * If one the first port is a fixed output
1418 * port and the second is a fixed input port.
1420 if (!inl(dev->iobase + ME4000_DIO_DIR_REG))
1423 s->io_bits |= 0xFF00;
1424 tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_2 |
1425 ME4000_DIO_CTRL_BIT_MODE_3);
1426 tmp |= ME4000_DIO_CTRL_BIT_MODE_2;
1427 } else if (chan < 24) {
1428 s->io_bits |= 0xFF0000;
1429 tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_4 |
1430 ME4000_DIO_CTRL_BIT_MODE_5);
1431 tmp |= ME4000_DIO_CTRL_BIT_MODE_4;
1432 } else if (chan < 32) {
1433 s->io_bits |= 0xFF000000;
1434 tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_6 |
1435 ME4000_DIO_CTRL_BIT_MODE_7);
1436 tmp |= ME4000_DIO_CTRL_BIT_MODE_6;
1443 * Chech for optoisolated ME-4000 version.
1444 * If one the first port is a fixed output
1445 * port and the second is a fixed input port.
1447 if (!inl(dev->iobase + ME4000_DIO_DIR_REG))
1450 s->io_bits &= ~0xFF;
1451 tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_0 |
1452 ME4000_DIO_CTRL_BIT_MODE_1);
1453 } else if (chan < 16) {
1454 s->io_bits &= ~0xFF00;
1455 tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_2 |
1456 ME4000_DIO_CTRL_BIT_MODE_3);
1457 } else if (chan < 24) {
1458 s->io_bits &= ~0xFF0000;
1459 tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_4 |
1460 ME4000_DIO_CTRL_BIT_MODE_5);
1461 } else if (chan < 32) {
1462 s->io_bits &= ~0xFF000000;
1463 tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_6 |
1464 ME4000_DIO_CTRL_BIT_MODE_7);
1470 outl(tmp, dev->iobase + ME4000_DIO_CTRL_REG);
1475 /*=============================================================================
1477 ===========================================================================*/
1479 static int me4000_cnt_insn_config(struct comedi_device *dev,
1480 struct comedi_subdevice *s,
1481 struct comedi_insn *insn,
1484 struct me4000_info *info = dev->private;
1492 err = i8254_load(info->timer_regbase, 0, insn->chanspec, 0,
1493 I8254_MODE0 | I8254_BINARY);
1497 case GPCT_SET_OPERATION:
1501 err = i8254_set_mode(info->timer_regbase, 0, insn->chanspec,
1502 (data[1] << 1) | I8254_BINARY);
1513 static int me4000_cnt_insn_read(struct comedi_device *dev,
1514 struct comedi_subdevice *s,
1515 struct comedi_insn *insn, unsigned int *data)
1517 struct me4000_info *info = dev->private;
1523 dev_err(dev->class_dev, "Invalid instruction length %d\n",
1528 data[0] = i8254_read(info->timer_regbase, 0, insn->chanspec);
1533 static int me4000_cnt_insn_write(struct comedi_device *dev,
1534 struct comedi_subdevice *s,
1535 struct comedi_insn *insn, unsigned int *data)
1537 struct me4000_info *info = dev->private;
1541 } else if (insn->n > 1) {
1542 dev_err(dev->class_dev, "Invalid instruction length %d\n",
1547 i8254_write(info->timer_regbase, 0, insn->chanspec, data[0]);
1552 static const void *me4000_find_boardinfo(struct comedi_device *dev,
1553 struct pci_dev *pcidev)
1555 const struct me4000_board *thisboard;
1558 for (i = 0; i < ARRAY_SIZE(me4000_boards); i++) {
1559 thisboard = &me4000_boards[i];
1560 if (thisboard->device_id == pcidev->device)
1566 static int me4000_auto_attach(struct comedi_device *dev,
1567 unsigned long context_unused)
1569 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1570 const struct me4000_board *thisboard;
1571 struct me4000_info *info;
1572 struct comedi_subdevice *s;
1575 thisboard = me4000_find_boardinfo(dev, pcidev);
1578 dev->board_ptr = thisboard;
1579 dev->board_name = thisboard->name;
1581 info = kzalloc(sizeof(*info), GFP_KERNEL);
1584 dev->private = info;
1586 result = comedi_pci_enable(pcidev, dev->board_name);
1590 info->plx_regbase = pci_resource_start(pcidev, 1);
1591 dev->iobase = pci_resource_start(pcidev, 2);
1592 info->timer_regbase = pci_resource_start(pcidev, 3);
1593 if (!info->plx_regbase || !dev->iobase || !info->timer_regbase)
1596 result = xilinx_download(dev);
1602 result = comedi_alloc_subdevices(dev, 4);
1606 /*=========================================================================
1607 Analog input subdevice
1608 ========================================================================*/
1610 s = &dev->subdevices[0];
1612 if (thisboard->ai_nchan) {
1613 s->type = COMEDI_SUBD_AI;
1615 SDF_READABLE | SDF_COMMON | SDF_GROUND | SDF_DIFF;
1616 s->n_chan = thisboard->ai_nchan;
1617 s->maxdata = 0xFFFF; /* 16 bit ADC */
1618 s->len_chanlist = ME4000_AI_CHANNEL_LIST_COUNT;
1619 s->range_table = &me4000_ai_range;
1620 s->insn_read = me4000_ai_insn_read;
1622 if (pcidev->irq > 0) {
1623 if (request_irq(pcidev->irq, me4000_ai_isr,
1624 IRQF_SHARED, dev->board_name, dev)) {
1625 dev_warn(dev->class_dev,
1626 "request_irq failed\n");
1628 dev->read_subdev = s;
1629 s->subdev_flags |= SDF_CMD_READ;
1630 s->cancel = me4000_ai_cancel;
1631 s->do_cmdtest = me4000_ai_do_cmd_test;
1632 s->do_cmd = me4000_ai_do_cmd;
1634 dev->irq = pcidev->irq;
1637 dev_warn(dev->class_dev, "No interrupt available\n");
1640 s->type = COMEDI_SUBD_UNUSED;
1643 /*=========================================================================
1644 Analog output subdevice
1645 ========================================================================*/
1647 s = &dev->subdevices[1];
1649 if (thisboard->ao_nchan) {
1650 s->type = COMEDI_SUBD_AO;
1651 s->subdev_flags = SDF_WRITEABLE | SDF_COMMON | SDF_GROUND;
1652 s->n_chan = thisboard->ao_nchan;
1653 s->maxdata = 0xFFFF; /* 16 bit DAC */
1654 s->range_table = &range_bipolar10;
1655 s->insn_write = me4000_ao_insn_write;
1656 s->insn_read = me4000_ao_insn_read;
1658 s->type = COMEDI_SUBD_UNUSED;
1661 /*=========================================================================
1662 Digital I/O subdevice
1663 ========================================================================*/
1665 s = &dev->subdevices[2];
1667 if (thisboard->dio_nchan) {
1668 s->type = COMEDI_SUBD_DIO;
1669 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1670 s->n_chan = thisboard->dio_nchan;
1672 s->range_table = &range_digital;
1673 s->insn_bits = me4000_dio_insn_bits;
1674 s->insn_config = me4000_dio_insn_config;
1676 s->type = COMEDI_SUBD_UNUSED;
1680 * Check for optoisolated ME-4000 version. If one the first
1681 * port is a fixed output port and the second is a fixed input port.
1683 if (!inl(dev->iobase + ME4000_DIO_DIR_REG)) {
1685 outl(ME4000_DIO_CTRL_BIT_MODE_0,
1686 dev->iobase + ME4000_DIO_DIR_REG);
1689 /*=========================================================================
1691 ========================================================================*/
1693 s = &dev->subdevices[3];
1695 if (thisboard->has_counter) {
1696 s->type = COMEDI_SUBD_COUNTER;
1697 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1699 s->maxdata = 0xFFFF; /* 16 bit counters */
1700 s->insn_read = me4000_cnt_insn_read;
1701 s->insn_write = me4000_cnt_insn_write;
1702 s->insn_config = me4000_cnt_insn_config;
1704 s->type = COMEDI_SUBD_UNUSED;
1710 static void me4000_detach(struct comedi_device *dev)
1712 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1715 free_irq(dev->irq, dev);
1719 comedi_pci_disable(pcidev);
1724 static struct comedi_driver me4000_driver = {
1725 .driver_name = "me4000",
1726 .module = THIS_MODULE,
1727 .auto_attach = me4000_auto_attach,
1728 .detach = me4000_detach,
1731 static int me4000_pci_probe(struct pci_dev *dev,
1732 const struct pci_device_id *ent)
1734 return comedi_pci_auto_config(dev, &me4000_driver);
1737 static void me4000_pci_remove(struct pci_dev *dev)
1739 comedi_pci_auto_unconfig(dev);
1742 static DEFINE_PCI_DEVICE_TABLE(me4000_pci_table) = {
1743 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4650)},
1744 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4660)},
1745 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4660I)},
1746 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4660S)},
1747 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4660IS)},
1748 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4670)},
1749 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4670I)},
1750 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4670S)},
1751 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4670IS)},
1752 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4680)},
1753 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4680I)},
1754 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4680S)},
1755 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4680IS)},
1758 MODULE_DEVICE_TABLE(pci, me4000_pci_table);
1760 static struct pci_driver me4000_pci_driver = {
1762 .id_table = me4000_pci_table,
1763 .probe = me4000_pci_probe,
1764 .remove = me4000_pci_remove,
1766 module_comedi_pci_driver(me4000_driver, me4000_pci_driver);
1768 MODULE_AUTHOR("Comedi http://www.comedi.org");
1769 MODULE_DESCRIPTION("Comedi low-level driver");
1770 MODULE_LICENSE("GPL");