2 * comedi/drivers/me_daq.c
3 * Hardware driver for Meilhaus data acquisition cards:
4 * ME-2000i, ME-2600i, ME-3000vm1
6 * Copyright (C) 2002 Michael Hillmann <hillmann@syscongroup.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 * Description: Meilhaus PCI data acquisition cards
26 * Devices: (Meilhaus) ME-2600i [me-2600i]
27 * (Meilhaus) ME-2000i [me-2000i]
28 * Author: Michael Hillmann <hillmann@syscongroup.de>
29 * Status: experimental
31 * Configuration options: not applicable, uses PCI auto config
34 * Analog Input, Analog Output, Digital I/O
37 #include <linux/pci.h>
38 #include <linux/interrupt.h>
39 #include <linux/sched.h>
40 #include <linux/firmware.h>
42 #include "../comedidev.h"
44 #define ME2600_FIRMWARE "me2600_firmware.bin"
46 #define ME2000_DEVICE_ID 0x2000
47 #define ME2600_DEVICE_ID 0x2600
49 #define PLX_INTCSR 0x4C /* PLX interrupt status register */
50 #define XILINX_DOWNLOAD_RESET 0x42 /* Xilinx registers */
52 #define ME_CONTROL_1 0x0000 /* - | W */
53 #define INTERRUPT_ENABLE (1<<15)
54 #define COUNTER_B_IRQ (1<<12)
55 #define COUNTER_A_IRQ (1<<11)
56 #define CHANLIST_READY_IRQ (1<<10)
57 #define EXT_IRQ (1<<9)
58 #define ADFIFO_HALFFULL_IRQ (1<<8)
59 #define SCAN_COUNT_ENABLE (1<<5)
60 #define SIMULTANEOUS_ENABLE (1<<4)
61 #define TRIGGER_FALLING_EDGE (1<<3)
62 #define CONTINUOUS_MODE (1<<2)
63 #define DISABLE_ADC (0<<0)
64 #define SOFTWARE_TRIGGERED_ADC (1<<0)
65 #define SCAN_TRIGGERED_ADC (2<<0)
66 #define EXT_TRIGGERED_ADC (3<<0)
67 #define ME_ADC_START 0x0000 /* R | - */
68 #define ME_CONTROL_2 0x0002 /* - | W */
69 #define ENABLE_ADFIFO (1<<10)
70 #define ENABLE_CHANLIST (1<<9)
71 #define ENABLE_PORT_B (1<<7)
72 #define ENABLE_PORT_A (1<<6)
73 #define ENABLE_COUNTER_B (1<<4)
74 #define ENABLE_COUNTER_A (1<<3)
75 #define ENABLE_DAC (1<<1)
76 #define BUFFERED_DAC (1<<0)
77 #define ME_DAC_UPDATE 0x0002 /* R | - */
78 #define ME_STATUS 0x0004 /* R | - */
79 #define COUNTER_B_IRQ_PENDING (1<<12)
80 #define COUNTER_A_IRQ_PENDING (1<<11)
81 #define CHANLIST_READY_IRQ_PENDING (1<<10)
82 #define EXT_IRQ_PENDING (1<<9)
83 #define ADFIFO_HALFFULL_IRQ_PENDING (1<<8)
84 #define ADFIFO_FULL (1<<4)
85 #define ADFIFO_HALFFULL (1<<3)
86 #define ADFIFO_EMPTY (1<<2)
87 #define CHANLIST_FULL (1<<1)
88 #define FST_ACTIVE (1<<0)
89 #define ME_RESET_INTERRUPT 0x0004 /* - | W */
90 #define ME_DIO_PORT_A 0x0006 /* R | W */
91 #define ME_DIO_PORT_B 0x0008 /* R | W */
92 #define ME_TIMER_DATA_0 0x000A /* - | W */
93 #define ME_TIMER_DATA_1 0x000C /* - | W */
94 #define ME_TIMER_DATA_2 0x000E /* - | W */
95 #define ME_CHANNEL_LIST 0x0010 /* - | W */
96 #define ADC_UNIPOLAR (1<<6)
97 #define ADC_GAIN_0 (0<<4)
98 #define ADC_GAIN_1 (1<<4)
99 #define ADC_GAIN_2 (2<<4)
100 #define ADC_GAIN_3 (3<<4)
101 #define ME_READ_AD_FIFO 0x0010 /* R | - */
102 #define ME_DAC_CONTROL 0x0012 /* - | W */
103 #define DAC_UNIPOLAR_D (0<<4)
104 #define DAC_BIPOLAR_D (1<<4)
105 #define DAC_UNIPOLAR_C (0<<5)
106 #define DAC_BIPOLAR_C (1<<5)
107 #define DAC_UNIPOLAR_B (0<<6)
108 #define DAC_BIPOLAR_B (1<<6)
109 #define DAC_UNIPOLAR_A (0<<7)
110 #define DAC_BIPOLAR_A (1<<7)
111 #define DAC_GAIN_0_D (0<<8)
112 #define DAC_GAIN_1_D (1<<8)
113 #define DAC_GAIN_0_C (0<<9)
114 #define DAC_GAIN_1_C (1<<9)
115 #define DAC_GAIN_0_B (0<<10)
116 #define DAC_GAIN_1_B (1<<10)
117 #define DAC_GAIN_0_A (0<<11)
118 #define DAC_GAIN_1_A (1<<11)
119 #define ME_DAC_CONTROL_UPDATE 0x0012 /* R | - */
120 #define ME_DAC_DATA_A 0x0014 /* - | W */
121 #define ME_DAC_DATA_B 0x0016 /* - | W */
122 #define ME_DAC_DATA_C 0x0018 /* - | W */
123 #define ME_DAC_DATA_D 0x001A /* - | W */
124 #define ME_COUNTER_ENDDATA_A 0x001C /* - | W */
125 #define ME_COUNTER_ENDDATA_B 0x001E /* - | W */
126 #define ME_COUNTER_STARTDATA_A 0x0020 /* - | W */
127 #define ME_COUNTER_VALUE_A 0x0020 /* R | - */
128 #define ME_COUNTER_STARTDATA_B 0x0022 /* - | W */
129 #define ME_COUNTER_VALUE_B 0x0022 /* R | - */
131 static const struct comedi_lrange me_ai_range = {
144 static const struct comedi_lrange me_ao_range = {
158 static const struct me_board me_boards[] = {
161 .device_id = ME2600_DEVICE_ID,
165 .device_id = ME2000_DEVICE_ID,
169 struct me_private_data {
170 void __iomem *plx_regbase; /* PLX configuration base address */
171 void __iomem *me_regbase; /* Base address of the Meilhaus card */
173 unsigned short control_1; /* Mirror of CONTROL_1 register */
174 unsigned short control_2; /* Mirror of CONTROL_2 register */
175 unsigned short dac_control; /* Mirror of the DAC_CONTROL register */
176 int ao_readback[4]; /* Mirror of analog output data */
179 static inline void sleep(unsigned sec)
181 current->state = TASK_INTERRUPTIBLE;
182 schedule_timeout(sec * HZ);
185 static int me_dio_insn_config(struct comedi_device *dev,
186 struct comedi_subdevice *s,
187 struct comedi_insn *insn,
190 struct me_private_data *dev_private = dev->private;
191 unsigned int mask = 1 << CR_CHAN(insn->chanspec);
195 if (mask & 0x0000ffff) {
197 port = ENABLE_PORT_A;
200 port = ENABLE_PORT_B;
204 case INSN_CONFIG_DIO_INPUT:
206 dev_private->control_2 &= ~port;
208 case INSN_CONFIG_DIO_OUTPUT:
210 dev_private->control_2 |= port;
212 case INSN_CONFIG_DIO_QUERY:
213 data[1] = (s->io_bits & bits) ? COMEDI_OUTPUT : COMEDI_INPUT;
220 /* Update the port configuration */
221 writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
226 static int me_dio_insn_bits(struct comedi_device *dev,
227 struct comedi_subdevice *s,
228 struct comedi_insn *insn,
231 struct me_private_data *dev_private = dev->private;
232 void __iomem *mmio_porta = dev_private->me_regbase + ME_DIO_PORT_A;
233 void __iomem *mmio_portb = dev_private->me_regbase + ME_DIO_PORT_B;
234 unsigned int mask = data[0];
235 unsigned int bits = data[1];
238 mask &= s->io_bits; /* only update the COMEDI_OUTPUT channels */
241 s->state |= (bits & mask);
243 if (mask & 0x0000ffff)
244 writew((s->state & 0xffff), mmio_porta);
245 if (mask & 0xffff0000)
246 writew(((s->state >> 16) & 0xffff), mmio_portb);
249 if (s->io_bits & 0x0000ffff)
250 val = s->state & 0xffff;
252 val = readw(mmio_porta);
254 if (s->io_bits & 0xffff0000)
255 val |= (s->state & 0xffff0000);
257 val |= (readw(mmio_portb) << 16);
264 static int me_ai_insn_read(struct comedi_device *dev,
265 struct comedi_subdevice *s,
266 struct comedi_insn *insn,
269 struct me_private_data *dev_private = dev->private;
270 unsigned int chan = CR_CHAN(insn->chanspec);
271 unsigned int rang = CR_RANGE(insn->chanspec);
272 unsigned int aref = CR_AREF(insn->chanspec);
276 /* stop any running conversion */
277 dev_private->control_1 &= 0xFFFC;
278 writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
280 /* clear chanlist and ad fifo */
281 dev_private->control_2 &= ~(ENABLE_ADFIFO | ENABLE_CHANLIST);
282 writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
284 /* reset any pending interrupt */
285 writew(0x00, dev_private->me_regbase + ME_RESET_INTERRUPT);
287 /* enable the chanlist and ADC fifo */
288 dev_private->control_2 |= (ENABLE_ADFIFO | ENABLE_CHANLIST);
289 writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
291 /* write to channel list fifo */
292 val = chan & 0x0f; /* b3:b0 channel */
293 val |= (rang & 0x03) << 4; /* b5:b4 gain */
294 val |= (rang & 0x04) << 4; /* b6 polarity */
295 val |= ((aref & AREF_DIFF) ? 0x80 : 0); /* b7 differential */
296 writew(val & 0xff, dev_private->me_regbase + ME_CHANNEL_LIST);
298 /* set ADC mode to software trigger */
299 dev_private->control_1 |= SOFTWARE_TRIGGERED_ADC;
300 writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
302 /* start conversion by reading from ADC_START */
303 readw(dev_private->me_regbase + ME_ADC_START);
305 /* wait for ADC fifo not empty flag */
306 for (i = 100000; i > 0; i--)
307 if (!(readw(dev_private->me_regbase + ME_STATUS) & 0x0004))
310 /* get value from ADC fifo */
312 val = readw(dev_private->me_regbase + ME_READ_AD_FIFO);
313 val = (val ^ 0x800) & 0x0fff;
316 dev_err(dev->class_dev, "Cannot get single value\n");
320 /* stop any running conversion */
321 dev_private->control_1 &= 0xFFFC;
322 writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
327 static int me_ao_insn_write(struct comedi_device *dev,
328 struct comedi_subdevice *s,
329 struct comedi_insn *insn,
332 struct me_private_data *dev_private = dev->private;
333 unsigned int chan = CR_CHAN(insn->chanspec);
334 unsigned int rang = CR_RANGE(insn->chanspec);
338 dev_private->control_2 |= ENABLE_DAC;
339 writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
341 /* and set DAC to "buffered" mode */
342 dev_private->control_2 |= BUFFERED_DAC;
343 writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
345 /* Set dac-control register */
346 for (i = 0; i < insn->n; i++) {
347 /* clear bits for this channel */
348 dev_private->dac_control &= ~(0x0880 >> chan);
350 dev_private->dac_control |=
351 ((DAC_BIPOLAR_A | DAC_GAIN_1_A) >> chan);
353 dev_private->dac_control |=
354 ((DAC_BIPOLAR_A | DAC_GAIN_0_A) >> chan);
356 writew(dev_private->dac_control,
357 dev_private->me_regbase + ME_DAC_CONTROL);
359 /* Update dac-control register */
360 readw(dev_private->me_regbase + ME_DAC_CONTROL_UPDATE);
362 /* Set data register */
363 for (i = 0; i < insn->n; i++) {
364 writew((data[0] & s->maxdata),
365 dev_private->me_regbase + ME_DAC_DATA_A + (chan << 1));
366 dev_private->ao_readback[chan] = (data[0] & s->maxdata);
369 /* Update dac with data registers */
370 readw(dev_private->me_regbase + ME_DAC_UPDATE);
375 static int me_ao_insn_read(struct comedi_device *dev,
376 struct comedi_subdevice *s,
377 struct comedi_insn *insn,
380 struct me_private_data *dev_private = dev->private;
381 unsigned int chan = CR_CHAN(insn->chanspec);
384 for (i = 0; i < insn->n; i++)
385 data[i] = dev_private->ao_readback[chan];
390 static int me2600_xilinx_download(struct comedi_device *dev,
391 const u8 *data, size_t size)
393 struct me_private_data *dev_private = dev->private;
395 unsigned int file_length;
398 /* disable irq's on PLX */
399 writel(0x00, dev_private->plx_regbase + PLX_INTCSR);
401 /* First, make a dummy read to reset xilinx */
402 value = readw(dev_private->me_regbase + XILINX_DOWNLOAD_RESET);
404 /* Wait until reset is over */
407 /* Write a dummy value to Xilinx */
408 writeb(0x00, dev_private->me_regbase + 0x0);
412 * Format of the firmware
413 * Build longs from the byte-wise coded header
414 * Byte 1-3: length of the array
417 * Byte 12-15: reserved
422 file_length = (((unsigned int)data[0] & 0xff) << 24) +
423 (((unsigned int)data[1] & 0xff) << 16) +
424 (((unsigned int)data[2] & 0xff) << 8) +
425 ((unsigned int)data[3] & 0xff);
428 * Loop for writing firmware byte by byte to xilinx
429 * Firmware data start at offfset 16
431 for (i = 0; i < file_length; i++)
432 writeb((data[16 + i] & 0xff),
433 dev_private->me_regbase + 0x0);
435 /* Write 5 dummy values to xilinx */
436 for (i = 0; i < 5; i++)
437 writeb(0x00, dev_private->me_regbase + 0x0);
439 /* Test if there was an error during download -> INTB was thrown */
440 value = readl(dev_private->plx_regbase + PLX_INTCSR);
442 /* Disable interrupt */
443 writel(0x00, dev_private->plx_regbase + PLX_INTCSR);
444 dev_err(dev->class_dev, "Xilinx download failed\n");
448 /* Wait until the Xilinx is ready for real work */
451 /* Enable PLX-Interrupts */
452 writel(0x43, dev_private->plx_regbase + PLX_INTCSR);
457 static int me2600_upload_firmware(struct comedi_device *dev)
459 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
460 const struct firmware *fw;
463 ret = request_firmware(&fw, ME2600_FIRMWARE, &pcidev->dev);
467 ret = me2600_xilinx_download(dev, fw->data, fw->size);
468 release_firmware(fw);
473 static int me_reset(struct comedi_device *dev)
475 struct me_private_data *dev_private = dev->private;
478 writew(0x00, dev_private->me_regbase + ME_CONTROL_1);
479 writew(0x00, dev_private->me_regbase + ME_CONTROL_2);
480 writew(0x00, dev_private->me_regbase + ME_RESET_INTERRUPT);
481 writew(0x00, dev_private->me_regbase + ME_DAC_CONTROL);
483 /* Save values in the board context */
484 dev_private->dac_control = 0;
485 dev_private->control_1 = 0;
486 dev_private->control_2 = 0;
491 static const void *me_find_boardinfo(struct comedi_device *dev,
492 struct pci_dev *pcidev)
494 const struct me_board *board;
497 for (i = 0; i < ARRAY_SIZE(me_boards); i++) {
498 board = &me_boards[i];
499 if (board->device_id == pcidev->device)
505 static int me_auto_attach(struct comedi_device *dev,
506 unsigned long context_unused)
508 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
509 const struct me_board *board;
510 struct me_private_data *dev_private;
511 struct comedi_subdevice *s;
514 board = me_find_boardinfo(dev, pcidev);
517 dev->board_ptr = board;
518 dev->board_name = board->name;
520 dev_private = kzalloc(sizeof(*dev_private), GFP_KERNEL);
523 dev->private = dev_private;
525 ret = comedi_pci_enable(pcidev, dev->board_name);
528 dev->iobase = 1; /* detach needs this */
530 dev_private->plx_regbase = ioremap(pci_resource_start(pcidev, 0),
531 pci_resource_len(pcidev, 0));
532 if (!dev_private->plx_regbase)
535 dev_private->me_regbase = ioremap(pci_resource_start(pcidev, 2),
536 pci_resource_len(pcidev, 2));
537 if (!dev_private->me_regbase)
540 /* Download firmware and reset card */
541 if (board->device_id == ME2600_DEVICE_ID) {
542 ret = me2600_upload_firmware(dev);
548 ret = comedi_alloc_subdevices(dev, 3);
552 s = &dev->subdevices[0];
553 s->type = COMEDI_SUBD_AI;
554 s->subdev_flags = SDF_READABLE | SDF_COMMON;
557 s->len_chanlist = 16;
558 s->range_table = &me_ai_range;
559 s->insn_read = me_ai_insn_read;
561 s = &dev->subdevices[1];
563 s->type = COMEDI_SUBD_AO;
564 s->subdev_flags = SDF_WRITEABLE | SDF_COMMON;
568 s->range_table = &me_ao_range;
569 s->insn_read = me_ao_insn_read;
570 s->insn_write = me_ao_insn_write;
572 s->type = COMEDI_SUBD_UNUSED;
575 s = &dev->subdevices[2];
576 s->type = COMEDI_SUBD_DIO;
577 s->subdev_flags = SDF_READABLE | SDF_WRITEABLE;
580 s->len_chanlist = 32;
581 s->range_table = &range_digital;
582 s->insn_bits = me_dio_insn_bits;
583 s->insn_config = me_dio_insn_config;
586 dev_info(dev->class_dev, "%s: %s attached\n",
587 dev->driver->driver_name, dev->board_name);
592 static void me_detach(struct comedi_device *dev)
594 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
595 struct me_private_data *dev_private = dev->private;
598 if (dev_private->me_regbase) {
600 iounmap(dev_private->me_regbase);
602 if (dev_private->plx_regbase)
603 iounmap(dev_private->plx_regbase);
607 comedi_pci_disable(pcidev);
611 static struct comedi_driver me_daq_driver = {
612 .driver_name = "me_daq",
613 .module = THIS_MODULE,
614 .auto_attach = me_auto_attach,
618 static int me_daq_pci_probe(struct pci_dev *dev,
619 const struct pci_device_id *ent)
621 return comedi_pci_auto_config(dev, &me_daq_driver);
624 static DEFINE_PCI_DEVICE_TABLE(me_daq_pci_table) = {
625 { PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, ME2600_DEVICE_ID) },
626 { PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, ME2000_DEVICE_ID) },
629 MODULE_DEVICE_TABLE(pci, me_daq_pci_table);
631 static struct pci_driver me_daq_pci_driver = {
633 .id_table = me_daq_pci_table,
634 .probe = me_daq_pci_probe,
635 .remove = comedi_pci_auto_unconfig,
637 module_comedi_pci_driver(me_daq_driver, me_daq_pci_driver);
639 MODULE_AUTHOR("Comedi http://www.comedi.org");
640 MODULE_DESCRIPTION("Comedi low-level driver");
641 MODULE_LICENSE("GPL");
642 MODULE_FIRMWARE(ME2600_FIRMWARE);