3 Hardware driver for NI Mite PCI interface chip
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-2002 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 The PCI-MIO E series driver was originally written by
26 Tomasz Motylewski <...>, and ported to comedi by ds.
28 References for specifications:
30 321747b.pdf Register Level Programmer Manual (obsolete)
31 321747c.pdf Register Level Programmer Manual (new)
32 DAQ-STC reference manual
34 Other possibly relevant info:
36 320517c.pdf User manual (obsolete)
37 320517f.pdf User manual (new)
39 320906c.pdf maximum signal ratings
41 321791a.pdf discontinuation of at-mio-16e-10 rev. c
42 321808a.pdf about at-mio-16e-10 rev P
43 321837a.pdf discontinuation of at-mio-16de-10 rev d
44 321838a.pdf about at-mio-16de-10 rev N
50 /* #define USE_KMALLOC */
52 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
54 #include <linux/pci.h>
56 #include "../comedidev.h"
58 #include "comedi_fc.h"
61 #define TOP_OF_PAGE(x) ((x)|(~(PAGE_MASK)))
63 struct mite_struct *mite_alloc(struct pci_dev *pcidev)
65 struct mite_struct *mite;
68 mite = kzalloc(sizeof(*mite), GFP_KERNEL);
70 spin_lock_init(&mite->lock);
71 mite->pcidev = pcidev;
72 for (i = 0; i < MAX_MITE_DMA_CHANNELS; ++i) {
73 mite->channels[i].mite = mite;
74 mite->channels[i].channel = i;
75 mite->channels[i].done = 1;
80 EXPORT_SYMBOL_GPL(mite_alloc);
82 static void dump_chip_signature(u32 csigr_bits)
84 pr_info("version = %i, type = %i, mite mode = %i, interface mode = %i\n",
85 mite_csigr_version(csigr_bits), mite_csigr_type(csigr_bits),
86 mite_csigr_mmode(csigr_bits), mite_csigr_imode(csigr_bits));
87 pr_info("num channels = %i, write post fifo depth = %i, wins = %i, iowins = %i\n",
88 mite_csigr_dmac(csigr_bits), mite_csigr_wpdep(csigr_bits),
89 mite_csigr_wins(csigr_bits), mite_csigr_iowins(csigr_bits));
92 static unsigned mite_fifo_size(struct mite_struct *mite, unsigned channel)
94 unsigned fcr_bits = readl(mite->mite_io_addr + MITE_FCR(channel));
95 unsigned empty_count = (fcr_bits >> 16) & 0xff;
96 unsigned full_count = fcr_bits & 0xff;
97 return empty_count + full_count;
100 int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1)
102 unsigned long length;
105 unsigned unknown_dma_burst_bits;
107 pci_set_master(mite->pcidev);
109 mite->mite_io_addr = pci_ioremap_bar(mite->pcidev, 0);
110 if (!mite->mite_io_addr) {
111 dev_err(&mite->pcidev->dev,
112 "Failed to remap mite io memory address\n");
115 mite->mite_phys_addr = pci_resource_start(mite->pcidev, 0);
117 mite->daq_io_addr = pci_ioremap_bar(mite->pcidev, 1);
118 if (!mite->daq_io_addr) {
119 dev_err(&mite->pcidev->dev,
120 "Failed to remap daq io memory address\n");
123 mite->daq_phys_addr = pci_resource_start(mite->pcidev, 1);
124 length = pci_resource_len(mite->pcidev, 1);
127 writel(0, mite->mite_io_addr + MITE_IODWBSR);
128 dev_info(&mite->pcidev->dev,
129 "using I/O Window Base Size register 1\n");
130 writel(mite->daq_phys_addr | WENAB |
131 MITE_IODWBSR_1_WSIZE_bits(length),
132 mite->mite_io_addr + MITE_IODWBSR_1);
133 writel(0, mite->mite_io_addr + MITE_IODWCR_1);
135 writel(mite->daq_phys_addr | WENAB,
136 mite->mite_io_addr + MITE_IODWBSR);
139 * make sure dma bursts work. I got this from running a bus analyzer
140 * on a pxi-6281 and a pxi-6713. 6713 powered up with register value
141 * of 0x61f and bursts worked. 6281 powered up with register value of
142 * 0x1f and bursts didn't work. The NI windows driver reads the
143 * register, then does a bitwise-or of 0x600 with it and writes it back.
145 unknown_dma_burst_bits =
146 readl(mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG);
147 unknown_dma_burst_bits |= UNKNOWN_DMA_BURST_ENABLE_BITS;
148 writel(unknown_dma_burst_bits,
149 mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG);
151 csigr_bits = readl(mite->mite_io_addr + MITE_CSIGR);
152 mite->num_channels = mite_csigr_dmac(csigr_bits);
153 if (mite->num_channels > MAX_MITE_DMA_CHANNELS) {
154 dev_warn(&mite->pcidev->dev,
155 "mite: bug? chip claims to have %i dma channels. Setting to %i.\n",
156 mite->num_channels, MAX_MITE_DMA_CHANNELS);
157 mite->num_channels = MAX_MITE_DMA_CHANNELS;
159 dump_chip_signature(csigr_bits);
160 for (i = 0; i < mite->num_channels; i++) {
161 writel(CHOR_DMARESET, mite->mite_io_addr + MITE_CHOR(i));
162 /* disable interrupts */
163 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE |
164 CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
165 CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
166 mite->mite_io_addr + MITE_CHCR(i));
168 mite->fifo_size = mite_fifo_size(mite, 0);
169 dev_info(&mite->pcidev->dev, "fifo size is %i.\n", mite->fifo_size);
172 EXPORT_SYMBOL_GPL(mite_setup2);
174 int mite_setup(struct mite_struct *mite)
176 return mite_setup2(mite, 0);
178 EXPORT_SYMBOL_GPL(mite_setup);
180 void mite_unsetup(struct mite_struct *mite)
182 /* unsigned long offset, start, length; */
187 if (mite->mite_io_addr) {
188 iounmap(mite->mite_io_addr);
189 mite->mite_io_addr = NULL;
191 if (mite->daq_io_addr) {
192 iounmap(mite->daq_io_addr);
193 mite->daq_io_addr = NULL;
195 if (mite->mite_phys_addr)
196 mite->mite_phys_addr = 0;
198 EXPORT_SYMBOL_GPL(mite_unsetup);
200 struct mite_dma_descriptor_ring *mite_alloc_ring(struct mite_struct *mite)
202 struct mite_dma_descriptor_ring *ring =
203 kmalloc(sizeof(struct mite_dma_descriptor_ring), GFP_KERNEL);
207 ring->hw_dev = get_device(&mite->pcidev->dev);
208 if (ring->hw_dev == NULL) {
213 ring->descriptors = NULL;
214 ring->descriptors_dma_addr = 0;
217 EXPORT_SYMBOL_GPL(mite_alloc_ring);
219 void mite_free_ring(struct mite_dma_descriptor_ring *ring)
222 if (ring->descriptors) {
223 dma_free_coherent(ring->hw_dev,
225 sizeof(struct mite_dma_descriptor),
227 ring->descriptors_dma_addr);
229 put_device(ring->hw_dev);
233 EXPORT_SYMBOL_GPL(mite_free_ring);
235 struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite,
237 mite_dma_descriptor_ring
238 *ring, unsigned min_channel,
239 unsigned max_channel)
243 struct mite_channel *channel = NULL;
245 /* spin lock so mite_release_channel can be called safely
248 spin_lock_irqsave(&mite->lock, flags);
249 for (i = min_channel; i <= max_channel; ++i) {
250 if (mite->channel_allocated[i] == 0) {
251 mite->channel_allocated[i] = 1;
252 channel = &mite->channels[i];
253 channel->ring = ring;
257 spin_unlock_irqrestore(&mite->lock, flags);
260 EXPORT_SYMBOL_GPL(mite_request_channel_in_range);
262 void mite_release_channel(struct mite_channel *mite_chan)
264 struct mite_struct *mite = mite_chan->mite;
267 /* spin lock to prevent races with mite_request_channel */
268 spin_lock_irqsave(&mite->lock, flags);
269 if (mite->channel_allocated[mite_chan->channel]) {
270 mite_dma_disarm(mite_chan);
271 mite_dma_reset(mite_chan);
273 * disable all channel's interrupts (do it after disarm/reset so
274 * MITE_CHCR reg isn't changed while dma is still active!)
276 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE |
277 CHCR_CLR_SAR_IE | CHCR_CLR_DONE_IE |
278 CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
279 CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
280 mite->mite_io_addr + MITE_CHCR(mite_chan->channel));
281 mite->channel_allocated[mite_chan->channel] = 0;
282 mite_chan->ring = NULL;
285 spin_unlock_irqrestore(&mite->lock, flags);
287 EXPORT_SYMBOL_GPL(mite_release_channel);
289 void mite_dma_arm(struct mite_channel *mite_chan)
291 struct mite_struct *mite = mite_chan->mite;
295 MDPRINTK("mite_dma_arm ch%i\n", mite_chan->channel);
297 * memory barrier is intended to insure any twiddling with the buffer
298 * is done before writing to the mite to arm dma transfer
303 spin_lock_irqsave(&mite->lock, flags);
305 writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
307 spin_unlock_irqrestore(&mite->lock, flags);
308 /* mite_dma_tcr(mite, channel); */
310 EXPORT_SYMBOL_GPL(mite_dma_arm);
312 /**************************************/
314 int mite_buf_change(struct mite_dma_descriptor_ring *ring,
315 struct comedi_async *async)
317 unsigned int n_links;
320 if (ring->descriptors) {
321 dma_free_coherent(ring->hw_dev,
323 sizeof(struct mite_dma_descriptor),
325 ring->descriptors_dma_addr);
327 ring->descriptors = NULL;
328 ring->descriptors_dma_addr = 0;
331 if (async->prealloc_bufsz == 0)
334 n_links = async->prealloc_bufsz >> PAGE_SHIFT;
336 MDPRINTK("ring->hw_dev=%p, n_links=0x%04x\n", ring->hw_dev, n_links);
339 dma_alloc_coherent(ring->hw_dev,
340 n_links * sizeof(struct mite_dma_descriptor),
341 &ring->descriptors_dma_addr, GFP_KERNEL);
342 if (!ring->descriptors) {
343 dev_err(async->subdevice->device->class_dev,
344 "mite: ring buffer allocation failed\n");
347 ring->n_links = n_links;
349 for (i = 0; i < n_links; i++) {
350 ring->descriptors[i].count = cpu_to_le32(PAGE_SIZE);
351 ring->descriptors[i].addr =
352 cpu_to_le32(async->buf_page_list[i].dma_addr);
353 ring->descriptors[i].next =
354 cpu_to_le32(ring->descriptors_dma_addr + (i +
356 sizeof(struct mite_dma_descriptor));
358 ring->descriptors[n_links - 1].next =
359 cpu_to_le32(ring->descriptors_dma_addr);
361 * barrier is meant to insure that all the writes to the dma descriptors
362 * have completed before the dma controller is commanded to read them
367 EXPORT_SYMBOL_GPL(mite_buf_change);
369 void mite_prep_dma(struct mite_channel *mite_chan,
370 unsigned int num_device_bits, unsigned int num_memory_bits)
372 unsigned int chor, chcr, mcr, dcr, lkcr;
373 struct mite_struct *mite = mite_chan->mite;
375 MDPRINTK("mite_prep_dma ch%i\n", mite_chan->channel);
377 /* reset DMA and FIFO */
378 chor = CHOR_DMARESET | CHOR_FRESET;
379 writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
381 /* short link chaining mode */
382 chcr = CHCR_SET_DMA_IE | CHCR_LINKSHORT | CHCR_SET_DONE_IE |
385 * Link Complete Interrupt: interrupt every time a link
386 * in MITE_RING is completed. This can generate a lot of
387 * extra interrupts, but right now we update the values
388 * of buf_int_ptr and buf_int_count at each interrupt. A
389 * better method is to poll the MITE before each user
390 * "read()" to calculate the number of bytes available.
392 chcr |= CHCR_SET_LC_IE;
393 if (num_memory_bits == 32 && num_device_bits == 16) {
395 * Doing a combined 32 and 16 bit byteswap gets the 16 bit
396 * samples into the fifo in the right order. Tested doing 32 bit
397 * memory to 16 bit device transfers to the analog out of a
398 * pxi-6281, which has mite version = 1, type = 4. This also
399 * works for dma reads from the counters on e-series boards.
401 chcr |= CHCR_BYTE_SWAP_DEVICE | CHCR_BYTE_SWAP_MEMORY;
403 if (mite_chan->dir == COMEDI_INPUT)
404 chcr |= CHCR_DEV_TO_MEM;
406 writel(chcr, mite->mite_io_addr + MITE_CHCR(mite_chan->channel));
409 mcr = CR_RL(64) | CR_ASEQUP;
410 switch (num_memory_bits) {
421 pr_warn("bug! invalid mem bit width for dma transfer\n");
424 writel(mcr, mite->mite_io_addr + MITE_MCR(mite_chan->channel));
427 dcr = CR_RL(64) | CR_ASEQUP;
428 dcr |= CR_PORTIO | CR_AMDEVICE | CR_REQSDRQ(mite_chan->channel);
429 switch (num_device_bits) {
440 pr_warn("bug! invalid dev bit width for dma transfer\n");
443 writel(dcr, mite->mite_io_addr + MITE_DCR(mite_chan->channel));
446 writel(0, mite->mite_io_addr + MITE_DAR(mite_chan->channel));
448 /* the link is 32bits */
449 lkcr = CR_RL(64) | CR_ASEQUP | CR_PSIZE32;
450 writel(lkcr, mite->mite_io_addr + MITE_LKCR(mite_chan->channel));
452 /* starting address for link chaining */
453 writel(mite_chan->ring->descriptors_dma_addr,
454 mite->mite_io_addr + MITE_LKAR(mite_chan->channel));
456 MDPRINTK("exit mite_prep_dma\n");
458 EXPORT_SYMBOL_GPL(mite_prep_dma);
460 static u32 mite_device_bytes_transferred(struct mite_channel *mite_chan)
462 struct mite_struct *mite = mite_chan->mite;
463 return readl(mite->mite_io_addr + MITE_DAR(mite_chan->channel));
466 u32 mite_bytes_in_transit(struct mite_channel *mite_chan)
468 struct mite_struct *mite = mite_chan->mite;
469 return readl(mite->mite_io_addr +
470 MITE_FCR(mite_chan->channel)) & 0x000000FF;
472 EXPORT_SYMBOL_GPL(mite_bytes_in_transit);
474 /* returns lower bound for number of bytes transferred from device to memory */
475 u32 mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan)
477 u32 device_byte_count;
479 device_byte_count = mite_device_bytes_transferred(mite_chan);
480 return device_byte_count - mite_bytes_in_transit(mite_chan);
482 EXPORT_SYMBOL_GPL(mite_bytes_written_to_memory_lb);
484 /* returns upper bound for number of bytes transferred from device to memory */
485 u32 mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan)
487 u32 in_transit_count;
489 in_transit_count = mite_bytes_in_transit(mite_chan);
490 return mite_device_bytes_transferred(mite_chan) - in_transit_count;
492 EXPORT_SYMBOL_GPL(mite_bytes_written_to_memory_ub);
494 /* returns lower bound for number of bytes read from memory to device */
495 u32 mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan)
497 u32 device_byte_count;
499 device_byte_count = mite_device_bytes_transferred(mite_chan);
500 return device_byte_count + mite_bytes_in_transit(mite_chan);
502 EXPORT_SYMBOL_GPL(mite_bytes_read_from_memory_lb);
504 /* returns upper bound for number of bytes read from memory to device */
505 u32 mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan)
507 u32 in_transit_count;
509 in_transit_count = mite_bytes_in_transit(mite_chan);
510 return mite_device_bytes_transferred(mite_chan) + in_transit_count;
512 EXPORT_SYMBOL_GPL(mite_bytes_read_from_memory_ub);
514 unsigned mite_dma_tcr(struct mite_channel *mite_chan)
516 struct mite_struct *mite = mite_chan->mite;
520 lkar = readl(mite->mite_io_addr + MITE_LKAR(mite_chan->channel));
521 tcr = readl(mite->mite_io_addr + MITE_TCR(mite_chan->channel));
522 MDPRINTK("mite_dma_tcr ch%i, lkar=0x%08x tcr=%d\n", mite_chan->channel,
527 EXPORT_SYMBOL_GPL(mite_dma_tcr);
529 void mite_dma_disarm(struct mite_channel *mite_chan)
531 struct mite_struct *mite = mite_chan->mite;
536 writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
538 EXPORT_SYMBOL_GPL(mite_dma_disarm);
540 int mite_sync_input_dma(struct mite_channel *mite_chan,
541 struct comedi_async *async)
544 unsigned int nbytes, old_alloc_count;
545 const unsigned bytes_per_scan = cfc_bytes_per_scan(async->subdevice);
547 old_alloc_count = async->buf_write_alloc_count;
548 /* write alloc as much as we can */
549 comedi_buf_write_alloc(async, async->prealloc_bufsz);
551 nbytes = mite_bytes_written_to_memory_lb(mite_chan);
552 if ((int)(mite_bytes_written_to_memory_ub(mite_chan) -
553 old_alloc_count) > 0) {
554 dev_warn(async->subdevice->device->class_dev,
555 "mite: DMA overwrite of free area\n");
556 async->events |= COMEDI_CB_OVERFLOW;
560 count = nbytes - async->buf_write_count;
561 /* it's possible count will be negative due to
562 * conservative value returned by mite_bytes_written_to_memory_lb */
566 comedi_buf_write_free(async, count);
568 async->scan_progress += count;
569 if (async->scan_progress >= bytes_per_scan) {
570 async->scan_progress %= bytes_per_scan;
571 async->events |= COMEDI_CB_EOS;
573 async->events |= COMEDI_CB_BLOCK;
576 EXPORT_SYMBOL_GPL(mite_sync_input_dma);
578 int mite_sync_output_dma(struct mite_channel *mite_chan,
579 struct comedi_async *async)
582 u32 nbytes_ub, nbytes_lb;
583 unsigned int old_alloc_count;
585 async->cmd.stop_arg * cfc_bytes_per_scan(async->subdevice);
587 old_alloc_count = async->buf_read_alloc_count;
588 /* read alloc as much as we can */
589 comedi_buf_read_alloc(async, async->prealloc_bufsz);
590 nbytes_lb = mite_bytes_read_from_memory_lb(mite_chan);
591 if (async->cmd.stop_src == TRIG_COUNT &&
592 (int)(nbytes_lb - stop_count) > 0)
593 nbytes_lb = stop_count;
594 nbytes_ub = mite_bytes_read_from_memory_ub(mite_chan);
595 if (async->cmd.stop_src == TRIG_COUNT &&
596 (int)(nbytes_ub - stop_count) > 0)
597 nbytes_ub = stop_count;
598 if ((int)(nbytes_ub - old_alloc_count) > 0) {
599 dev_warn(async->subdevice->device->class_dev,
600 "mite: DMA underrun\n");
601 async->events |= COMEDI_CB_OVERFLOW;
604 count = nbytes_lb - async->buf_read_count;
609 comedi_buf_read_free(async, count);
610 async->events |= COMEDI_CB_BLOCK;
614 EXPORT_SYMBOL_GPL(mite_sync_output_dma);
616 unsigned mite_get_status(struct mite_channel *mite_chan)
618 struct mite_struct *mite = mite_chan->mite;
622 spin_lock_irqsave(&mite->lock, flags);
623 status = readl(mite->mite_io_addr + MITE_CHSR(mite_chan->channel));
624 if (status & CHSR_DONE) {
627 mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
630 spin_unlock_irqrestore(&mite->lock, flags);
633 EXPORT_SYMBOL_GPL(mite_get_status);
635 int mite_done(struct mite_channel *mite_chan)
637 struct mite_struct *mite = mite_chan->mite;
641 mite_get_status(mite_chan);
642 spin_lock_irqsave(&mite->lock, flags);
643 done = mite_chan->done;
644 spin_unlock_irqrestore(&mite->lock, flags);
647 EXPORT_SYMBOL_GPL(mite_done);
651 /* names of bits in mite registers */
653 static const char *const mite_CHOR_strings[] = {
654 "start", "cont", "stop", "abort",
655 "freset", "clrlc", "clrrb", "clrdone",
656 "clr_lpause", "set_lpause", "clr_send_tc",
657 "set_send_tc", "12", "13", "14",
658 "15", "16", "17", "18",
659 "19", "20", "21", "22",
660 "23", "24", "25", "26",
661 "27", "28", "29", "30",
665 static const char *const mite_CHCR_strings[] = {
666 "continue", "ringbuff", "2", "3",
668 "8", "9", "10", "11",
669 "12", "13", "bursten", "fifodis",
670 "clr_cont_rb_ie", "set_cont_rb_ie", "clr_lc_ie", "set_lc_ie",
671 "clr_drdy_ie", "set_drdy_ie", "clr_mrdy_ie", "set_mrdy_ie",
672 "clr_done_ie", "set_done_ie", "clr_sar_ie", "set_sar_ie",
673 "clr_linkp_ie", "set_linkp_ie", "clr_dma_ie", "set_dma_ie",
676 static const char *const mite_MCR_strings[] = {
677 "amdevice", "1", "2", "3",
678 "4", "5", "portio", "portvxi",
679 "psizebyte", "psizehalf (byte & half = word)", "aseqxp1", "11",
680 "12", "13", "blocken", "berhand",
681 "reqsintlim/reqs0", "reqs1", "reqs2", "rd32",
682 "rd512", "rl1", "rl2", "rl8",
683 "24", "25", "26", "27",
684 "28", "29", "30", "stopen",
687 static const char *const mite_DCR_strings[] = {
688 "amdevice", "1", "2", "3",
689 "4", "5", "portio", "portvxi",
690 "psizebyte", "psizehalf (byte & half = word)", "aseqxp1", "aseqxp2",
691 "aseqxp8", "13", "blocken", "berhand",
692 "reqsintlim", "reqs1", "reqs2", "rd32",
693 "rd512", "rl1", "rl2", "rl8",
694 "23", "24", "25", "27",
695 "28", "wsdevc", "wsdevs", "rwdevpack",
698 static const char *const mite_LKCR_strings[] = {
699 "amdevice", "1", "2", "3",
700 "4", "5", "portio", "portvxi",
701 "psizebyte", "psizehalf (byte & half = word)", "asequp", "aseqdown",
702 "12", "13", "14", "berhand",
703 "16", "17", "18", "rd32",
704 "rd512", "rl1", "rl2", "rl8",
705 "24", "25", "26", "27",
706 "28", "29", "30", "chngend",
709 static const char *const mite_CHSR_strings[] = {
710 "d.err0", "d.err1", "m.err0", "m.err1",
711 "l.err0", "l.err1", "drq0", "drq1",
712 "end", "xferr", "operr0", "operr1",
713 "stops", "habort", "sabort", "error",
714 "16", "conts_rb", "18", "linkc",
715 "20", "drdy", "22", "mrdy",
716 "24", "done", "26", "sars",
717 "28", "lpauses", "30", "int",
720 static void mite_decode(const char *const *bit_str, unsigned int bits)
724 for (i = 31; i >= 0; i--) {
726 pr_debug(" %s\n", bit_str[i]);
730 void mite_dump_regs(struct mite_channel *mite_chan)
732 void __iomem *mite_io_addr = mite_chan->mite->mite_io_addr;
735 int channel = mite_chan->channel;
737 pr_debug("mite_dump_regs ch%i\n", channel);
738 pr_debug("mite address is =%p\n", mite_io_addr);
740 offset = MITE_CHOR(channel);
741 value = readl(mite_io_addr + offset);
742 pr_debug("mite status[CHOR] at 0x%08x =0x%08x\n", offset, value);
743 mite_decode(mite_CHOR_strings, value);
744 offset = MITE_CHCR(channel);
745 value = readl(mite_io_addr + offset);
746 pr_debug("mite status[CHCR] at 0x%08x =0x%08x\n", offset, value);
747 mite_decode(mite_CHCR_strings, value);
748 offset = MITE_TCR(channel);
749 value = readl(mite_io_addr + offset);
750 pr_debug("mite status[TCR] at 0x%08x =0x%08x\n", offset, value);
751 offset = MITE_MCR(channel);
752 value = readl(mite_io_addr + offset);
753 pr_debug("mite status[MCR] at 0x%08x =0x%08x\n", offset, value);
754 mite_decode(mite_MCR_strings, value);
755 offset = MITE_MAR(channel);
756 value = readl(mite_io_addr + offset);
757 pr_debug("mite status[MAR] at 0x%08x =0x%08x\n", offset, value);
758 offset = MITE_DCR(channel);
759 value = readl(mite_io_addr + offset);
760 pr_debug("mite status[DCR] at 0x%08x =0x%08x\n", offset, value);
761 mite_decode(mite_DCR_strings, value);
762 offset = MITE_DAR(channel);
763 value = readl(mite_io_addr + offset);
764 pr_debug("mite status[DAR] at 0x%08x =0x%08x\n", offset, value);
765 offset = MITE_LKCR(channel);
766 value = readl(mite_io_addr + offset);
767 pr_debug("mite status[LKCR] at 0x%08x =0x%08x\n", offset, value);
768 mite_decode(mite_LKCR_strings, value);
769 offset = MITE_LKAR(channel);
770 value = readl(mite_io_addr + offset);
771 pr_debug("mite status[LKAR] at 0x%08x =0x%08x\n", offset, value);
772 offset = MITE_CHSR(channel);
773 value = readl(mite_io_addr + offset);
774 pr_debug("mite status[CHSR] at 0x%08x =0x%08x\n", offset, value);
775 mite_decode(mite_CHSR_strings, value);
776 offset = MITE_FCR(channel);
777 value = readl(mite_io_addr + offset);
778 pr_debug("mite status[FCR] at 0x%08x =0x%08x\n", offset, value);
780 EXPORT_SYMBOL_GPL(mite_dump_regs);
783 static int __init mite_module_init(void)
788 static void __exit mite_module_exit(void)
792 module_init(mite_module_init);
793 module_exit(mite_module_exit);
795 MODULE_AUTHOR("Comedi http://www.comedi.org");
796 MODULE_DESCRIPTION("Comedi low-level driver");
797 MODULE_LICENSE("GPL");