2 comedi/drivers/ni_6527.c
3 driver for National Instruments PCI-6527
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1999,2002,2003 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
20 Description: National Instruments 6527
23 Devices: [National Instruments] PCI-6527 (ni6527), PXI-6527
24 Updated: Sat, 25 Jan 2003 13:24:40 -0800
30 Manuals (available from ftp://ftp.natinst.com/support/manuals)
32 370106b.pdf 6527 Register Level Programmer Manual
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/interrupt.h>
40 #include "../comedidev.h"
42 #include "comedi_fc.h"
45 #define NI6527_DI_REG(x) (0x00 + (x))
46 #define NI6527_DO_REG(x) (0x03 + (x))
47 #define NI6527_ID_REG 0x06
49 #define Clear_Register 0x07
51 #define ClrOverflow 0x04
52 #define ClrFilter 0x02
53 #define ClrInterval 0x01
55 #define NI6527_FILT_INTERVAL_REG(x) (0x08 + (x))
56 #define NI6527_FILT_ENA_REG(x) (0x0c + (x))
58 #define Change_Status 0x14
59 #define MasterInterruptStatus 0x04
61 #define EdgeStatus 0x01
63 #define Master_Interrupt_Control 0x15
64 #define FallingEdgeIntEnable 0x10
65 #define RisingEdgeIntEnable 0x08
66 #define MasterInterruptEnable 0x04
67 #define OverflowIntEnable 0x02
68 #define EdgeIntEnable 0x01
70 #define Rising_Edge_Detection_Enable(x) (0x018+(x))
71 #define Falling_Edge_Detection_Enable(x) (0x020+(x))
82 static const struct ni6527_board ni6527_boards[] = {
91 struct ni6527_private {
92 struct mite_struct *mite;
93 unsigned int filter_interval;
94 unsigned int filter_enable;
97 static void ni6527_set_filter_interval(struct comedi_device *dev,
100 struct ni6527_private *devpriv = dev->private;
101 void __iomem *mmio = devpriv->mite->daq_io_addr;
103 if (val != devpriv->filter_interval) {
104 writeb(val & 0xff, mmio + NI6527_FILT_INTERVAL_REG(0));
105 writeb((val >> 8) & 0xff, mmio + NI6527_FILT_INTERVAL_REG(1));
106 writeb((val >> 16) & 0x0f, mmio + NI6527_FILT_INTERVAL_REG(2));
108 writeb(ClrInterval, mmio + Clear_Register);
110 devpriv->filter_interval = val;
114 static void ni6527_set_filter_enable(struct comedi_device *dev,
117 struct ni6527_private *devpriv = dev->private;
118 void __iomem *mmio = devpriv->mite->daq_io_addr;
120 writeb(val & 0xff, mmio + NI6527_FILT_ENA_REG(0));
121 writeb((val >> 8) & 0xff, mmio + NI6527_FILT_ENA_REG(1));
122 writeb((val >> 16) & 0xff, mmio + NI6527_FILT_ENA_REG(2));
125 static int ni6527_di_insn_config(struct comedi_device *dev,
126 struct comedi_subdevice *s,
127 struct comedi_insn *insn,
130 struct ni6527_private *devpriv = dev->private;
131 unsigned int chan = CR_CHAN(insn->chanspec);
132 unsigned int interval;
135 case INSN_CONFIG_FILTER:
137 * The deglitch filter interval is specified in nanoseconds.
138 * The hardware supports intervals in 200ns increments. Round
139 * the user values up and return the actual interval.
141 interval = (data[1] + 100) / 200;
142 data[1] = interval * 200;
145 ni6527_set_filter_interval(dev, interval);
146 devpriv->filter_enable |= 1 << chan;
148 devpriv->filter_enable &= ~(1 << chan);
150 ni6527_set_filter_enable(dev, devpriv->filter_enable);
159 static int ni6527_di_insn_bits(struct comedi_device *dev,
160 struct comedi_subdevice *s,
161 struct comedi_insn *insn,
164 struct ni6527_private *devpriv = dev->private;
165 void __iomem *mmio = devpriv->mite->daq_io_addr;
168 val = readb(mmio + NI6527_DI_REG(0));
169 val |= (readb(mmio + NI6527_DI_REG(1)) << 8);
170 val |= (readb(mmio + NI6527_DI_REG(2)) << 16);
177 static int ni6527_do_insn_bits(struct comedi_device *dev,
178 struct comedi_subdevice *s,
179 struct comedi_insn *insn,
182 struct ni6527_private *devpriv = dev->private;
183 void __iomem *mmio = devpriv->mite->daq_io_addr;
186 mask = comedi_dio_update_state(s, data);
188 /* Outputs are inverted */
189 unsigned int val = s->state ^ 0xffffff;
192 writeb(val & 0xff, mmio + NI6527_DO_REG(0));
194 writeb((val >> 8) & 0xff, mmio + NI6527_DO_REG(1));
196 writeb((val >> 16) & 0xff, mmio + NI6527_DO_REG(2));
204 static irqreturn_t ni6527_interrupt(int irq, void *d)
206 struct comedi_device *dev = d;
207 struct ni6527_private *devpriv = dev->private;
208 struct comedi_subdevice *s = &dev->subdevices[2];
211 status = readb(devpriv->mite->daq_io_addr + Change_Status);
212 if ((status & MasterInterruptStatus) == 0)
214 if ((status & EdgeStatus) == 0)
217 writeb(ClrEdge | ClrOverflow,
218 devpriv->mite->daq_io_addr + Clear_Register);
220 comedi_buf_put(s->async, 0);
221 s->async->events |= COMEDI_CB_EOS;
222 comedi_event(dev, s);
226 static int ni6527_intr_cmdtest(struct comedi_device *dev,
227 struct comedi_subdevice *s,
228 struct comedi_cmd *cmd)
232 /* Step 1 : check if triggers are trivially valid */
234 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
235 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_OTHER);
236 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
237 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
238 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT);
243 /* Step 2a : make sure trigger sources are unique */
244 /* Step 2b : and mutually compatible */
249 /* Step 3: check if arguments are trivially valid */
251 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
252 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
253 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
254 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, 1);
255 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
260 /* step 4: fix up any arguments */
268 static int ni6527_intr_cmd(struct comedi_device *dev,
269 struct comedi_subdevice *s)
271 struct ni6527_private *devpriv = dev->private;
272 /* struct comedi_cmd *cmd = &s->async->cmd; */
274 writeb(ClrEdge | ClrOverflow,
275 devpriv->mite->daq_io_addr + Clear_Register);
276 writeb(FallingEdgeIntEnable | RisingEdgeIntEnable |
277 MasterInterruptEnable | EdgeIntEnable,
278 devpriv->mite->daq_io_addr + Master_Interrupt_Control);
283 static int ni6527_intr_cancel(struct comedi_device *dev,
284 struct comedi_subdevice *s)
286 struct ni6527_private *devpriv = dev->private;
288 writeb(0x00, devpriv->mite->daq_io_addr + Master_Interrupt_Control);
293 static int ni6527_intr_insn_bits(struct comedi_device *dev,
294 struct comedi_subdevice *s,
295 struct comedi_insn *insn, unsigned int *data)
301 static int ni6527_intr_insn_config(struct comedi_device *dev,
302 struct comedi_subdevice *s,
303 struct comedi_insn *insn, unsigned int *data)
305 struct ni6527_private *devpriv = dev->private;
309 if (data[0] != INSN_CONFIG_CHANGE_NOTIFY)
313 devpriv->mite->daq_io_addr + Rising_Edge_Detection_Enable(0));
315 devpriv->mite->daq_io_addr + Rising_Edge_Detection_Enable(1));
316 writeb(data[1] >> 16,
317 devpriv->mite->daq_io_addr + Rising_Edge_Detection_Enable(2));
320 devpriv->mite->daq_io_addr + Falling_Edge_Detection_Enable(0));
322 devpriv->mite->daq_io_addr + Falling_Edge_Detection_Enable(1));
323 writeb(data[2] >> 16,
324 devpriv->mite->daq_io_addr + Falling_Edge_Detection_Enable(2));
329 static int ni6527_auto_attach(struct comedi_device *dev,
330 unsigned long context)
332 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
333 const struct ni6527_board *board = NULL;
334 struct ni6527_private *devpriv;
335 struct comedi_subdevice *s;
338 if (context < ARRAY_SIZE(ni6527_boards))
339 board = &ni6527_boards[context];
342 dev->board_ptr = board;
343 dev->board_name = board->name;
345 ret = comedi_pci_enable(dev);
349 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
353 devpriv->mite = mite_alloc(pcidev);
357 ret = mite_setup(devpriv->mite);
359 dev_err(dev->class_dev, "error setting up mite\n");
363 /* make sure this is actually a 6527 device */
364 if (readb(devpriv->mite->daq_io_addr + NI6527_ID_REG) != 0x27)
367 ret = comedi_alloc_subdevices(dev, 3);
371 s = &dev->subdevices[0];
372 s->type = COMEDI_SUBD_DI;
373 s->subdev_flags = SDF_READABLE;
375 s->range_table = &range_digital;
377 s->insn_config = ni6527_di_insn_config;
378 s->insn_bits = ni6527_di_insn_bits;
380 s = &dev->subdevices[1];
381 s->type = COMEDI_SUBD_DO;
382 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
384 s->range_table = &range_unknown; /* FIXME: actually conductance */
386 s->insn_bits = ni6527_do_insn_bits;
388 s = &dev->subdevices[2];
389 dev->read_subdev = s;
390 s->type = COMEDI_SUBD_DI;
391 s->subdev_flags = SDF_READABLE | SDF_CMD_READ;
393 s->range_table = &range_unknown;
395 s->do_cmdtest = ni6527_intr_cmdtest;
396 s->do_cmd = ni6527_intr_cmd;
397 s->cancel = ni6527_intr_cancel;
398 s->insn_bits = ni6527_intr_insn_bits;
399 s->insn_config = ni6527_intr_insn_config;
401 ni6527_set_filter_enable(dev, 0);
403 writeb(ClrEdge | ClrOverflow | ClrFilter | ClrInterval,
404 devpriv->mite->daq_io_addr + Clear_Register);
405 writeb(0x00, devpriv->mite->daq_io_addr + Master_Interrupt_Control);
407 ret = request_irq(mite_irq(devpriv->mite), ni6527_interrupt,
408 IRQF_SHARED, dev->board_name, dev);
410 dev_warn(dev->class_dev, "irq not available\n");
412 dev->irq = mite_irq(devpriv->mite);
417 static void ni6527_detach(struct comedi_device *dev)
419 struct ni6527_private *devpriv = dev->private;
421 if (devpriv && devpriv->mite && devpriv->mite->daq_io_addr)
423 devpriv->mite->daq_io_addr + Master_Interrupt_Control);
425 free_irq(dev->irq, dev);
426 if (devpriv && devpriv->mite) {
427 mite_unsetup(devpriv->mite);
428 mite_free(devpriv->mite);
430 comedi_pci_disable(dev);
433 static struct comedi_driver ni6527_driver = {
434 .driver_name = "ni_6527",
435 .module = THIS_MODULE,
436 .auto_attach = ni6527_auto_attach,
437 .detach = ni6527_detach,
440 static int ni6527_pci_probe(struct pci_dev *dev,
441 const struct pci_device_id *id)
443 return comedi_pci_auto_config(dev, &ni6527_driver, id->driver_data);
446 static DEFINE_PCI_DEVICE_TABLE(ni6527_pci_table) = {
447 { PCI_VDEVICE(NI, 0x2b10), BOARD_PXI6527 },
448 { PCI_VDEVICE(NI, 0x2b20), BOARD_PCI6527 },
451 MODULE_DEVICE_TABLE(pci, ni6527_pci_table);
453 static struct pci_driver ni6527_pci_driver = {
455 .id_table = ni6527_pci_table,
456 .probe = ni6527_pci_probe,
457 .remove = comedi_pci_auto_unconfig,
459 module_comedi_pci_driver(ni6527_driver, ni6527_pci_driver);
461 MODULE_AUTHOR("Comedi http://www.comedi.org");
462 MODULE_DESCRIPTION("Comedi low-level driver");
463 MODULE_LICENSE("GPL");