2 comedi/drivers/ni_6527.c
3 driver for National Instruments PCI-6527
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1999,2002,2003 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
20 Description: National Instruments 6527
23 Devices: [National Instruments] PCI-6527 (ni6527), PXI-6527
24 Updated: Sat, 25 Jan 2003 13:24:40 -0800
30 Manuals (available from ftp://ftp.natinst.com/support/manuals)
32 370106b.pdf 6527 Register Level Programmer Manual
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/interrupt.h>
40 #include "../comedidev.h"
42 #include "comedi_fc.h"
44 #define NI6527_DI_REG(x) (0x00 + (x))
45 #define NI6527_DO_REG(x) (0x03 + (x))
46 #define NI6527_ID_REG 0x06
47 #define NI6527_CLR_REG 0x07
48 #define NI6527_CLR_EDGE (1 << 3)
49 #define NI6527_CLR_OVERFLOW (1 << 2)
50 #define NI6527_CLR_FILT (1 << 1)
51 #define NI6527_CLR_INTERVAL (1 << 0)
52 #define NI6527_CLR_IRQS (NI6527_CLR_EDGE | NI6527_CLR_OVERFLOW)
53 #define NI6527_CLR_RESET_FILT (NI6527_CLR_FILT | NI6527_CLR_INTERVAL)
54 #define NI6527_FILT_INTERVAL_REG(x) (0x08 + (x))
55 #define NI6527_FILT_ENA_REG(x) (0x0c + (x))
56 #define NI6527_STATUS_REG 0x14
57 #define NI6527_STATUS_IRQ (1 << 2)
58 #define NI6527_STATUS_OVERFLOW (1 << 1)
59 #define NI6527_STATUS_EDGE (1 << 0)
60 #define NI6527_CTRL_REG 0x15
61 #define NI6527_CTRL_FALLING (1 << 4)
62 #define NI6527_CTRL_RISING (1 << 3)
63 #define NI6527_CTRL_IRQ (1 << 2)
64 #define NI6527_CTRL_OVERFLOW (1 << 1)
65 #define NI6527_CTRL_EDGE (1 << 0)
66 #define NI6527_CTRL_DISABLE_IRQS 0
67 #define NI6527_CTRL_ENABLE_IRQS (NI6527_CTRL_FALLING | \
68 NI6527_CTRL_RISING | \
69 NI6527_CTRL_IRQ | NI6527_CTRL_EDGE)
70 #define NI6527_RISING_EDGE_REG(x) (0x18 + (x))
71 #define NI6527_FALLING_EDGE_REG(x) (0x20 + (x))
82 static const struct ni6527_board ni6527_boards[] = {
91 struct ni6527_private {
92 void __iomem *mmio_base;
93 unsigned int filter_interval;
94 unsigned int filter_enable;
97 static void ni6527_set_filter_interval(struct comedi_device *dev,
100 struct ni6527_private *devpriv = dev->private;
101 void __iomem *mmio = devpriv->mmio_base;
103 if (val != devpriv->filter_interval) {
104 writeb(val & 0xff, mmio + NI6527_FILT_INTERVAL_REG(0));
105 writeb((val >> 8) & 0xff, mmio + NI6527_FILT_INTERVAL_REG(1));
106 writeb((val >> 16) & 0x0f, mmio + NI6527_FILT_INTERVAL_REG(2));
108 writeb(NI6527_CLR_INTERVAL, mmio + NI6527_CLR_REG);
110 devpriv->filter_interval = val;
114 static void ni6527_set_filter_enable(struct comedi_device *dev,
117 struct ni6527_private *devpriv = dev->private;
118 void __iomem *mmio = devpriv->mmio_base;
120 writeb(val & 0xff, mmio + NI6527_FILT_ENA_REG(0));
121 writeb((val >> 8) & 0xff, mmio + NI6527_FILT_ENA_REG(1));
122 writeb((val >> 16) & 0xff, mmio + NI6527_FILT_ENA_REG(2));
125 static int ni6527_di_insn_config(struct comedi_device *dev,
126 struct comedi_subdevice *s,
127 struct comedi_insn *insn,
130 struct ni6527_private *devpriv = dev->private;
131 unsigned int chan = CR_CHAN(insn->chanspec);
132 unsigned int interval;
135 case INSN_CONFIG_FILTER:
137 * The deglitch filter interval is specified in nanoseconds.
138 * The hardware supports intervals in 200ns increments. Round
139 * the user values up and return the actual interval.
141 interval = (data[1] + 100) / 200;
142 data[1] = interval * 200;
145 ni6527_set_filter_interval(dev, interval);
146 devpriv->filter_enable |= 1 << chan;
148 devpriv->filter_enable &= ~(1 << chan);
150 ni6527_set_filter_enable(dev, devpriv->filter_enable);
159 static int ni6527_di_insn_bits(struct comedi_device *dev,
160 struct comedi_subdevice *s,
161 struct comedi_insn *insn,
164 struct ni6527_private *devpriv = dev->private;
165 void __iomem *mmio = devpriv->mmio_base;
168 val = readb(mmio + NI6527_DI_REG(0));
169 val |= (readb(mmio + NI6527_DI_REG(1)) << 8);
170 val |= (readb(mmio + NI6527_DI_REG(2)) << 16);
177 static int ni6527_do_insn_bits(struct comedi_device *dev,
178 struct comedi_subdevice *s,
179 struct comedi_insn *insn,
182 struct ni6527_private *devpriv = dev->private;
183 void __iomem *mmio = devpriv->mmio_base;
186 mask = comedi_dio_update_state(s, data);
188 /* Outputs are inverted */
189 unsigned int val = s->state ^ 0xffffff;
192 writeb(val & 0xff, mmio + NI6527_DO_REG(0));
194 writeb((val >> 8) & 0xff, mmio + NI6527_DO_REG(1));
196 writeb((val >> 16) & 0xff, mmio + NI6527_DO_REG(2));
204 static irqreturn_t ni6527_interrupt(int irq, void *d)
206 struct comedi_device *dev = d;
207 struct ni6527_private *devpriv = dev->private;
208 struct comedi_subdevice *s = dev->read_subdev;
209 void __iomem *mmio = devpriv->mmio_base;
212 status = readb(mmio + NI6527_STATUS_REG);
213 if (!(status & NI6527_STATUS_IRQ))
216 if (status & NI6527_STATUS_EDGE) {
217 comedi_buf_put(s->async, 0);
218 s->async->events |= COMEDI_CB_EOS;
219 comedi_event(dev, s);
222 writeb(NI6527_CLR_IRQS, mmio + NI6527_CLR_REG);
227 static int ni6527_intr_cmdtest(struct comedi_device *dev,
228 struct comedi_subdevice *s,
229 struct comedi_cmd *cmd)
233 /* Step 1 : check if triggers are trivially valid */
235 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
236 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_OTHER);
237 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
238 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
239 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT);
244 /* Step 2a : make sure trigger sources are unique */
245 /* Step 2b : and mutually compatible */
250 /* Step 3: check if arguments are trivially valid */
252 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
253 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
254 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
255 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, 1);
256 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
261 /* step 4: fix up any arguments */
269 static int ni6527_intr_cmd(struct comedi_device *dev,
270 struct comedi_subdevice *s)
272 struct ni6527_private *devpriv = dev->private;
273 void __iomem *mmio = devpriv->mmio_base;
275 writeb(NI6527_CLR_IRQS, mmio + NI6527_CLR_REG);
276 writeb(NI6527_CTRL_ENABLE_IRQS, mmio + NI6527_CTRL_REG);
281 static int ni6527_intr_cancel(struct comedi_device *dev,
282 struct comedi_subdevice *s)
284 struct ni6527_private *devpriv = dev->private;
285 void __iomem *mmio = devpriv->mmio_base;
287 writeb(NI6527_CTRL_DISABLE_IRQS, mmio + NI6527_CTRL_REG);
292 static int ni6527_intr_insn_bits(struct comedi_device *dev,
293 struct comedi_subdevice *s,
294 struct comedi_insn *insn, unsigned int *data)
300 static void ni6527_set_edge_detection(struct comedi_device *dev,
302 unsigned int falling)
304 struct ni6527_private *devpriv = dev->private;
305 void __iomem *mmio = devpriv->mmio_base;
307 /* enable rising-edge detection channels */
308 writeb(rising & 0xff, mmio + NI6527_RISING_EDGE_REG(0));
309 writeb((rising >> 8) & 0xff, mmio + NI6527_RISING_EDGE_REG(1));
310 writeb((rising >> 16) & 0xff, mmio + NI6527_RISING_EDGE_REG(2));
312 /* enable falling-edge detection channels */
313 writeb(falling & 0xff, mmio + NI6527_FALLING_EDGE_REG(0));
314 writeb((falling >> 8) & 0xff, mmio + NI6527_FALLING_EDGE_REG(1));
315 writeb((falling >> 16) & 0xff, mmio + NI6527_FALLING_EDGE_REG(2));
318 static int ni6527_intr_insn_config(struct comedi_device *dev,
319 struct comedi_subdevice *s,
320 struct comedi_insn *insn,
324 case INSN_CONFIG_CHANGE_NOTIFY:
325 /* check_insn_config_length() does not check this instruction */
328 ni6527_set_edge_detection(dev, data[1], data[2]);
337 static void ni6527_reset(struct comedi_device *dev)
339 struct ni6527_private *devpriv = dev->private;
340 void __iomem *mmio = devpriv->mmio_base;
342 /* disable deglitch filters on all channels */
343 ni6527_set_filter_enable(dev, 0);
345 writeb(NI6527_CLR_IRQS | NI6527_CLR_RESET_FILT,
346 mmio + NI6527_CLR_REG);
347 writeb(NI6527_CTRL_DISABLE_IRQS, mmio + NI6527_CTRL_REG);
350 static int ni6527_auto_attach(struct comedi_device *dev,
351 unsigned long context)
353 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
354 const struct ni6527_board *board = NULL;
355 struct ni6527_private *devpriv;
356 struct comedi_subdevice *s;
359 if (context < ARRAY_SIZE(ni6527_boards))
360 board = &ni6527_boards[context];
363 dev->board_ptr = board;
364 dev->board_name = board->name;
366 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
370 ret = comedi_pci_enable(dev);
374 devpriv->mmio_base = pci_ioremap_bar(pcidev, 1);
375 if (!devpriv->mmio_base)
378 /* make sure this is actually a 6527 device */
379 if (readb(devpriv->mmio_base + NI6527_ID_REG) != 0x27)
384 ret = request_irq(pcidev->irq, ni6527_interrupt, IRQF_SHARED,
385 dev->board_name, dev);
387 dev->irq = pcidev->irq;
389 ret = comedi_alloc_subdevices(dev, 3);
393 /* Digital Input subdevice */
394 s = &dev->subdevices[0];
395 s->type = COMEDI_SUBD_DI;
396 s->subdev_flags = SDF_READABLE;
399 s->range_table = &range_digital;
400 s->insn_config = ni6527_di_insn_config;
401 s->insn_bits = ni6527_di_insn_bits;
403 /* Digital Output subdevice */
404 s = &dev->subdevices[1];
405 s->type = COMEDI_SUBD_DO;
406 s->subdev_flags = SDF_WRITABLE;
409 s->range_table = &range_digital;
410 s->insn_bits = ni6527_do_insn_bits;
412 /* Edge detection interrupt subdevice */
413 s = &dev->subdevices[2];
415 dev->read_subdev = s;
416 s->type = COMEDI_SUBD_DI;
417 s->subdev_flags = SDF_READABLE | SDF_CMD_READ;
420 s->range_table = &range_digital;
421 s->insn_config = ni6527_intr_insn_config;
422 s->insn_bits = ni6527_intr_insn_bits;
423 s->do_cmdtest = ni6527_intr_cmdtest;
424 s->do_cmd = ni6527_intr_cmd;
425 s->cancel = ni6527_intr_cancel;
427 s->type = COMEDI_SUBD_UNUSED;
433 static void ni6527_detach(struct comedi_device *dev)
435 struct ni6527_private *devpriv = dev->private;
437 if (devpriv && devpriv->mmio_base)
440 free_irq(dev->irq, dev);
441 comedi_pci_disable(dev);
444 static struct comedi_driver ni6527_driver = {
445 .driver_name = "ni_6527",
446 .module = THIS_MODULE,
447 .auto_attach = ni6527_auto_attach,
448 .detach = ni6527_detach,
451 static int ni6527_pci_probe(struct pci_dev *dev,
452 const struct pci_device_id *id)
454 return comedi_pci_auto_config(dev, &ni6527_driver, id->driver_data);
457 static DEFINE_PCI_DEVICE_TABLE(ni6527_pci_table) = {
458 { PCI_VDEVICE(NI, 0x2b10), BOARD_PXI6527 },
459 { PCI_VDEVICE(NI, 0x2b20), BOARD_PCI6527 },
462 MODULE_DEVICE_TABLE(pci, ni6527_pci_table);
464 static struct pci_driver ni6527_pci_driver = {
466 .id_table = ni6527_pci_table,
467 .probe = ni6527_pci_probe,
468 .remove = comedi_pci_auto_unconfig,
470 module_comedi_pci_driver(ni6527_driver, ni6527_pci_driver);
472 MODULE_AUTHOR("Comedi http://www.comedi.org");
473 MODULE_DESCRIPTION("Comedi low-level driver");
474 MODULE_LICENSE("GPL");