2 comedi/drivers/ni_6527.c
3 driver for National Instruments PCI-6527
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1999,2002,2003 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
20 Description: National Instruments 6527
23 Devices: [National Instruments] PCI-6527 (ni6527), PXI-6527
24 Updated: Sat, 25 Jan 2003 13:24:40 -0800
30 Manuals (available from ftp://ftp.natinst.com/support/manuals)
32 370106b.pdf 6527 Register Level Programmer Manual
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/interrupt.h>
40 #include "../comedidev.h"
42 #include "comedi_fc.h"
45 #define NI6527_DI_REG(x) (0x00 + (x))
46 #define NI6527_DO_REG(x) (0x03 + (x))
47 #define NI6527_ID_REG 0x06
48 #define NI6527_CLR_REG 0x07
49 #define NI6527_CLR_EDGE (1 << 3)
50 #define NI6527_CLR_OVERFLOW (1 << 2)
51 #define NI6527_CLR_FILT (1 << 1)
52 #define NI6527_CLR_INTERVAL (1 << 0)
53 #define NI6527_CLR_IRQS (NI6527_CLR_EDGE | NI6527_CLR_OVERFLOW)
54 #define NI6527_CLR_RESET_FILT (NI6527_CLR_FILT | NI6527_CLR_INTERVAL)
55 #define NI6527_FILT_INTERVAL_REG(x) (0x08 + (x))
56 #define NI6527_FILT_ENA_REG(x) (0x0c + (x))
57 #define NI6527_STATUS_REG 0x14
58 #define NI6527_STATUS_IRQ (1 << 2)
59 #define NI6527_STATUS_OVERFLOW (1 << 1)
60 #define NI6527_STATUS_EDGE (1 << 0)
61 #define NI6527_CTRL_REG 0x15
62 #define NI6527_CTRL_FALLING (1 << 4)
63 #define NI6527_CTRL_RISING (1 << 3)
64 #define NI6527_CTRL_IRQ (1 << 2)
65 #define NI6527_CTRL_OVERFLOW (1 << 1)
66 #define NI6527_CTRL_EDGE (1 << 0)
67 #define NI6527_CTRL_DISABLE_IRQS 0
68 #define NI6527_CTRL_ENABLE_IRQS (NI6527_CTRL_FALLING | \
69 NI6527_CTRL_RISING | \
70 NI6527_CTRL_IRQ | NI6527_CTRL_EDGE)
71 #define NI6527_RISING_EDGE_REG(x) (0x18 + (x))
72 #define NI6527_FALLING_EDGE_REG(x) (0x20 + (x))
83 static const struct ni6527_board ni6527_boards[] = {
92 struct ni6527_private {
93 struct mite_struct *mite;
94 unsigned int filter_interval;
95 unsigned int filter_enable;
98 static void ni6527_set_filter_interval(struct comedi_device *dev,
101 struct ni6527_private *devpriv = dev->private;
102 void __iomem *mmio = devpriv->mite->daq_io_addr;
104 if (val != devpriv->filter_interval) {
105 writeb(val & 0xff, mmio + NI6527_FILT_INTERVAL_REG(0));
106 writeb((val >> 8) & 0xff, mmio + NI6527_FILT_INTERVAL_REG(1));
107 writeb((val >> 16) & 0x0f, mmio + NI6527_FILT_INTERVAL_REG(2));
109 writeb(NI6527_CLR_INTERVAL, mmio + NI6527_CLR_REG);
111 devpriv->filter_interval = val;
115 static void ni6527_set_filter_enable(struct comedi_device *dev,
118 struct ni6527_private *devpriv = dev->private;
119 void __iomem *mmio = devpriv->mite->daq_io_addr;
121 writeb(val & 0xff, mmio + NI6527_FILT_ENA_REG(0));
122 writeb((val >> 8) & 0xff, mmio + NI6527_FILT_ENA_REG(1));
123 writeb((val >> 16) & 0xff, mmio + NI6527_FILT_ENA_REG(2));
126 static int ni6527_di_insn_config(struct comedi_device *dev,
127 struct comedi_subdevice *s,
128 struct comedi_insn *insn,
131 struct ni6527_private *devpriv = dev->private;
132 unsigned int chan = CR_CHAN(insn->chanspec);
133 unsigned int interval;
136 case INSN_CONFIG_FILTER:
138 * The deglitch filter interval is specified in nanoseconds.
139 * The hardware supports intervals in 200ns increments. Round
140 * the user values up and return the actual interval.
142 interval = (data[1] + 100) / 200;
143 data[1] = interval * 200;
146 ni6527_set_filter_interval(dev, interval);
147 devpriv->filter_enable |= 1 << chan;
149 devpriv->filter_enable &= ~(1 << chan);
151 ni6527_set_filter_enable(dev, devpriv->filter_enable);
160 static int ni6527_di_insn_bits(struct comedi_device *dev,
161 struct comedi_subdevice *s,
162 struct comedi_insn *insn,
165 struct ni6527_private *devpriv = dev->private;
166 void __iomem *mmio = devpriv->mite->daq_io_addr;
169 val = readb(mmio + NI6527_DI_REG(0));
170 val |= (readb(mmio + NI6527_DI_REG(1)) << 8);
171 val |= (readb(mmio + NI6527_DI_REG(2)) << 16);
178 static int ni6527_do_insn_bits(struct comedi_device *dev,
179 struct comedi_subdevice *s,
180 struct comedi_insn *insn,
183 struct ni6527_private *devpriv = dev->private;
184 void __iomem *mmio = devpriv->mite->daq_io_addr;
187 mask = comedi_dio_update_state(s, data);
189 /* Outputs are inverted */
190 unsigned int val = s->state ^ 0xffffff;
193 writeb(val & 0xff, mmio + NI6527_DO_REG(0));
195 writeb((val >> 8) & 0xff, mmio + NI6527_DO_REG(1));
197 writeb((val >> 16) & 0xff, mmio + NI6527_DO_REG(2));
205 static irqreturn_t ni6527_interrupt(int irq, void *d)
207 struct comedi_device *dev = d;
208 struct ni6527_private *devpriv = dev->private;
209 struct comedi_subdevice *s = dev->read_subdev;
210 void __iomem *mmio = devpriv->mite->daq_io_addr;
213 status = readb(mmio + NI6527_STATUS_REG);
214 if (!(status & NI6527_STATUS_IRQ))
217 if (status & NI6527_STATUS_EDGE) {
218 comedi_buf_put(s->async, 0);
219 s->async->events |= COMEDI_CB_EOS;
220 comedi_event(dev, s);
223 writeb(NI6527_CLR_IRQS, mmio + NI6527_CLR_REG);
228 static int ni6527_intr_cmdtest(struct comedi_device *dev,
229 struct comedi_subdevice *s,
230 struct comedi_cmd *cmd)
234 /* Step 1 : check if triggers are trivially valid */
236 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
237 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_OTHER);
238 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
239 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
240 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT);
245 /* Step 2a : make sure trigger sources are unique */
246 /* Step 2b : and mutually compatible */
251 /* Step 3: check if arguments are trivially valid */
253 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
254 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
255 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
256 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, 1);
257 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
262 /* step 4: fix up any arguments */
270 static int ni6527_intr_cmd(struct comedi_device *dev,
271 struct comedi_subdevice *s)
273 struct ni6527_private *devpriv = dev->private;
274 void __iomem *mmio = devpriv->mite->daq_io_addr;
276 writeb(NI6527_CLR_IRQS, mmio + NI6527_CLR_REG);
277 writeb(NI6527_CTRL_ENABLE_IRQS, mmio + NI6527_CTRL_REG);
282 static int ni6527_intr_cancel(struct comedi_device *dev,
283 struct comedi_subdevice *s)
285 struct ni6527_private *devpriv = dev->private;
286 void __iomem *mmio = devpriv->mite->daq_io_addr;
288 writeb(NI6527_CTRL_DISABLE_IRQS, mmio + NI6527_CTRL_REG);
293 static int ni6527_intr_insn_bits(struct comedi_device *dev,
294 struct comedi_subdevice *s,
295 struct comedi_insn *insn, unsigned int *data)
301 static void ni6527_set_edge_detection(struct comedi_device *dev,
303 unsigned int falling)
305 struct ni6527_private *devpriv = dev->private;
306 void __iomem *mmio = devpriv->mite->daq_io_addr;
308 /* enable rising-edge detection channels */
309 writeb(rising & 0xff, mmio + NI6527_RISING_EDGE_REG(0));
310 writeb((rising >> 8) & 0xff, mmio + NI6527_RISING_EDGE_REG(1));
311 writeb((rising >> 16) & 0xff, mmio + NI6527_RISING_EDGE_REG(2));
313 /* enable falling-edge detection channels */
314 writeb(falling & 0xff, mmio + NI6527_FALLING_EDGE_REG(0));
315 writeb((falling >> 8) & 0xff, mmio + NI6527_FALLING_EDGE_REG(1));
316 writeb((falling >> 16) & 0xff, mmio + NI6527_FALLING_EDGE_REG(2));
319 static int ni6527_intr_insn_config(struct comedi_device *dev,
320 struct comedi_subdevice *s,
321 struct comedi_insn *insn,
325 case INSN_CONFIG_CHANGE_NOTIFY:
326 /* check_insn_config_length() does not check this instruction */
329 ni6527_set_edge_detection(dev, data[1], data[2]);
338 static int ni6527_auto_attach(struct comedi_device *dev,
339 unsigned long context)
341 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
342 const struct ni6527_board *board = NULL;
343 struct ni6527_private *devpriv;
344 struct comedi_subdevice *s;
347 if (context < ARRAY_SIZE(ni6527_boards))
348 board = &ni6527_boards[context];
351 dev->board_ptr = board;
352 dev->board_name = board->name;
354 ret = comedi_pci_enable(dev);
358 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
362 devpriv->mite = mite_alloc(pcidev);
366 ret = mite_setup(devpriv->mite);
368 dev_err(dev->class_dev, "error setting up mite\n");
372 /* make sure this is actually a 6527 device */
373 if (readb(devpriv->mite->daq_io_addr + NI6527_ID_REG) != 0x27)
376 ret = comedi_alloc_subdevices(dev, 3);
380 s = &dev->subdevices[0];
381 s->type = COMEDI_SUBD_DI;
382 s->subdev_flags = SDF_READABLE;
384 s->range_table = &range_digital;
386 s->insn_config = ni6527_di_insn_config;
387 s->insn_bits = ni6527_di_insn_bits;
389 s = &dev->subdevices[1];
390 s->type = COMEDI_SUBD_DO;
391 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
393 s->range_table = &range_unknown; /* FIXME: actually conductance */
395 s->insn_bits = ni6527_do_insn_bits;
397 s = &dev->subdevices[2];
398 dev->read_subdev = s;
399 s->type = COMEDI_SUBD_DI;
400 s->subdev_flags = SDF_READABLE | SDF_CMD_READ;
402 s->range_table = &range_unknown;
404 s->do_cmdtest = ni6527_intr_cmdtest;
405 s->do_cmd = ni6527_intr_cmd;
406 s->cancel = ni6527_intr_cancel;
407 s->insn_bits = ni6527_intr_insn_bits;
408 s->insn_config = ni6527_intr_insn_config;
410 ni6527_set_filter_enable(dev, 0);
412 writeb(NI6527_CLR_IRQS | NI6527_CLR_RESET_FILT,
413 devpriv->mite->daq_io_addr + NI6527_CLR_REG);
414 writeb(NI6527_CTRL_DISABLE_IRQS,
415 devpriv->mite->daq_io_addr + NI6527_CTRL_REG);
417 ret = request_irq(mite_irq(devpriv->mite), ni6527_interrupt,
418 IRQF_SHARED, dev->board_name, dev);
420 dev_warn(dev->class_dev, "irq not available\n");
422 dev->irq = mite_irq(devpriv->mite);
427 static void ni6527_detach(struct comedi_device *dev)
429 struct ni6527_private *devpriv = dev->private;
431 if (devpriv && devpriv->mite && devpriv->mite->daq_io_addr)
432 writeb(NI6527_CTRL_DISABLE_IRQS,
433 devpriv->mite->daq_io_addr + NI6527_CTRL_REG);
435 free_irq(dev->irq, dev);
436 if (devpriv && devpriv->mite) {
437 mite_unsetup(devpriv->mite);
438 mite_free(devpriv->mite);
440 comedi_pci_disable(dev);
443 static struct comedi_driver ni6527_driver = {
444 .driver_name = "ni_6527",
445 .module = THIS_MODULE,
446 .auto_attach = ni6527_auto_attach,
447 .detach = ni6527_detach,
450 static int ni6527_pci_probe(struct pci_dev *dev,
451 const struct pci_device_id *id)
453 return comedi_pci_auto_config(dev, &ni6527_driver, id->driver_data);
456 static DEFINE_PCI_DEVICE_TABLE(ni6527_pci_table) = {
457 { PCI_VDEVICE(NI, 0x2b10), BOARD_PXI6527 },
458 { PCI_VDEVICE(NI, 0x2b20), BOARD_PCI6527 },
461 MODULE_DEVICE_TABLE(pci, ni6527_pci_table);
463 static struct pci_driver ni6527_pci_driver = {
465 .id_table = ni6527_pci_table,
466 .probe = ni6527_pci_probe,
467 .remove = comedi_pci_auto_unconfig,
469 module_comedi_pci_driver(ni6527_driver, ni6527_pci_driver);
471 MODULE_AUTHOR("Comedi http://www.comedi.org");
472 MODULE_DESCRIPTION("Comedi low-level driver");
473 MODULE_LICENSE("GPL");