3 * Comedi driver for National Instruments PCI-65xx static dio boards
5 * Copyright (C) 2006 Jon Grierson <jd@renko.co.uk>
6 * Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
8 * COMEDI - Linux Control and Measurement Device Interface
9 * Copyright (C) 1999,2002,2003 David A. Schleef <ds@schleef.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
24 * Description: National Instruments 65xx static dio boards
25 * Author: Jon Grierson <jd@renko.co.uk>,
26 * Frank Mori Hess <fmhess@users.sourceforge.net>
28 * Devices: (National Instruments) PCI-6509 [ni_65xx]
29 * (National Instruments) PXI-6509 [ni_65xx]
30 * (National Instruments) PCI-6510 [ni_65xx]
31 * (National Instruments) PCI-6511 [ni_65xx]
32 * (National Instruments) PXI-6511 [ni_65xx]
33 * (National Instruments) PCI-6512 [ni_65xx]
34 * (National Instruments) PXI-6512 [ni_65xx]
35 * (National Instruments) PCI-6513 [ni_65xx]
36 * (National Instruments) PXI-6513 [ni_65xx]
37 * (National Instruments) PCI-6514 [ni_65xx]
38 * (National Instruments) PXI-6514 [ni_65xx]
39 * (National Instruments) PCI-6515 [ni_65xx]
40 * (National Instruments) PXI-6515 [ni_65xx]
41 * (National Instruments) PCI-6516 [ni_65xx]
42 * (National Instruments) PCI-6517 [ni_65xx]
43 * (National Instruments) PCI-6518 [ni_65xx]
44 * (National Instruments) PCI-6519 [ni_65xx]
45 * (National Instruments) PCI-6520 [ni_65xx]
46 * (National Instruments) PCI-6521 [ni_65xx]
47 * (National Instruments) PXI-6521 [ni_65xx]
48 * (National Instruments) PCI-6528 [ni_65xx]
49 * (National Instruments) PXI-6528 [ni_65xx]
50 * Updated: Mon, 21 Jul 2014 12:49:58 +0000
52 * Configuration Options: not applicable, uses PCI auto config
54 * Based on the PCI-6527 driver by ds.
55 * The interrupt subdevice (subdevice 3) is probably broken for all
56 * boards except maybe the 6514.
58 * This driver previously inverted the outputs on PCI-6513 through to
59 * PCI-6519 and on PXI-6513 through to PXI-6515. It no longer inverts
60 * outputs on those cards by default as it didn't make much sense. If
61 * you require the outputs to be inverted on those cards for legacy
62 * reasons, set the module parameter "legacy_invert_outputs=true" when
63 * loading the module, or set "ni_65xx.legacy_invert_outputs=true" on
64 * the kernel command line if the driver is built in to the kernel.
68 * Manuals (available from ftp://ftp.natinst.com/support/manuals)
70 * 370106b.pdf 6514 Register Level Programmer Manual
73 #include <linux/module.h>
74 #include <linux/pci.h>
75 #include <linux/interrupt.h>
77 #include "../comedidev.h"
79 #include "comedi_fc.h"
82 * PCI BAR1 Register Map
85 /* Non-recurring Registers (8-bit except where noted) */
86 #define NI_65XX_ID_REG 0x00
87 #define NI_65XX_CLR_REG 0x01
88 #define NI_65XX_CLR_WDOG_INT (1 << 6)
89 #define NI_65XX_CLR_WDOG_PING (1 << 5)
90 #define NI_65XX_CLR_WDOG_EXP (1 << 4)
91 #define NI_65XX_CLR_EDGE_INT (1 << 3)
92 #define NI_65XX_CLR_OVERFLOW_INT (1 << 2)
93 #define NI_65XX_STATUS_REG 0x02
94 #define NI_65XX_STATUS_WDOG_INT (1 << 5)
95 #define NI_65XX_STATUS_FALL_EDGE (1 << 4)
96 #define NI_65XX_STATUS_RISE_EDGE (1 << 3)
97 #define NI_65XX_STATUS_INT (1 << 2)
98 #define NI_65XX_STATUS_OVERFLOW_INT (1 << 1)
99 #define NI_65XX_STATUS_EDGE_INT (1 << 0)
100 #define NI_65XX_CTRL_REG 0x03
101 #define NI_65XX_CTRL_WDOG_ENA (1 << 5)
102 #define NI_65XX_CTRL_FALL_EDGE_ENA (1 << 4)
103 #define NI_65XX_CTRL_RISE_EDGE_ENA (1 << 3)
104 #define NI_65XX_CTRL_INT_ENA (1 << 2)
105 #define NI_65XX_CTRL_OVERFLOW_ENA (1 << 1)
106 #define NI_65XX_CTRL_EDGE_ENA (1 << 0)
107 #define NI_65XX_REV_REG 0x04 /* 32-bit */
108 #define NI_65XX_FILTER_REG 0x08 /* 32-bit */
109 #define NI_65XX_RTSI_ROUTE_REG 0x0c /* 16-bit */
110 #define NI_65XX_RTSI_EDGE_REG 0x0e /* 16-bit */
111 #define NI_65XX_RTSI_WDOG_REG 0x10 /* 16-bit */
112 #define NI_65XX_RTSI_TRIG_REG 0x12 /* 16-bit */
113 #define NI_65XX_AUTO_CLK_SEL_REG 0x14 /* PXI-6528 only */
114 #define NI_65XX_AUTO_CLK_SEL_STATUS (1 << 1)
115 #define NI_65XX_AUTO_CLK_SEL_DISABLE (1 << 0)
116 #define NI_65XX_WDOG_CTRL_REG 0x15
117 #define NI_65XX_WDOG_CTRL_ENA (1 << 0)
118 #define NI_65XX_RTSI_CFG_REG 0x16
119 #define NI_65XX_RTSI_CFG_RISE_SENSE (1 << 2)
120 #define NI_65XX_RTSI_CFG_FALL_SENSE (1 << 1)
121 #define NI_65XX_RTSI_CFG_SYNC_DETECT (1 << 0)
122 #define NI_65XX_WDOG_STATUS_REG 0x17
123 #define NI_65XX_WDOG_STATUS_EXP (1 << 0)
124 #define NI_65XX_WDOG_INTERVAL_REG 0x18 /* 32-bit */
126 /* Recurring port registers (8-bit) */
127 #define NI_65XX_PORT(x) ((x) * 0x10)
128 #define NI_65XX_IO_DATA_REG(x) (0x40 + NI_65XX_PORT(x))
129 #define NI_65XX_IO_SEL_REG(x) (0x41 + NI_65XX_PORT(x))
130 #define NI_65XX_IO_SEL_OUTPUT (0 << 0)
131 #define NI_65XX_IO_SEL_INPUT (1 << 0)
132 #define NI_65XX_RISE_EDGE_ENA_REG(x) (0x42 + NI_65XX_PORT(x))
133 #define NI_65XX_FALL_EDGE_ENA_REG(x) (0x43 + NI_65XX_PORT(x))
134 #define NI_65XX_FILTER_ENA(x) (0x44 + NI_65XX_PORT(x))
135 #define NI_65XX_WDOG_HIZ_REG(x) (0x46 + NI_65XX_PORT(x))
136 #define NI_65XX_WDOG_ENA(x) (0x47 + NI_65XX_PORT(x))
137 #define NI_65XX_WDOG_HI_LO_REG(x) (0x48 + NI_65XX_PORT(x))
138 #define NI_65XX_RTSI_ENA(x) (0x49 + NI_65XX_PORT(x))
140 #define NI_65XX_PORT_TO_CHAN(x) ((x) * 8)
141 #define NI_65XX_CHAN_TO_PORT(x) ((x) / 8)
142 #define NI_65XX_CHAN_TO_MASK(x) (1 << ((x) % 8))
144 enum ni_65xx_boardid {
169 struct ni_65xx_board {
171 unsigned num_dio_ports;
172 unsigned num_di_ports;
173 unsigned num_do_ports;
174 unsigned legacy_invert:1;
177 static const struct ni_65xx_board ni_65xx_boards[] = {
289 static bool ni_65xx_legacy_invert_outputs;
290 module_param_named(legacy_invert_outputs, ni_65xx_legacy_invert_outputs,
292 MODULE_PARM_DESC(legacy_invert_outputs,
293 "invert outputs of PCI/PXI-6513/6514/6515/6516/6517/6518/6519 for compatibility with old user code");
295 struct ni_65xx_private {
299 static unsigned int ni_65xx_num_ports(struct comedi_device *dev)
301 const struct ni_65xx_board *board = comedi_board(dev);
303 return board->num_dio_ports + board->num_di_ports + board->num_do_ports;
306 static void ni_65xx_disable_input_filters(struct comedi_device *dev)
308 struct ni_65xx_private *devpriv = dev->private;
309 unsigned int num_ports = ni_65xx_num_ports(dev);
312 /* disable input filtering on all ports */
313 for (i = 0; i < num_ports; ++i)
314 writeb(0x00, devpriv->mmio + NI_65XX_FILTER_ENA(i));
316 /* set filter interval to 0 (32bit reg) */
317 writel(0x00000000, devpriv->mmio + NI_65XX_FILTER_REG);
320 /* updates edge detection for base_chan to base_chan+31 */
321 static void ni_65xx_update_edge_detection(struct comedi_device *dev,
322 unsigned int base_chan,
324 unsigned int falling)
326 struct ni_65xx_private *devpriv = dev->private;
327 unsigned int num_ports = ni_65xx_num_ports(dev);
330 if (base_chan >= NI_65XX_PORT_TO_CHAN(num_ports))
333 for (port = NI_65XX_CHAN_TO_PORT(base_chan); port < num_ports; port++) {
334 int bitshift = (int)(NI_65XX_PORT_TO_CHAN(port) - base_chan);
335 unsigned int port_mask, port_rising, port_falling;
341 port_mask = ~0U >> bitshift;
342 port_rising = rising >> bitshift;
343 port_falling = falling >> bitshift;
345 port_mask = ~0U << -bitshift;
346 port_rising = rising << -bitshift;
347 port_falling = falling << -bitshift;
349 if (port_mask & 0xff) {
350 if (~port_mask & 0xff) {
352 readb(devpriv->mmio +
353 NI_65XX_RISE_EDGE_ENA_REG(port)) &
356 readb(devpriv->mmio +
357 NI_65XX_FALL_EDGE_ENA_REG(port)) &
360 writeb(port_rising & 0xff,
361 devpriv->mmio + NI_65XX_RISE_EDGE_ENA_REG(port));
362 writeb(port_falling & 0xff,
363 devpriv->mmio + NI_65XX_FALL_EDGE_ENA_REG(port));
368 static int ni_65xx_dio_insn_config(struct comedi_device *dev,
369 struct comedi_subdevice *s,
370 struct comedi_insn *insn,
373 struct ni_65xx_private *devpriv = dev->private;
374 unsigned long base_port = (unsigned long)s->private;
375 unsigned int chan = CR_CHAN(insn->chanspec);
376 unsigned int chan_mask = NI_65XX_CHAN_TO_MASK(chan);
377 unsigned port = base_port + NI_65XX_CHAN_TO_PORT(chan);
378 unsigned int interval;
382 case INSN_CONFIG_FILTER:
384 * The deglitch filter interval is specified in nanoseconds.
385 * The hardware supports intervals in 200ns increments. Round
386 * the user values up and return the actual interval.
388 interval = (data[1] + 100) / 200;
389 if (interval > 0xfffff)
391 data[1] = interval * 200;
394 * Enable/disable the channel for deglitch filtering. Note
395 * that the filter interval is never set to '0'. This is done
396 * because other channels might still be enabled for filtering.
398 val = readb(devpriv->mmio + NI_65XX_FILTER_ENA(port));
400 writel(interval, devpriv->mmio + NI_65XX_FILTER_REG);
405 writeb(val, devpriv->mmio + NI_65XX_FILTER_ENA(port));
408 case INSN_CONFIG_DIO_OUTPUT:
409 if (s->type != COMEDI_SUBD_DIO)
411 writeb(NI_65XX_IO_SEL_OUTPUT,
412 devpriv->mmio + NI_65XX_IO_SEL_REG(port));
415 case INSN_CONFIG_DIO_INPUT:
416 if (s->type != COMEDI_SUBD_DIO)
418 writeb(NI_65XX_IO_SEL_INPUT,
419 devpriv->mmio + NI_65XX_IO_SEL_REG(port));
422 case INSN_CONFIG_DIO_QUERY:
423 if (s->type != COMEDI_SUBD_DIO)
425 val = readb(devpriv->mmio + NI_65XX_IO_SEL_REG(port));
426 data[1] = (val == NI_65XX_IO_SEL_INPUT) ? COMEDI_INPUT
437 static int ni_65xx_dio_insn_bits(struct comedi_device *dev,
438 struct comedi_subdevice *s,
439 struct comedi_insn *insn,
442 struct ni_65xx_private *devpriv = dev->private;
443 unsigned long base_port = (unsigned long)s->private;
444 unsigned int base_chan = CR_CHAN(insn->chanspec);
445 int last_port_offset = NI_65XX_CHAN_TO_PORT(s->n_chan - 1);
446 unsigned read_bits = 0;
449 for (port_offset = NI_65XX_CHAN_TO_PORT(base_chan);
450 port_offset <= last_port_offset; port_offset++) {
451 unsigned port = base_port + port_offset;
452 int base_port_channel = NI_65XX_PORT_TO_CHAN(port_offset);
453 unsigned port_mask, port_data, bits;
454 int bitshift = base_port_channel - base_chan;
461 port_mask >>= bitshift;
462 port_data >>= bitshift;
464 port_mask <<= -bitshift;
465 port_data <<= -bitshift;
470 /* update the outputs */
472 bits = readb(devpriv->mmio + NI_65XX_IO_DATA_REG(port));
473 bits ^= s->io_bits; /* invert if necessary */
475 bits |= (port_data & port_mask);
476 bits ^= s->io_bits; /* invert back */
477 writeb(bits, devpriv->mmio + NI_65XX_IO_DATA_REG(port));
480 /* read back the actual state */
481 bits = readb(devpriv->mmio + NI_65XX_IO_DATA_REG(port));
482 bits ^= s->io_bits; /* invert if necessary */
494 static irqreturn_t ni_65xx_interrupt(int irq, void *d)
496 struct comedi_device *dev = d;
497 struct ni_65xx_private *devpriv = dev->private;
498 struct comedi_subdevice *s = dev->read_subdev;
501 status = readb(devpriv->mmio + NI_65XX_STATUS_REG);
502 if ((status & NI_65XX_STATUS_INT) == 0)
504 if ((status & NI_65XX_STATUS_EDGE_INT) == 0)
507 writeb(NI_65XX_CLR_EDGE_INT | NI_65XX_CLR_OVERFLOW_INT,
508 devpriv->mmio + NI_65XX_CLR_REG);
510 comedi_buf_put(s, 0);
511 s->async->events |= COMEDI_CB_EOS;
512 comedi_event(dev, s);
516 static int ni_65xx_intr_cmdtest(struct comedi_device *dev,
517 struct comedi_subdevice *s,
518 struct comedi_cmd *cmd)
522 /* Step 1 : check if triggers are trivially valid */
524 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
525 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_OTHER);
526 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
527 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
528 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT);
533 /* Step 2a : make sure trigger sources are unique */
534 /* Step 2b : and mutually compatible */
539 /* Step 3: check if arguments are trivially valid */
541 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
542 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
543 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
544 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
545 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
550 /* step 4: fix up any arguments */
558 static int ni_65xx_intr_cmd(struct comedi_device *dev,
559 struct comedi_subdevice *s)
561 struct ni_65xx_private *devpriv = dev->private;
563 writeb(NI_65XX_CLR_EDGE_INT | NI_65XX_CLR_OVERFLOW_INT,
564 devpriv->mmio + NI_65XX_CLR_REG);
565 writeb(NI_65XX_CTRL_FALL_EDGE_ENA | NI_65XX_CTRL_RISE_EDGE_ENA |
566 NI_65XX_CTRL_INT_ENA | NI_65XX_CTRL_EDGE_ENA,
567 devpriv->mmio + NI_65XX_CTRL_REG);
572 static int ni_65xx_intr_cancel(struct comedi_device *dev,
573 struct comedi_subdevice *s)
575 struct ni_65xx_private *devpriv = dev->private;
577 writeb(0x00, devpriv->mmio + NI_65XX_CTRL_REG);
582 static int ni_65xx_intr_insn_bits(struct comedi_device *dev,
583 struct comedi_subdevice *s,
584 struct comedi_insn *insn,
591 static int ni_65xx_intr_insn_config(struct comedi_device *dev,
592 struct comedi_subdevice *s,
593 struct comedi_insn *insn,
597 case INSN_CONFIG_CHANGE_NOTIFY:
598 /* add instruction to check_insn_config_length() */
603 * This only works for the first 4 ports (32 channels)!
605 ni_65xx_update_edge_detection(dev, 0, data[1], data[2]);
614 /* ripped from mite.h and mite_setup2() to avoid mite dependancy */
615 #define MITE_IODWBSR 0xc0 /* IO Device Window Base Size Register */
616 #define WENAB (1 << 7) /* window enable */
618 static int ni_65xx_mite_init(struct pci_dev *pcidev)
620 void __iomem *mite_base;
623 /* ioremap the MITE registers (BAR 0) temporarily */
624 mite_base = pci_ioremap_bar(pcidev, 0);
628 /* set data window to main registers (BAR 1) */
629 main_phys_addr = pci_resource_start(pcidev, 1);
630 writel(main_phys_addr | WENAB, mite_base + MITE_IODWBSR);
632 /* finished with MITE registers */
637 static int ni_65xx_auto_attach(struct comedi_device *dev,
638 unsigned long context)
640 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
641 const struct ni_65xx_board *board = NULL;
642 struct ni_65xx_private *devpriv;
643 struct comedi_subdevice *s;
647 if (context < ARRAY_SIZE(ni_65xx_boards))
648 board = &ni_65xx_boards[context];
651 dev->board_ptr = board;
652 dev->board_name = board->name;
654 ret = comedi_pci_enable(dev);
658 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
662 ret = ni_65xx_mite_init(pcidev);
666 devpriv->mmio = pci_ioremap_bar(pcidev, 1);
670 writeb(NI_65XX_CLR_EDGE_INT | NI_65XX_CLR_OVERFLOW_INT,
671 devpriv->mmio + NI_65XX_CLR_REG);
672 writeb(0x00, devpriv->mmio + NI_65XX_CTRL_REG);
675 ret = request_irq(pcidev->irq, ni_65xx_interrupt, IRQF_SHARED,
676 dev->board_name, dev);
678 dev->irq = pcidev->irq;
681 dev_info(dev->class_dev, "board: %s, ID=0x%02x", dev->board_name,
682 readb(devpriv->mmio + NI_65XX_ID_REG));
684 ret = comedi_alloc_subdevices(dev, 4);
688 s = &dev->subdevices[0];
689 if (board->num_di_ports) {
690 s->type = COMEDI_SUBD_DI;
691 s->subdev_flags = SDF_READABLE;
692 s->n_chan = NI_65XX_PORT_TO_CHAN(board->num_di_ports);
694 s->range_table = &range_digital;
695 s->insn_bits = ni_65xx_dio_insn_bits;
696 s->insn_config = ni_65xx_dio_insn_config;
698 /* the input ports always start at port 0 */
699 s->private = (void *)0;
701 s->type = COMEDI_SUBD_UNUSED;
704 s = &dev->subdevices[1];
705 if (board->num_do_ports) {
706 s->type = COMEDI_SUBD_DO;
707 s->subdev_flags = SDF_WRITABLE;
708 s->n_chan = NI_65XX_PORT_TO_CHAN(board->num_do_ports);
710 s->range_table = &range_digital;
711 s->insn_bits = ni_65xx_dio_insn_bits;
713 /* the output ports always start after the input ports */
714 s->private = (void *)(unsigned long)board->num_di_ports;
717 * Use the io_bits to handle the inverted outputs. Inverted
718 * outputs are only supported if the "legacy_invert_outputs"
719 * module parameter is set to "true".
721 if (ni_65xx_legacy_invert_outputs && board->legacy_invert)
724 /* reset all output ports to comedi '0' */
725 for (i = 0; i < board->num_do_ports; ++i) {
726 writeb(s->io_bits, /* inverted if necessary */
728 NI_65XX_IO_DATA_REG(board->num_di_ports + i));
731 s->type = COMEDI_SUBD_UNUSED;
734 s = &dev->subdevices[2];
735 if (board->num_dio_ports) {
736 s->type = COMEDI_SUBD_DIO;
737 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
738 s->n_chan = NI_65XX_PORT_TO_CHAN(board->num_dio_ports);
740 s->range_table = &range_digital;
741 s->insn_bits = ni_65xx_dio_insn_bits;
742 s->insn_config = ni_65xx_dio_insn_config;
744 /* the input/output ports always start at port 0 */
745 s->private = (void *)0;
747 /* configure all ports for input */
748 for (i = 0; i < board->num_dio_ports; ++i) {
749 writeb(NI_65XX_IO_SEL_INPUT,
750 devpriv->mmio + NI_65XX_IO_SEL_REG(i));
753 s->type = COMEDI_SUBD_UNUSED;
756 s = &dev->subdevices[3];
757 s->type = COMEDI_SUBD_DI;
758 s->subdev_flags = SDF_READABLE;
761 s->range_table = &range_digital;
762 s->insn_bits = ni_65xx_intr_insn_bits;
764 dev->read_subdev = s;
765 s->subdev_flags |= SDF_CMD_READ;
767 s->insn_config = ni_65xx_intr_insn_config;
768 s->do_cmdtest = ni_65xx_intr_cmdtest;
769 s->do_cmd = ni_65xx_intr_cmd;
770 s->cancel = ni_65xx_intr_cancel;
773 ni_65xx_disable_input_filters(dev);
778 static void ni_65xx_detach(struct comedi_device *dev)
780 struct ni_65xx_private *devpriv = dev->private;
782 if (devpriv && devpriv->mmio) {
783 writeb(0x00, devpriv->mmio + NI_65XX_CTRL_REG);
784 iounmap(devpriv->mmio);
787 free_irq(dev->irq, dev);
788 comedi_pci_disable(dev);
791 static struct comedi_driver ni_65xx_driver = {
792 .driver_name = "ni_65xx",
793 .module = THIS_MODULE,
794 .auto_attach = ni_65xx_auto_attach,
795 .detach = ni_65xx_detach,
798 static int ni_65xx_pci_probe(struct pci_dev *dev,
799 const struct pci_device_id *id)
801 return comedi_pci_auto_config(dev, &ni_65xx_driver, id->driver_data);
804 static const struct pci_device_id ni_65xx_pci_table[] = {
805 { PCI_VDEVICE(NI, 0x1710), BOARD_PXI6509 },
806 { PCI_VDEVICE(NI, 0x7085), BOARD_PCI6509 },
807 { PCI_VDEVICE(NI, 0x7086), BOARD_PXI6528 },
808 { PCI_VDEVICE(NI, 0x7087), BOARD_PCI6515 },
809 { PCI_VDEVICE(NI, 0x7088), BOARD_PCI6514 },
810 { PCI_VDEVICE(NI, 0x70a9), BOARD_PCI6528 },
811 { PCI_VDEVICE(NI, 0x70c3), BOARD_PCI6511 },
812 { PCI_VDEVICE(NI, 0x70c8), BOARD_PCI6513 },
813 { PCI_VDEVICE(NI, 0x70c9), BOARD_PXI6515 },
814 { PCI_VDEVICE(NI, 0x70cc), BOARD_PCI6512 },
815 { PCI_VDEVICE(NI, 0x70cd), BOARD_PXI6514 },
816 { PCI_VDEVICE(NI, 0x70d1), BOARD_PXI6513 },
817 { PCI_VDEVICE(NI, 0x70d2), BOARD_PXI6512 },
818 { PCI_VDEVICE(NI, 0x70d3), BOARD_PXI6511 },
819 { PCI_VDEVICE(NI, 0x7124), BOARD_PCI6510 },
820 { PCI_VDEVICE(NI, 0x7125), BOARD_PCI6516 },
821 { PCI_VDEVICE(NI, 0x7126), BOARD_PCI6517 },
822 { PCI_VDEVICE(NI, 0x7127), BOARD_PCI6518 },
823 { PCI_VDEVICE(NI, 0x7128), BOARD_PCI6519 },
824 { PCI_VDEVICE(NI, 0x718b), BOARD_PCI6521 },
825 { PCI_VDEVICE(NI, 0x718c), BOARD_PXI6521 },
826 { PCI_VDEVICE(NI, 0x71c5), BOARD_PCI6520 },
829 MODULE_DEVICE_TABLE(pci, ni_65xx_pci_table);
831 static struct pci_driver ni_65xx_pci_driver = {
833 .id_table = ni_65xx_pci_table,
834 .probe = ni_65xx_pci_probe,
835 .remove = comedi_pci_auto_unconfig,
837 module_comedi_pci_driver(ni_65xx_driver, ni_65xx_pci_driver);
839 MODULE_AUTHOR("Comedi http://www.comedi.org");
840 MODULE_DESCRIPTION("Comedi driver for NI PCI-65xx static dio boards");
841 MODULE_LICENSE("GPL");