2 comedi/drivers/ni_6514.c
3 driver for National Instruments PCI-6514
5 Copyright (C) 2006 Jon Grierson <jd@renko.co.uk>
6 Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
8 COMEDI - Linux Control and Measurement Device Interface
9 Copyright (C) 1999,2002,2003 David A. Schleef <ds@schleef.org>
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
23 Description: National Instruments 65xx static dio boards
24 Author: Jon Grierson <jd@renko.co.uk>,
25 Frank Mori Hess <fmhess@users.sourceforge.net>
27 Devices: [National Instruments] PCI-6509 (ni_65xx), PXI-6509, PCI-6510,
28 PCI-6511, PXI-6511, PCI-6512, PXI-6512, PCI-6513, PXI-6513, PCI-6514,
29 PXI-6514, PCI-6515, PXI-6515, PCI-6516, PCI-6517, PCI-6518, PCI-6519,
30 PCI-6520, PCI-6521, PXI-6521, PCI-6528, PXI-6528
31 Updated: Wed Oct 18 08:59:11 EDT 2006
33 Based on the PCI-6527 driver by ds.
34 The interrupt subdevice (subdevice 3) is probably broken for all boards
35 except maybe the 6514.
40 Manuals (available from ftp://ftp.natinst.com/support/manuals)
42 370106b.pdf 6514 Register Level Programmer Manual
46 #include <linux/module.h>
47 #include <linux/pci.h>
48 #include <linux/interrupt.h>
50 #include "../comedidev.h"
52 #include "comedi_fc.h"
55 * PCI BAR1 Register Map
58 /* Non-recurring Registers (8-bit except where noted) */
59 #define NI_65XX_ID_REG 0x00
60 #define NI_65XX_CLR_REG 0x01
61 #define NI_65XX_CLR_WDOG_INT (1 << 6)
62 #define NI_65XX_CLR_WDOG_PING (1 << 5)
63 #define NI_65XX_CLR_WDOG_EXP (1 << 4)
64 #define NI_65XX_CLR_EDGE_INT (1 << 3)
65 #define NI_65XX_CLR_OVERFLOW_INT (1 << 2)
66 #define NI_65XX_STATUS_REG 0x02
67 #define NI_65XX_STATUS_WDOG_INT (1 << 5)
68 #define NI_65XX_STATUS_FALL_EDGE (1 << 4)
69 #define NI_65XX_STATUS_RISE_EDGE (1 << 3)
70 #define NI_65XX_STATUS_INT (1 << 2)
71 #define NI_65XX_STATUS_OVERFLOW_INT (1 << 1)
72 #define NI_65XX_STATUS_EDGE_INT (1 << 0)
73 #define NI_65XX_CTRL_REG 0x03
74 #define NI_65XX_CTRL_WDOG_ENA (1 << 5)
75 #define NI_65XX_CTRL_FALL_EDGE_ENA (1 << 4)
76 #define NI_65XX_CTRL_RISE_EDGE_ENA (1 << 3)
77 #define NI_65XX_CTRL_INT_ENA (1 << 2)
78 #define NI_65XX_CTRL_OVERFLOW_ENA (1 << 1)
79 #define NI_65XX_CTRL_EDGE_ENA (1 << 0)
80 #define NI_65XX_REV_REG 0x04 /* 32-bit */
81 #define NI_65XX_FILTER_REG 0x08 /* 32-bit */
82 #define NI_65XX_RTSI_ROUTE_REG 0x0c /* 16-bit */
83 #define NI_65XX_RTSI_EDGE_REG 0x0e /* 16-bit */
84 #define NI_65XX_RTSI_WDOG_REG 0x10 /* 16-bit */
85 #define NI_65XX_RTSI_TRIG_REG 0x12 /* 16-bit */
86 #define NI_65XX_AUTO_CLK_SEL_REG 0x14 /* PXI-6528 only */
87 #define NI_65XX_AUTO_CLK_SEL_STATUS (1 << 1)
88 #define NI_65XX_AUTO_CLK_SEL_DISABLE (1 << 0)
89 #define NI_65XX_WDOG_CTRL_REG 0x15
90 #define NI_65XX_WDOG_CTRL_ENA (1 << 0)
91 #define NI_65XX_RTSI_CFG_REG 0x16
92 #define NI_65XX_RTSI_CFG_RISE_SENSE (1 << 2)
93 #define NI_65XX_RTSI_CFG_FALL_SENSE (1 << 1)
94 #define NI_65XX_RTSI_CFG_SYNC_DETECT (1 << 0)
95 #define NI_65XX_WDOG_STATUS_REG 0x17
96 #define NI_65XX_WDOG_STATUS_EXP (1 << 0)
97 #define NI_65XX_WDOG_INTERVAL_REG 0x18 /* 32-bit */
99 /* Recurring port registers (8-bit) */
100 #define NI_65XX_PORT(x) ((x) * 0x10)
101 #define NI_65XX_IO_DATA_REG(x) (0x40 + NI_65XX_PORT(x))
102 #define NI_65XX_IO_SEL_REG(x) (0x41 + NI_65XX_PORT(x))
103 #define NI_65XX_IO_SEL_OUTPUT (0 << 0)
104 #define NI_65XX_IO_SEL_INPUT (1 << 0)
105 #define NI_65XX_RISE_EDGE_ENA_REG(x) (0x42 + NI_65XX_PORT(x))
106 #define NI_65XX_FALL_EDGE_ENA_REG(x) (0x43 + NI_65XX_PORT(x))
107 #define NI_65XX_FILTER_ENA(x) (0x44 + NI_65XX_PORT(x))
108 #define NI_65XX_WDOG_HIZ_REG(x) (0x46 + NI_65XX_PORT(x))
109 #define NI_65XX_WDOG_ENA(x) (0x47 + NI_65XX_PORT(x))
110 #define NI_65XX_WDOG_HI_LO_REG(x) (0x48 + NI_65XX_PORT(x))
111 #define NI_65XX_RTSI_ENA(x) (0x49 + NI_65XX_PORT(x))
113 #define NI_65XX_MAX_NUM_PORTS 12
114 static const unsigned ni_65xx_channels_per_port = 8;
116 enum ni_65xx_boardid {
141 struct ni_65xx_board {
143 unsigned num_dio_ports;
144 unsigned num_di_ports;
145 unsigned num_do_ports;
146 unsigned invert_outputs:1;
149 static const struct ni_65xx_board ni_65xx_boards[] = {
261 static inline unsigned ni_65xx_port_by_channel(unsigned channel)
263 return channel / ni_65xx_channels_per_port;
266 static inline unsigned ni_65xx_total_num_ports(const struct ni_65xx_board
269 return board->num_dio_ports + board->num_di_ports + board->num_do_ports;
272 struct ni_65xx_private {
274 unsigned short output_bits[NI_65XX_MAX_NUM_PORTS];
277 static int ni_65xx_dio_insn_config(struct comedi_device *dev,
278 struct comedi_subdevice *s,
279 struct comedi_insn *insn,
282 struct ni_65xx_private *devpriv = dev->private;
283 unsigned long base_port = (unsigned long)s->private;
284 unsigned int chan = CR_CHAN(insn->chanspec);
285 unsigned int chan_mask = 1 << (chan % ni_65xx_channels_per_port);
286 unsigned port = base_port + ni_65xx_port_by_channel(chan);
287 unsigned int interval;
291 case INSN_CONFIG_FILTER:
293 * The deglitch filter interval is specified in nanoseconds.
294 * The hardware supports intervals in 200ns increments. Round
295 * the user values up and return the actual interval.
297 interval = (data[1] + 100) / 200;
298 if (interval > 0xfffff)
300 data[1] = interval * 200;
303 * Enable/disable the channel for deglitch filtering. Note
304 * that the filter interval is never set to '0'. This is done
305 * because other channels might still be enabled for filtering.
307 val = readb(devpriv->mmio + NI_65XX_FILTER_ENA(port));
309 writel(interval, devpriv->mmio + NI_65XX_FILTER_REG);
314 writeb(val, devpriv->mmio + NI_65XX_FILTER_ENA(port));
317 case INSN_CONFIG_DIO_OUTPUT:
318 if (s->type != COMEDI_SUBD_DIO)
320 writeb(NI_65XX_IO_SEL_OUTPUT,
321 devpriv->mmio + NI_65XX_IO_SEL_REG(port));
324 case INSN_CONFIG_DIO_INPUT:
325 if (s->type != COMEDI_SUBD_DIO)
327 writeb(NI_65XX_IO_SEL_INPUT,
328 devpriv->mmio + NI_65XX_IO_SEL_REG(port));
331 case INSN_CONFIG_DIO_QUERY:
332 if (s->type != COMEDI_SUBD_DIO)
334 val = readb(devpriv->mmio + NI_65XX_IO_SEL_REG(port));
335 data[1] = (val == NI_65XX_IO_SEL_INPUT) ? COMEDI_INPUT
346 static int ni_65xx_dio_insn_bits(struct comedi_device *dev,
347 struct comedi_subdevice *s,
348 struct comedi_insn *insn, unsigned int *data)
350 const struct ni_65xx_board *board = comedi_board(dev);
351 unsigned long base_port = (unsigned long)s->private;
352 struct ni_65xx_private *devpriv = dev->private;
353 int base_bitfield_channel;
354 unsigned read_bits = 0;
355 int last_port_offset = ni_65xx_port_by_channel(s->n_chan - 1);
358 base_bitfield_channel = CR_CHAN(insn->chanspec);
359 for (port_offset = ni_65xx_port_by_channel(base_bitfield_channel);
360 port_offset <= last_port_offset; port_offset++) {
361 unsigned port = base_port + port_offset;
362 int base_port_channel = port_offset * ni_65xx_channels_per_port;
363 unsigned port_mask, port_data, port_read_bits;
364 int bitshift = base_port_channel - base_bitfield_channel;
371 port_mask >>= bitshift;
372 port_data >>= bitshift;
374 port_mask <<= -bitshift;
375 port_data <<= -bitshift;
381 devpriv->output_bits[port] &= ~port_mask;
382 devpriv->output_bits[port] |=
383 port_data & port_mask;
384 bits = devpriv->output_bits[port];
385 if (board->invert_outputs)
387 writeb(bits, devpriv->mmio + NI_65XX_IO_DATA_REG(port));
389 port_read_bits = readb(devpriv->mmio +
390 NI_65XX_IO_DATA_REG(port));
391 if (s->type == COMEDI_SUBD_DO && board->invert_outputs) {
392 /* Outputs inverted, so invert value read back from
393 * DO subdevice. (Does not apply to boards with DIO
395 port_read_bits ^= 0xFF;
398 port_read_bits <<= bitshift;
400 port_read_bits >>= -bitshift;
402 read_bits |= port_read_bits;
408 static irqreturn_t ni_65xx_interrupt(int irq, void *d)
410 struct comedi_device *dev = d;
411 struct ni_65xx_private *devpriv = dev->private;
412 struct comedi_subdevice *s = dev->read_subdev;
415 status = readb(devpriv->mmio + NI_65XX_STATUS_REG);
416 if ((status & NI_65XX_STATUS_INT) == 0)
418 if ((status & NI_65XX_STATUS_EDGE_INT) == 0)
421 writeb(NI_65XX_CLR_EDGE_INT | NI_65XX_CLR_OVERFLOW_INT,
422 devpriv->mmio + NI_65XX_CLR_REG);
424 comedi_buf_put(s, 0);
425 s->async->events |= COMEDI_CB_EOS;
426 comedi_event(dev, s);
430 static int ni_65xx_intr_cmdtest(struct comedi_device *dev,
431 struct comedi_subdevice *s,
432 struct comedi_cmd *cmd)
436 /* Step 1 : check if triggers are trivially valid */
438 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
439 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_OTHER);
440 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
441 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
442 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT);
447 /* Step 2a : make sure trigger sources are unique */
448 /* Step 2b : and mutually compatible */
453 /* Step 3: check if arguments are trivially valid */
455 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
456 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
457 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
458 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
459 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
464 /* step 4: fix up any arguments */
472 static int ni_65xx_intr_cmd(struct comedi_device *dev,
473 struct comedi_subdevice *s)
475 struct ni_65xx_private *devpriv = dev->private;
477 writeb(NI_65XX_CLR_EDGE_INT | NI_65XX_CLR_OVERFLOW_INT,
478 devpriv->mmio + NI_65XX_CLR_REG);
479 writeb(NI_65XX_CTRL_FALL_EDGE_ENA | NI_65XX_CTRL_RISE_EDGE_ENA |
480 NI_65XX_CTRL_INT_ENA | NI_65XX_CTRL_EDGE_ENA,
481 devpriv->mmio + NI_65XX_CTRL_REG);
486 static int ni_65xx_intr_cancel(struct comedi_device *dev,
487 struct comedi_subdevice *s)
489 struct ni_65xx_private *devpriv = dev->private;
491 writeb(0x00, devpriv->mmio + NI_65XX_CTRL_REG);
496 static int ni_65xx_intr_insn_bits(struct comedi_device *dev,
497 struct comedi_subdevice *s,
498 struct comedi_insn *insn, unsigned int *data)
504 static int ni_65xx_intr_insn_config(struct comedi_device *dev,
505 struct comedi_subdevice *s,
506 struct comedi_insn *insn,
509 struct ni_65xx_private *devpriv = dev->private;
513 if (data[0] != INSN_CONFIG_CHANGE_NOTIFY)
516 writeb(data[1], devpriv->mmio + NI_65XX_RISE_EDGE_ENA_REG(0));
517 writeb(data[1] >> 8, devpriv->mmio + NI_65XX_RISE_EDGE_ENA_REG(0x10));
518 writeb(data[1] >> 16, devpriv->mmio + NI_65XX_RISE_EDGE_ENA_REG(0x20));
519 writeb(data[1] >> 24, devpriv->mmio + NI_65XX_RISE_EDGE_ENA_REG(0x30));
521 writeb(data[2], devpriv->mmio + NI_65XX_FALL_EDGE_ENA_REG(0));
522 writeb(data[2] >> 8, devpriv->mmio + NI_65XX_FALL_EDGE_ENA_REG(0x10));
523 writeb(data[2] >> 16, devpriv->mmio + NI_65XX_FALL_EDGE_ENA_REG(0x20));
524 writeb(data[2] >> 24, devpriv->mmio + NI_65XX_FALL_EDGE_ENA_REG(0x30));
529 /* ripped from mite.h and mite_setup2() to avoid mite dependancy */
530 #define MITE_IODWBSR 0xc0 /* IO Device Window Base Size Register */
531 #define WENAB (1 << 7) /* window enable */
533 static int ni_65xx_mite_init(struct pci_dev *pcidev)
535 void __iomem *mite_base;
538 /* ioremap the MITE registers (BAR 0) temporarily */
539 mite_base = pci_ioremap_bar(pcidev, 0);
543 /* set data window to main registers (BAR 1) */
544 main_phys_addr = pci_resource_start(pcidev, 1);
545 writel(main_phys_addr | WENAB, mite_base + MITE_IODWBSR);
547 /* finished with MITE registers */
552 static int ni_65xx_auto_attach(struct comedi_device *dev,
553 unsigned long context)
555 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
556 const struct ni_65xx_board *board = NULL;
557 struct ni_65xx_private *devpriv;
558 struct comedi_subdevice *s;
562 if (context < ARRAY_SIZE(ni_65xx_boards))
563 board = &ni_65xx_boards[context];
566 dev->board_ptr = board;
567 dev->board_name = board->name;
569 ret = comedi_pci_enable(dev);
573 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
577 ret = ni_65xx_mite_init(pcidev);
581 devpriv->mmio = pci_ioremap_bar(pcidev, 1);
585 writeb(NI_65XX_CLR_EDGE_INT | NI_65XX_CLR_OVERFLOW_INT,
586 devpriv->mmio + NI_65XX_CLR_REG);
587 writeb(0x00, devpriv->mmio + NI_65XX_CTRL_REG);
590 ret = request_irq(pcidev->irq, ni_65xx_interrupt, IRQF_SHARED,
591 dev->board_name, dev);
593 dev->irq = pcidev->irq;
596 dev_info(dev->class_dev, "board: %s, ID=0x%02x", dev->board_name,
597 readb(devpriv->mmio + NI_65XX_ID_REG));
599 ret = comedi_alloc_subdevices(dev, 4);
603 s = &dev->subdevices[0];
604 if (board->num_di_ports) {
605 s->type = COMEDI_SUBD_DI;
606 s->subdev_flags = SDF_READABLE;
608 board->num_di_ports * ni_65xx_channels_per_port;
609 s->range_table = &range_digital;
611 s->insn_config = ni_65xx_dio_insn_config;
612 s->insn_bits = ni_65xx_dio_insn_bits;
614 /* the input ports always start at port 0 */
615 s->private = (void *)0;
617 s->type = COMEDI_SUBD_UNUSED;
620 s = &dev->subdevices[1];
621 if (board->num_do_ports) {
622 s->type = COMEDI_SUBD_DO;
623 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
625 board->num_do_ports * ni_65xx_channels_per_port;
626 s->range_table = &range_digital;
628 s->insn_bits = ni_65xx_dio_insn_bits;
630 /* the output ports always start after the input ports */
631 s->private = (void *)(unsigned long)board->num_di_ports;
633 s->type = COMEDI_SUBD_UNUSED;
636 s = &dev->subdevices[2];
637 if (board->num_dio_ports) {
638 s->type = COMEDI_SUBD_DIO;
639 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
641 board->num_dio_ports * ni_65xx_channels_per_port;
642 s->range_table = &range_digital;
644 s->insn_config = ni_65xx_dio_insn_config;
645 s->insn_bits = ni_65xx_dio_insn_bits;
647 /* the input/output ports always start at port 0 */
648 s->private = (void *)0;
650 /* configure all ports for input */
651 for (i = 0; i < board->num_dio_ports; ++i) {
652 writeb(NI_65XX_IO_SEL_INPUT,
653 devpriv->mmio + NI_65XX_IO_SEL_REG(i));
656 s->type = COMEDI_SUBD_UNUSED;
659 s = &dev->subdevices[3];
660 s->type = COMEDI_SUBD_DI;
661 s->subdev_flags = SDF_READABLE;
664 s->range_table = &range_digital;
665 s->insn_bits = ni_65xx_intr_insn_bits;
667 dev->read_subdev = s;
668 s->subdev_flags |= SDF_CMD_READ;
670 s->insn_config = ni_65xx_intr_insn_config;
671 s->do_cmdtest = ni_65xx_intr_cmdtest;
672 s->do_cmd = ni_65xx_intr_cmd;
673 s->cancel = ni_65xx_intr_cancel;
676 for (i = 0; i < ni_65xx_total_num_ports(board); ++i) {
677 writeb(0x00, devpriv->mmio + NI_65XX_FILTER_ENA(i));
678 if (board->invert_outputs)
679 writeb(0x01, devpriv->mmio + NI_65XX_IO_DATA_REG(i));
681 writeb(0x00, devpriv->mmio + NI_65XX_IO_DATA_REG(i));
684 /* Set filter interval to 0 (32bit reg) */
685 writel(0x00000000, devpriv->mmio + NI_65XX_FILTER_REG);
690 static void ni_65xx_detach(struct comedi_device *dev)
692 struct ni_65xx_private *devpriv = dev->private;
694 if (devpriv && devpriv->mmio) {
695 writeb(0x00, devpriv->mmio + NI_65XX_CTRL_REG);
696 iounmap(devpriv->mmio);
699 free_irq(dev->irq, dev);
700 comedi_pci_disable(dev);
703 static struct comedi_driver ni_65xx_driver = {
704 .driver_name = "ni_65xx",
705 .module = THIS_MODULE,
706 .auto_attach = ni_65xx_auto_attach,
707 .detach = ni_65xx_detach,
710 static int ni_65xx_pci_probe(struct pci_dev *dev,
711 const struct pci_device_id *id)
713 return comedi_pci_auto_config(dev, &ni_65xx_driver, id->driver_data);
716 static const struct pci_device_id ni_65xx_pci_table[] = {
717 { PCI_VDEVICE(NI, 0x1710), BOARD_PXI6509 },
718 { PCI_VDEVICE(NI, 0x7085), BOARD_PCI6509 },
719 { PCI_VDEVICE(NI, 0x7086), BOARD_PXI6528 },
720 { PCI_VDEVICE(NI, 0x7087), BOARD_PCI6515 },
721 { PCI_VDEVICE(NI, 0x7088), BOARD_PCI6514 },
722 { PCI_VDEVICE(NI, 0x70a9), BOARD_PCI6528 },
723 { PCI_VDEVICE(NI, 0x70c3), BOARD_PCI6511 },
724 { PCI_VDEVICE(NI, 0x70c8), BOARD_PCI6513 },
725 { PCI_VDEVICE(NI, 0x70c9), BOARD_PXI6515 },
726 { PCI_VDEVICE(NI, 0x70cc), BOARD_PCI6512 },
727 { PCI_VDEVICE(NI, 0x70cd), BOARD_PXI6514 },
728 { PCI_VDEVICE(NI, 0x70d1), BOARD_PXI6513 },
729 { PCI_VDEVICE(NI, 0x70d2), BOARD_PXI6512 },
730 { PCI_VDEVICE(NI, 0x70d3), BOARD_PXI6511 },
731 { PCI_VDEVICE(NI, 0x7124), BOARD_PCI6510 },
732 { PCI_VDEVICE(NI, 0x7125), BOARD_PCI6516 },
733 { PCI_VDEVICE(NI, 0x7126), BOARD_PCI6517 },
734 { PCI_VDEVICE(NI, 0x7127), BOARD_PCI6518 },
735 { PCI_VDEVICE(NI, 0x7128), BOARD_PCI6519 },
736 { PCI_VDEVICE(NI, 0x718b), BOARD_PCI6521 },
737 { PCI_VDEVICE(NI, 0x718c), BOARD_PXI6521 },
738 { PCI_VDEVICE(NI, 0x71c5), BOARD_PCI6520 },
741 MODULE_DEVICE_TABLE(pci, ni_65xx_pci_table);
743 static struct pci_driver ni_65xx_pci_driver = {
745 .id_table = ni_65xx_pci_table,
746 .probe = ni_65xx_pci_probe,
747 .remove = comedi_pci_auto_unconfig,
749 module_comedi_pci_driver(ni_65xx_driver, ni_65xx_pci_driver);
751 MODULE_AUTHOR("Comedi http://www.comedi.org");
752 MODULE_DESCRIPTION("Comedi low-level driver");
753 MODULE_LICENSE("GPL");