2 comedi/drivers/ni_6514.c
3 driver for National Instruments PCI-6514
5 Copyright (C) 2006 Jon Grierson <jd@renko.co.uk>
6 Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
8 COMEDI - Linux Control and Measurement Device Interface
9 Copyright (C) 1999,2002,2003 David A. Schleef <ds@schleef.org>
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
23 Description: National Instruments 65xx static dio boards
24 Author: Jon Grierson <jd@renko.co.uk>,
25 Frank Mori Hess <fmhess@users.sourceforge.net>
27 Devices: [National Instruments] PCI-6509 (ni_65xx), PXI-6509, PCI-6510,
28 PCI-6511, PXI-6511, PCI-6512, PXI-6512, PCI-6513, PXI-6513, PCI-6514,
29 PXI-6514, PCI-6515, PXI-6515, PCI-6516, PCI-6517, PCI-6518, PCI-6519,
30 PCI-6520, PCI-6521, PXI-6521, PCI-6528, PXI-6528
31 Updated: Wed Oct 18 08:59:11 EDT 2006
33 Based on the PCI-6527 driver by ds.
34 The interrupt subdevice (subdevice 3) is probably broken for all boards
35 except maybe the 6514.
40 Manuals (available from ftp://ftp.natinst.com/support/manuals)
42 370106b.pdf 6514 Register Level Programmer Manual
46 #include <linux/module.h>
47 #include <linux/pci.h>
48 #include <linux/interrupt.h>
50 #include "../comedidev.h"
52 #include "comedi_fc.h"
55 * PCI BAR1 Register Map
58 /* Non-recurring Registers (8-bit except where noted) */
59 #define NI_65XX_ID_REG 0x00
60 #define NI_65XX_CLR_REG 0x01
61 #define NI_65XX_CLR_WDOG_INT (1 << 6)
62 #define NI_65XX_CLR_WDOG_PING (1 << 5)
63 #define NI_65XX_CLR_WDOG_EXP (1 << 4)
64 #define NI_65XX_CLR_EDGE_INT (1 << 3)
65 #define NI_65XX_CLR_OVERFLOW_INT (1 << 2)
66 #define NI_65XX_STATUS_REG 0x02
67 #define NI_65XX_STATUS_WDOG_INT (1 << 5)
68 #define NI_65XX_STATUS_FALL_EDGE (1 << 4)
69 #define NI_65XX_STATUS_RISE_EDGE (1 << 3)
70 #define NI_65XX_STATUS_INT (1 << 2)
71 #define NI_65XX_STATUS_OVERFLOW_INT (1 << 1)
72 #define NI_65XX_STATUS_EDGE_INT (1 << 0)
73 #define NI_65XX_CTRL_REG 0x03
74 #define NI_65XX_CTRL_WDOG_ENA (1 << 5)
75 #define NI_65XX_CTRL_FALL_EDGE_ENA (1 << 4)
76 #define NI_65XX_CTRL_RISE_EDGE_ENA (1 << 3)
77 #define NI_65XX_CTRL_INT_ENA (1 << 2)
78 #define NI_65XX_CTRL_OVERFLOW_ENA (1 << 1)
79 #define NI_65XX_CTRL_EDGE_ENA (1 << 0)
80 #define NI_65XX_REV_REG 0x04 /* 32-bit */
81 #define NI_65XX_FILTER_REG 0x08 /* 32-bit */
82 #define NI_65XX_RTSI_ROUTE_REG 0x0c /* 16-bit */
83 #define NI_65XX_RTSI_EDGE_REG 0x0e /* 16-bit */
84 #define NI_65XX_RTSI_WDOG_REG 0x10 /* 16-bit */
85 #define NI_65XX_RTSI_TRIG_REG 0x12 /* 16-bit */
86 #define NI_65XX_AUTO_CLK_SEL_REG 0x14 /* PXI-6528 only */
87 #define NI_65XX_AUTO_CLK_SEL_STATUS (1 << 1)
88 #define NI_65XX_AUTO_CLK_SEL_DISABLE (1 << 0)
89 #define NI_65XX_WDOG_CTRL_REG 0x15
90 #define NI_65XX_WDOG_CTRL_ENA (1 << 0)
91 #define NI_65XX_RTSI_CFG_REG 0x16
92 #define NI_65XX_RTSI_CFG_RISE_SENSE (1 << 2)
93 #define NI_65XX_RTSI_CFG_FALL_SENSE (1 << 1)
94 #define NI_65XX_RTSI_CFG_SYNC_DETECT (1 << 0)
95 #define NI_65XX_WDOG_STATUS_REG 0x17
96 #define NI_65XX_WDOG_STATUS_EXP (1 << 0)
97 #define NI_65XX_WDOG_INTERVAL_REG 0x18 /* 32-bit */
99 /* Recurring port registers (8-bit) */
100 #define NI_65XX_PORT(x) ((x) * 0x10)
101 #define NI_65XX_IO_DATA_REG(x) (0x40 + NI_65XX_PORT(x))
102 #define NI_65XX_IO_SEL_REG(x) (0x41 + NI_65XX_PORT(x))
103 #define NI_65XX_IO_SEL_OUTPUT (0 << 0)
104 #define NI_65XX_IO_SEL_INPUT (1 << 0)
105 #define NI_65XX_RISE_EDGE_ENA_REG(x) (0x42 + NI_65XX_PORT(x))
106 #define NI_65XX_FALL_EDGE_ENA_REG(x) (0x43 + NI_65XX_PORT(x))
107 #define NI_65XX_FILTER_ENA(x) (0x44 + NI_65XX_PORT(x))
108 #define NI_65XX_WDOG_HIZ_REG(x) (0x46 + NI_65XX_PORT(x))
109 #define NI_65XX_WDOG_ENA(x) (0x47 + NI_65XX_PORT(x))
110 #define NI_65XX_WDOG_HI_LO_REG(x) (0x48 + NI_65XX_PORT(x))
111 #define NI_65XX_RTSI_ENA(x) (0x49 + NI_65XX_PORT(x))
113 #define NI_65XX_MAX_NUM_PORTS 12
114 static const unsigned ni_65xx_channels_per_port = 8;
116 enum ni_65xx_boardid {
141 struct ni_65xx_board {
143 unsigned num_dio_ports;
144 unsigned num_di_ports;
145 unsigned num_do_ports;
146 unsigned invert_outputs:1;
149 static const struct ni_65xx_board ni_65xx_boards[] = {
261 static inline unsigned ni_65xx_port_by_channel(unsigned channel)
263 return channel / ni_65xx_channels_per_port;
266 static inline unsigned ni_65xx_total_num_ports(const struct ni_65xx_board
269 return board->num_dio_ports + board->num_di_ports + board->num_do_ports;
272 struct ni_65xx_private {
274 unsigned int filter_interval;
275 unsigned short filter_enable[NI_65XX_MAX_NUM_PORTS];
276 unsigned short output_bits[NI_65XX_MAX_NUM_PORTS];
277 unsigned short dio_direction[NI_65XX_MAX_NUM_PORTS];
280 struct ni_65xx_subdevice_private {
284 static inline struct ni_65xx_subdevice_private *sprivate(struct comedi_subdevice
287 return subdev->private;
290 static int ni_65xx_config_filter(struct comedi_device *dev,
291 struct comedi_subdevice *s,
292 struct comedi_insn *insn, unsigned int *data)
294 struct ni_65xx_private *devpriv = dev->private;
295 const unsigned chan = CR_CHAN(insn->chanspec);
296 const unsigned port =
297 sprivate(s)->base_port + ni_65xx_port_by_channel(chan);
299 if (data[0] != INSN_CONFIG_FILTER)
302 static const unsigned filter_resolution_ns = 200;
303 static const unsigned max_filter_interval = 0xfffff;
306 (filter_resolution_ns / 2)) / filter_resolution_ns;
307 if (interval > max_filter_interval)
308 interval = max_filter_interval;
309 data[1] = interval * filter_resolution_ns;
311 if (interval != devpriv->filter_interval) {
312 writel(interval, devpriv->mmio + NI_65XX_FILTER_REG);
313 devpriv->filter_interval = interval;
316 devpriv->filter_enable[port] |=
317 1 << (chan % ni_65xx_channels_per_port);
319 devpriv->filter_enable[port] &=
320 ~(1 << (chan % ni_65xx_channels_per_port));
323 writeb(devpriv->filter_enable[port],
324 devpriv->mmio + NI_65XX_FILTER_ENA(port));
329 static int ni_65xx_dio_insn_config(struct comedi_device *dev,
330 struct comedi_subdevice *s,
331 struct comedi_insn *insn, unsigned int *data)
333 struct ni_65xx_private *devpriv = dev->private;
338 port = sprivate(s)->base_port +
339 ni_65xx_port_by_channel(CR_CHAN(insn->chanspec));
341 case INSN_CONFIG_FILTER:
342 return ni_65xx_config_filter(dev, s, insn, data);
344 case INSN_CONFIG_DIO_OUTPUT:
345 if (s->type != COMEDI_SUBD_DIO)
347 devpriv->dio_direction[port] = COMEDI_OUTPUT;
348 writeb(NI_65XX_IO_SEL_OUTPUT,
349 devpriv->mmio + NI_65XX_IO_SEL_REG(port));
352 case INSN_CONFIG_DIO_INPUT:
353 if (s->type != COMEDI_SUBD_DIO)
355 devpriv->dio_direction[port] = COMEDI_INPUT;
356 writeb(NI_65XX_IO_SEL_INPUT,
357 devpriv->mmio + NI_65XX_IO_SEL_REG(port));
360 case INSN_CONFIG_DIO_QUERY:
361 if (s->type != COMEDI_SUBD_DIO)
363 data[1] = devpriv->dio_direction[port];
372 static int ni_65xx_dio_insn_bits(struct comedi_device *dev,
373 struct comedi_subdevice *s,
374 struct comedi_insn *insn, unsigned int *data)
376 const struct ni_65xx_board *board = comedi_board(dev);
377 struct ni_65xx_private *devpriv = dev->private;
378 int base_bitfield_channel;
379 unsigned read_bits = 0;
380 int last_port_offset = ni_65xx_port_by_channel(s->n_chan - 1);
383 base_bitfield_channel = CR_CHAN(insn->chanspec);
384 for (port_offset = ni_65xx_port_by_channel(base_bitfield_channel);
385 port_offset <= last_port_offset; port_offset++) {
386 unsigned port = sprivate(s)->base_port + port_offset;
387 int base_port_channel = port_offset * ni_65xx_channels_per_port;
388 unsigned port_mask, port_data, port_read_bits;
389 int bitshift = base_port_channel - base_bitfield_channel;
396 port_mask >>= bitshift;
397 port_data >>= bitshift;
399 port_mask <<= -bitshift;
400 port_data <<= -bitshift;
406 devpriv->output_bits[port] &= ~port_mask;
407 devpriv->output_bits[port] |=
408 port_data & port_mask;
409 bits = devpriv->output_bits[port];
410 if (board->invert_outputs)
412 writeb(bits, devpriv->mmio + NI_65XX_IO_DATA_REG(port));
414 port_read_bits = readb(devpriv->mmio +
415 NI_65XX_IO_DATA_REG(port));
416 if (s->type == COMEDI_SUBD_DO && board->invert_outputs) {
417 /* Outputs inverted, so invert value read back from
418 * DO subdevice. (Does not apply to boards with DIO
420 port_read_bits ^= 0xFF;
423 port_read_bits <<= bitshift;
425 port_read_bits >>= -bitshift;
427 read_bits |= port_read_bits;
433 static irqreturn_t ni_65xx_interrupt(int irq, void *d)
435 struct comedi_device *dev = d;
436 struct ni_65xx_private *devpriv = dev->private;
437 struct comedi_subdevice *s = dev->read_subdev;
440 status = readb(devpriv->mmio + NI_65XX_STATUS_REG);
441 if ((status & NI_65XX_STATUS_INT) == 0)
443 if ((status & NI_65XX_STATUS_EDGE_INT) == 0)
446 writeb(NI_65XX_CLR_EDGE_INT | NI_65XX_CLR_OVERFLOW_INT,
447 devpriv->mmio + NI_65XX_CLR_REG);
449 comedi_buf_put(s, 0);
450 s->async->events |= COMEDI_CB_EOS;
451 comedi_event(dev, s);
455 static int ni_65xx_intr_cmdtest(struct comedi_device *dev,
456 struct comedi_subdevice *s,
457 struct comedi_cmd *cmd)
461 /* Step 1 : check if triggers are trivially valid */
463 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
464 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_OTHER);
465 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
466 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
467 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT);
472 /* Step 2a : make sure trigger sources are unique */
473 /* Step 2b : and mutually compatible */
478 /* Step 3: check if arguments are trivially valid */
480 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
481 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
482 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
483 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
484 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
489 /* step 4: fix up any arguments */
497 static int ni_65xx_intr_cmd(struct comedi_device *dev,
498 struct comedi_subdevice *s)
500 struct ni_65xx_private *devpriv = dev->private;
502 writeb(NI_65XX_CLR_EDGE_INT | NI_65XX_CLR_OVERFLOW_INT,
503 devpriv->mmio + NI_65XX_CLR_REG);
504 writeb(NI_65XX_CTRL_FALL_EDGE_ENA | NI_65XX_CTRL_RISE_EDGE_ENA |
505 NI_65XX_CTRL_INT_ENA | NI_65XX_CTRL_EDGE_ENA,
506 devpriv->mmio + NI_65XX_CTRL_REG);
511 static int ni_65xx_intr_cancel(struct comedi_device *dev,
512 struct comedi_subdevice *s)
514 struct ni_65xx_private *devpriv = dev->private;
516 writeb(0x00, devpriv->mmio + NI_65XX_CTRL_REG);
521 static int ni_65xx_intr_insn_bits(struct comedi_device *dev,
522 struct comedi_subdevice *s,
523 struct comedi_insn *insn, unsigned int *data)
529 static int ni_65xx_intr_insn_config(struct comedi_device *dev,
530 struct comedi_subdevice *s,
531 struct comedi_insn *insn,
534 struct ni_65xx_private *devpriv = dev->private;
538 if (data[0] != INSN_CONFIG_CHANGE_NOTIFY)
541 writeb(data[1], devpriv->mmio + NI_65XX_RISE_EDGE_ENA_REG(0));
542 writeb(data[1] >> 8, devpriv->mmio + NI_65XX_RISE_EDGE_ENA_REG(0x10));
543 writeb(data[1] >> 16, devpriv->mmio + NI_65XX_RISE_EDGE_ENA_REG(0x20));
544 writeb(data[1] >> 24, devpriv->mmio + NI_65XX_RISE_EDGE_ENA_REG(0x30));
546 writeb(data[2], devpriv->mmio + NI_65XX_FALL_EDGE_ENA_REG(0));
547 writeb(data[2] >> 8, devpriv->mmio + NI_65XX_FALL_EDGE_ENA_REG(0x10));
548 writeb(data[2] >> 16, devpriv->mmio + NI_65XX_FALL_EDGE_ENA_REG(0x20));
549 writeb(data[2] >> 24, devpriv->mmio + NI_65XX_FALL_EDGE_ENA_REG(0x30));
554 /* ripped from mite.h and mite_setup2() to avoid mite dependancy */
555 #define MITE_IODWBSR 0xc0 /* IO Device Window Base Size Register */
556 #define WENAB (1 << 7) /* window enable */
558 static int ni_65xx_mite_init(struct pci_dev *pcidev)
560 void __iomem *mite_base;
563 /* ioremap the MITE registers (BAR 0) temporarily */
564 mite_base = pci_ioremap_bar(pcidev, 0);
568 /* set data window to main registers (BAR 1) */
569 main_phys_addr = pci_resource_start(pcidev, 1);
570 writel(main_phys_addr | WENAB, mite_base + MITE_IODWBSR);
572 /* finished with MITE registers */
577 static int ni_65xx_auto_attach(struct comedi_device *dev,
578 unsigned long context)
580 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
581 const struct ni_65xx_board *board = NULL;
582 struct ni_65xx_private *devpriv;
583 struct ni_65xx_subdevice_private *spriv;
584 struct comedi_subdevice *s;
588 if (context < ARRAY_SIZE(ni_65xx_boards))
589 board = &ni_65xx_boards[context];
592 dev->board_ptr = board;
593 dev->board_name = board->name;
595 ret = comedi_pci_enable(dev);
599 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
603 ret = ni_65xx_mite_init(pcidev);
607 devpriv->mmio = pci_ioremap_bar(pcidev, 1);
611 dev->irq = pcidev->irq;
612 dev_info(dev->class_dev, "board: %s, ID=0x%02x", dev->board_name,
613 readb(devpriv->mmio + NI_65XX_ID_REG));
615 ret = comedi_alloc_subdevices(dev, 4);
619 s = &dev->subdevices[0];
620 if (board->num_di_ports) {
621 s->type = COMEDI_SUBD_DI;
622 s->subdev_flags = SDF_READABLE;
624 board->num_di_ports * ni_65xx_channels_per_port;
625 s->range_table = &range_digital;
627 s->insn_config = ni_65xx_dio_insn_config;
628 s->insn_bits = ni_65xx_dio_insn_bits;
629 spriv = comedi_alloc_spriv(s, sizeof(*spriv));
632 spriv->base_port = 0;
634 s->type = COMEDI_SUBD_UNUSED;
637 s = &dev->subdevices[1];
638 if (board->num_do_ports) {
639 s->type = COMEDI_SUBD_DO;
640 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
642 board->num_do_ports * ni_65xx_channels_per_port;
643 s->range_table = &range_digital;
645 s->insn_bits = ni_65xx_dio_insn_bits;
646 spriv = comedi_alloc_spriv(s, sizeof(*spriv));
649 spriv->base_port = board->num_di_ports;
651 s->type = COMEDI_SUBD_UNUSED;
654 s = &dev->subdevices[2];
655 if (board->num_dio_ports) {
656 s->type = COMEDI_SUBD_DIO;
657 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
659 board->num_dio_ports * ni_65xx_channels_per_port;
660 s->range_table = &range_digital;
662 s->insn_config = ni_65xx_dio_insn_config;
663 s->insn_bits = ni_65xx_dio_insn_bits;
664 spriv = comedi_alloc_spriv(s, sizeof(*spriv));
667 spriv->base_port = 0;
668 /* configure all ports for input */
669 for (i = 0; i < board->num_dio_ports; ++i) {
670 writeb(NI_65XX_IO_SEL_INPUT,
671 devpriv->mmio + NI_65XX_IO_SEL_REG(i));
674 s->type = COMEDI_SUBD_UNUSED;
677 s = &dev->subdevices[3];
678 dev->read_subdev = s;
679 s->type = COMEDI_SUBD_DI;
680 s->subdev_flags = SDF_READABLE | SDF_CMD_READ;
682 s->range_table = &range_unknown;
685 s->do_cmdtest = ni_65xx_intr_cmdtest;
686 s->do_cmd = ni_65xx_intr_cmd;
687 s->cancel = ni_65xx_intr_cancel;
688 s->insn_bits = ni_65xx_intr_insn_bits;
689 s->insn_config = ni_65xx_intr_insn_config;
691 for (i = 0; i < ni_65xx_total_num_ports(board); ++i) {
692 writeb(0x00, devpriv->mmio + NI_65XX_FILTER_ENA(i));
693 if (board->invert_outputs)
694 writeb(0x01, devpriv->mmio + NI_65XX_IO_DATA_REG(i));
696 writeb(0x00, devpriv->mmio + NI_65XX_IO_DATA_REG(i));
698 writeb(NI_65XX_CLR_EDGE_INT | NI_65XX_CLR_OVERFLOW_INT,
699 devpriv->mmio + NI_65XX_CLR_REG);
700 writeb(0x00, devpriv->mmio + NI_65XX_CTRL_REG);
702 /* Set filter interval to 0 (32bit reg) */
703 writel(0x00000000, devpriv->mmio + NI_65XX_FILTER_REG);
705 ret = request_irq(dev->irq, ni_65xx_interrupt, IRQF_SHARED,
709 dev_warn(dev->class_dev, "irq not available\n");
715 static void ni_65xx_detach(struct comedi_device *dev)
717 struct ni_65xx_private *devpriv = dev->private;
719 if (devpriv && devpriv->mmio) {
720 writeb(0x00, devpriv->mmio + NI_65XX_CTRL_REG);
721 iounmap(devpriv->mmio);
724 free_irq(dev->irq, dev);
725 comedi_pci_disable(dev);
728 static struct comedi_driver ni_65xx_driver = {
729 .driver_name = "ni_65xx",
730 .module = THIS_MODULE,
731 .auto_attach = ni_65xx_auto_attach,
732 .detach = ni_65xx_detach,
735 static int ni_65xx_pci_probe(struct pci_dev *dev,
736 const struct pci_device_id *id)
738 return comedi_pci_auto_config(dev, &ni_65xx_driver, id->driver_data);
741 static const struct pci_device_id ni_65xx_pci_table[] = {
742 { PCI_VDEVICE(NI, 0x1710), BOARD_PXI6509 },
743 { PCI_VDEVICE(NI, 0x7085), BOARD_PCI6509 },
744 { PCI_VDEVICE(NI, 0x7086), BOARD_PXI6528 },
745 { PCI_VDEVICE(NI, 0x7087), BOARD_PCI6515 },
746 { PCI_VDEVICE(NI, 0x7088), BOARD_PCI6514 },
747 { PCI_VDEVICE(NI, 0x70a9), BOARD_PCI6528 },
748 { PCI_VDEVICE(NI, 0x70c3), BOARD_PCI6511 },
749 { PCI_VDEVICE(NI, 0x70c8), BOARD_PCI6513 },
750 { PCI_VDEVICE(NI, 0x70c9), BOARD_PXI6515 },
751 { PCI_VDEVICE(NI, 0x70cc), BOARD_PCI6512 },
752 { PCI_VDEVICE(NI, 0x70cd), BOARD_PXI6514 },
753 { PCI_VDEVICE(NI, 0x70d1), BOARD_PXI6513 },
754 { PCI_VDEVICE(NI, 0x70d2), BOARD_PXI6512 },
755 { PCI_VDEVICE(NI, 0x70d3), BOARD_PXI6511 },
756 { PCI_VDEVICE(NI, 0x7124), BOARD_PCI6510 },
757 { PCI_VDEVICE(NI, 0x7125), BOARD_PCI6516 },
758 { PCI_VDEVICE(NI, 0x7126), BOARD_PCI6517 },
759 { PCI_VDEVICE(NI, 0x7127), BOARD_PCI6518 },
760 { PCI_VDEVICE(NI, 0x7128), BOARD_PCI6519 },
761 { PCI_VDEVICE(NI, 0x718b), BOARD_PCI6521 },
762 { PCI_VDEVICE(NI, 0x718c), BOARD_PXI6521 },
763 { PCI_VDEVICE(NI, 0x71c5), BOARD_PCI6520 },
766 MODULE_DEVICE_TABLE(pci, ni_65xx_pci_table);
768 static struct pci_driver ni_65xx_pci_driver = {
770 .id_table = ni_65xx_pci_table,
771 .probe = ni_65xx_pci_probe,
772 .remove = comedi_pci_auto_unconfig,
774 module_comedi_pci_driver(ni_65xx_driver, ni_65xx_pci_driver);
776 MODULE_AUTHOR("Comedi http://www.comedi.org");
777 MODULE_DESCRIPTION("Comedi low-level driver");
778 MODULE_LICENSE("GPL");