3 * Comedi driver for National Instruments PCI-65xx static dio boards
5 * Copyright (C) 2006 Jon Grierson <jd@renko.co.uk>
6 * Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
8 * COMEDI - Linux Control and Measurement Device Interface
9 * Copyright (C) 1999,2002,2003 David A. Schleef <ds@schleef.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
24 * Description: National Instruments 65xx static dio boards
25 * Author: Jon Grierson <jd@renko.co.uk>,
26 * Frank Mori Hess <fmhess@users.sourceforge.net>
28 * Devices: (National Instruments) PCI-6509 [ni_65xx]
29 * (National Instruments) PXI-6509 [ni_65xx]
30 * (National Instruments) PCI-6510 [ni_65xx]
31 * (National Instruments) PCI-6511 [ni_65xx]
32 * (National Instruments) PXI-6511 [ni_65xx]
33 * (National Instruments) PCI-6512 [ni_65xx]
34 * (National Instruments) PXI-6512 [ni_65xx]
35 * (National Instruments) PCI-6513 [ni_65xx]
36 * (National Instruments) PXI-6513 [ni_65xx]
37 * (National Instruments) PCI-6514 [ni_65xx]
38 * (National Instruments) PXI-6514 [ni_65xx]
39 * (National Instruments) PCI-6515 [ni_65xx]
40 * (National Instruments) PXI-6515 [ni_65xx]
41 * (National Instruments) PCI-6516 [ni_65xx]
42 * (National Instruments) PCI-6517 [ni_65xx]
43 * (National Instruments) PCI-6518 [ni_65xx]
44 * (National Instruments) PCI-6519 [ni_65xx]
45 * (National Instruments) PCI-6520 [ni_65xx]
46 * (National Instruments) PCI-6521 [ni_65xx]
47 * (National Instruments) PXI-6521 [ni_65xx]
48 * (National Instruments) PCI-6528 [ni_65xx]
49 * (National Instruments) PXI-6528 [ni_65xx]
50 * Updated: Mon, 21 Jul 2014 12:49:58 +0000
52 * Configuration Options: not applicable, uses PCI auto config
54 * Based on the PCI-6527 driver by ds.
55 * The interrupt subdevice (subdevice 3) is probably broken for all
56 * boards except maybe the 6514.
58 * This driver previously inverted the outputs on PCI-6513 through to
59 * PCI-6519 and on PXI-6513 through to PXI-6515. It no longer inverts
60 * outputs on those cards by default as it didn't make much sense. If
61 * you require the outputs to be inverted on those cards for legacy
62 * reasons, set the module parameter "legacy_invert_outputs=true" when
63 * loading the module, or set "ni_65xx.legacy_invert_outputs=true" on
64 * the kernel command line if the driver is built in to the kernel.
68 * Manuals (available from ftp://ftp.natinst.com/support/manuals)
70 * 370106b.pdf 6514 Register Level Programmer Manual
73 #include <linux/module.h>
74 #include <linux/pci.h>
75 #include <linux/interrupt.h>
77 #include "../comedidev.h"
79 #include "comedi_fc.h"
82 * PCI BAR1 Register Map
85 /* Non-recurring Registers (8-bit except where noted) */
86 #define NI_65XX_ID_REG 0x00
87 #define NI_65XX_CLR_REG 0x01
88 #define NI_65XX_CLR_WDOG_INT (1 << 6)
89 #define NI_65XX_CLR_WDOG_PING (1 << 5)
90 #define NI_65XX_CLR_WDOG_EXP (1 << 4)
91 #define NI_65XX_CLR_EDGE_INT (1 << 3)
92 #define NI_65XX_CLR_OVERFLOW_INT (1 << 2)
93 #define NI_65XX_STATUS_REG 0x02
94 #define NI_65XX_STATUS_WDOG_INT (1 << 5)
95 #define NI_65XX_STATUS_FALL_EDGE (1 << 4)
96 #define NI_65XX_STATUS_RISE_EDGE (1 << 3)
97 #define NI_65XX_STATUS_INT (1 << 2)
98 #define NI_65XX_STATUS_OVERFLOW_INT (1 << 1)
99 #define NI_65XX_STATUS_EDGE_INT (1 << 0)
100 #define NI_65XX_CTRL_REG 0x03
101 #define NI_65XX_CTRL_WDOG_ENA (1 << 5)
102 #define NI_65XX_CTRL_FALL_EDGE_ENA (1 << 4)
103 #define NI_65XX_CTRL_RISE_EDGE_ENA (1 << 3)
104 #define NI_65XX_CTRL_INT_ENA (1 << 2)
105 #define NI_65XX_CTRL_OVERFLOW_ENA (1 << 1)
106 #define NI_65XX_CTRL_EDGE_ENA (1 << 0)
107 #define NI_65XX_REV_REG 0x04 /* 32-bit */
108 #define NI_65XX_FILTER_REG 0x08 /* 32-bit */
109 #define NI_65XX_RTSI_ROUTE_REG 0x0c /* 16-bit */
110 #define NI_65XX_RTSI_EDGE_REG 0x0e /* 16-bit */
111 #define NI_65XX_RTSI_WDOG_REG 0x10 /* 16-bit */
112 #define NI_65XX_RTSI_TRIG_REG 0x12 /* 16-bit */
113 #define NI_65XX_AUTO_CLK_SEL_REG 0x14 /* PXI-6528 only */
114 #define NI_65XX_AUTO_CLK_SEL_STATUS (1 << 1)
115 #define NI_65XX_AUTO_CLK_SEL_DISABLE (1 << 0)
116 #define NI_65XX_WDOG_CTRL_REG 0x15
117 #define NI_65XX_WDOG_CTRL_ENA (1 << 0)
118 #define NI_65XX_RTSI_CFG_REG 0x16
119 #define NI_65XX_RTSI_CFG_RISE_SENSE (1 << 2)
120 #define NI_65XX_RTSI_CFG_FALL_SENSE (1 << 1)
121 #define NI_65XX_RTSI_CFG_SYNC_DETECT (1 << 0)
122 #define NI_65XX_WDOG_STATUS_REG 0x17
123 #define NI_65XX_WDOG_STATUS_EXP (1 << 0)
124 #define NI_65XX_WDOG_INTERVAL_REG 0x18 /* 32-bit */
126 /* Recurring port registers (8-bit) */
127 #define NI_65XX_PORT(x) ((x) * 0x10)
128 #define NI_65XX_IO_DATA_REG(x) (0x40 + NI_65XX_PORT(x))
129 #define NI_65XX_IO_SEL_REG(x) (0x41 + NI_65XX_PORT(x))
130 #define NI_65XX_IO_SEL_OUTPUT (0 << 0)
131 #define NI_65XX_IO_SEL_INPUT (1 << 0)
132 #define NI_65XX_RISE_EDGE_ENA_REG(x) (0x42 + NI_65XX_PORT(x))
133 #define NI_65XX_FALL_EDGE_ENA_REG(x) (0x43 + NI_65XX_PORT(x))
134 #define NI_65XX_FILTER_ENA(x) (0x44 + NI_65XX_PORT(x))
135 #define NI_65XX_WDOG_HIZ_REG(x) (0x46 + NI_65XX_PORT(x))
136 #define NI_65XX_WDOG_ENA(x) (0x47 + NI_65XX_PORT(x))
137 #define NI_65XX_WDOG_HI_LO_REG(x) (0x48 + NI_65XX_PORT(x))
138 #define NI_65XX_RTSI_ENA(x) (0x49 + NI_65XX_PORT(x))
140 #define NI_65XX_PORT_TO_CHAN(x) ((x) * 8)
141 #define NI_65XX_CHAN_TO_PORT(x) ((x) / 8)
142 #define NI_65XX_CHAN_TO_MASK(x) (1 << ((x) % 8))
144 enum ni_65xx_boardid {
169 struct ni_65xx_board {
171 unsigned num_dio_ports;
172 unsigned num_di_ports;
173 unsigned num_do_ports;
174 unsigned legacy_invert:1;
177 static const struct ni_65xx_board ni_65xx_boards[] = {
289 static bool ni_65xx_legacy_invert_outputs;
290 module_param_named(legacy_invert_outputs, ni_65xx_legacy_invert_outputs,
292 MODULE_PARM_DESC(legacy_invert_outputs,
293 "invert outputs of PCI/PXI-6513/6514/6515/6516/6517/6518/6519 for compatibility with old user code");
295 struct ni_65xx_private {
299 static void ni_65xx_disable_input_filters(struct comedi_device *dev)
301 const struct ni_65xx_board *board = comedi_board(dev);
302 struct ni_65xx_private *devpriv = dev->private;
306 num_ports = board->num_dio_ports +
307 board->num_di_ports +
310 /* disable input filtering on all ports */
311 for (i = 0; i < num_ports; ++i)
312 writeb(0x00, devpriv->mmio + NI_65XX_FILTER_ENA(i));
314 /* set filter interval to 0 (32bit reg) */
315 writel(0x00000000, devpriv->mmio + NI_65XX_FILTER_REG);
318 static int ni_65xx_dio_insn_config(struct comedi_device *dev,
319 struct comedi_subdevice *s,
320 struct comedi_insn *insn,
323 struct ni_65xx_private *devpriv = dev->private;
324 unsigned long base_port = (unsigned long)s->private;
325 unsigned int chan = CR_CHAN(insn->chanspec);
326 unsigned int chan_mask = NI_65XX_CHAN_TO_MASK(chan);
327 unsigned port = base_port + NI_65XX_CHAN_TO_PORT(chan);
328 unsigned int interval;
332 case INSN_CONFIG_FILTER:
334 * The deglitch filter interval is specified in nanoseconds.
335 * The hardware supports intervals in 200ns increments. Round
336 * the user values up and return the actual interval.
338 interval = (data[1] + 100) / 200;
339 if (interval > 0xfffff)
341 data[1] = interval * 200;
344 * Enable/disable the channel for deglitch filtering. Note
345 * that the filter interval is never set to '0'. This is done
346 * because other channels might still be enabled for filtering.
348 val = readb(devpriv->mmio + NI_65XX_FILTER_ENA(port));
350 writel(interval, devpriv->mmio + NI_65XX_FILTER_REG);
355 writeb(val, devpriv->mmio + NI_65XX_FILTER_ENA(port));
358 case INSN_CONFIG_DIO_OUTPUT:
359 if (s->type != COMEDI_SUBD_DIO)
361 writeb(NI_65XX_IO_SEL_OUTPUT,
362 devpriv->mmio + NI_65XX_IO_SEL_REG(port));
365 case INSN_CONFIG_DIO_INPUT:
366 if (s->type != COMEDI_SUBD_DIO)
368 writeb(NI_65XX_IO_SEL_INPUT,
369 devpriv->mmio + NI_65XX_IO_SEL_REG(port));
372 case INSN_CONFIG_DIO_QUERY:
373 if (s->type != COMEDI_SUBD_DIO)
375 val = readb(devpriv->mmio + NI_65XX_IO_SEL_REG(port));
376 data[1] = (val == NI_65XX_IO_SEL_INPUT) ? COMEDI_INPUT
387 static int ni_65xx_dio_insn_bits(struct comedi_device *dev,
388 struct comedi_subdevice *s,
389 struct comedi_insn *insn,
392 struct ni_65xx_private *devpriv = dev->private;
393 unsigned long base_port = (unsigned long)s->private;
394 unsigned int base_chan = CR_CHAN(insn->chanspec);
395 int last_port_offset = NI_65XX_CHAN_TO_PORT(s->n_chan - 1);
396 unsigned read_bits = 0;
399 for (port_offset = NI_65XX_CHAN_TO_PORT(base_chan);
400 port_offset <= last_port_offset; port_offset++) {
401 unsigned port = base_port + port_offset;
402 int base_port_channel = NI_65XX_PORT_TO_CHAN(port_offset);
403 unsigned port_mask, port_data, bits;
404 int bitshift = base_port_channel - base_chan;
411 port_mask >>= bitshift;
412 port_data >>= bitshift;
414 port_mask <<= -bitshift;
415 port_data <<= -bitshift;
420 /* update the outputs */
422 bits = readb(devpriv->mmio + NI_65XX_IO_DATA_REG(port));
423 bits ^= s->io_bits; /* invert if necessary */
425 bits |= (port_data & port_mask);
426 bits ^= s->io_bits; /* invert back */
427 writeb(bits, devpriv->mmio + NI_65XX_IO_DATA_REG(port));
430 /* read back the actual state */
431 bits = readb(devpriv->mmio + NI_65XX_IO_DATA_REG(port));
432 bits ^= s->io_bits; /* invert if necessary */
444 static irqreturn_t ni_65xx_interrupt(int irq, void *d)
446 struct comedi_device *dev = d;
447 struct ni_65xx_private *devpriv = dev->private;
448 struct comedi_subdevice *s = dev->read_subdev;
451 status = readb(devpriv->mmio + NI_65XX_STATUS_REG);
452 if ((status & NI_65XX_STATUS_INT) == 0)
454 if ((status & NI_65XX_STATUS_EDGE_INT) == 0)
457 writeb(NI_65XX_CLR_EDGE_INT | NI_65XX_CLR_OVERFLOW_INT,
458 devpriv->mmio + NI_65XX_CLR_REG);
460 comedi_buf_put(s, 0);
461 s->async->events |= COMEDI_CB_EOS;
462 comedi_event(dev, s);
466 static int ni_65xx_intr_cmdtest(struct comedi_device *dev,
467 struct comedi_subdevice *s,
468 struct comedi_cmd *cmd)
472 /* Step 1 : check if triggers are trivially valid */
474 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
475 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_OTHER);
476 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
477 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
478 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT);
483 /* Step 2a : make sure trigger sources are unique */
484 /* Step 2b : and mutually compatible */
489 /* Step 3: check if arguments are trivially valid */
491 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
492 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
493 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
494 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
495 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
500 /* step 4: fix up any arguments */
508 static int ni_65xx_intr_cmd(struct comedi_device *dev,
509 struct comedi_subdevice *s)
511 struct ni_65xx_private *devpriv = dev->private;
513 writeb(NI_65XX_CLR_EDGE_INT | NI_65XX_CLR_OVERFLOW_INT,
514 devpriv->mmio + NI_65XX_CLR_REG);
515 writeb(NI_65XX_CTRL_FALL_EDGE_ENA | NI_65XX_CTRL_RISE_EDGE_ENA |
516 NI_65XX_CTRL_INT_ENA | NI_65XX_CTRL_EDGE_ENA,
517 devpriv->mmio + NI_65XX_CTRL_REG);
522 static int ni_65xx_intr_cancel(struct comedi_device *dev,
523 struct comedi_subdevice *s)
525 struct ni_65xx_private *devpriv = dev->private;
527 writeb(0x00, devpriv->mmio + NI_65XX_CTRL_REG);
532 static int ni_65xx_intr_insn_bits(struct comedi_device *dev,
533 struct comedi_subdevice *s,
534 struct comedi_insn *insn,
541 static int ni_65xx_intr_insn_config(struct comedi_device *dev,
542 struct comedi_subdevice *s,
543 struct comedi_insn *insn,
546 struct ni_65xx_private *devpriv = dev->private;
549 case INSN_CONFIG_CHANGE_NOTIFY:
550 /* add instruction to check_insn_config_length() */
555 * This only works for the first 4 ports (32 channels)!
558 /* set the channels to monitor for rising edges */
559 writeb(data[1] & 0xff,
560 devpriv->mmio + NI_65XX_RISE_EDGE_ENA_REG(0));
561 writeb((data[1] >> 8) & 0xff,
562 devpriv->mmio + NI_65XX_RISE_EDGE_ENA_REG(1));
563 writeb((data[1] >> 16) & 0xff,
564 devpriv->mmio + NI_65XX_RISE_EDGE_ENA_REG(2));
565 writeb((data[1] >> 24) & 0xff,
566 devpriv->mmio + NI_65XX_RISE_EDGE_ENA_REG(3));
568 /* set the channels to monitor for falling edges */
569 writeb(data[2] & 0xff,
570 devpriv->mmio + NI_65XX_FALL_EDGE_ENA_REG(0));
571 writeb((data[2] >> 8) & 0xff,
572 devpriv->mmio + NI_65XX_FALL_EDGE_ENA_REG(1));
573 writeb((data[2] >> 16) & 0xff,
574 devpriv->mmio + NI_65XX_FALL_EDGE_ENA_REG(2));
575 writeb((data[2] >> 24) & 0xff,
576 devpriv->mmio + NI_65XX_FALL_EDGE_ENA_REG(3));
585 /* ripped from mite.h and mite_setup2() to avoid mite dependancy */
586 #define MITE_IODWBSR 0xc0 /* IO Device Window Base Size Register */
587 #define WENAB (1 << 7) /* window enable */
589 static int ni_65xx_mite_init(struct pci_dev *pcidev)
591 void __iomem *mite_base;
594 /* ioremap the MITE registers (BAR 0) temporarily */
595 mite_base = pci_ioremap_bar(pcidev, 0);
599 /* set data window to main registers (BAR 1) */
600 main_phys_addr = pci_resource_start(pcidev, 1);
601 writel(main_phys_addr | WENAB, mite_base + MITE_IODWBSR);
603 /* finished with MITE registers */
608 static int ni_65xx_auto_attach(struct comedi_device *dev,
609 unsigned long context)
611 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
612 const struct ni_65xx_board *board = NULL;
613 struct ni_65xx_private *devpriv;
614 struct comedi_subdevice *s;
618 if (context < ARRAY_SIZE(ni_65xx_boards))
619 board = &ni_65xx_boards[context];
622 dev->board_ptr = board;
623 dev->board_name = board->name;
625 ret = comedi_pci_enable(dev);
629 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
633 ret = ni_65xx_mite_init(pcidev);
637 devpriv->mmio = pci_ioremap_bar(pcidev, 1);
641 writeb(NI_65XX_CLR_EDGE_INT | NI_65XX_CLR_OVERFLOW_INT,
642 devpriv->mmio + NI_65XX_CLR_REG);
643 writeb(0x00, devpriv->mmio + NI_65XX_CTRL_REG);
646 ret = request_irq(pcidev->irq, ni_65xx_interrupt, IRQF_SHARED,
647 dev->board_name, dev);
649 dev->irq = pcidev->irq;
652 dev_info(dev->class_dev, "board: %s, ID=0x%02x", dev->board_name,
653 readb(devpriv->mmio + NI_65XX_ID_REG));
655 ret = comedi_alloc_subdevices(dev, 4);
659 s = &dev->subdevices[0];
660 if (board->num_di_ports) {
661 s->type = COMEDI_SUBD_DI;
662 s->subdev_flags = SDF_READABLE;
663 s->n_chan = NI_65XX_PORT_TO_CHAN(board->num_di_ports);
665 s->range_table = &range_digital;
666 s->insn_bits = ni_65xx_dio_insn_bits;
667 s->insn_config = ni_65xx_dio_insn_config;
669 /* the input ports always start at port 0 */
670 s->private = (void *)0;
672 s->type = COMEDI_SUBD_UNUSED;
675 s = &dev->subdevices[1];
676 if (board->num_do_ports) {
677 s->type = COMEDI_SUBD_DO;
678 s->subdev_flags = SDF_WRITABLE;
679 s->n_chan = NI_65XX_PORT_TO_CHAN(board->num_do_ports);
681 s->range_table = &range_digital;
682 s->insn_bits = ni_65xx_dio_insn_bits;
684 /* the output ports always start after the input ports */
685 s->private = (void *)(unsigned long)board->num_di_ports;
688 * Use the io_bits to handle the inverted outputs. Inverted
689 * outputs are only supported if the "legacy_invert_outputs"
690 * module parameter is set to "true".
692 if (ni_65xx_legacy_invert_outputs && board->legacy_invert)
695 /* reset all output ports to comedi '0' */
696 for (i = 0; i < board->num_do_ports; ++i) {
697 writeb(s->io_bits, /* inverted if necessary */
699 NI_65XX_IO_DATA_REG(board->num_di_ports + i));
702 s->type = COMEDI_SUBD_UNUSED;
705 s = &dev->subdevices[2];
706 if (board->num_dio_ports) {
707 s->type = COMEDI_SUBD_DIO;
708 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
709 s->n_chan = NI_65XX_PORT_TO_CHAN(board->num_dio_ports);
711 s->range_table = &range_digital;
712 s->insn_bits = ni_65xx_dio_insn_bits;
713 s->insn_config = ni_65xx_dio_insn_config;
715 /* the input/output ports always start at port 0 */
716 s->private = (void *)0;
718 /* configure all ports for input */
719 for (i = 0; i < board->num_dio_ports; ++i) {
720 writeb(NI_65XX_IO_SEL_INPUT,
721 devpriv->mmio + NI_65XX_IO_SEL_REG(i));
724 s->type = COMEDI_SUBD_UNUSED;
727 s = &dev->subdevices[3];
728 s->type = COMEDI_SUBD_DI;
729 s->subdev_flags = SDF_READABLE;
732 s->range_table = &range_digital;
733 s->insn_bits = ni_65xx_intr_insn_bits;
735 dev->read_subdev = s;
736 s->subdev_flags |= SDF_CMD_READ;
738 s->insn_config = ni_65xx_intr_insn_config;
739 s->do_cmdtest = ni_65xx_intr_cmdtest;
740 s->do_cmd = ni_65xx_intr_cmd;
741 s->cancel = ni_65xx_intr_cancel;
744 ni_65xx_disable_input_filters(dev);
749 static void ni_65xx_detach(struct comedi_device *dev)
751 struct ni_65xx_private *devpriv = dev->private;
753 if (devpriv && devpriv->mmio) {
754 writeb(0x00, devpriv->mmio + NI_65XX_CTRL_REG);
755 iounmap(devpriv->mmio);
758 free_irq(dev->irq, dev);
759 comedi_pci_disable(dev);
762 static struct comedi_driver ni_65xx_driver = {
763 .driver_name = "ni_65xx",
764 .module = THIS_MODULE,
765 .auto_attach = ni_65xx_auto_attach,
766 .detach = ni_65xx_detach,
769 static int ni_65xx_pci_probe(struct pci_dev *dev,
770 const struct pci_device_id *id)
772 return comedi_pci_auto_config(dev, &ni_65xx_driver, id->driver_data);
775 static const struct pci_device_id ni_65xx_pci_table[] = {
776 { PCI_VDEVICE(NI, 0x1710), BOARD_PXI6509 },
777 { PCI_VDEVICE(NI, 0x7085), BOARD_PCI6509 },
778 { PCI_VDEVICE(NI, 0x7086), BOARD_PXI6528 },
779 { PCI_VDEVICE(NI, 0x7087), BOARD_PCI6515 },
780 { PCI_VDEVICE(NI, 0x7088), BOARD_PCI6514 },
781 { PCI_VDEVICE(NI, 0x70a9), BOARD_PCI6528 },
782 { PCI_VDEVICE(NI, 0x70c3), BOARD_PCI6511 },
783 { PCI_VDEVICE(NI, 0x70c8), BOARD_PCI6513 },
784 { PCI_VDEVICE(NI, 0x70c9), BOARD_PXI6515 },
785 { PCI_VDEVICE(NI, 0x70cc), BOARD_PCI6512 },
786 { PCI_VDEVICE(NI, 0x70cd), BOARD_PXI6514 },
787 { PCI_VDEVICE(NI, 0x70d1), BOARD_PXI6513 },
788 { PCI_VDEVICE(NI, 0x70d2), BOARD_PXI6512 },
789 { PCI_VDEVICE(NI, 0x70d3), BOARD_PXI6511 },
790 { PCI_VDEVICE(NI, 0x7124), BOARD_PCI6510 },
791 { PCI_VDEVICE(NI, 0x7125), BOARD_PCI6516 },
792 { PCI_VDEVICE(NI, 0x7126), BOARD_PCI6517 },
793 { PCI_VDEVICE(NI, 0x7127), BOARD_PCI6518 },
794 { PCI_VDEVICE(NI, 0x7128), BOARD_PCI6519 },
795 { PCI_VDEVICE(NI, 0x718b), BOARD_PCI6521 },
796 { PCI_VDEVICE(NI, 0x718c), BOARD_PXI6521 },
797 { PCI_VDEVICE(NI, 0x71c5), BOARD_PCI6520 },
800 MODULE_DEVICE_TABLE(pci, ni_65xx_pci_table);
802 static struct pci_driver ni_65xx_pci_driver = {
804 .id_table = ni_65xx_pci_table,
805 .probe = ni_65xx_pci_probe,
806 .remove = comedi_pci_auto_unconfig,
808 module_comedi_pci_driver(ni_65xx_driver, ni_65xx_pci_driver);
810 MODULE_AUTHOR("Comedi http://www.comedi.org");
811 MODULE_DESCRIPTION("Comedi driver for NI PCI-65xx static dio boards");
812 MODULE_LICENSE("GPL");