3 * Comedi driver for National Instruments PCI-65xx static dio boards
5 * Copyright (C) 2006 Jon Grierson <jd@renko.co.uk>
6 * Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
8 * COMEDI - Linux Control and Measurement Device Interface
9 * Copyright (C) 1999,2002,2003 David A. Schleef <ds@schleef.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
24 * Description: National Instruments 65xx static dio boards
25 * Author: Jon Grierson <jd@renko.co.uk>,
26 * Frank Mori Hess <fmhess@users.sourceforge.net>
28 * Devices: (National Instruments) PCI-6509 [ni_65xx]
29 * (National Instruments) PXI-6509 [ni_65xx]
30 * (National Instruments) PCI-6510 [ni_65xx]
31 * (National Instruments) PCI-6511 [ni_65xx]
32 * (National Instruments) PXI-6511 [ni_65xx]
33 * (National Instruments) PCI-6512 [ni_65xx]
34 * (National Instruments) PXI-6512 [ni_65xx]
35 * (National Instruments) PCI-6513 [ni_65xx]
36 * (National Instruments) PXI-6513 [ni_65xx]
37 * (National Instruments) PCI-6514 [ni_65xx]
38 * (National Instruments) PXI-6514 [ni_65xx]
39 * (National Instruments) PCI-6515 [ni_65xx]
40 * (National Instruments) PXI-6515 [ni_65xx]
41 * (National Instruments) PCI-6516 [ni_65xx]
42 * (National Instruments) PCI-6517 [ni_65xx]
43 * (National Instruments) PCI-6518 [ni_65xx]
44 * (National Instruments) PCI-6519 [ni_65xx]
45 * (National Instruments) PCI-6520 [ni_65xx]
46 * (National Instruments) PCI-6521 [ni_65xx]
47 * (National Instruments) PXI-6521 [ni_65xx]
48 * (National Instruments) PCI-6528 [ni_65xx]
49 * (National Instruments) PXI-6528 [ni_65xx]
50 * Updated: Wed Oct 18 08:59:11 EDT 2006
52 * Configuration Options: not applicable, uses PCI auto config
54 * Based on the PCI-6527 driver by ds.
55 * The interrupt subdevice (subdevice 3) is probably broken for all
56 * boards except maybe the 6514.
60 * Manuals (available from ftp://ftp.natinst.com/support/manuals)
62 * 370106b.pdf 6514 Register Level Programmer Manual
65 #include <linux/module.h>
66 #include <linux/pci.h>
67 #include <linux/interrupt.h>
69 #include "../comedidev.h"
71 #include "comedi_fc.h"
74 * PCI BAR1 Register Map
77 /* Non-recurring Registers (8-bit except where noted) */
78 #define NI_65XX_ID_REG 0x00
79 #define NI_65XX_CLR_REG 0x01
80 #define NI_65XX_CLR_WDOG_INT (1 << 6)
81 #define NI_65XX_CLR_WDOG_PING (1 << 5)
82 #define NI_65XX_CLR_WDOG_EXP (1 << 4)
83 #define NI_65XX_CLR_EDGE_INT (1 << 3)
84 #define NI_65XX_CLR_OVERFLOW_INT (1 << 2)
85 #define NI_65XX_STATUS_REG 0x02
86 #define NI_65XX_STATUS_WDOG_INT (1 << 5)
87 #define NI_65XX_STATUS_FALL_EDGE (1 << 4)
88 #define NI_65XX_STATUS_RISE_EDGE (1 << 3)
89 #define NI_65XX_STATUS_INT (1 << 2)
90 #define NI_65XX_STATUS_OVERFLOW_INT (1 << 1)
91 #define NI_65XX_STATUS_EDGE_INT (1 << 0)
92 #define NI_65XX_CTRL_REG 0x03
93 #define NI_65XX_CTRL_WDOG_ENA (1 << 5)
94 #define NI_65XX_CTRL_FALL_EDGE_ENA (1 << 4)
95 #define NI_65XX_CTRL_RISE_EDGE_ENA (1 << 3)
96 #define NI_65XX_CTRL_INT_ENA (1 << 2)
97 #define NI_65XX_CTRL_OVERFLOW_ENA (1 << 1)
98 #define NI_65XX_CTRL_EDGE_ENA (1 << 0)
99 #define NI_65XX_REV_REG 0x04 /* 32-bit */
100 #define NI_65XX_FILTER_REG 0x08 /* 32-bit */
101 #define NI_65XX_RTSI_ROUTE_REG 0x0c /* 16-bit */
102 #define NI_65XX_RTSI_EDGE_REG 0x0e /* 16-bit */
103 #define NI_65XX_RTSI_WDOG_REG 0x10 /* 16-bit */
104 #define NI_65XX_RTSI_TRIG_REG 0x12 /* 16-bit */
105 #define NI_65XX_AUTO_CLK_SEL_REG 0x14 /* PXI-6528 only */
106 #define NI_65XX_AUTO_CLK_SEL_STATUS (1 << 1)
107 #define NI_65XX_AUTO_CLK_SEL_DISABLE (1 << 0)
108 #define NI_65XX_WDOG_CTRL_REG 0x15
109 #define NI_65XX_WDOG_CTRL_ENA (1 << 0)
110 #define NI_65XX_RTSI_CFG_REG 0x16
111 #define NI_65XX_RTSI_CFG_RISE_SENSE (1 << 2)
112 #define NI_65XX_RTSI_CFG_FALL_SENSE (1 << 1)
113 #define NI_65XX_RTSI_CFG_SYNC_DETECT (1 << 0)
114 #define NI_65XX_WDOG_STATUS_REG 0x17
115 #define NI_65XX_WDOG_STATUS_EXP (1 << 0)
116 #define NI_65XX_WDOG_INTERVAL_REG 0x18 /* 32-bit */
118 /* Recurring port registers (8-bit) */
119 #define NI_65XX_PORT(x) ((x) * 0x10)
120 #define NI_65XX_IO_DATA_REG(x) (0x40 + NI_65XX_PORT(x))
121 #define NI_65XX_IO_SEL_REG(x) (0x41 + NI_65XX_PORT(x))
122 #define NI_65XX_IO_SEL_OUTPUT (0 << 0)
123 #define NI_65XX_IO_SEL_INPUT (1 << 0)
124 #define NI_65XX_RISE_EDGE_ENA_REG(x) (0x42 + NI_65XX_PORT(x))
125 #define NI_65XX_FALL_EDGE_ENA_REG(x) (0x43 + NI_65XX_PORT(x))
126 #define NI_65XX_FILTER_ENA(x) (0x44 + NI_65XX_PORT(x))
127 #define NI_65XX_WDOG_HIZ_REG(x) (0x46 + NI_65XX_PORT(x))
128 #define NI_65XX_WDOG_ENA(x) (0x47 + NI_65XX_PORT(x))
129 #define NI_65XX_WDOG_HI_LO_REG(x) (0x48 + NI_65XX_PORT(x))
130 #define NI_65XX_RTSI_ENA(x) (0x49 + NI_65XX_PORT(x))
132 #define NI_65XX_PORT_TO_CHAN(x) ((x) * 8)
133 #define NI_65XX_CHAN_TO_PORT(x) ((x) / 8)
134 #define NI_65XX_CHAN_TO_MASK(x) (1 << ((x) % 8))
136 enum ni_65xx_boardid {
161 struct ni_65xx_board {
163 unsigned num_dio_ports;
164 unsigned num_di_ports;
165 unsigned num_do_ports;
166 unsigned invert_outputs:1;
169 static const struct ni_65xx_board ni_65xx_boards[] = {
281 static inline unsigned ni_65xx_total_num_ports(const struct ni_65xx_board
284 return board->num_dio_ports + board->num_di_ports + board->num_do_ports;
287 struct ni_65xx_private {
291 static int ni_65xx_dio_insn_config(struct comedi_device *dev,
292 struct comedi_subdevice *s,
293 struct comedi_insn *insn,
296 struct ni_65xx_private *devpriv = dev->private;
297 unsigned long base_port = (unsigned long)s->private;
298 unsigned int chan = CR_CHAN(insn->chanspec);
299 unsigned int chan_mask = NI_65XX_CHAN_TO_MASK(chan);
300 unsigned port = base_port + NI_65XX_CHAN_TO_PORT(chan);
301 unsigned int interval;
305 case INSN_CONFIG_FILTER:
307 * The deglitch filter interval is specified in nanoseconds.
308 * The hardware supports intervals in 200ns increments. Round
309 * the user values up and return the actual interval.
311 interval = (data[1] + 100) / 200;
312 if (interval > 0xfffff)
314 data[1] = interval * 200;
317 * Enable/disable the channel for deglitch filtering. Note
318 * that the filter interval is never set to '0'. This is done
319 * because other channels might still be enabled for filtering.
321 val = readb(devpriv->mmio + NI_65XX_FILTER_ENA(port));
323 writel(interval, devpriv->mmio + NI_65XX_FILTER_REG);
328 writeb(val, devpriv->mmio + NI_65XX_FILTER_ENA(port));
331 case INSN_CONFIG_DIO_OUTPUT:
332 if (s->type != COMEDI_SUBD_DIO)
334 writeb(NI_65XX_IO_SEL_OUTPUT,
335 devpriv->mmio + NI_65XX_IO_SEL_REG(port));
338 case INSN_CONFIG_DIO_INPUT:
339 if (s->type != COMEDI_SUBD_DIO)
341 writeb(NI_65XX_IO_SEL_INPUT,
342 devpriv->mmio + NI_65XX_IO_SEL_REG(port));
345 case INSN_CONFIG_DIO_QUERY:
346 if (s->type != COMEDI_SUBD_DIO)
348 val = readb(devpriv->mmio + NI_65XX_IO_SEL_REG(port));
349 data[1] = (val == NI_65XX_IO_SEL_INPUT) ? COMEDI_INPUT
360 static int ni_65xx_dio_insn_bits(struct comedi_device *dev,
361 struct comedi_subdevice *s,
362 struct comedi_insn *insn,
365 struct ni_65xx_private *devpriv = dev->private;
366 unsigned long base_port = (unsigned long)s->private;
367 unsigned int base_chan = CR_CHAN(insn->chanspec);
368 int last_port_offset = NI_65XX_CHAN_TO_PORT(s->n_chan - 1);
369 unsigned read_bits = 0;
372 for (port_offset = NI_65XX_CHAN_TO_PORT(base_chan);
373 port_offset <= last_port_offset; port_offset++) {
374 unsigned port = base_port + port_offset;
375 int base_port_channel = NI_65XX_PORT_TO_CHAN(port_offset);
376 unsigned port_mask, port_data, bits;
377 int bitshift = base_port_channel - base_chan;
384 port_mask >>= bitshift;
385 port_data >>= bitshift;
387 port_mask <<= -bitshift;
388 port_data <<= -bitshift;
393 /* update the outputs */
395 bits = readb(devpriv->mmio + NI_65XX_IO_DATA_REG(port));
396 bits ^= s->io_bits; /* invert if necessary */
398 bits |= (port_data & port_mask);
399 bits ^= s->io_bits; /* invert back */
400 writeb(bits, devpriv->mmio + NI_65XX_IO_DATA_REG(port));
403 /* read back the actual state */
404 bits = readb(devpriv->mmio + NI_65XX_IO_DATA_REG(port));
405 bits ^= s->io_bits; /* invert if necessary */
417 static irqreturn_t ni_65xx_interrupt(int irq, void *d)
419 struct comedi_device *dev = d;
420 struct ni_65xx_private *devpriv = dev->private;
421 struct comedi_subdevice *s = dev->read_subdev;
424 status = readb(devpriv->mmio + NI_65XX_STATUS_REG);
425 if ((status & NI_65XX_STATUS_INT) == 0)
427 if ((status & NI_65XX_STATUS_EDGE_INT) == 0)
430 writeb(NI_65XX_CLR_EDGE_INT | NI_65XX_CLR_OVERFLOW_INT,
431 devpriv->mmio + NI_65XX_CLR_REG);
433 comedi_buf_put(s, 0);
434 s->async->events |= COMEDI_CB_EOS;
435 comedi_event(dev, s);
439 static int ni_65xx_intr_cmdtest(struct comedi_device *dev,
440 struct comedi_subdevice *s,
441 struct comedi_cmd *cmd)
445 /* Step 1 : check if triggers are trivially valid */
447 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
448 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_OTHER);
449 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
450 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
451 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT);
456 /* Step 2a : make sure trigger sources are unique */
457 /* Step 2b : and mutually compatible */
462 /* Step 3: check if arguments are trivially valid */
464 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
465 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
466 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
467 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
468 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
473 /* step 4: fix up any arguments */
481 static int ni_65xx_intr_cmd(struct comedi_device *dev,
482 struct comedi_subdevice *s)
484 struct ni_65xx_private *devpriv = dev->private;
486 writeb(NI_65XX_CLR_EDGE_INT | NI_65XX_CLR_OVERFLOW_INT,
487 devpriv->mmio + NI_65XX_CLR_REG);
488 writeb(NI_65XX_CTRL_FALL_EDGE_ENA | NI_65XX_CTRL_RISE_EDGE_ENA |
489 NI_65XX_CTRL_INT_ENA | NI_65XX_CTRL_EDGE_ENA,
490 devpriv->mmio + NI_65XX_CTRL_REG);
495 static int ni_65xx_intr_cancel(struct comedi_device *dev,
496 struct comedi_subdevice *s)
498 struct ni_65xx_private *devpriv = dev->private;
500 writeb(0x00, devpriv->mmio + NI_65XX_CTRL_REG);
505 static int ni_65xx_intr_insn_bits(struct comedi_device *dev,
506 struct comedi_subdevice *s,
507 struct comedi_insn *insn,
514 static int ni_65xx_intr_insn_config(struct comedi_device *dev,
515 struct comedi_subdevice *s,
516 struct comedi_insn *insn,
519 struct ni_65xx_private *devpriv = dev->private;
522 case INSN_CONFIG_CHANGE_NOTIFY:
523 /* add instruction to check_insn_config_length() */
528 * This only works for the first 4 ports (32 channels)!
531 /* set the channels to monitor for rising edges */
532 writeb(data[1] & 0xff,
533 devpriv->mmio + NI_65XX_RISE_EDGE_ENA_REG(0));
534 writeb((data[1] >> 8) & 0xff,
535 devpriv->mmio + NI_65XX_RISE_EDGE_ENA_REG(1));
536 writeb((data[1] >> 16) & 0xff,
537 devpriv->mmio + NI_65XX_RISE_EDGE_ENA_REG(2));
538 writeb((data[1] >> 24) & 0xff,
539 devpriv->mmio + NI_65XX_RISE_EDGE_ENA_REG(3));
541 /* set the channels to monitor for falling edges */
542 writeb(data[2] & 0xff,
543 devpriv->mmio + NI_65XX_FALL_EDGE_ENA_REG(0));
544 writeb((data[2] >> 8) & 0xff,
545 devpriv->mmio + NI_65XX_FALL_EDGE_ENA_REG(1));
546 writeb((data[2] >> 16) & 0xff,
547 devpriv->mmio + NI_65XX_FALL_EDGE_ENA_REG(2));
548 writeb((data[2] >> 24) & 0xff,
549 devpriv->mmio + NI_65XX_FALL_EDGE_ENA_REG(3));
558 /* ripped from mite.h and mite_setup2() to avoid mite dependancy */
559 #define MITE_IODWBSR 0xc0 /* IO Device Window Base Size Register */
560 #define WENAB (1 << 7) /* window enable */
562 static int ni_65xx_mite_init(struct pci_dev *pcidev)
564 void __iomem *mite_base;
567 /* ioremap the MITE registers (BAR 0) temporarily */
568 mite_base = pci_ioremap_bar(pcidev, 0);
572 /* set data window to main registers (BAR 1) */
573 main_phys_addr = pci_resource_start(pcidev, 1);
574 writel(main_phys_addr | WENAB, mite_base + MITE_IODWBSR);
576 /* finished with MITE registers */
581 static int ni_65xx_auto_attach(struct comedi_device *dev,
582 unsigned long context)
584 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
585 const struct ni_65xx_board *board = NULL;
586 struct ni_65xx_private *devpriv;
587 struct comedi_subdevice *s;
591 if (context < ARRAY_SIZE(ni_65xx_boards))
592 board = &ni_65xx_boards[context];
595 dev->board_ptr = board;
596 dev->board_name = board->name;
598 ret = comedi_pci_enable(dev);
602 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
606 ret = ni_65xx_mite_init(pcidev);
610 devpriv->mmio = pci_ioremap_bar(pcidev, 1);
614 writeb(NI_65XX_CLR_EDGE_INT | NI_65XX_CLR_OVERFLOW_INT,
615 devpriv->mmio + NI_65XX_CLR_REG);
616 writeb(0x00, devpriv->mmio + NI_65XX_CTRL_REG);
619 ret = request_irq(pcidev->irq, ni_65xx_interrupt, IRQF_SHARED,
620 dev->board_name, dev);
622 dev->irq = pcidev->irq;
625 dev_info(dev->class_dev, "board: %s, ID=0x%02x", dev->board_name,
626 readb(devpriv->mmio + NI_65XX_ID_REG));
628 ret = comedi_alloc_subdevices(dev, 4);
632 s = &dev->subdevices[0];
633 if (board->num_di_ports) {
634 s->type = COMEDI_SUBD_DI;
635 s->subdev_flags = SDF_READABLE;
636 s->n_chan = NI_65XX_PORT_TO_CHAN(board->num_di_ports);
638 s->range_table = &range_digital;
639 s->insn_bits = ni_65xx_dio_insn_bits;
640 s->insn_config = ni_65xx_dio_insn_config;
642 /* the input ports always start at port 0 */
643 s->private = (void *)0;
645 s->type = COMEDI_SUBD_UNUSED;
648 s = &dev->subdevices[1];
649 if (board->num_do_ports) {
650 s->type = COMEDI_SUBD_DO;
651 s->subdev_flags = SDF_WRITABLE;
652 s->n_chan = NI_65XX_PORT_TO_CHAN(board->num_do_ports);
654 s->range_table = &range_digital;
655 s->insn_bits = ni_65xx_dio_insn_bits;
657 /* the output ports always start after the input ports */
658 s->private = (void *)(unsigned long)board->num_di_ports;
660 /* use the io_bits to handle the inverted outputs */
661 s->io_bits = (board->invert_outputs) ? 0xff : 0x00;
663 /* reset all output ports to comedi '0' */
664 for (i = 0; i < board->num_do_ports; ++i) {
665 writeb(s->io_bits, /* inverted if necessary */
667 NI_65XX_IO_DATA_REG(board->num_di_ports + i));
670 s->type = COMEDI_SUBD_UNUSED;
673 s = &dev->subdevices[2];
674 if (board->num_dio_ports) {
675 s->type = COMEDI_SUBD_DIO;
676 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
677 s->n_chan = NI_65XX_PORT_TO_CHAN(board->num_dio_ports);
679 s->range_table = &range_digital;
680 s->insn_bits = ni_65xx_dio_insn_bits;
681 s->insn_config = ni_65xx_dio_insn_config;
683 /* the input/output ports always start at port 0 */
684 s->private = (void *)0;
686 /* configure all ports for input */
687 for (i = 0; i < board->num_dio_ports; ++i) {
688 writeb(NI_65XX_IO_SEL_INPUT,
689 devpriv->mmio + NI_65XX_IO_SEL_REG(i));
692 s->type = COMEDI_SUBD_UNUSED;
695 s = &dev->subdevices[3];
696 s->type = COMEDI_SUBD_DI;
697 s->subdev_flags = SDF_READABLE;
700 s->range_table = &range_digital;
701 s->insn_bits = ni_65xx_intr_insn_bits;
703 dev->read_subdev = s;
704 s->subdev_flags |= SDF_CMD_READ;
706 s->insn_config = ni_65xx_intr_insn_config;
707 s->do_cmdtest = ni_65xx_intr_cmdtest;
708 s->do_cmd = ni_65xx_intr_cmd;
709 s->cancel = ni_65xx_intr_cancel;
712 for (i = 0; i < ni_65xx_total_num_ports(board); ++i)
713 writeb(0x00, devpriv->mmio + NI_65XX_FILTER_ENA(i));
715 /* Set filter interval to 0 (32bit reg) */
716 writel(0x00000000, devpriv->mmio + NI_65XX_FILTER_REG);
721 static void ni_65xx_detach(struct comedi_device *dev)
723 struct ni_65xx_private *devpriv = dev->private;
725 if (devpriv && devpriv->mmio) {
726 writeb(0x00, devpriv->mmio + NI_65XX_CTRL_REG);
727 iounmap(devpriv->mmio);
730 free_irq(dev->irq, dev);
731 comedi_pci_disable(dev);
734 static struct comedi_driver ni_65xx_driver = {
735 .driver_name = "ni_65xx",
736 .module = THIS_MODULE,
737 .auto_attach = ni_65xx_auto_attach,
738 .detach = ni_65xx_detach,
741 static int ni_65xx_pci_probe(struct pci_dev *dev,
742 const struct pci_device_id *id)
744 return comedi_pci_auto_config(dev, &ni_65xx_driver, id->driver_data);
747 static const struct pci_device_id ni_65xx_pci_table[] = {
748 { PCI_VDEVICE(NI, 0x1710), BOARD_PXI6509 },
749 { PCI_VDEVICE(NI, 0x7085), BOARD_PCI6509 },
750 { PCI_VDEVICE(NI, 0x7086), BOARD_PXI6528 },
751 { PCI_VDEVICE(NI, 0x7087), BOARD_PCI6515 },
752 { PCI_VDEVICE(NI, 0x7088), BOARD_PCI6514 },
753 { PCI_VDEVICE(NI, 0x70a9), BOARD_PCI6528 },
754 { PCI_VDEVICE(NI, 0x70c3), BOARD_PCI6511 },
755 { PCI_VDEVICE(NI, 0x70c8), BOARD_PCI6513 },
756 { PCI_VDEVICE(NI, 0x70c9), BOARD_PXI6515 },
757 { PCI_VDEVICE(NI, 0x70cc), BOARD_PCI6512 },
758 { PCI_VDEVICE(NI, 0x70cd), BOARD_PXI6514 },
759 { PCI_VDEVICE(NI, 0x70d1), BOARD_PXI6513 },
760 { PCI_VDEVICE(NI, 0x70d2), BOARD_PXI6512 },
761 { PCI_VDEVICE(NI, 0x70d3), BOARD_PXI6511 },
762 { PCI_VDEVICE(NI, 0x7124), BOARD_PCI6510 },
763 { PCI_VDEVICE(NI, 0x7125), BOARD_PCI6516 },
764 { PCI_VDEVICE(NI, 0x7126), BOARD_PCI6517 },
765 { PCI_VDEVICE(NI, 0x7127), BOARD_PCI6518 },
766 { PCI_VDEVICE(NI, 0x7128), BOARD_PCI6519 },
767 { PCI_VDEVICE(NI, 0x718b), BOARD_PCI6521 },
768 { PCI_VDEVICE(NI, 0x718c), BOARD_PXI6521 },
769 { PCI_VDEVICE(NI, 0x71c5), BOARD_PCI6520 },
772 MODULE_DEVICE_TABLE(pci, ni_65xx_pci_table);
774 static struct pci_driver ni_65xx_pci_driver = {
776 .id_table = ni_65xx_pci_table,
777 .probe = ni_65xx_pci_probe,
778 .remove = comedi_pci_auto_unconfig,
780 module_comedi_pci_driver(ni_65xx_driver, ni_65xx_pci_driver);
782 MODULE_AUTHOR("Comedi http://www.comedi.org");
783 MODULE_DESCRIPTION("Comedi driver for NI PCI-65xx static dio boards");
784 MODULE_LICENSE("GPL");