2 comedi/drivers/ni_6514.c
3 driver for National Instruments PCI-6514
5 Copyright (C) 2006 Jon Grierson <jd@renko.co.uk>
6 Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
8 COMEDI - Linux Control and Measurement Device Interface
9 Copyright (C) 1999,2002,2003 David A. Schleef <ds@schleef.org>
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
23 Description: National Instruments 65xx static dio boards
24 Author: Jon Grierson <jd@renko.co.uk>,
25 Frank Mori Hess <fmhess@users.sourceforge.net>
27 Devices: [National Instruments] PCI-6509 (ni_65xx), PXI-6509, PCI-6510,
28 PCI-6511, PXI-6511, PCI-6512, PXI-6512, PCI-6513, PXI-6513, PCI-6514,
29 PXI-6514, PCI-6515, PXI-6515, PCI-6516, PCI-6517, PCI-6518, PCI-6519,
30 PCI-6520, PCI-6521, PXI-6521, PCI-6528, PXI-6528
31 Updated: Wed Oct 18 08:59:11 EDT 2006
33 Based on the PCI-6527 driver by ds.
34 The interrupt subdevice (subdevice 3) is probably broken for all boards
35 except maybe the 6514.
40 Manuals (available from ftp://ftp.natinst.com/support/manuals)
42 370106b.pdf 6514 Register Level Programmer Manual
46 #include <linux/module.h>
47 #include <linux/pci.h>
48 #include <linux/interrupt.h>
50 #include "../comedidev.h"
52 #include "comedi_fc.h"
55 * PCI BAR1 Register Map
58 /* Non-recurring Registers (8-bit except where noted) */
59 #define NI_65XX_ID_REG 0x00
60 #define NI_65XX_CLR_REG 0x01
61 #define NI_65XX_CLR_WDOG_INT (1 << 6)
62 #define NI_65XX_CLR_WDOG_PING (1 << 5)
63 #define NI_65XX_CLR_WDOG_EXP (1 << 4)
64 #define NI_65XX_CLR_EDGE_INT (1 << 3)
65 #define NI_65XX_CLR_OVERFLOW_INT (1 << 2)
66 #define NI_65XX_STATUS_REG 0x02
67 #define NI_65XX_STATUS_WDOG_INT (1 << 5)
68 #define NI_65XX_STATUS_FALL_EDGE (1 << 4)
69 #define NI_65XX_STATUS_RISE_EDGE (1 << 3)
70 #define NI_65XX_STATUS_INT (1 << 2)
71 #define NI_65XX_STATUS_OVERFLOW_INT (1 << 1)
72 #define NI_65XX_STATUS_EDGE_INT (1 << 0)
73 #define NI_65XX_CTRL_REG 0x03
74 #define NI_65XX_CTRL_WDOG_ENA (1 << 5)
75 #define NI_65XX_CTRL_FALL_EDGE_ENA (1 << 4)
76 #define NI_65XX_CTRL_RISE_EDGE_ENA (1 << 3)
77 #define NI_65XX_CTRL_INT_ENA (1 << 2)
78 #define NI_65XX_CTRL_OVERFLOW_ENA (1 << 1)
79 #define NI_65XX_CTRL_EDGE_ENA (1 << 0)
80 #define NI_65XX_REV_REG 0x04 /* 32-bit */
81 #define NI_65XX_FILTER_REG 0x08 /* 32-bit */
82 #define NI_65XX_RTSI_ROUTE_REG 0x0c /* 16-bit */
83 #define NI_65XX_RTSI_EDGE_REG 0x0e /* 16-bit */
84 #define NI_65XX_RTSI_WDOG_REG 0x10 /* 16-bit */
85 #define NI_65XX_RTSI_TRIG_REG 0x12 /* 16-bit */
86 #define NI_65XX_AUTO_CLK_SEL_REG 0x14 /* PXI-6528 only */
87 #define NI_65XX_AUTO_CLK_SEL_STATUS (1 << 1)
88 #define NI_65XX_AUTO_CLK_SEL_DISABLE (1 << 0)
89 #define NI_65XX_WDOG_CTRL_REG 0x15
90 #define NI_65XX_WDOG_CTRL_ENA (1 << 0)
91 #define NI_65XX_RTSI_CFG_REG 0x16
92 #define NI_65XX_RTSI_CFG_RISE_SENSE (1 << 2)
93 #define NI_65XX_RTSI_CFG_FALL_SENSE (1 << 1)
94 #define NI_65XX_RTSI_CFG_SYNC_DETECT (1 << 0)
95 #define NI_65XX_WDOG_STATUS_REG 0x17
96 #define NI_65XX_WDOG_STATUS_EXP (1 << 0)
97 #define NI_65XX_WDOG_INTERVAL_REG 0x18 /* 32-bit */
99 /* Recurring port registers (8-bit) */
100 #define NI_65XX_PORT(x) ((x) * 0x10)
101 #define NI_65XX_IO_DATA_REG(x) (0x40 + NI_65XX_PORT(x))
102 #define NI_65XX_IO_SEL_REG(x) (0x41 + NI_65XX_PORT(x))
103 #define NI_65XX_IO_SEL_OUTPUT (0 << 0)
104 #define NI_65XX_IO_SEL_INPUT (1 << 0)
105 #define NI_65XX_RISE_EDGE_ENA_REG(x) (0x42 + NI_65XX_PORT(x))
106 #define NI_65XX_FALL_EDGE_ENA_REG(x) (0x43 + NI_65XX_PORT(x))
107 #define NI_65XX_FILTER_ENA(x) (0x44 + NI_65XX_PORT(x))
108 #define NI_65XX_WDOG_HIZ_REG(x) (0x46 + NI_65XX_PORT(x))
109 #define NI_65XX_WDOG_ENA(x) (0x47 + NI_65XX_PORT(x))
110 #define NI_65XX_WDOG_HI_LO_REG(x) (0x48 + NI_65XX_PORT(x))
111 #define NI_65XX_RTSI_ENA(x) (0x49 + NI_65XX_PORT(x))
113 #define NI_65XX_MAX_NUM_PORTS 12
114 #define NI_65XX_PORT_TO_CHAN(x) ((x) * 8)
115 #define NI_65XX_CHAN_TO_PORT(x) ((x) / 8)
116 #define NI_65XX_CHAN_TO_MASK(x) (1 << ((x) % 8))
118 enum ni_65xx_boardid {
143 struct ni_65xx_board {
145 unsigned num_dio_ports;
146 unsigned num_di_ports;
147 unsigned num_do_ports;
148 unsigned invert_outputs:1;
151 static const struct ni_65xx_board ni_65xx_boards[] = {
263 static inline unsigned ni_65xx_total_num_ports(const struct ni_65xx_board
266 return board->num_dio_ports + board->num_di_ports + board->num_do_ports;
269 struct ni_65xx_private {
271 unsigned short output_bits[NI_65XX_MAX_NUM_PORTS];
274 static int ni_65xx_dio_insn_config(struct comedi_device *dev,
275 struct comedi_subdevice *s,
276 struct comedi_insn *insn,
279 struct ni_65xx_private *devpriv = dev->private;
280 unsigned long base_port = (unsigned long)s->private;
281 unsigned int chan = CR_CHAN(insn->chanspec);
282 unsigned int chan_mask = NI_65XX_CHAN_TO_MASK(chan);
283 unsigned port = base_port + NI_65XX_CHAN_TO_PORT(chan);
284 unsigned int interval;
288 case INSN_CONFIG_FILTER:
290 * The deglitch filter interval is specified in nanoseconds.
291 * The hardware supports intervals in 200ns increments. Round
292 * the user values up and return the actual interval.
294 interval = (data[1] + 100) / 200;
295 if (interval > 0xfffff)
297 data[1] = interval * 200;
300 * Enable/disable the channel for deglitch filtering. Note
301 * that the filter interval is never set to '0'. This is done
302 * because other channels might still be enabled for filtering.
304 val = readb(devpriv->mmio + NI_65XX_FILTER_ENA(port));
306 writel(interval, devpriv->mmio + NI_65XX_FILTER_REG);
311 writeb(val, devpriv->mmio + NI_65XX_FILTER_ENA(port));
314 case INSN_CONFIG_DIO_OUTPUT:
315 if (s->type != COMEDI_SUBD_DIO)
317 writeb(NI_65XX_IO_SEL_OUTPUT,
318 devpriv->mmio + NI_65XX_IO_SEL_REG(port));
321 case INSN_CONFIG_DIO_INPUT:
322 if (s->type != COMEDI_SUBD_DIO)
324 writeb(NI_65XX_IO_SEL_INPUT,
325 devpriv->mmio + NI_65XX_IO_SEL_REG(port));
328 case INSN_CONFIG_DIO_QUERY:
329 if (s->type != COMEDI_SUBD_DIO)
331 val = readb(devpriv->mmio + NI_65XX_IO_SEL_REG(port));
332 data[1] = (val == NI_65XX_IO_SEL_INPUT) ? COMEDI_INPUT
343 static int ni_65xx_dio_insn_bits(struct comedi_device *dev,
344 struct comedi_subdevice *s,
345 struct comedi_insn *insn,
348 const struct ni_65xx_board *board = comedi_board(dev);
349 struct ni_65xx_private *devpriv = dev->private;
350 unsigned long base_port = (unsigned long)s->private;
351 unsigned int base_chan = CR_CHAN(insn->chanspec);
352 int last_port_offset = NI_65XX_CHAN_TO_PORT(s->n_chan - 1);
353 unsigned read_bits = 0;
356 for (port_offset = NI_65XX_CHAN_TO_PORT(base_chan);
357 port_offset <= last_port_offset; port_offset++) {
358 unsigned port = base_port + port_offset;
359 int base_port_channel = NI_65XX_PORT_TO_CHAN(port_offset);
360 unsigned port_mask, port_data, port_read_bits;
361 int bitshift = base_port_channel - base_chan;
368 port_mask >>= bitshift;
369 port_data >>= bitshift;
371 port_mask <<= -bitshift;
372 port_data <<= -bitshift;
378 devpriv->output_bits[port] &= ~port_mask;
379 devpriv->output_bits[port] |=
380 port_data & port_mask;
381 bits = devpriv->output_bits[port];
382 if (board->invert_outputs)
384 writeb(bits, devpriv->mmio + NI_65XX_IO_DATA_REG(port));
386 port_read_bits = readb(devpriv->mmio +
387 NI_65XX_IO_DATA_REG(port));
388 if (s->type == COMEDI_SUBD_DO && board->invert_outputs) {
389 /* Outputs inverted, so invert value read back from
390 * DO subdevice. (Does not apply to boards with DIO
392 port_read_bits ^= 0xFF;
395 port_read_bits <<= bitshift;
397 port_read_bits >>= -bitshift;
399 read_bits |= port_read_bits;
405 static irqreturn_t ni_65xx_interrupt(int irq, void *d)
407 struct comedi_device *dev = d;
408 struct ni_65xx_private *devpriv = dev->private;
409 struct comedi_subdevice *s = dev->read_subdev;
412 status = readb(devpriv->mmio + NI_65XX_STATUS_REG);
413 if ((status & NI_65XX_STATUS_INT) == 0)
415 if ((status & NI_65XX_STATUS_EDGE_INT) == 0)
418 writeb(NI_65XX_CLR_EDGE_INT | NI_65XX_CLR_OVERFLOW_INT,
419 devpriv->mmio + NI_65XX_CLR_REG);
421 comedi_buf_put(s, 0);
422 s->async->events |= COMEDI_CB_EOS;
423 comedi_event(dev, s);
427 static int ni_65xx_intr_cmdtest(struct comedi_device *dev,
428 struct comedi_subdevice *s,
429 struct comedi_cmd *cmd)
433 /* Step 1 : check if triggers are trivially valid */
435 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
436 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_OTHER);
437 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
438 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
439 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT);
444 /* Step 2a : make sure trigger sources are unique */
445 /* Step 2b : and mutually compatible */
450 /* Step 3: check if arguments are trivially valid */
452 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
453 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
454 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
455 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
456 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
461 /* step 4: fix up any arguments */
469 static int ni_65xx_intr_cmd(struct comedi_device *dev,
470 struct comedi_subdevice *s)
472 struct ni_65xx_private *devpriv = dev->private;
474 writeb(NI_65XX_CLR_EDGE_INT | NI_65XX_CLR_OVERFLOW_INT,
475 devpriv->mmio + NI_65XX_CLR_REG);
476 writeb(NI_65XX_CTRL_FALL_EDGE_ENA | NI_65XX_CTRL_RISE_EDGE_ENA |
477 NI_65XX_CTRL_INT_ENA | NI_65XX_CTRL_EDGE_ENA,
478 devpriv->mmio + NI_65XX_CTRL_REG);
483 static int ni_65xx_intr_cancel(struct comedi_device *dev,
484 struct comedi_subdevice *s)
486 struct ni_65xx_private *devpriv = dev->private;
488 writeb(0x00, devpriv->mmio + NI_65XX_CTRL_REG);
493 static int ni_65xx_intr_insn_bits(struct comedi_device *dev,
494 struct comedi_subdevice *s,
495 struct comedi_insn *insn, unsigned int *data)
501 static int ni_65xx_intr_insn_config(struct comedi_device *dev,
502 struct comedi_subdevice *s,
503 struct comedi_insn *insn,
506 struct ni_65xx_private *devpriv = dev->private;
509 case INSN_CONFIG_CHANGE_NOTIFY:
510 /* add instruction to check_insn_config_length() */
515 * This only works for the first 4 ports (32 channels)!
518 /* set the channels to monitor for rising edges */
519 writeb(data[1] & 0xff,
520 devpriv->mmio + NI_65XX_RISE_EDGE_ENA_REG(0));
521 writeb((data[1] >> 8) & 0xff,
522 devpriv->mmio + NI_65XX_RISE_EDGE_ENA_REG(1));
523 writeb((data[1] >> 16) & 0xff,
524 devpriv->mmio + NI_65XX_RISE_EDGE_ENA_REG(2));
525 writeb((data[1] >> 24) & 0xff,
526 devpriv->mmio + NI_65XX_RISE_EDGE_ENA_REG(3));
528 /* set the channels to monitor for falling edges */
529 writeb(data[2] & 0xff,
530 devpriv->mmio + NI_65XX_FALL_EDGE_ENA_REG(0));
531 writeb((data[2] >> 8) & 0xff,
532 devpriv->mmio + NI_65XX_FALL_EDGE_ENA_REG(1));
533 writeb((data[2] >> 16) & 0xff,
534 devpriv->mmio + NI_65XX_FALL_EDGE_ENA_REG(2));
535 writeb((data[2] >> 24) & 0xff,
536 devpriv->mmio + NI_65XX_FALL_EDGE_ENA_REG(3));
545 /* ripped from mite.h and mite_setup2() to avoid mite dependancy */
546 #define MITE_IODWBSR 0xc0 /* IO Device Window Base Size Register */
547 #define WENAB (1 << 7) /* window enable */
549 static int ni_65xx_mite_init(struct pci_dev *pcidev)
551 void __iomem *mite_base;
554 /* ioremap the MITE registers (BAR 0) temporarily */
555 mite_base = pci_ioremap_bar(pcidev, 0);
559 /* set data window to main registers (BAR 1) */
560 main_phys_addr = pci_resource_start(pcidev, 1);
561 writel(main_phys_addr | WENAB, mite_base + MITE_IODWBSR);
563 /* finished with MITE registers */
568 static int ni_65xx_auto_attach(struct comedi_device *dev,
569 unsigned long context)
571 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
572 const struct ni_65xx_board *board = NULL;
573 struct ni_65xx_private *devpriv;
574 struct comedi_subdevice *s;
578 if (context < ARRAY_SIZE(ni_65xx_boards))
579 board = &ni_65xx_boards[context];
582 dev->board_ptr = board;
583 dev->board_name = board->name;
585 ret = comedi_pci_enable(dev);
589 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
593 ret = ni_65xx_mite_init(pcidev);
597 devpriv->mmio = pci_ioremap_bar(pcidev, 1);
601 writeb(NI_65XX_CLR_EDGE_INT | NI_65XX_CLR_OVERFLOW_INT,
602 devpriv->mmio + NI_65XX_CLR_REG);
603 writeb(0x00, devpriv->mmio + NI_65XX_CTRL_REG);
606 ret = request_irq(pcidev->irq, ni_65xx_interrupt, IRQF_SHARED,
607 dev->board_name, dev);
609 dev->irq = pcidev->irq;
612 dev_info(dev->class_dev, "board: %s, ID=0x%02x", dev->board_name,
613 readb(devpriv->mmio + NI_65XX_ID_REG));
615 ret = comedi_alloc_subdevices(dev, 4);
619 s = &dev->subdevices[0];
620 if (board->num_di_ports) {
621 s->type = COMEDI_SUBD_DI;
622 s->subdev_flags = SDF_READABLE;
623 s->n_chan = NI_65XX_PORT_TO_CHAN(board->num_di_ports);
625 s->range_table = &range_digital;
626 s->insn_bits = ni_65xx_dio_insn_bits;
627 s->insn_config = ni_65xx_dio_insn_config;
629 /* the input ports always start at port 0 */
630 s->private = (void *)0;
632 s->type = COMEDI_SUBD_UNUSED;
635 s = &dev->subdevices[1];
636 if (board->num_do_ports) {
637 s->type = COMEDI_SUBD_DO;
638 s->subdev_flags = SDF_WRITABLE;
639 s->n_chan = NI_65XX_PORT_TO_CHAN(board->num_do_ports);
641 s->range_table = &range_digital;
642 s->insn_bits = ni_65xx_dio_insn_bits;
644 /* the output ports always start after the input ports */
645 s->private = (void *)(unsigned long)board->num_di_ports;
647 s->type = COMEDI_SUBD_UNUSED;
650 s = &dev->subdevices[2];
651 if (board->num_dio_ports) {
652 s->type = COMEDI_SUBD_DIO;
653 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
654 s->n_chan = NI_65XX_PORT_TO_CHAN(board->num_dio_ports);
656 s->range_table = &range_digital;
657 s->insn_bits = ni_65xx_dio_insn_bits;
658 s->insn_config = ni_65xx_dio_insn_config;
660 /* the input/output ports always start at port 0 */
661 s->private = (void *)0;
663 /* configure all ports for input */
664 for (i = 0; i < board->num_dio_ports; ++i) {
665 writeb(NI_65XX_IO_SEL_INPUT,
666 devpriv->mmio + NI_65XX_IO_SEL_REG(i));
669 s->type = COMEDI_SUBD_UNUSED;
672 s = &dev->subdevices[3];
673 s->type = COMEDI_SUBD_DI;
674 s->subdev_flags = SDF_READABLE;
677 s->range_table = &range_digital;
678 s->insn_bits = ni_65xx_intr_insn_bits;
680 dev->read_subdev = s;
681 s->subdev_flags |= SDF_CMD_READ;
683 s->insn_config = ni_65xx_intr_insn_config;
684 s->do_cmdtest = ni_65xx_intr_cmdtest;
685 s->do_cmd = ni_65xx_intr_cmd;
686 s->cancel = ni_65xx_intr_cancel;
689 for (i = 0; i < ni_65xx_total_num_ports(board); ++i) {
690 writeb(0x00, devpriv->mmio + NI_65XX_FILTER_ENA(i));
691 if (board->invert_outputs)
692 writeb(0x01, devpriv->mmio + NI_65XX_IO_DATA_REG(i));
694 writeb(0x00, devpriv->mmio + NI_65XX_IO_DATA_REG(i));
697 /* Set filter interval to 0 (32bit reg) */
698 writel(0x00000000, devpriv->mmio + NI_65XX_FILTER_REG);
703 static void ni_65xx_detach(struct comedi_device *dev)
705 struct ni_65xx_private *devpriv = dev->private;
707 if (devpriv && devpriv->mmio) {
708 writeb(0x00, devpriv->mmio + NI_65XX_CTRL_REG);
709 iounmap(devpriv->mmio);
712 free_irq(dev->irq, dev);
713 comedi_pci_disable(dev);
716 static struct comedi_driver ni_65xx_driver = {
717 .driver_name = "ni_65xx",
718 .module = THIS_MODULE,
719 .auto_attach = ni_65xx_auto_attach,
720 .detach = ni_65xx_detach,
723 static int ni_65xx_pci_probe(struct pci_dev *dev,
724 const struct pci_device_id *id)
726 return comedi_pci_auto_config(dev, &ni_65xx_driver, id->driver_data);
729 static const struct pci_device_id ni_65xx_pci_table[] = {
730 { PCI_VDEVICE(NI, 0x1710), BOARD_PXI6509 },
731 { PCI_VDEVICE(NI, 0x7085), BOARD_PCI6509 },
732 { PCI_VDEVICE(NI, 0x7086), BOARD_PXI6528 },
733 { PCI_VDEVICE(NI, 0x7087), BOARD_PCI6515 },
734 { PCI_VDEVICE(NI, 0x7088), BOARD_PCI6514 },
735 { PCI_VDEVICE(NI, 0x70a9), BOARD_PCI6528 },
736 { PCI_VDEVICE(NI, 0x70c3), BOARD_PCI6511 },
737 { PCI_VDEVICE(NI, 0x70c8), BOARD_PCI6513 },
738 { PCI_VDEVICE(NI, 0x70c9), BOARD_PXI6515 },
739 { PCI_VDEVICE(NI, 0x70cc), BOARD_PCI6512 },
740 { PCI_VDEVICE(NI, 0x70cd), BOARD_PXI6514 },
741 { PCI_VDEVICE(NI, 0x70d1), BOARD_PXI6513 },
742 { PCI_VDEVICE(NI, 0x70d2), BOARD_PXI6512 },
743 { PCI_VDEVICE(NI, 0x70d3), BOARD_PXI6511 },
744 { PCI_VDEVICE(NI, 0x7124), BOARD_PCI6510 },
745 { PCI_VDEVICE(NI, 0x7125), BOARD_PCI6516 },
746 { PCI_VDEVICE(NI, 0x7126), BOARD_PCI6517 },
747 { PCI_VDEVICE(NI, 0x7127), BOARD_PCI6518 },
748 { PCI_VDEVICE(NI, 0x7128), BOARD_PCI6519 },
749 { PCI_VDEVICE(NI, 0x718b), BOARD_PCI6521 },
750 { PCI_VDEVICE(NI, 0x718c), BOARD_PXI6521 },
751 { PCI_VDEVICE(NI, 0x71c5), BOARD_PCI6520 },
754 MODULE_DEVICE_TABLE(pci, ni_65xx_pci_table);
756 static struct pci_driver ni_65xx_pci_driver = {
758 .id_table = ni_65xx_pci_table,
759 .probe = ni_65xx_pci_probe,
760 .remove = comedi_pci_auto_unconfig,
762 module_comedi_pci_driver(ni_65xx_driver, ni_65xx_pci_driver);
764 MODULE_AUTHOR("Comedi http://www.comedi.org");
765 MODULE_DESCRIPTION("Comedi low-level driver");
766 MODULE_LICENSE("GPL");