2 comedi/drivers/ni_660x.c
3 Hardware driver for NI 660x devices
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 Description: National Instruments 660x counter/timer boards
24 [National Instruments] PCI-6601 (ni_660x), PCI-6602, PXI-6602,
26 Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
27 Herman.Bruyninckx@mech.kuleuven.ac.be,
28 Wim.Meeussen@mech.kuleuven.ac.be,
29 Klaas.Gadeyne@mech.kuleuven.ac.be,
30 Frank Mori Hess <fmhess@users.sourceforge.net>
31 Updated: Thu Oct 18 12:56:06 EDT 2007
34 Encoders work. PulseGeneration (both single pulse and pulse train)
35 works. Buffered commands work for input but not output.
38 DAQ 660x Register-Level Programmer Manual (NI 370505A-01)
39 DAQ 6601/6602 User Manual (NI 322137B-01)
43 #include <linux/pci.h>
44 #include <linux/interrupt.h>
46 #include "../comedidev.h"
51 enum ni_660x_constants {
52 min_counter_pfi_chan = 8,
53 max_dio_pfi_chan = 31,
57 #define NUM_PFI_CHANNELS 40
58 /* really there are only up to 3 dma channels, but the register layout allows
60 #define MAX_DMA_CHANNEL 4
62 /* See Register-Level Programmer Manual page 3.1 */
63 enum NI_660x_Register {
64 G0InterruptAcknowledge,
66 G1InterruptAcknowledge,
79 G01JointStatus1Register,
83 G01JointStatus2Register,
87 G0InputSelectRegister,
88 G1InputSelectRegister,
89 G0AutoincrementRegister,
90 G1AutoincrementRegister,
91 G01JointResetRegister,
94 G0CountingModeRegister,
95 G1CountingModeRegister,
102 G2InterruptAcknowledge,
104 G3InterruptAcknowledge,
114 G23JointStatus1Register,
117 G23JointStatus2Register,
121 G2InputSelectRegister,
122 G3InputSelectRegister,
123 G2AutoincrementRegister,
124 G3AutoincrementRegister,
125 G23JointResetRegister,
128 G2CountingModeRegister,
129 G3CountingModeRegister,
130 G3SecondGateRegister,
131 G2SecondGateRegister,
139 GlobalInterruptStatusRegister,
141 GlobalInterruptConfigRegister,
165 static inline unsigned IOConfigReg(unsigned pfi_channel)
167 unsigned reg = IOConfigReg0_1 + pfi_channel / 2;
168 BUG_ON(reg > IOConfigReg38_39);
172 enum ni_660x_register_width {
178 enum ni_660x_register_direction {
184 enum ni_660x_pfi_output_select {
185 pfi_output_select_high_Z = 0,
186 pfi_output_select_counter = 1,
187 pfi_output_select_do = 2,
188 num_pfi_output_selects
191 enum ni_660x_subdevices {
192 NI_660X_DIO_SUBDEV = 1,
193 NI_660X_GPCT_SUBDEV_0 = 2
195 static inline unsigned NI_660X_GPCT_SUBDEV(unsigned index)
197 return NI_660X_GPCT_SUBDEV_0 + index;
200 struct NI_660xRegisterData {
202 const char *name; /* Register Name */
203 int offset; /* Offset from base address from GPCT chip */
204 enum ni_660x_register_direction direction;
205 enum ni_660x_register_width size; /* 1 byte, 2 bytes, or 4 bytes */
208 static const struct NI_660xRegisterData registerData[NumRegisters] = {
209 {"G0 Interrupt Acknowledge", 0x004, NI_660x_WRITE, DATA_2B},
210 {"G0 Status Register", 0x004, NI_660x_READ, DATA_2B},
211 {"G1 Interrupt Acknowledge", 0x006, NI_660x_WRITE, DATA_2B},
212 {"G1 Status Register", 0x006, NI_660x_READ, DATA_2B},
213 {"G01 Status Register ", 0x008, NI_660x_READ, DATA_2B},
214 {"G0 Command Register", 0x00C, NI_660x_WRITE, DATA_2B},
215 {"STC DIO Parallel Input", 0x00E, NI_660x_READ, DATA_2B},
216 {"G1 Command Register", 0x00E, NI_660x_WRITE, DATA_2B},
217 {"G0 HW Save Register", 0x010, NI_660x_READ, DATA_4B},
218 {"G1 HW Save Register", 0x014, NI_660x_READ, DATA_4B},
219 {"STC DIO Output", 0x014, NI_660x_WRITE, DATA_2B},
220 {"STC DIO Control", 0x016, NI_660x_WRITE, DATA_2B},
221 {"G0 SW Save Register", 0x018, NI_660x_READ, DATA_4B},
222 {"G1 SW Save Register", 0x01C, NI_660x_READ, DATA_4B},
223 {"G0 Mode Register", 0x034, NI_660x_WRITE, DATA_2B},
224 {"G01 Joint Status 1 Register", 0x036, NI_660x_READ, DATA_2B},
225 {"G1 Mode Register", 0x036, NI_660x_WRITE, DATA_2B},
226 {"STC DIO Serial Input", 0x038, NI_660x_READ, DATA_2B},
227 {"G0 Load A Register", 0x038, NI_660x_WRITE, DATA_4B},
228 {"G01 Joint Status 2 Register", 0x03A, NI_660x_READ, DATA_2B},
229 {"G0 Load B Register", 0x03C, NI_660x_WRITE, DATA_4B},
230 {"G1 Load A Register", 0x040, NI_660x_WRITE, DATA_4B},
231 {"G1 Load B Register", 0x044, NI_660x_WRITE, DATA_4B},
232 {"G0 Input Select Register", 0x048, NI_660x_WRITE, DATA_2B},
233 {"G1 Input Select Register", 0x04A, NI_660x_WRITE, DATA_2B},
234 {"G0 Autoincrement Register", 0x088, NI_660x_WRITE, DATA_2B},
235 {"G1 Autoincrement Register", 0x08A, NI_660x_WRITE, DATA_2B},
236 {"G01 Joint Reset Register", 0x090, NI_660x_WRITE, DATA_2B},
237 {"G0 Interrupt Enable", 0x092, NI_660x_WRITE, DATA_2B},
238 {"G1 Interrupt Enable", 0x096, NI_660x_WRITE, DATA_2B},
239 {"G0 Counting Mode Register", 0x0B0, NI_660x_WRITE, DATA_2B},
240 {"G1 Counting Mode Register", 0x0B2, NI_660x_WRITE, DATA_2B},
241 {"G0 Second Gate Register", 0x0B4, NI_660x_WRITE, DATA_2B},
242 {"G1 Second Gate Register", 0x0B6, NI_660x_WRITE, DATA_2B},
243 {"G0 DMA Config Register", 0x0B8, NI_660x_WRITE, DATA_2B},
244 {"G0 DMA Status Register", 0x0B8, NI_660x_READ, DATA_2B},
245 {"G1 DMA Config Register", 0x0BA, NI_660x_WRITE, DATA_2B},
246 {"G1 DMA Status Register", 0x0BA, NI_660x_READ, DATA_2B},
247 {"G2 Interrupt Acknowledge", 0x104, NI_660x_WRITE, DATA_2B},
248 {"G2 Status Register", 0x104, NI_660x_READ, DATA_2B},
249 {"G3 Interrupt Acknowledge", 0x106, NI_660x_WRITE, DATA_2B},
250 {"G3 Status Register", 0x106, NI_660x_READ, DATA_2B},
251 {"G23 Status Register", 0x108, NI_660x_READ, DATA_2B},
252 {"G2 Command Register", 0x10C, NI_660x_WRITE, DATA_2B},
253 {"G3 Command Register", 0x10E, NI_660x_WRITE, DATA_2B},
254 {"G2 HW Save Register", 0x110, NI_660x_READ, DATA_4B},
255 {"G3 HW Save Register", 0x114, NI_660x_READ, DATA_4B},
256 {"G2 SW Save Register", 0x118, NI_660x_READ, DATA_4B},
257 {"G3 SW Save Register", 0x11C, NI_660x_READ, DATA_4B},
258 {"G2 Mode Register", 0x134, NI_660x_WRITE, DATA_2B},
259 {"G23 Joint Status 1 Register", 0x136, NI_660x_READ, DATA_2B},
260 {"G3 Mode Register", 0x136, NI_660x_WRITE, DATA_2B},
261 {"G2 Load A Register", 0x138, NI_660x_WRITE, DATA_4B},
262 {"G23 Joint Status 2 Register", 0x13A, NI_660x_READ, DATA_2B},
263 {"G2 Load B Register", 0x13C, NI_660x_WRITE, DATA_4B},
264 {"G3 Load A Register", 0x140, NI_660x_WRITE, DATA_4B},
265 {"G3 Load B Register", 0x144, NI_660x_WRITE, DATA_4B},
266 {"G2 Input Select Register", 0x148, NI_660x_WRITE, DATA_2B},
267 {"G3 Input Select Register", 0x14A, NI_660x_WRITE, DATA_2B},
268 {"G2 Autoincrement Register", 0x188, NI_660x_WRITE, DATA_2B},
269 {"G3 Autoincrement Register", 0x18A, NI_660x_WRITE, DATA_2B},
270 {"G23 Joint Reset Register", 0x190, NI_660x_WRITE, DATA_2B},
271 {"G2 Interrupt Enable", 0x192, NI_660x_WRITE, DATA_2B},
272 {"G3 Interrupt Enable", 0x196, NI_660x_WRITE, DATA_2B},
273 {"G2 Counting Mode Register", 0x1B0, NI_660x_WRITE, DATA_2B},
274 {"G3 Counting Mode Register", 0x1B2, NI_660x_WRITE, DATA_2B},
275 {"G3 Second Gate Register", 0x1B6, NI_660x_WRITE, DATA_2B},
276 {"G2 Second Gate Register", 0x1B4, NI_660x_WRITE, DATA_2B},
277 {"G2 DMA Config Register", 0x1B8, NI_660x_WRITE, DATA_2B},
278 {"G2 DMA Status Register", 0x1B8, NI_660x_READ, DATA_2B},
279 {"G3 DMA Config Register", 0x1BA, NI_660x_WRITE, DATA_2B},
280 {"G3 DMA Status Register", 0x1BA, NI_660x_READ, DATA_2B},
281 {"32 bit Digital Input", 0x414, NI_660x_READ, DATA_4B},
282 {"32 bit Digital Output", 0x510, NI_660x_WRITE, DATA_4B},
283 {"Clock Config Register", 0x73C, NI_660x_WRITE, DATA_4B},
284 {"Global Interrupt Status Register", 0x754, NI_660x_READ, DATA_4B},
285 {"DMA Configuration Register", 0x76C, NI_660x_WRITE, DATA_4B},
286 {"Global Interrupt Config Register", 0x770, NI_660x_WRITE, DATA_4B},
287 {"IO Config Register 0-1", 0x77C, NI_660x_READ_WRITE, DATA_2B},
288 {"IO Config Register 2-3", 0x77E, NI_660x_READ_WRITE, DATA_2B},
289 {"IO Config Register 4-5", 0x780, NI_660x_READ_WRITE, DATA_2B},
290 {"IO Config Register 6-7", 0x782, NI_660x_READ_WRITE, DATA_2B},
291 {"IO Config Register 8-9", 0x784, NI_660x_READ_WRITE, DATA_2B},
292 {"IO Config Register 10-11", 0x786, NI_660x_READ_WRITE, DATA_2B},
293 {"IO Config Register 12-13", 0x788, NI_660x_READ_WRITE, DATA_2B},
294 {"IO Config Register 14-15", 0x78A, NI_660x_READ_WRITE, DATA_2B},
295 {"IO Config Register 16-17", 0x78C, NI_660x_READ_WRITE, DATA_2B},
296 {"IO Config Register 18-19", 0x78E, NI_660x_READ_WRITE, DATA_2B},
297 {"IO Config Register 20-21", 0x790, NI_660x_READ_WRITE, DATA_2B},
298 {"IO Config Register 22-23", 0x792, NI_660x_READ_WRITE, DATA_2B},
299 {"IO Config Register 24-25", 0x794, NI_660x_READ_WRITE, DATA_2B},
300 {"IO Config Register 26-27", 0x796, NI_660x_READ_WRITE, DATA_2B},
301 {"IO Config Register 28-29", 0x798, NI_660x_READ_WRITE, DATA_2B},
302 {"IO Config Register 30-31", 0x79A, NI_660x_READ_WRITE, DATA_2B},
303 {"IO Config Register 32-33", 0x79C, NI_660x_READ_WRITE, DATA_2B},
304 {"IO Config Register 34-35", 0x79E, NI_660x_READ_WRITE, DATA_2B},
305 {"IO Config Register 36-37", 0x7A0, NI_660x_READ_WRITE, DATA_2B},
306 {"IO Config Register 38-39", 0x7A2, NI_660x_READ_WRITE, DATA_2B}
309 /* kind of ENABLE for the second counter */
310 enum clock_config_register_bits {
311 CounterSwap = 0x1 << 21
315 static inline unsigned ioconfig_bitshift(unsigned pfi_channel)
323 static inline unsigned pfi_output_select_mask(unsigned pfi_channel)
325 return 0x3 << ioconfig_bitshift(pfi_channel);
328 static inline unsigned pfi_output_select_bits(unsigned pfi_channel,
329 unsigned output_select)
331 return (output_select & 0x3) << ioconfig_bitshift(pfi_channel);
334 static inline unsigned pfi_input_select_mask(unsigned pfi_channel)
336 return 0x7 << (4 + ioconfig_bitshift(pfi_channel));
339 static inline unsigned pfi_input_select_bits(unsigned pfi_channel,
340 unsigned input_select)
342 return (input_select & 0x7) << (4 + ioconfig_bitshift(pfi_channel));
345 /* dma configuration register bits */
346 static inline unsigned dma_select_mask(unsigned dma_channel)
348 BUG_ON(dma_channel >= MAX_DMA_CHANNEL);
349 return 0x1f << (8 * dma_channel);
353 dma_selection_none = 0x1f,
355 static inline unsigned dma_selection_counter(unsigned counter_index)
357 BUG_ON(counter_index >= counters_per_chip);
358 return counter_index;
361 static inline unsigned dma_select_bits(unsigned dma_channel, unsigned selection)
363 BUG_ON(dma_channel >= MAX_DMA_CHANNEL);
364 return (selection << (8 * dma_channel)) & dma_select_mask(dma_channel);
367 static inline unsigned dma_reset_bit(unsigned dma_channel)
369 BUG_ON(dma_channel >= MAX_DMA_CHANNEL);
370 return 0x80 << (8 * dma_channel);
373 enum global_interrupt_status_register_bits {
374 Counter_0_Int_Bit = 0x100,
375 Counter_1_Int_Bit = 0x200,
376 Counter_2_Int_Bit = 0x400,
377 Counter_3_Int_Bit = 0x800,
378 Cascade_Int_Bit = 0x20000000,
379 Global_Int_Bit = 0x80000000
382 enum global_interrupt_config_register_bits {
383 Cascade_Int_Enable_Bit = 0x20000000,
384 Global_Int_Polarity_Bit = 0x40000000,
385 Global_Int_Enable_Bit = 0x80000000
388 /* Offset of the GPCT chips from the base-address of the card */
389 /* First chip is at base-address + 0x00, etc. */
390 static const unsigned GPCT_OFFSET[2] = { 0x0, 0x800 };
392 /* Board description*/
393 struct ni_660x_board {
394 unsigned short dev_id; /* `lspci` will show you this */
396 unsigned n_chips; /* total number of TIO chips */
399 static const struct ni_660x_board ni_660x_boards[] = {
422 #define NI_660X_MAX_NUM_CHIPS 2
423 #define NI_660X_MAX_NUM_COUNTERS (NI_660X_MAX_NUM_CHIPS * counters_per_chip)
425 struct ni_660x_private {
426 struct mite_struct *mite;
427 struct ni_gpct_device *counter_dev;
428 uint64_t pfi_direction_bits;
429 struct mite_dma_descriptor_ring
430 *mite_rings[NI_660X_MAX_NUM_CHIPS][counters_per_chip];
431 spinlock_t mite_channel_lock;
432 /* interrupt_lock prevents races between interrupt and comedi_poll */
433 spinlock_t interrupt_lock;
434 unsigned dma_configuration_soft_copies[NI_660X_MAX_NUM_CHIPS];
435 spinlock_t soft_reg_copy_lock;
436 unsigned short pfi_output_selects[NUM_PFI_CHANNELS];
439 static inline unsigned ni_660x_num_counters(struct comedi_device *dev)
441 const struct ni_660x_board *board = comedi_board(dev);
443 return board->n_chips * counters_per_chip;
446 static enum NI_660x_Register ni_gpct_to_660x_register(enum ni_gpct_register reg)
448 enum NI_660x_Register ni_660x_register;
450 case NITIO_G0_Autoincrement_Reg:
451 ni_660x_register = G0AutoincrementRegister;
453 case NITIO_G1_Autoincrement_Reg:
454 ni_660x_register = G1AutoincrementRegister;
456 case NITIO_G2_Autoincrement_Reg:
457 ni_660x_register = G2AutoincrementRegister;
459 case NITIO_G3_Autoincrement_Reg:
460 ni_660x_register = G3AutoincrementRegister;
462 case NITIO_G0_Command_Reg:
463 ni_660x_register = G0CommandRegister;
465 case NITIO_G1_Command_Reg:
466 ni_660x_register = G1CommandRegister;
468 case NITIO_G2_Command_Reg:
469 ni_660x_register = G2CommandRegister;
471 case NITIO_G3_Command_Reg:
472 ni_660x_register = G3CommandRegister;
474 case NITIO_G0_HW_Save_Reg:
475 ni_660x_register = G0HWSaveRegister;
477 case NITIO_G1_HW_Save_Reg:
478 ni_660x_register = G1HWSaveRegister;
480 case NITIO_G2_HW_Save_Reg:
481 ni_660x_register = G2HWSaveRegister;
483 case NITIO_G3_HW_Save_Reg:
484 ni_660x_register = G3HWSaveRegister;
486 case NITIO_G0_SW_Save_Reg:
487 ni_660x_register = G0SWSaveRegister;
489 case NITIO_G1_SW_Save_Reg:
490 ni_660x_register = G1SWSaveRegister;
492 case NITIO_G2_SW_Save_Reg:
493 ni_660x_register = G2SWSaveRegister;
495 case NITIO_G3_SW_Save_Reg:
496 ni_660x_register = G3SWSaveRegister;
498 case NITIO_G0_Mode_Reg:
499 ni_660x_register = G0ModeRegister;
501 case NITIO_G1_Mode_Reg:
502 ni_660x_register = G1ModeRegister;
504 case NITIO_G2_Mode_Reg:
505 ni_660x_register = G2ModeRegister;
507 case NITIO_G3_Mode_Reg:
508 ni_660x_register = G3ModeRegister;
510 case NITIO_G0_LoadA_Reg:
511 ni_660x_register = G0LoadARegister;
513 case NITIO_G1_LoadA_Reg:
514 ni_660x_register = G1LoadARegister;
516 case NITIO_G2_LoadA_Reg:
517 ni_660x_register = G2LoadARegister;
519 case NITIO_G3_LoadA_Reg:
520 ni_660x_register = G3LoadARegister;
522 case NITIO_G0_LoadB_Reg:
523 ni_660x_register = G0LoadBRegister;
525 case NITIO_G1_LoadB_Reg:
526 ni_660x_register = G1LoadBRegister;
528 case NITIO_G2_LoadB_Reg:
529 ni_660x_register = G2LoadBRegister;
531 case NITIO_G3_LoadB_Reg:
532 ni_660x_register = G3LoadBRegister;
534 case NITIO_G0_Input_Select_Reg:
535 ni_660x_register = G0InputSelectRegister;
537 case NITIO_G1_Input_Select_Reg:
538 ni_660x_register = G1InputSelectRegister;
540 case NITIO_G2_Input_Select_Reg:
541 ni_660x_register = G2InputSelectRegister;
543 case NITIO_G3_Input_Select_Reg:
544 ni_660x_register = G3InputSelectRegister;
546 case NITIO_G01_Status_Reg:
547 ni_660x_register = G01StatusRegister;
549 case NITIO_G23_Status_Reg:
550 ni_660x_register = G23StatusRegister;
552 case NITIO_G01_Joint_Reset_Reg:
553 ni_660x_register = G01JointResetRegister;
555 case NITIO_G23_Joint_Reset_Reg:
556 ni_660x_register = G23JointResetRegister;
558 case NITIO_G01_Joint_Status1_Reg:
559 ni_660x_register = G01JointStatus1Register;
561 case NITIO_G23_Joint_Status1_Reg:
562 ni_660x_register = G23JointStatus1Register;
564 case NITIO_G01_Joint_Status2_Reg:
565 ni_660x_register = G01JointStatus2Register;
567 case NITIO_G23_Joint_Status2_Reg:
568 ni_660x_register = G23JointStatus2Register;
570 case NITIO_G0_Counting_Mode_Reg:
571 ni_660x_register = G0CountingModeRegister;
573 case NITIO_G1_Counting_Mode_Reg:
574 ni_660x_register = G1CountingModeRegister;
576 case NITIO_G2_Counting_Mode_Reg:
577 ni_660x_register = G2CountingModeRegister;
579 case NITIO_G3_Counting_Mode_Reg:
580 ni_660x_register = G3CountingModeRegister;
582 case NITIO_G0_Second_Gate_Reg:
583 ni_660x_register = G0SecondGateRegister;
585 case NITIO_G1_Second_Gate_Reg:
586 ni_660x_register = G1SecondGateRegister;
588 case NITIO_G2_Second_Gate_Reg:
589 ni_660x_register = G2SecondGateRegister;
591 case NITIO_G3_Second_Gate_Reg:
592 ni_660x_register = G3SecondGateRegister;
594 case NITIO_G0_DMA_Config_Reg:
595 ni_660x_register = G0DMAConfigRegister;
597 case NITIO_G0_DMA_Status_Reg:
598 ni_660x_register = G0DMAStatusRegister;
600 case NITIO_G1_DMA_Config_Reg:
601 ni_660x_register = G1DMAConfigRegister;
603 case NITIO_G1_DMA_Status_Reg:
604 ni_660x_register = G1DMAStatusRegister;
606 case NITIO_G2_DMA_Config_Reg:
607 ni_660x_register = G2DMAConfigRegister;
609 case NITIO_G2_DMA_Status_Reg:
610 ni_660x_register = G2DMAStatusRegister;
612 case NITIO_G3_DMA_Config_Reg:
613 ni_660x_register = G3DMAConfigRegister;
615 case NITIO_G3_DMA_Status_Reg:
616 ni_660x_register = G3DMAStatusRegister;
618 case NITIO_G0_Interrupt_Acknowledge_Reg:
619 ni_660x_register = G0InterruptAcknowledge;
621 case NITIO_G1_Interrupt_Acknowledge_Reg:
622 ni_660x_register = G1InterruptAcknowledge;
624 case NITIO_G2_Interrupt_Acknowledge_Reg:
625 ni_660x_register = G2InterruptAcknowledge;
627 case NITIO_G3_Interrupt_Acknowledge_Reg:
628 ni_660x_register = G3InterruptAcknowledge;
630 case NITIO_G0_Status_Reg:
631 ni_660x_register = G0StatusRegister;
633 case NITIO_G1_Status_Reg:
634 ni_660x_register = G1StatusRegister;
636 case NITIO_G2_Status_Reg:
637 ni_660x_register = G2StatusRegister;
639 case NITIO_G3_Status_Reg:
640 ni_660x_register = G3StatusRegister;
642 case NITIO_G0_Interrupt_Enable_Reg:
643 ni_660x_register = G0InterruptEnable;
645 case NITIO_G1_Interrupt_Enable_Reg:
646 ni_660x_register = G1InterruptEnable;
648 case NITIO_G2_Interrupt_Enable_Reg:
649 ni_660x_register = G2InterruptEnable;
651 case NITIO_G3_Interrupt_Enable_Reg:
652 ni_660x_register = G3InterruptEnable;
659 return ni_660x_register;
662 static inline void ni_660x_write_register(struct comedi_device *dev,
663 unsigned chip_index, unsigned bits,
664 enum NI_660x_Register reg)
666 struct ni_660x_private *devpriv = dev->private;
667 void __iomem *write_address =
668 devpriv->mite->daq_io_addr + GPCT_OFFSET[chip_index] +
669 registerData[reg].offset;
671 switch (registerData[reg].size) {
673 writew(bits, write_address);
676 writel(bits, write_address);
684 static inline unsigned ni_660x_read_register(struct comedi_device *dev,
686 enum NI_660x_Register reg)
688 struct ni_660x_private *devpriv = dev->private;
689 void __iomem *read_address =
690 devpriv->mite->daq_io_addr + GPCT_OFFSET[chip_index] +
691 registerData[reg].offset;
693 switch (registerData[reg].size) {
695 return readw(read_address);
698 return readl(read_address);
707 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
708 enum ni_gpct_register reg)
710 struct comedi_device *dev = counter->counter_dev->dev;
711 enum NI_660x_Register ni_660x_register = ni_gpct_to_660x_register(reg);
712 ni_660x_write_register(dev, counter->chip_index, bits,
716 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
717 enum ni_gpct_register reg)
719 struct comedi_device *dev = counter->counter_dev->dev;
720 enum NI_660x_Register ni_660x_register = ni_gpct_to_660x_register(reg);
721 return ni_660x_read_register(dev, counter->chip_index,
725 static inline struct mite_dma_descriptor_ring *mite_ring(struct ni_660x_private
730 return priv->mite_rings[counter->chip_index][counter->counter_index];
733 static inline void ni_660x_set_dma_channel(struct comedi_device *dev,
734 unsigned mite_channel,
735 struct ni_gpct *counter)
737 struct ni_660x_private *devpriv = dev->private;
740 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
741 devpriv->dma_configuration_soft_copies[counter->chip_index] &=
742 ~dma_select_mask(mite_channel);
743 devpriv->dma_configuration_soft_copies[counter->chip_index] |=
744 dma_select_bits(mite_channel,
745 dma_selection_counter(counter->counter_index));
746 ni_660x_write_register(dev, counter->chip_index,
747 devpriv->dma_configuration_soft_copies
748 [counter->chip_index] |
749 dma_reset_bit(mite_channel), DMAConfigRegister);
751 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
754 static inline void ni_660x_unset_dma_channel(struct comedi_device *dev,
755 unsigned mite_channel,
756 struct ni_gpct *counter)
758 struct ni_660x_private *devpriv = dev->private;
761 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
762 devpriv->dma_configuration_soft_copies[counter->chip_index] &=
763 ~dma_select_mask(mite_channel);
764 devpriv->dma_configuration_soft_copies[counter->chip_index] |=
765 dma_select_bits(mite_channel, dma_selection_none);
766 ni_660x_write_register(dev, counter->chip_index,
767 devpriv->dma_configuration_soft_copies
768 [counter->chip_index], DMAConfigRegister);
770 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
773 static int ni_660x_request_mite_channel(struct comedi_device *dev,
774 struct ni_gpct *counter,
775 enum comedi_io_direction direction)
777 struct ni_660x_private *devpriv = dev->private;
779 struct mite_channel *mite_chan;
781 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
782 BUG_ON(counter->mite_chan);
783 mite_chan = mite_request_channel(devpriv->mite,
784 mite_ring(devpriv, counter));
785 if (mite_chan == NULL) {
786 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
788 "failed to reserve mite dma channel for counter.");
791 mite_chan->dir = direction;
792 ni_tio_set_mite_channel(counter, mite_chan);
793 ni_660x_set_dma_channel(dev, mite_chan->channel, counter);
794 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
798 static void ni_660x_release_mite_channel(struct comedi_device *dev,
799 struct ni_gpct *counter)
801 struct ni_660x_private *devpriv = dev->private;
804 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
805 if (counter->mite_chan) {
806 struct mite_channel *mite_chan = counter->mite_chan;
808 ni_660x_unset_dma_channel(dev, mite_chan->channel, counter);
809 ni_tio_set_mite_channel(counter, NULL);
810 mite_release_channel(mite_chan);
812 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
815 static int ni_660x_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
819 struct ni_gpct *counter = subdev_to_counter(s);
820 /* const struct comedi_cmd *cmd = &s->async->cmd; */
822 retval = ni_660x_request_mite_channel(dev, counter, COMEDI_INPUT);
825 "no dma channel available for use by counter");
828 ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
829 retval = ni_tio_cmd(counter, s->async);
834 static int ni_660x_cmdtest(struct comedi_device *dev,
835 struct comedi_subdevice *s, struct comedi_cmd *cmd)
837 struct ni_gpct *counter = subdev_to_counter(s);
839 return ni_tio_cmdtest(counter, cmd);
842 static int ni_660x_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
844 struct ni_gpct *counter = subdev_to_counter(s);
847 retval = ni_tio_cancel(counter);
848 ni_660x_release_mite_channel(dev, counter);
852 static void set_tio_counterswap(struct comedi_device *dev, int chipset)
854 /* See P. 3.5 of the Register-Level Programming manual. The
855 CounterSwap bit has to be set on the second chip, otherwise
856 it will try to use the same pins as the first chip.
859 ni_660x_write_register(dev, chipset, CounterSwap,
860 ClockConfigRegister);
862 ni_660x_write_register(dev, chipset, 0, ClockConfigRegister);
865 static void ni_660x_handle_gpct_interrupt(struct comedi_device *dev,
866 struct comedi_subdevice *s)
868 ni_tio_handle_interrupt(subdev_to_counter(s), s);
869 if (s->async->events) {
870 if (s->async->events & (COMEDI_CB_EOA | COMEDI_CB_ERROR |
871 COMEDI_CB_OVERFLOW)) {
872 ni_660x_cancel(dev, s);
874 comedi_event(dev, s);
878 static irqreturn_t ni_660x_interrupt(int irq, void *d)
880 struct comedi_device *dev = d;
881 struct ni_660x_private *devpriv = dev->private;
882 struct comedi_subdevice *s;
886 if (dev->attached == 0)
888 /* lock to avoid race with comedi_poll */
889 spin_lock_irqsave(&devpriv->interrupt_lock, flags);
891 for (i = 0; i < ni_660x_num_counters(dev); ++i) {
892 s = &dev->subdevices[NI_660X_GPCT_SUBDEV(i)];
893 ni_660x_handle_gpct_interrupt(dev, s);
895 spin_unlock_irqrestore(&devpriv->interrupt_lock, flags);
899 static int ni_660x_input_poll(struct comedi_device *dev,
900 struct comedi_subdevice *s)
902 struct ni_660x_private *devpriv = dev->private;
905 /* lock to avoid race with comedi_poll */
906 spin_lock_irqsave(&devpriv->interrupt_lock, flags);
907 mite_sync_input_dma(subdev_to_counter(s)->mite_chan, s->async);
908 spin_unlock_irqrestore(&devpriv->interrupt_lock, flags);
909 return comedi_buf_read_n_available(s->async);
912 static int ni_660x_buf_change(struct comedi_device *dev,
913 struct comedi_subdevice *s,
914 unsigned long new_size)
916 struct ni_660x_private *devpriv = dev->private;
919 ret = mite_buf_change(mite_ring(devpriv, subdev_to_counter(s)),
927 static int ni_660x_allocate_private(struct comedi_device *dev)
929 struct ni_660x_private *devpriv;
932 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
935 dev->private = devpriv;
937 spin_lock_init(&devpriv->mite_channel_lock);
938 spin_lock_init(&devpriv->interrupt_lock);
939 spin_lock_init(&devpriv->soft_reg_copy_lock);
940 for (i = 0; i < NUM_PFI_CHANNELS; ++i)
941 devpriv->pfi_output_selects[i] = pfi_output_select_counter;
946 static int ni_660x_alloc_mite_rings(struct comedi_device *dev)
948 const struct ni_660x_board *board = comedi_board(dev);
949 struct ni_660x_private *devpriv = dev->private;
953 for (i = 0; i < board->n_chips; ++i) {
954 for (j = 0; j < counters_per_chip; ++j) {
955 devpriv->mite_rings[i][j] =
956 mite_alloc_ring(devpriv->mite);
957 if (devpriv->mite_rings[i][j] == NULL)
964 static void ni_660x_free_mite_rings(struct comedi_device *dev)
966 const struct ni_660x_board *board = comedi_board(dev);
967 struct ni_660x_private *devpriv = dev->private;
971 for (i = 0; i < board->n_chips; ++i) {
972 for (j = 0; j < counters_per_chip; ++j)
973 mite_free_ring(devpriv->mite_rings[i][j]);
977 static const struct ni_660x_board *
978 ni_660x_find_boardinfo(struct pci_dev *pcidev)
980 unsigned int dev_id = pcidev->device;
983 for (n = 0; n < ARRAY_SIZE(ni_660x_boards); n++) {
984 const struct ni_660x_board *board = &ni_660x_boards[n];
985 if (board->dev_id == dev_id)
992 ni_660x_GPCT_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
993 struct comedi_insn *insn, unsigned int *data)
995 return ni_tio_rinsn(subdev_to_counter(s), insn, data);
998 static void init_tio_chip(struct comedi_device *dev, int chipset)
1000 struct ni_660x_private *devpriv = dev->private;
1003 /* init dma configuration register */
1004 devpriv->dma_configuration_soft_copies[chipset] = 0;
1005 for (i = 0; i < MAX_DMA_CHANNEL; ++i) {
1006 devpriv->dma_configuration_soft_copies[chipset] |=
1007 dma_select_bits(i, dma_selection_none) & dma_select_mask(i);
1009 ni_660x_write_register(dev, chipset,
1010 devpriv->dma_configuration_soft_copies[chipset],
1012 for (i = 0; i < NUM_PFI_CHANNELS; ++i)
1013 ni_660x_write_register(dev, chipset, 0, IOConfigReg(i));
1017 ni_660x_GPCT_insn_config(struct comedi_device *dev, struct comedi_subdevice *s,
1018 struct comedi_insn *insn, unsigned int *data)
1020 return ni_tio_insn_config(subdev_to_counter(s), insn, data);
1023 static int ni_660x_GPCT_winsn(struct comedi_device *dev,
1024 struct comedi_subdevice *s,
1025 struct comedi_insn *insn, unsigned int *data)
1027 return ni_tio_winsn(subdev_to_counter(s), insn, data);
1030 static int ni_660x_dio_insn_bits(struct comedi_device *dev,
1031 struct comedi_subdevice *s,
1032 struct comedi_insn *insn, unsigned int *data)
1034 unsigned base_bitfield_channel = CR_CHAN(insn->chanspec);
1036 /* Check if we have to write some bits */
1038 s->state &= ~(data[0] << base_bitfield_channel);
1039 s->state |= (data[0] & data[1]) << base_bitfield_channel;
1040 /* Write out the new digital output lines */
1041 ni_660x_write_register(dev, 0, s->state, DIO32Output);
1043 /* on return, data[1] contains the value of the digital
1044 * input and output lines. */
1046 (ni_660x_read_register(dev, 0,
1047 DIO32Input) >> base_bitfield_channel);
1051 static void ni_660x_select_pfi_output(struct comedi_device *dev,
1052 unsigned pfi_channel,
1053 unsigned output_select)
1055 const struct ni_660x_board *board = comedi_board(dev);
1056 static const unsigned counter_4_7_first_pfi = 8;
1057 static const unsigned counter_4_7_last_pfi = 23;
1058 unsigned active_chipset = 0;
1059 unsigned idle_chipset = 0;
1060 unsigned active_bits;
1063 if (board->n_chips > 1) {
1064 if (output_select == pfi_output_select_counter &&
1065 pfi_channel >= counter_4_7_first_pfi &&
1066 pfi_channel <= counter_4_7_last_pfi) {
1075 if (idle_chipset != active_chipset) {
1077 ni_660x_read_register(dev, idle_chipset,
1078 IOConfigReg(pfi_channel));
1079 idle_bits &= ~pfi_output_select_mask(pfi_channel);
1081 pfi_output_select_bits(pfi_channel,
1082 pfi_output_select_high_Z);
1083 ni_660x_write_register(dev, idle_chipset, idle_bits,
1084 IOConfigReg(pfi_channel));
1088 ni_660x_read_register(dev, active_chipset,
1089 IOConfigReg(pfi_channel));
1090 active_bits &= ~pfi_output_select_mask(pfi_channel);
1091 active_bits |= pfi_output_select_bits(pfi_channel, output_select);
1092 ni_660x_write_register(dev, active_chipset, active_bits,
1093 IOConfigReg(pfi_channel));
1096 static int ni_660x_set_pfi_routing(struct comedi_device *dev, unsigned chan,
1099 struct ni_660x_private *devpriv = dev->private;
1101 if (source > num_pfi_output_selects)
1103 if (source == pfi_output_select_high_Z)
1105 if (chan < min_counter_pfi_chan) {
1106 if (source == pfi_output_select_counter)
1108 } else if (chan > max_dio_pfi_chan) {
1109 if (source == pfi_output_select_do)
1113 devpriv->pfi_output_selects[chan] = source;
1114 if (devpriv->pfi_direction_bits & (((uint64_t) 1) << chan))
1115 ni_660x_select_pfi_output(dev, chan,
1116 devpriv->pfi_output_selects[chan]);
1120 static int ni_660x_dio_insn_config(struct comedi_device *dev,
1121 struct comedi_subdevice *s,
1122 struct comedi_insn *insn,
1125 struct ni_660x_private *devpriv = dev->private;
1126 unsigned int chan = CR_CHAN(insn->chanspec);
1127 uint64_t bit = 1ULL << chan;
1132 case INSN_CONFIG_DIO_OUTPUT:
1133 devpriv->pfi_direction_bits |= bit;
1134 ni_660x_select_pfi_output(dev, chan,
1135 devpriv->pfi_output_selects[chan]);
1138 case INSN_CONFIG_DIO_INPUT:
1139 devpriv->pfi_direction_bits &= ~bit;
1140 ni_660x_select_pfi_output(dev, chan, pfi_output_select_high_Z);
1143 case INSN_CONFIG_DIO_QUERY:
1144 data[1] = (devpriv->pfi_direction_bits & bit) ? COMEDI_OUTPUT
1148 case INSN_CONFIG_SET_ROUTING:
1149 ret = ni_660x_set_pfi_routing(dev, chan, data[1]);
1154 case INSN_CONFIG_GET_ROUTING:
1155 data[1] = devpriv->pfi_output_selects[chan];
1158 case INSN_CONFIG_FILTER:
1159 val = ni_660x_read_register(dev, 0, IOConfigReg(chan));
1160 val &= ~pfi_input_select_mask(chan);
1161 val |= pfi_input_select_bits(chan, data[1]);
1162 ni_660x_write_register(dev, 0, val, IOConfigReg(chan));
1172 static int ni_660x_auto_attach(struct comedi_device *dev,
1173 unsigned long context_unused)
1175 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1176 const struct ni_660x_board *board;
1177 struct ni_660x_private *devpriv;
1178 struct comedi_subdevice *s;
1181 unsigned global_interrupt_config_bits;
1183 ret = ni_660x_allocate_private(dev);
1186 devpriv = dev->private;
1188 dev->board_ptr = ni_660x_find_boardinfo(pcidev);
1189 if (!dev->board_ptr)
1191 board = comedi_board(dev);
1193 devpriv->mite = mite_alloc(pcidev);
1197 dev->board_name = board->name;
1199 ret = mite_setup2(devpriv->mite, 1);
1201 dev_warn(dev->class_dev, "error setting up mite\n");
1205 ret = ni_660x_alloc_mite_rings(dev);
1209 ret = comedi_alloc_subdevices(dev, 2 + NI_660X_MAX_NUM_COUNTERS);
1213 s = &dev->subdevices[0];
1214 /* Old GENERAL-PURPOSE COUNTER/TIME (GPCT) subdevice, no longer used */
1215 s->type = COMEDI_SUBD_UNUSED;
1217 s = &dev->subdevices[NI_660X_DIO_SUBDEV];
1218 /* DIGITAL I/O SUBDEVICE */
1219 s->type = COMEDI_SUBD_DIO;
1220 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1221 s->n_chan = NUM_PFI_CHANNELS;
1223 s->range_table = &range_digital;
1224 s->insn_bits = ni_660x_dio_insn_bits;
1225 s->insn_config = ni_660x_dio_insn_config;
1226 s->io_bits = 0; /* all bits default to input */
1227 /* we use the ioconfig registers to control dio direction, so zero
1228 output enables in stc dio control reg */
1229 ni_660x_write_register(dev, 0, 0, STCDIOControl);
1231 devpriv->counter_dev = ni_gpct_device_construct(dev,
1232 &ni_gpct_write_register,
1233 &ni_gpct_read_register,
1234 ni_gpct_variant_660x,
1235 ni_660x_num_counters
1237 if (devpriv->counter_dev == NULL)
1239 for (i = 0; i < NI_660X_MAX_NUM_COUNTERS; ++i) {
1240 s = &dev->subdevices[NI_660X_GPCT_SUBDEV(i)];
1241 if (i < ni_660x_num_counters(dev)) {
1242 s->type = COMEDI_SUBD_COUNTER;
1244 SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL |
1245 SDF_CMD_READ /* | SDF_CMD_WRITE */ ;
1247 s->maxdata = 0xffffffff;
1248 s->insn_read = ni_660x_GPCT_rinsn;
1249 s->insn_write = ni_660x_GPCT_winsn;
1250 s->insn_config = ni_660x_GPCT_insn_config;
1251 s->do_cmd = &ni_660x_cmd;
1252 s->len_chanlist = 1;
1253 s->do_cmdtest = &ni_660x_cmdtest;
1254 s->cancel = &ni_660x_cancel;
1255 s->poll = &ni_660x_input_poll;
1256 s->async_dma_dir = DMA_BIDIRECTIONAL;
1257 s->buf_change = &ni_660x_buf_change;
1258 s->private = &devpriv->counter_dev->counters[i];
1260 devpriv->counter_dev->counters[i].chip_index =
1261 i / counters_per_chip;
1262 devpriv->counter_dev->counters[i].counter_index =
1263 i % counters_per_chip;
1265 s->type = COMEDI_SUBD_UNUSED;
1268 for (i = 0; i < board->n_chips; ++i)
1269 init_tio_chip(dev, i);
1271 for (i = 0; i < ni_660x_num_counters(dev); ++i)
1272 ni_tio_init_counter(&devpriv->counter_dev->counters[i]);
1274 for (i = 0; i < NUM_PFI_CHANNELS; ++i) {
1275 if (i < min_counter_pfi_chan)
1276 ni_660x_set_pfi_routing(dev, i, pfi_output_select_do);
1278 ni_660x_set_pfi_routing(dev, i,
1279 pfi_output_select_counter);
1280 ni_660x_select_pfi_output(dev, i, pfi_output_select_high_Z);
1282 /* to be safe, set counterswap bits on tio chips after all the counter
1283 outputs have been set to high impedance mode */
1284 for (i = 0; i < board->n_chips; ++i)
1285 set_tio_counterswap(dev, i);
1287 ret = request_irq(mite_irq(devpriv->mite), ni_660x_interrupt,
1288 IRQF_SHARED, "ni_660x", dev);
1290 dev_warn(dev->class_dev, " irq not available\n");
1293 dev->irq = mite_irq(devpriv->mite);
1294 global_interrupt_config_bits = Global_Int_Enable_Bit;
1295 if (board->n_chips > 1)
1296 global_interrupt_config_bits |= Cascade_Int_Enable_Bit;
1297 ni_660x_write_register(dev, 0, global_interrupt_config_bits,
1298 GlobalInterruptConfigRegister);
1299 dev_info(dev->class_dev, "ni_660x: %s attached\n", dev->board_name);
1303 static void ni_660x_detach(struct comedi_device *dev)
1305 struct ni_660x_private *devpriv = dev->private;
1308 free_irq(dev->irq, dev);
1310 if (devpriv->counter_dev)
1311 ni_gpct_device_destroy(devpriv->counter_dev);
1312 if (devpriv->mite) {
1313 ni_660x_free_mite_rings(dev);
1314 mite_unsetup(devpriv->mite);
1315 mite_free(devpriv->mite);
1320 static struct comedi_driver ni_660x_driver = {
1321 .driver_name = "ni_660x",
1322 .module = THIS_MODULE,
1323 .auto_attach = ni_660x_auto_attach,
1324 .detach = ni_660x_detach,
1327 static int ni_660x_pci_probe(struct pci_dev *dev,
1328 const struct pci_device_id *ent)
1330 return comedi_pci_auto_config(dev, &ni_660x_driver);
1333 static DEFINE_PCI_DEVICE_TABLE(ni_660x_pci_table) = {
1334 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2c60)},
1335 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1310)},
1336 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1360)},
1337 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2cc0)},
1340 MODULE_DEVICE_TABLE(pci, ni_660x_pci_table);
1342 static struct pci_driver ni_660x_pci_driver = {
1344 .id_table = ni_660x_pci_table,
1345 .probe = ni_660x_pci_probe,
1346 .remove = comedi_pci_auto_unconfig,
1348 module_comedi_pci_driver(ni_660x_driver, ni_660x_pci_driver);
1350 MODULE_AUTHOR("Comedi http://www.comedi.org");
1351 MODULE_DESCRIPTION("Comedi low-level driver");
1352 MODULE_LICENSE("GPL");