2 comedi/drivers/ni_660x.c
3 Hardware driver for NI 660x devices
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 Description: National Instruments 660x counter/timer boards
24 [National Instruments] PCI-6601 (ni_660x), PCI-6602, PXI-6602,
26 Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
27 Herman.Bruyninckx@mech.kuleuven.ac.be,
28 Wim.Meeussen@mech.kuleuven.ac.be,
29 Klaas.Gadeyne@mech.kuleuven.ac.be,
30 Frank Mori Hess <fmhess@users.sourceforge.net>
31 Updated: Thu Oct 18 12:56:06 EDT 2007
34 Encoders work. PulseGeneration (both single pulse and pulse train)
35 works. Buffered commands work for input but not output.
38 DAQ 660x Register-Level Programmer Manual (NI 370505A-01)
39 DAQ 6601/6602 User Manual (NI 322137B-01)
43 #include <linux/interrupt.h>
44 #include "../comedidev.h"
48 enum ni_660x_constants {
49 min_counter_pfi_chan = 8,
50 max_dio_pfi_chan = 31,
54 #define NUM_PFI_CHANNELS 40
55 /* really there are only up to 3 dma channels, but the register layout allows
57 #define MAX_DMA_CHANNEL 4
59 /* See Register-Level Programmer Manual page 3.1 */
60 enum NI_660x_Register {
61 G0InterruptAcknowledge,
63 G1InterruptAcknowledge,
76 G01JointStatus1Register,
80 G01JointStatus2Register,
84 G0InputSelectRegister,
85 G1InputSelectRegister,
86 G0AutoincrementRegister,
87 G1AutoincrementRegister,
88 G01JointResetRegister,
91 G0CountingModeRegister,
92 G1CountingModeRegister,
99 G2InterruptAcknowledge,
101 G3InterruptAcknowledge,
111 G23JointStatus1Register,
114 G23JointStatus2Register,
118 G2InputSelectRegister,
119 G3InputSelectRegister,
120 G2AutoincrementRegister,
121 G3AutoincrementRegister,
122 G23JointResetRegister,
125 G2CountingModeRegister,
126 G3CountingModeRegister,
127 G3SecondGateRegister,
128 G2SecondGateRegister,
136 GlobalInterruptStatusRegister,
138 GlobalInterruptConfigRegister,
162 static inline unsigned IOConfigReg(unsigned pfi_channel)
164 unsigned reg = IOConfigReg0_1 + pfi_channel / 2;
165 BUG_ON(reg > IOConfigReg38_39);
169 enum ni_660x_register_width {
175 enum ni_660x_register_direction {
181 enum ni_660x_pfi_output_select {
182 pfi_output_select_high_Z = 0,
183 pfi_output_select_counter = 1,
184 pfi_output_select_do = 2,
185 num_pfi_output_selects
188 enum ni_660x_subdevices {
189 NI_660X_DIO_SUBDEV = 1,
190 NI_660X_GPCT_SUBDEV_0 = 2
192 static inline unsigned NI_660X_GPCT_SUBDEV(unsigned index)
194 return NI_660X_GPCT_SUBDEV_0 + index;
197 struct NI_660xRegisterData {
199 const char *name; /* Register Name */
200 int offset; /* Offset from base address from GPCT chip */
201 enum ni_660x_register_direction direction;
202 enum ni_660x_register_width size; /* 1 byte, 2 bytes, or 4 bytes */
205 static const struct NI_660xRegisterData registerData[NumRegisters] = {
206 {"G0 Interrupt Acknowledge", 0x004, NI_660x_WRITE, DATA_2B},
207 {"G0 Status Register", 0x004, NI_660x_READ, DATA_2B},
208 {"G1 Interrupt Acknowledge", 0x006, NI_660x_WRITE, DATA_2B},
209 {"G1 Status Register", 0x006, NI_660x_READ, DATA_2B},
210 {"G01 Status Register ", 0x008, NI_660x_READ, DATA_2B},
211 {"G0 Command Register", 0x00C, NI_660x_WRITE, DATA_2B},
212 {"STC DIO Parallel Input", 0x00E, NI_660x_READ, DATA_2B},
213 {"G1 Command Register", 0x00E, NI_660x_WRITE, DATA_2B},
214 {"G0 HW Save Register", 0x010, NI_660x_READ, DATA_4B},
215 {"G1 HW Save Register", 0x014, NI_660x_READ, DATA_4B},
216 {"STC DIO Output", 0x014, NI_660x_WRITE, DATA_2B},
217 {"STC DIO Control", 0x016, NI_660x_WRITE, DATA_2B},
218 {"G0 SW Save Register", 0x018, NI_660x_READ, DATA_4B},
219 {"G1 SW Save Register", 0x01C, NI_660x_READ, DATA_4B},
220 {"G0 Mode Register", 0x034, NI_660x_WRITE, DATA_2B},
221 {"G01 Joint Status 1 Register", 0x036, NI_660x_READ, DATA_2B},
222 {"G1 Mode Register", 0x036, NI_660x_WRITE, DATA_2B},
223 {"STC DIO Serial Input", 0x038, NI_660x_READ, DATA_2B},
224 {"G0 Load A Register", 0x038, NI_660x_WRITE, DATA_4B},
225 {"G01 Joint Status 2 Register", 0x03A, NI_660x_READ, DATA_2B},
226 {"G0 Load B Register", 0x03C, NI_660x_WRITE, DATA_4B},
227 {"G1 Load A Register", 0x040, NI_660x_WRITE, DATA_4B},
228 {"G1 Load B Register", 0x044, NI_660x_WRITE, DATA_4B},
229 {"G0 Input Select Register", 0x048, NI_660x_WRITE, DATA_2B},
230 {"G1 Input Select Register", 0x04A, NI_660x_WRITE, DATA_2B},
231 {"G0 Autoincrement Register", 0x088, NI_660x_WRITE, DATA_2B},
232 {"G1 Autoincrement Register", 0x08A, NI_660x_WRITE, DATA_2B},
233 {"G01 Joint Reset Register", 0x090, NI_660x_WRITE, DATA_2B},
234 {"G0 Interrupt Enable", 0x092, NI_660x_WRITE, DATA_2B},
235 {"G1 Interrupt Enable", 0x096, NI_660x_WRITE, DATA_2B},
236 {"G0 Counting Mode Register", 0x0B0, NI_660x_WRITE, DATA_2B},
237 {"G1 Counting Mode Register", 0x0B2, NI_660x_WRITE, DATA_2B},
238 {"G0 Second Gate Register", 0x0B4, NI_660x_WRITE, DATA_2B},
239 {"G1 Second Gate Register", 0x0B6, NI_660x_WRITE, DATA_2B},
240 {"G0 DMA Config Register", 0x0B8, NI_660x_WRITE, DATA_2B},
241 {"G0 DMA Status Register", 0x0B8, NI_660x_READ, DATA_2B},
242 {"G1 DMA Config Register", 0x0BA, NI_660x_WRITE, DATA_2B},
243 {"G1 DMA Status Register", 0x0BA, NI_660x_READ, DATA_2B},
244 {"G2 Interrupt Acknowledge", 0x104, NI_660x_WRITE, DATA_2B},
245 {"G2 Status Register", 0x104, NI_660x_READ, DATA_2B},
246 {"G3 Interrupt Acknowledge", 0x106, NI_660x_WRITE, DATA_2B},
247 {"G3 Status Register", 0x106, NI_660x_READ, DATA_2B},
248 {"G23 Status Register", 0x108, NI_660x_READ, DATA_2B},
249 {"G2 Command Register", 0x10C, NI_660x_WRITE, DATA_2B},
250 {"G3 Command Register", 0x10E, NI_660x_WRITE, DATA_2B},
251 {"G2 HW Save Register", 0x110, NI_660x_READ, DATA_4B},
252 {"G3 HW Save Register", 0x114, NI_660x_READ, DATA_4B},
253 {"G2 SW Save Register", 0x118, NI_660x_READ, DATA_4B},
254 {"G3 SW Save Register", 0x11C, NI_660x_READ, DATA_4B},
255 {"G2 Mode Register", 0x134, NI_660x_WRITE, DATA_2B},
256 {"G23 Joint Status 1 Register", 0x136, NI_660x_READ, DATA_2B},
257 {"G3 Mode Register", 0x136, NI_660x_WRITE, DATA_2B},
258 {"G2 Load A Register", 0x138, NI_660x_WRITE, DATA_4B},
259 {"G23 Joint Status 2 Register", 0x13A, NI_660x_READ, DATA_2B},
260 {"G2 Load B Register", 0x13C, NI_660x_WRITE, DATA_4B},
261 {"G3 Load A Register", 0x140, NI_660x_WRITE, DATA_4B},
262 {"G3 Load B Register", 0x144, NI_660x_WRITE, DATA_4B},
263 {"G2 Input Select Register", 0x148, NI_660x_WRITE, DATA_2B},
264 {"G3 Input Select Register", 0x14A, NI_660x_WRITE, DATA_2B},
265 {"G2 Autoincrement Register", 0x188, NI_660x_WRITE, DATA_2B},
266 {"G3 Autoincrement Register", 0x18A, NI_660x_WRITE, DATA_2B},
267 {"G23 Joint Reset Register", 0x190, NI_660x_WRITE, DATA_2B},
268 {"G2 Interrupt Enable", 0x192, NI_660x_WRITE, DATA_2B},
269 {"G3 Interrupt Enable", 0x196, NI_660x_WRITE, DATA_2B},
270 {"G2 Counting Mode Register", 0x1B0, NI_660x_WRITE, DATA_2B},
271 {"G3 Counting Mode Register", 0x1B2, NI_660x_WRITE, DATA_2B},
272 {"G3 Second Gate Register", 0x1B6, NI_660x_WRITE, DATA_2B},
273 {"G2 Second Gate Register", 0x1B4, NI_660x_WRITE, DATA_2B},
274 {"G2 DMA Config Register", 0x1B8, NI_660x_WRITE, DATA_2B},
275 {"G2 DMA Status Register", 0x1B8, NI_660x_READ, DATA_2B},
276 {"G3 DMA Config Register", 0x1BA, NI_660x_WRITE, DATA_2B},
277 {"G3 DMA Status Register", 0x1BA, NI_660x_READ, DATA_2B},
278 {"32 bit Digital Input", 0x414, NI_660x_READ, DATA_4B},
279 {"32 bit Digital Output", 0x510, NI_660x_WRITE, DATA_4B},
280 {"Clock Config Register", 0x73C, NI_660x_WRITE, DATA_4B},
281 {"Global Interrupt Status Register", 0x754, NI_660x_READ, DATA_4B},
282 {"DMA Configuration Register", 0x76C, NI_660x_WRITE, DATA_4B},
283 {"Global Interrupt Config Register", 0x770, NI_660x_WRITE, DATA_4B},
284 {"IO Config Register 0-1", 0x77C, NI_660x_READ_WRITE, DATA_2B},
285 {"IO Config Register 2-3", 0x77E, NI_660x_READ_WRITE, DATA_2B},
286 {"IO Config Register 4-5", 0x780, NI_660x_READ_WRITE, DATA_2B},
287 {"IO Config Register 6-7", 0x782, NI_660x_READ_WRITE, DATA_2B},
288 {"IO Config Register 8-9", 0x784, NI_660x_READ_WRITE, DATA_2B},
289 {"IO Config Register 10-11", 0x786, NI_660x_READ_WRITE, DATA_2B},
290 {"IO Config Register 12-13", 0x788, NI_660x_READ_WRITE, DATA_2B},
291 {"IO Config Register 14-15", 0x78A, NI_660x_READ_WRITE, DATA_2B},
292 {"IO Config Register 16-17", 0x78C, NI_660x_READ_WRITE, DATA_2B},
293 {"IO Config Register 18-19", 0x78E, NI_660x_READ_WRITE, DATA_2B},
294 {"IO Config Register 20-21", 0x790, NI_660x_READ_WRITE, DATA_2B},
295 {"IO Config Register 22-23", 0x792, NI_660x_READ_WRITE, DATA_2B},
296 {"IO Config Register 24-25", 0x794, NI_660x_READ_WRITE, DATA_2B},
297 {"IO Config Register 26-27", 0x796, NI_660x_READ_WRITE, DATA_2B},
298 {"IO Config Register 28-29", 0x798, NI_660x_READ_WRITE, DATA_2B},
299 {"IO Config Register 30-31", 0x79A, NI_660x_READ_WRITE, DATA_2B},
300 {"IO Config Register 32-33", 0x79C, NI_660x_READ_WRITE, DATA_2B},
301 {"IO Config Register 34-35", 0x79E, NI_660x_READ_WRITE, DATA_2B},
302 {"IO Config Register 36-37", 0x7A0, NI_660x_READ_WRITE, DATA_2B},
303 {"IO Config Register 38-39", 0x7A2, NI_660x_READ_WRITE, DATA_2B}
306 /* kind of ENABLE for the second counter */
307 enum clock_config_register_bits {
308 CounterSwap = 0x1 << 21
312 static inline unsigned ioconfig_bitshift(unsigned pfi_channel)
320 static inline unsigned pfi_output_select_mask(unsigned pfi_channel)
322 return 0x3 << ioconfig_bitshift(pfi_channel);
325 static inline unsigned pfi_output_select_bits(unsigned pfi_channel,
326 unsigned output_select)
328 return (output_select & 0x3) << ioconfig_bitshift(pfi_channel);
331 static inline unsigned pfi_input_select_mask(unsigned pfi_channel)
333 return 0x7 << (4 + ioconfig_bitshift(pfi_channel));
336 static inline unsigned pfi_input_select_bits(unsigned pfi_channel,
337 unsigned input_select)
339 return (input_select & 0x7) << (4 + ioconfig_bitshift(pfi_channel));
342 /* dma configuration register bits */
343 static inline unsigned dma_select_mask(unsigned dma_channel)
345 BUG_ON(dma_channel >= MAX_DMA_CHANNEL);
346 return 0x1f << (8 * dma_channel);
350 dma_selection_none = 0x1f,
352 static inline unsigned dma_selection_counter(unsigned counter_index)
354 BUG_ON(counter_index >= counters_per_chip);
355 return counter_index;
358 static inline unsigned dma_select_bits(unsigned dma_channel, unsigned selection)
360 BUG_ON(dma_channel >= MAX_DMA_CHANNEL);
361 return (selection << (8 * dma_channel)) & dma_select_mask(dma_channel);
364 static inline unsigned dma_reset_bit(unsigned dma_channel)
366 BUG_ON(dma_channel >= MAX_DMA_CHANNEL);
367 return 0x80 << (8 * dma_channel);
370 enum global_interrupt_status_register_bits {
371 Counter_0_Int_Bit = 0x100,
372 Counter_1_Int_Bit = 0x200,
373 Counter_2_Int_Bit = 0x400,
374 Counter_3_Int_Bit = 0x800,
375 Cascade_Int_Bit = 0x20000000,
376 Global_Int_Bit = 0x80000000
379 enum global_interrupt_config_register_bits {
380 Cascade_Int_Enable_Bit = 0x20000000,
381 Global_Int_Polarity_Bit = 0x40000000,
382 Global_Int_Enable_Bit = 0x80000000
385 /* Offset of the GPCT chips from the base-address of the card */
386 /* First chip is at base-address + 0x00, etc. */
387 static const unsigned GPCT_OFFSET[2] = { 0x0, 0x800 };
389 /* Board description*/
390 struct ni_660x_board {
391 unsigned short dev_id; /* `lspci` will show you this */
393 unsigned n_chips; /* total number of TIO chips */
396 static const struct ni_660x_board ni_660x_boards[] = {
419 #define NI_660X_MAX_NUM_CHIPS 2
420 #define NI_660X_MAX_NUM_COUNTERS (NI_660X_MAX_NUM_CHIPS * counters_per_chip)
422 struct ni_660x_private {
423 struct mite_struct *mite;
424 struct ni_gpct_device *counter_dev;
425 uint64_t pfi_direction_bits;
426 struct mite_dma_descriptor_ring
427 *mite_rings[NI_660X_MAX_NUM_CHIPS][counters_per_chip];
428 spinlock_t mite_channel_lock;
429 /* interrupt_lock prevents races between interrupt and comedi_poll */
430 spinlock_t interrupt_lock;
431 unsigned dma_configuration_soft_copies[NI_660X_MAX_NUM_CHIPS];
432 spinlock_t soft_reg_copy_lock;
433 unsigned short pfi_output_selects[NUM_PFI_CHANNELS];
436 static inline unsigned ni_660x_num_counters(struct comedi_device *dev)
438 const struct ni_660x_board *board = comedi_board(dev);
440 return board->n_chips * counters_per_chip;
443 static enum NI_660x_Register ni_gpct_to_660x_register(enum ni_gpct_register reg)
445 enum NI_660x_Register ni_660x_register;
447 case NITIO_G0_Autoincrement_Reg:
448 ni_660x_register = G0AutoincrementRegister;
450 case NITIO_G1_Autoincrement_Reg:
451 ni_660x_register = G1AutoincrementRegister;
453 case NITIO_G2_Autoincrement_Reg:
454 ni_660x_register = G2AutoincrementRegister;
456 case NITIO_G3_Autoincrement_Reg:
457 ni_660x_register = G3AutoincrementRegister;
459 case NITIO_G0_Command_Reg:
460 ni_660x_register = G0CommandRegister;
462 case NITIO_G1_Command_Reg:
463 ni_660x_register = G1CommandRegister;
465 case NITIO_G2_Command_Reg:
466 ni_660x_register = G2CommandRegister;
468 case NITIO_G3_Command_Reg:
469 ni_660x_register = G3CommandRegister;
471 case NITIO_G0_HW_Save_Reg:
472 ni_660x_register = G0HWSaveRegister;
474 case NITIO_G1_HW_Save_Reg:
475 ni_660x_register = G1HWSaveRegister;
477 case NITIO_G2_HW_Save_Reg:
478 ni_660x_register = G2HWSaveRegister;
480 case NITIO_G3_HW_Save_Reg:
481 ni_660x_register = G3HWSaveRegister;
483 case NITIO_G0_SW_Save_Reg:
484 ni_660x_register = G0SWSaveRegister;
486 case NITIO_G1_SW_Save_Reg:
487 ni_660x_register = G1SWSaveRegister;
489 case NITIO_G2_SW_Save_Reg:
490 ni_660x_register = G2SWSaveRegister;
492 case NITIO_G3_SW_Save_Reg:
493 ni_660x_register = G3SWSaveRegister;
495 case NITIO_G0_Mode_Reg:
496 ni_660x_register = G0ModeRegister;
498 case NITIO_G1_Mode_Reg:
499 ni_660x_register = G1ModeRegister;
501 case NITIO_G2_Mode_Reg:
502 ni_660x_register = G2ModeRegister;
504 case NITIO_G3_Mode_Reg:
505 ni_660x_register = G3ModeRegister;
507 case NITIO_G0_LoadA_Reg:
508 ni_660x_register = G0LoadARegister;
510 case NITIO_G1_LoadA_Reg:
511 ni_660x_register = G1LoadARegister;
513 case NITIO_G2_LoadA_Reg:
514 ni_660x_register = G2LoadARegister;
516 case NITIO_G3_LoadA_Reg:
517 ni_660x_register = G3LoadARegister;
519 case NITIO_G0_LoadB_Reg:
520 ni_660x_register = G0LoadBRegister;
522 case NITIO_G1_LoadB_Reg:
523 ni_660x_register = G1LoadBRegister;
525 case NITIO_G2_LoadB_Reg:
526 ni_660x_register = G2LoadBRegister;
528 case NITIO_G3_LoadB_Reg:
529 ni_660x_register = G3LoadBRegister;
531 case NITIO_G0_Input_Select_Reg:
532 ni_660x_register = G0InputSelectRegister;
534 case NITIO_G1_Input_Select_Reg:
535 ni_660x_register = G1InputSelectRegister;
537 case NITIO_G2_Input_Select_Reg:
538 ni_660x_register = G2InputSelectRegister;
540 case NITIO_G3_Input_Select_Reg:
541 ni_660x_register = G3InputSelectRegister;
543 case NITIO_G01_Status_Reg:
544 ni_660x_register = G01StatusRegister;
546 case NITIO_G23_Status_Reg:
547 ni_660x_register = G23StatusRegister;
549 case NITIO_G01_Joint_Reset_Reg:
550 ni_660x_register = G01JointResetRegister;
552 case NITIO_G23_Joint_Reset_Reg:
553 ni_660x_register = G23JointResetRegister;
555 case NITIO_G01_Joint_Status1_Reg:
556 ni_660x_register = G01JointStatus1Register;
558 case NITIO_G23_Joint_Status1_Reg:
559 ni_660x_register = G23JointStatus1Register;
561 case NITIO_G01_Joint_Status2_Reg:
562 ni_660x_register = G01JointStatus2Register;
564 case NITIO_G23_Joint_Status2_Reg:
565 ni_660x_register = G23JointStatus2Register;
567 case NITIO_G0_Counting_Mode_Reg:
568 ni_660x_register = G0CountingModeRegister;
570 case NITIO_G1_Counting_Mode_Reg:
571 ni_660x_register = G1CountingModeRegister;
573 case NITIO_G2_Counting_Mode_Reg:
574 ni_660x_register = G2CountingModeRegister;
576 case NITIO_G3_Counting_Mode_Reg:
577 ni_660x_register = G3CountingModeRegister;
579 case NITIO_G0_Second_Gate_Reg:
580 ni_660x_register = G0SecondGateRegister;
582 case NITIO_G1_Second_Gate_Reg:
583 ni_660x_register = G1SecondGateRegister;
585 case NITIO_G2_Second_Gate_Reg:
586 ni_660x_register = G2SecondGateRegister;
588 case NITIO_G3_Second_Gate_Reg:
589 ni_660x_register = G3SecondGateRegister;
591 case NITIO_G0_DMA_Config_Reg:
592 ni_660x_register = G0DMAConfigRegister;
594 case NITIO_G0_DMA_Status_Reg:
595 ni_660x_register = G0DMAStatusRegister;
597 case NITIO_G1_DMA_Config_Reg:
598 ni_660x_register = G1DMAConfigRegister;
600 case NITIO_G1_DMA_Status_Reg:
601 ni_660x_register = G1DMAStatusRegister;
603 case NITIO_G2_DMA_Config_Reg:
604 ni_660x_register = G2DMAConfigRegister;
606 case NITIO_G2_DMA_Status_Reg:
607 ni_660x_register = G2DMAStatusRegister;
609 case NITIO_G3_DMA_Config_Reg:
610 ni_660x_register = G3DMAConfigRegister;
612 case NITIO_G3_DMA_Status_Reg:
613 ni_660x_register = G3DMAStatusRegister;
615 case NITIO_G0_Interrupt_Acknowledge_Reg:
616 ni_660x_register = G0InterruptAcknowledge;
618 case NITIO_G1_Interrupt_Acknowledge_Reg:
619 ni_660x_register = G1InterruptAcknowledge;
621 case NITIO_G2_Interrupt_Acknowledge_Reg:
622 ni_660x_register = G2InterruptAcknowledge;
624 case NITIO_G3_Interrupt_Acknowledge_Reg:
625 ni_660x_register = G3InterruptAcknowledge;
627 case NITIO_G0_Status_Reg:
628 ni_660x_register = G0StatusRegister;
630 case NITIO_G1_Status_Reg:
631 ni_660x_register = G1StatusRegister;
633 case NITIO_G2_Status_Reg:
634 ni_660x_register = G2StatusRegister;
636 case NITIO_G3_Status_Reg:
637 ni_660x_register = G3StatusRegister;
639 case NITIO_G0_Interrupt_Enable_Reg:
640 ni_660x_register = G0InterruptEnable;
642 case NITIO_G1_Interrupt_Enable_Reg:
643 ni_660x_register = G1InterruptEnable;
645 case NITIO_G2_Interrupt_Enable_Reg:
646 ni_660x_register = G2InterruptEnable;
648 case NITIO_G3_Interrupt_Enable_Reg:
649 ni_660x_register = G3InterruptEnable;
656 return ni_660x_register;
659 static inline void ni_660x_write_register(struct comedi_device *dev,
660 unsigned chip_index, unsigned bits,
661 enum NI_660x_Register reg)
663 struct ni_660x_private *devpriv = dev->private;
664 void __iomem *write_address =
665 devpriv->mite->daq_io_addr + GPCT_OFFSET[chip_index] +
666 registerData[reg].offset;
668 switch (registerData[reg].size) {
670 writew(bits, write_address);
673 writel(bits, write_address);
681 static inline unsigned ni_660x_read_register(struct comedi_device *dev,
683 enum NI_660x_Register reg)
685 struct ni_660x_private *devpriv = dev->private;
686 void __iomem *read_address =
687 devpriv->mite->daq_io_addr + GPCT_OFFSET[chip_index] +
688 registerData[reg].offset;
690 switch (registerData[reg].size) {
692 return readw(read_address);
695 return readl(read_address);
704 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
705 enum ni_gpct_register reg)
707 struct comedi_device *dev = counter->counter_dev->dev;
708 enum NI_660x_Register ni_660x_register = ni_gpct_to_660x_register(reg);
709 ni_660x_write_register(dev, counter->chip_index, bits,
713 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
714 enum ni_gpct_register reg)
716 struct comedi_device *dev = counter->counter_dev->dev;
717 enum NI_660x_Register ni_660x_register = ni_gpct_to_660x_register(reg);
718 return ni_660x_read_register(dev, counter->chip_index,
722 static inline struct mite_dma_descriptor_ring *mite_ring(struct ni_660x_private
727 return priv->mite_rings[counter->chip_index][counter->counter_index];
730 static inline void ni_660x_set_dma_channel(struct comedi_device *dev,
731 unsigned mite_channel,
732 struct ni_gpct *counter)
734 struct ni_660x_private *devpriv = dev->private;
737 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
738 devpriv->dma_configuration_soft_copies[counter->chip_index] &=
739 ~dma_select_mask(mite_channel);
740 devpriv->dma_configuration_soft_copies[counter->chip_index] |=
741 dma_select_bits(mite_channel,
742 dma_selection_counter(counter->counter_index));
743 ni_660x_write_register(dev, counter->chip_index,
744 devpriv->dma_configuration_soft_copies
745 [counter->chip_index] |
746 dma_reset_bit(mite_channel), DMAConfigRegister);
748 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
751 static inline void ni_660x_unset_dma_channel(struct comedi_device *dev,
752 unsigned mite_channel,
753 struct ni_gpct *counter)
755 struct ni_660x_private *devpriv = dev->private;
758 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
759 devpriv->dma_configuration_soft_copies[counter->chip_index] &=
760 ~dma_select_mask(mite_channel);
761 devpriv->dma_configuration_soft_copies[counter->chip_index] |=
762 dma_select_bits(mite_channel, dma_selection_none);
763 ni_660x_write_register(dev, counter->chip_index,
764 devpriv->dma_configuration_soft_copies
765 [counter->chip_index], DMAConfigRegister);
767 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
770 static int ni_660x_request_mite_channel(struct comedi_device *dev,
771 struct ni_gpct *counter,
772 enum comedi_io_direction direction)
774 struct ni_660x_private *devpriv = dev->private;
776 struct mite_channel *mite_chan;
778 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
779 BUG_ON(counter->mite_chan);
780 mite_chan = mite_request_channel(devpriv->mite,
781 mite_ring(devpriv, counter));
782 if (mite_chan == NULL) {
783 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
785 "failed to reserve mite dma channel for counter.");
788 mite_chan->dir = direction;
789 ni_tio_set_mite_channel(counter, mite_chan);
790 ni_660x_set_dma_channel(dev, mite_chan->channel, counter);
791 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
795 static void ni_660x_release_mite_channel(struct comedi_device *dev,
796 struct ni_gpct *counter)
798 struct ni_660x_private *devpriv = dev->private;
801 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
802 if (counter->mite_chan) {
803 struct mite_channel *mite_chan = counter->mite_chan;
805 ni_660x_unset_dma_channel(dev, mite_chan->channel, counter);
806 ni_tio_set_mite_channel(counter, NULL);
807 mite_release_channel(mite_chan);
809 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
812 static int ni_660x_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
816 struct ni_gpct *counter = subdev_to_counter(s);
817 /* const struct comedi_cmd *cmd = &s->async->cmd; */
819 retval = ni_660x_request_mite_channel(dev, counter, COMEDI_INPUT);
822 "no dma channel available for use by counter");
825 ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
826 retval = ni_tio_cmd(counter, s->async);
831 static int ni_660x_cmdtest(struct comedi_device *dev,
832 struct comedi_subdevice *s, struct comedi_cmd *cmd)
834 struct ni_gpct *counter = subdev_to_counter(s);
836 return ni_tio_cmdtest(counter, cmd);
839 static int ni_660x_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
841 struct ni_gpct *counter = subdev_to_counter(s);
844 retval = ni_tio_cancel(counter);
845 ni_660x_release_mite_channel(dev, counter);
849 static void set_tio_counterswap(struct comedi_device *dev, int chipset)
851 /* See P. 3.5 of the Register-Level Programming manual. The
852 CounterSwap bit has to be set on the second chip, otherwise
853 it will try to use the same pins as the first chip.
856 ni_660x_write_register(dev, chipset, CounterSwap,
857 ClockConfigRegister);
859 ni_660x_write_register(dev, chipset, 0, ClockConfigRegister);
862 static void ni_660x_handle_gpct_interrupt(struct comedi_device *dev,
863 struct comedi_subdevice *s)
865 ni_tio_handle_interrupt(subdev_to_counter(s), s);
866 if (s->async->events) {
867 if (s->async->events & (COMEDI_CB_EOA | COMEDI_CB_ERROR |
868 COMEDI_CB_OVERFLOW)) {
869 ni_660x_cancel(dev, s);
871 comedi_event(dev, s);
875 static irqreturn_t ni_660x_interrupt(int irq, void *d)
877 struct comedi_device *dev = d;
878 struct ni_660x_private *devpriv = dev->private;
879 struct comedi_subdevice *s;
883 if (dev->attached == 0)
885 /* lock to avoid race with comedi_poll */
886 spin_lock_irqsave(&devpriv->interrupt_lock, flags);
888 for (i = 0; i < ni_660x_num_counters(dev); ++i) {
889 s = &dev->subdevices[NI_660X_GPCT_SUBDEV(i)];
890 ni_660x_handle_gpct_interrupt(dev, s);
892 spin_unlock_irqrestore(&devpriv->interrupt_lock, flags);
896 static int ni_660x_input_poll(struct comedi_device *dev,
897 struct comedi_subdevice *s)
899 struct ni_660x_private *devpriv = dev->private;
902 /* lock to avoid race with comedi_poll */
903 spin_lock_irqsave(&devpriv->interrupt_lock, flags);
904 mite_sync_input_dma(subdev_to_counter(s)->mite_chan, s->async);
905 spin_unlock_irqrestore(&devpriv->interrupt_lock, flags);
906 return comedi_buf_read_n_available(s->async);
909 static int ni_660x_buf_change(struct comedi_device *dev,
910 struct comedi_subdevice *s,
911 unsigned long new_size)
913 struct ni_660x_private *devpriv = dev->private;
916 ret = mite_buf_change(mite_ring(devpriv, subdev_to_counter(s)),
924 static int ni_660x_allocate_private(struct comedi_device *dev)
926 struct ni_660x_private *devpriv;
929 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
932 dev->private = devpriv;
934 spin_lock_init(&devpriv->mite_channel_lock);
935 spin_lock_init(&devpriv->interrupt_lock);
936 spin_lock_init(&devpriv->soft_reg_copy_lock);
937 for (i = 0; i < NUM_PFI_CHANNELS; ++i)
938 devpriv->pfi_output_selects[i] = pfi_output_select_counter;
943 static int ni_660x_alloc_mite_rings(struct comedi_device *dev)
945 const struct ni_660x_board *board = comedi_board(dev);
946 struct ni_660x_private *devpriv = dev->private;
950 for (i = 0; i < board->n_chips; ++i) {
951 for (j = 0; j < counters_per_chip; ++j) {
952 devpriv->mite_rings[i][j] =
953 mite_alloc_ring(devpriv->mite);
954 if (devpriv->mite_rings[i][j] == NULL)
961 static void ni_660x_free_mite_rings(struct comedi_device *dev)
963 const struct ni_660x_board *board = comedi_board(dev);
964 struct ni_660x_private *devpriv = dev->private;
968 for (i = 0; i < board->n_chips; ++i) {
969 for (j = 0; j < counters_per_chip; ++j)
970 mite_free_ring(devpriv->mite_rings[i][j]);
974 static const struct ni_660x_board *
975 ni_660x_find_boardinfo(struct pci_dev *pcidev)
977 unsigned int dev_id = pcidev->device;
980 for (n = 0; n < ARRAY_SIZE(ni_660x_boards); n++) {
981 const struct ni_660x_board *board = &ni_660x_boards[n];
982 if (board->dev_id == dev_id)
989 ni_660x_GPCT_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
990 struct comedi_insn *insn, unsigned int *data)
992 return ni_tio_rinsn(subdev_to_counter(s), insn, data);
995 static void init_tio_chip(struct comedi_device *dev, int chipset)
997 struct ni_660x_private *devpriv = dev->private;
1000 /* init dma configuration register */
1001 devpriv->dma_configuration_soft_copies[chipset] = 0;
1002 for (i = 0; i < MAX_DMA_CHANNEL; ++i) {
1003 devpriv->dma_configuration_soft_copies[chipset] |=
1004 dma_select_bits(i, dma_selection_none) & dma_select_mask(i);
1006 ni_660x_write_register(dev, chipset,
1007 devpriv->dma_configuration_soft_copies[chipset],
1009 for (i = 0; i < NUM_PFI_CHANNELS; ++i)
1010 ni_660x_write_register(dev, chipset, 0, IOConfigReg(i));
1014 ni_660x_GPCT_insn_config(struct comedi_device *dev, struct comedi_subdevice *s,
1015 struct comedi_insn *insn, unsigned int *data)
1017 return ni_tio_insn_config(subdev_to_counter(s), insn, data);
1020 static int ni_660x_GPCT_winsn(struct comedi_device *dev,
1021 struct comedi_subdevice *s,
1022 struct comedi_insn *insn, unsigned int *data)
1024 return ni_tio_winsn(subdev_to_counter(s), insn, data);
1027 static int ni_660x_dio_insn_bits(struct comedi_device *dev,
1028 struct comedi_subdevice *s,
1029 struct comedi_insn *insn, unsigned int *data)
1031 unsigned base_bitfield_channel = CR_CHAN(insn->chanspec);
1033 /* Check if we have to write some bits */
1035 s->state &= ~(data[0] << base_bitfield_channel);
1036 s->state |= (data[0] & data[1]) << base_bitfield_channel;
1037 /* Write out the new digital output lines */
1038 ni_660x_write_register(dev, 0, s->state, DIO32Output);
1040 /* on return, data[1] contains the value of the digital
1041 * input and output lines. */
1043 (ni_660x_read_register(dev, 0,
1044 DIO32Input) >> base_bitfield_channel);
1048 static void ni_660x_select_pfi_output(struct comedi_device *dev,
1049 unsigned pfi_channel,
1050 unsigned output_select)
1052 const struct ni_660x_board *board = comedi_board(dev);
1053 static const unsigned counter_4_7_first_pfi = 8;
1054 static const unsigned counter_4_7_last_pfi = 23;
1055 unsigned active_chipset = 0;
1056 unsigned idle_chipset = 0;
1057 unsigned active_bits;
1060 if (board->n_chips > 1) {
1061 if (output_select == pfi_output_select_counter &&
1062 pfi_channel >= counter_4_7_first_pfi &&
1063 pfi_channel <= counter_4_7_last_pfi) {
1072 if (idle_chipset != active_chipset) {
1074 ni_660x_read_register(dev, idle_chipset,
1075 IOConfigReg(pfi_channel));
1076 idle_bits &= ~pfi_output_select_mask(pfi_channel);
1078 pfi_output_select_bits(pfi_channel,
1079 pfi_output_select_high_Z);
1080 ni_660x_write_register(dev, idle_chipset, idle_bits,
1081 IOConfigReg(pfi_channel));
1085 ni_660x_read_register(dev, active_chipset,
1086 IOConfigReg(pfi_channel));
1087 active_bits &= ~pfi_output_select_mask(pfi_channel);
1088 active_bits |= pfi_output_select_bits(pfi_channel, output_select);
1089 ni_660x_write_register(dev, active_chipset, active_bits,
1090 IOConfigReg(pfi_channel));
1093 static int ni_660x_set_pfi_routing(struct comedi_device *dev, unsigned chan,
1096 struct ni_660x_private *devpriv = dev->private;
1098 if (source > num_pfi_output_selects)
1100 if (source == pfi_output_select_high_Z)
1102 if (chan < min_counter_pfi_chan) {
1103 if (source == pfi_output_select_counter)
1105 } else if (chan > max_dio_pfi_chan) {
1106 if (source == pfi_output_select_do)
1110 devpriv->pfi_output_selects[chan] = source;
1111 if (devpriv->pfi_direction_bits & (((uint64_t) 1) << chan))
1112 ni_660x_select_pfi_output(dev, chan,
1113 devpriv->pfi_output_selects[chan]);
1117 static int ni_660x_dio_insn_config(struct comedi_device *dev,
1118 struct comedi_subdevice *s,
1119 struct comedi_insn *insn,
1122 struct ni_660x_private *devpriv = dev->private;
1123 unsigned int chan = CR_CHAN(insn->chanspec);
1124 uint64_t bit = 1ULL << chan;
1129 case INSN_CONFIG_DIO_OUTPUT:
1130 devpriv->pfi_direction_bits |= bit;
1131 ni_660x_select_pfi_output(dev, chan,
1132 devpriv->pfi_output_selects[chan]);
1135 case INSN_CONFIG_DIO_INPUT:
1136 devpriv->pfi_direction_bits &= ~bit;
1137 ni_660x_select_pfi_output(dev, chan, pfi_output_select_high_Z);
1140 case INSN_CONFIG_DIO_QUERY:
1141 data[1] = (devpriv->pfi_direction_bits & bit) ? COMEDI_OUTPUT
1145 case INSN_CONFIG_SET_ROUTING:
1146 ret = ni_660x_set_pfi_routing(dev, chan, data[1]);
1151 case INSN_CONFIG_GET_ROUTING:
1152 data[1] = devpriv->pfi_output_selects[chan];
1155 case INSN_CONFIG_FILTER:
1156 val = ni_660x_read_register(dev, 0, IOConfigReg(chan));
1157 val &= ~pfi_input_select_mask(chan);
1158 val |= pfi_input_select_bits(chan, data[1]);
1159 ni_660x_write_register(dev, 0, val, IOConfigReg(chan));
1169 static int ni_660x_auto_attach(struct comedi_device *dev,
1170 unsigned long context_unused)
1172 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1173 const struct ni_660x_board *board;
1174 struct ni_660x_private *devpriv;
1175 struct comedi_subdevice *s;
1178 unsigned global_interrupt_config_bits;
1180 ret = ni_660x_allocate_private(dev);
1183 devpriv = dev->private;
1185 dev->board_ptr = ni_660x_find_boardinfo(pcidev);
1186 if (!dev->board_ptr)
1188 board = comedi_board(dev);
1190 devpriv->mite = mite_alloc(pcidev);
1194 dev->board_name = board->name;
1196 ret = mite_setup2(devpriv->mite, 1);
1198 dev_warn(dev->class_dev, "error setting up mite\n");
1202 ret = ni_660x_alloc_mite_rings(dev);
1206 ret = comedi_alloc_subdevices(dev, 2 + NI_660X_MAX_NUM_COUNTERS);
1210 s = &dev->subdevices[0];
1211 /* Old GENERAL-PURPOSE COUNTER/TIME (GPCT) subdevice, no longer used */
1212 s->type = COMEDI_SUBD_UNUSED;
1214 s = &dev->subdevices[NI_660X_DIO_SUBDEV];
1215 /* DIGITAL I/O SUBDEVICE */
1216 s->type = COMEDI_SUBD_DIO;
1217 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1218 s->n_chan = NUM_PFI_CHANNELS;
1220 s->range_table = &range_digital;
1221 s->insn_bits = ni_660x_dio_insn_bits;
1222 s->insn_config = ni_660x_dio_insn_config;
1223 s->io_bits = 0; /* all bits default to input */
1224 /* we use the ioconfig registers to control dio direction, so zero
1225 output enables in stc dio control reg */
1226 ni_660x_write_register(dev, 0, 0, STCDIOControl);
1228 devpriv->counter_dev = ni_gpct_device_construct(dev,
1229 &ni_gpct_write_register,
1230 &ni_gpct_read_register,
1231 ni_gpct_variant_660x,
1232 ni_660x_num_counters
1234 if (devpriv->counter_dev == NULL)
1236 for (i = 0; i < NI_660X_MAX_NUM_COUNTERS; ++i) {
1237 s = &dev->subdevices[NI_660X_GPCT_SUBDEV(i)];
1238 if (i < ni_660x_num_counters(dev)) {
1239 s->type = COMEDI_SUBD_COUNTER;
1241 SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL |
1242 SDF_CMD_READ /* | SDF_CMD_WRITE */ ;
1244 s->maxdata = 0xffffffff;
1245 s->insn_read = ni_660x_GPCT_rinsn;
1246 s->insn_write = ni_660x_GPCT_winsn;
1247 s->insn_config = ni_660x_GPCT_insn_config;
1248 s->do_cmd = &ni_660x_cmd;
1249 s->len_chanlist = 1;
1250 s->do_cmdtest = &ni_660x_cmdtest;
1251 s->cancel = &ni_660x_cancel;
1252 s->poll = &ni_660x_input_poll;
1253 s->async_dma_dir = DMA_BIDIRECTIONAL;
1254 s->buf_change = &ni_660x_buf_change;
1255 s->private = &devpriv->counter_dev->counters[i];
1257 devpriv->counter_dev->counters[i].chip_index =
1258 i / counters_per_chip;
1259 devpriv->counter_dev->counters[i].counter_index =
1260 i % counters_per_chip;
1262 s->type = COMEDI_SUBD_UNUSED;
1265 for (i = 0; i < board->n_chips; ++i)
1266 init_tio_chip(dev, i);
1268 for (i = 0; i < ni_660x_num_counters(dev); ++i)
1269 ni_tio_init_counter(&devpriv->counter_dev->counters[i]);
1271 for (i = 0; i < NUM_PFI_CHANNELS; ++i) {
1272 if (i < min_counter_pfi_chan)
1273 ni_660x_set_pfi_routing(dev, i, pfi_output_select_do);
1275 ni_660x_set_pfi_routing(dev, i,
1276 pfi_output_select_counter);
1277 ni_660x_select_pfi_output(dev, i, pfi_output_select_high_Z);
1279 /* to be safe, set counterswap bits on tio chips after all the counter
1280 outputs have been set to high impedance mode */
1281 for (i = 0; i < board->n_chips; ++i)
1282 set_tio_counterswap(dev, i);
1284 ret = request_irq(mite_irq(devpriv->mite), ni_660x_interrupt,
1285 IRQF_SHARED, "ni_660x", dev);
1287 dev_warn(dev->class_dev, " irq not available\n");
1290 dev->irq = mite_irq(devpriv->mite);
1291 global_interrupt_config_bits = Global_Int_Enable_Bit;
1292 if (board->n_chips > 1)
1293 global_interrupt_config_bits |= Cascade_Int_Enable_Bit;
1294 ni_660x_write_register(dev, 0, global_interrupt_config_bits,
1295 GlobalInterruptConfigRegister);
1296 dev_info(dev->class_dev, "ni_660x: %s attached\n", dev->board_name);
1300 static void ni_660x_detach(struct comedi_device *dev)
1302 struct ni_660x_private *devpriv = dev->private;
1305 free_irq(dev->irq, dev);
1307 if (devpriv->counter_dev)
1308 ni_gpct_device_destroy(devpriv->counter_dev);
1309 if (devpriv->mite) {
1310 ni_660x_free_mite_rings(dev);
1311 mite_unsetup(devpriv->mite);
1312 mite_free(devpriv->mite);
1317 static struct comedi_driver ni_660x_driver = {
1318 .driver_name = "ni_660x",
1319 .module = THIS_MODULE,
1320 .auto_attach = ni_660x_auto_attach,
1321 .detach = ni_660x_detach,
1324 static int ni_660x_pci_probe(struct pci_dev *dev,
1325 const struct pci_device_id *ent)
1327 return comedi_pci_auto_config(dev, &ni_660x_driver);
1330 static void ni_660x_pci_remove(struct pci_dev *dev)
1332 comedi_pci_auto_unconfig(dev);
1335 static DEFINE_PCI_DEVICE_TABLE(ni_660x_pci_table) = {
1336 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2c60)},
1337 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1310)},
1338 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1360)},
1339 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2cc0)},
1342 MODULE_DEVICE_TABLE(pci, ni_660x_pci_table);
1344 static struct pci_driver ni_660x_pci_driver = {
1346 .id_table = ni_660x_pci_table,
1347 .probe = ni_660x_pci_probe,
1348 .remove = ni_660x_pci_remove,
1350 module_comedi_pci_driver(ni_660x_driver, ni_660x_pci_driver);
1352 MODULE_AUTHOR("Comedi http://www.comedi.org");
1353 MODULE_DESCRIPTION("Comedi low-level driver");
1354 MODULE_LICENSE("GPL");