2 comedi/drivers/ni_at_a2150.c
3 Driver for National Instruments AT-A2150 boards
4 Copyright (C) 2001, 2002 Frank Mori Hess <fmhess@users.sourceforge.net>
6 COMEDI - Linux Control and Measurement Device Interface
7 Copyright (C) 2000 David A. Schleef <ds@schleef.org>
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
21 Description: National Instruments AT-A2150
22 Author: Frank Mori Hess
24 Devices: [National Instruments] AT-A2150C (at_a2150c), AT-2150S (at_a2150s)
26 If you want to ac couple the board's inputs, use AREF_OTHER.
28 Configuration options:
29 [0] - I/O port base address
30 [1] - IRQ (optional, required for timed conversions)
31 [2] - DMA (optional, required for timed conversions)
35 Yet another driver for obsolete hardware brought to you by Frank Hess.
36 Testing and debugging help provided by Dave Andruczyk.
38 This driver supports the boards:
43 The only difference is their master clock frequencies.
50 References (from ftp://ftp.natinst.com/support/manuals):
52 320360.pdf AT-A2150 User Manual
56 analog level triggering
61 #include <linux/module.h>
62 #include <linux/delay.h>
63 #include <linux/interrupt.h>
64 #include <linux/slab.h>
65 #include "../comedidev.h"
72 #include "comedi_fc.h"
74 #define A2150_DMA_BUFFER_SIZE 0xff00 /* size in bytes of dma buffer */
76 /* Registers and bits */
77 #define CONFIG_REG 0x0
78 #define CHANNEL_BITS(x) ((x) & 0x7)
79 #define CHANNEL_MASK 0x7
80 #define CLOCK_SELECT_BITS(x) (((x) & 0x3) << 3)
81 #define CLOCK_DIVISOR_BITS(x) (((x) & 0x3) << 5)
82 #define CLOCK_MASK (0xf << 3)
83 #define ENABLE0_BIT 0x80 /* enable (don't internally ground) channels 0 and 1 */
84 #define ENABLE1_BIT 0x100 /* enable (don't internally ground) channels 2 and 3 */
85 #define AC0_BIT 0x200 /* ac couple channels 0,1 */
86 #define AC1_BIT 0x400 /* ac couple channels 2,3 */
87 #define APD_BIT 0x800 /* analog power down */
88 #define DPD_BIT 0x1000 /* digital power down */
89 #define TRIGGER_REG 0x2 /* trigger config register */
90 #define POST_TRIGGER_BITS 0x2
91 #define DELAY_TRIGGER_BITS 0x3
92 #define HW_TRIG_EN 0x10 /* enable hardware trigger */
93 #define FIFO_START_REG 0x6 /* software start aquistion trigger */
94 #define FIFO_RESET_REG 0x8 /* clears fifo + fifo flags */
95 #define FIFO_DATA_REG 0xa /* read data */
96 #define DMA_TC_CLEAR_REG 0xe /* clear dma terminal count interrupt */
97 #define STATUS_REG 0x12 /* read only */
98 #define FNE_BIT 0x1 /* fifo not empty */
99 #define OVFL_BIT 0x8 /* fifo overflow */
100 #define EDAQ_BIT 0x10 /* end of acquisition interrupt */
101 #define DCAL_BIT 0x20 /* offset calibration in progress */
102 #define INTR_BIT 0x40 /* interrupt has occurred */
103 #define DMA_TC_BIT 0x80 /* dma terminal count interrupt has occurred */
104 #define ID_BITS(x) (((x) >> 8) & 0x3)
105 #define IRQ_DMA_CNTRL_REG 0x12 /* write only */
106 #define DMA_CHAN_BITS(x) ((x) & 0x7) /* sets dma channel */
107 #define DMA_EN_BIT 0x8 /* enables dma */
108 #define IRQ_LVL_BITS(x) (((x) & 0xf) << 4) /* sets irq level */
109 #define FIFO_INTR_EN_BIT 0x100 /* enable fifo interrupts */
110 #define FIFO_INTR_FHF_BIT 0x200 /* interrupt fifo half full */
111 #define DMA_INTR_EN_BIT 0x800 /* enable interrupt on dma terminal count */
112 #define DMA_DEM_EN_BIT 0x1000 /* enables demand mode dma */
113 #define I8253_BASE_REG 0x14
114 #define I8253_MODE_REG 0x17
115 #define HW_COUNT_DISABLE 0x30 /* disable hardware counting of conversions */
119 int clock[4]; /* master clock periods, in nanoseconds */
120 int num_clocks; /* number of available master clock speeds */
121 int ai_speed; /* maximum conversion rate in nanoseconds */
124 /* analog input range */
125 static const struct comedi_lrange range_a2150 = {
131 /* enum must match board indices */
132 enum { a2150_c, a2150_s };
133 static const struct a2150_board a2150_boards[] = {
136 .clock = {31250, 22676, 20833, 19531},
142 .clock = {62500, 50000, 41667, 0},
148 struct a2150_dma_desc {
149 unsigned int chan; /* DMA channel */
150 void *virt_addr; /* virtual address of DMA buffer */
151 dma_addr_t hw_addr; /* hardware (bus) address of DMA buffer */
152 unsigned int size; /* size of DMA transfer (in bytes) */
155 struct a2150_private {
156 struct a2150_dma_desc dma_desc;
157 unsigned int count; /* number of data points left to be taken */
158 int irq_dma_bits; /* irq/dma register bits */
159 int config_bits; /* config register bits */
162 static void a2150_isadma_program(struct a2150_dma_desc *dma)
166 flags = claim_dma_lock();
167 clear_dma_ff(dma->chan);
168 set_dma_mode(dma->chan, DMA_MODE_READ);
169 set_dma_addr(dma->chan, dma->hw_addr);
170 set_dma_count(dma->chan, dma->size);
171 enable_dma(dma->chan);
172 release_dma_lock(flags);
175 /* interrupt service routine */
176 static irqreturn_t a2150_interrupt(int irq, void *d)
181 struct comedi_device *dev = d;
182 struct a2150_private *devpriv = dev->private;
183 struct a2150_dma_desc *dma = &devpriv->dma_desc;
184 struct comedi_subdevice *s = dev->read_subdev;
185 struct comedi_async *async;
186 struct comedi_cmd *cmd;
187 unsigned short *buf = dma->virt_addr;
188 unsigned int max_points, num_points, residue, leftover;
191 if (!dev->attached) {
192 dev_err(dev->class_dev, "premature interrupt\n");
195 /* initialize async here to make sure s is not NULL */
199 status = inw(dev->iobase + STATUS_REG);
201 if ((status & INTR_BIT) == 0) {
202 dev_err(dev->class_dev, "spurious interrupt\n");
206 if (status & OVFL_BIT) {
207 dev_err(dev->class_dev, "fifo overflow\n");
208 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
209 comedi_handle_events(dev, s);
212 if ((status & DMA_TC_BIT) == 0) {
213 dev_err(dev->class_dev,
214 "caught non-dma interrupt? Aborting.\n");
215 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
216 comedi_handle_events(dev, s);
220 flags = claim_dma_lock();
221 disable_dma(dma->chan);
222 /* clear flip-flop to make sure 2-byte registers for
223 * count and address get set correctly */
224 clear_dma_ff(dma->chan);
226 /* figure out how many points to read */
227 max_points = comedi_bytes_to_samples(s, dma->size);
228 /* residue is the number of points left to be done on the dma
229 * transfer. It should always be zero at this point unless
230 * the stop_src is set to external triggering.
232 residue = comedi_bytes_to_samples(s, get_dma_residue(dma->chan));
233 release_dma_lock(flags);
234 num_points = max_points - residue;
235 if (devpriv->count < num_points && cmd->stop_src == TRIG_COUNT)
236 num_points = devpriv->count;
238 /* figure out how many points will be stored next time */
240 if (cmd->stop_src == TRIG_NONE) {
241 leftover = comedi_bytes_to_samples(s, dma->size);
242 } else if (devpriv->count > max_points) {
243 leftover = devpriv->count - max_points;
244 if (leftover > max_points)
245 leftover = max_points;
247 /* there should only be a residue if collection was stopped by having
248 * the stop_src set to an external trigger, in which case there
249 * will be no more data
254 for (i = 0; i < num_points; i++) {
255 /* write data point to comedi buffer */
257 /* convert from 2's complement to unsigned coding */
259 comedi_buf_write_samples(s, &dpnt, 1);
260 if (cmd->stop_src == TRIG_COUNT) {
261 if (--devpriv->count == 0) { /* end of acquisition */
262 async->events |= COMEDI_CB_EOA;
269 dma->size = comedi_samples_to_bytes(s, leftover);
270 a2150_isadma_program(dma);
273 comedi_handle_events(dev, s);
275 /* clear interrupt */
276 outw(0x00, dev->iobase + DMA_TC_CLEAR_REG);
281 static int a2150_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
283 struct a2150_private *devpriv = dev->private;
284 struct a2150_dma_desc *dma = &devpriv->dma_desc;
286 /* disable dma on card */
287 devpriv->irq_dma_bits &= ~DMA_INTR_EN_BIT & ~DMA_EN_BIT;
288 outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG);
290 /* disable computer's dma */
291 disable_dma(dma->chan);
293 /* clear fifo and reset triggering circuitry */
294 outw(0, dev->iobase + FIFO_RESET_REG);
300 * sets bits in devpriv->clock_bits to nearest approximation of requested
301 * period, adjusts requested period to actual timing.
303 static int a2150_get_timing(struct comedi_device *dev, unsigned int *period,
306 const struct a2150_board *thisboard = dev->board_ptr;
307 struct a2150_private *devpriv = dev->private;
309 int lub_divisor_shift, lub_index, glb_divisor_shift, glb_index;
312 /* initialize greatest lower and least upper bounds */
313 lub_divisor_shift = 3;
315 lub = thisboard->clock[lub_index] * (1 << lub_divisor_shift);
316 glb_divisor_shift = 0;
317 glb_index = thisboard->num_clocks - 1;
318 glb = thisboard->clock[glb_index] * (1 << glb_divisor_shift);
320 /* make sure period is in available range */
326 /* we can multiply period by 1, 2, 4, or 8, using (1 << i) */
327 for (i = 0; i < 4; i++) {
328 /* there are a maximum of 4 master clocks */
329 for (j = 0; j < thisboard->num_clocks; j++) {
330 /* temp is the period in nanosec we are evaluating */
331 temp = thisboard->clock[j] * (1 << i);
332 /* if it is the best match yet */
333 if (temp < lub && temp >= *period) {
334 lub_divisor_shift = i;
338 if (temp > glb && temp <= *period) {
339 glb_divisor_shift = i;
345 switch (flags & CMDF_ROUND_MASK) {
346 case CMDF_ROUND_NEAREST:
348 /* if least upper bound is better approximation */
349 if (lub - *period < *period - glb)
357 case CMDF_ROUND_DOWN:
362 /* set clock bits for config register appropriately */
363 devpriv->config_bits &= ~CLOCK_MASK;
364 if (*period == lub) {
365 devpriv->config_bits |=
366 CLOCK_SELECT_BITS(lub_index) |
367 CLOCK_DIVISOR_BITS(lub_divisor_shift);
369 devpriv->config_bits |=
370 CLOCK_SELECT_BITS(glb_index) |
371 CLOCK_DIVISOR_BITS(glb_divisor_shift);
377 static int a2150_set_chanlist(struct comedi_device *dev,
378 unsigned int start_channel,
379 unsigned int num_channels)
381 struct a2150_private *devpriv = dev->private;
383 if (start_channel + num_channels > 4)
386 devpriv->config_bits &= ~CHANNEL_MASK;
388 switch (num_channels) {
390 devpriv->config_bits |= CHANNEL_BITS(0x4 | start_channel);
393 if (start_channel == 0)
394 devpriv->config_bits |= CHANNEL_BITS(0x2);
395 else if (start_channel == 2)
396 devpriv->config_bits |= CHANNEL_BITS(0x3);
401 devpriv->config_bits |= CHANNEL_BITS(0x1);
410 static int a2150_ai_check_chanlist(struct comedi_device *dev,
411 struct comedi_subdevice *s,
412 struct comedi_cmd *cmd)
414 unsigned int chan0 = CR_CHAN(cmd->chanlist[0]);
415 unsigned int aref0 = CR_AREF(cmd->chanlist[0]);
418 if (cmd->chanlist_len == 2 && (chan0 == 1 || chan0 == 3)) {
419 dev_dbg(dev->class_dev,
420 "length 2 chanlist must be channels 0,1 or channels 2,3\n");
424 if (cmd->chanlist_len == 3) {
425 dev_dbg(dev->class_dev,
426 "chanlist must have 1,2 or 4 channels\n");
430 for (i = 1; i < cmd->chanlist_len; i++) {
431 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
432 unsigned int aref = CR_AREF(cmd->chanlist[i]);
434 if (chan != (chan0 + i)) {
435 dev_dbg(dev->class_dev,
436 "entries in chanlist must be consecutive channels, counting upwards\n");
443 dev_dbg(dev->class_dev,
444 "channels 0/1 and 2/3 must have the same analog reference\n");
452 static int a2150_ai_cmdtest(struct comedi_device *dev,
453 struct comedi_subdevice *s, struct comedi_cmd *cmd)
455 const struct a2150_board *thisboard = dev->board_ptr;
459 /* Step 1 : check if triggers are trivially valid */
461 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
462 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_TIMER);
463 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
464 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
465 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
470 /* Step 2a : make sure trigger sources are unique */
472 err |= cfc_check_trigger_is_unique(cmd->start_src);
473 err |= cfc_check_trigger_is_unique(cmd->stop_src);
475 /* Step 2b : and mutually compatible */
480 /* Step 3: check if arguments are trivially valid */
482 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
484 if (cmd->convert_src == TRIG_TIMER)
485 err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
486 thisboard->ai_speed);
488 err |= cfc_check_trigger_arg_min(&cmd->chanlist_len, 1);
489 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
491 if (cmd->stop_src == TRIG_COUNT)
492 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
494 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
499 /* step 4: fix up any arguments */
501 if (cmd->scan_begin_src == TRIG_TIMER) {
502 arg = cmd->scan_begin_arg;
503 a2150_get_timing(dev, &arg, cmd->flags);
504 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, arg);
510 /* Step 5: check channel list if it exists */
511 if (cmd->chanlist && cmd->chanlist_len > 0)
512 err |= a2150_ai_check_chanlist(dev, s, cmd);
520 static int a2150_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
522 struct a2150_private *devpriv = dev->private;
523 struct a2150_dma_desc *dma = &devpriv->dma_desc;
524 struct comedi_async *async = s->async;
525 struct comedi_cmd *cmd = &async->cmd;
526 unsigned long timer_base = dev->iobase + I8253_BASE_REG;
527 unsigned long lock_flags;
528 unsigned int old_config_bits = devpriv->config_bits;
529 unsigned int trigger_bits;
531 if (cmd->flags & CMDF_PRIORITY) {
532 dev_err(dev->class_dev,
533 "dma incompatible with hard real-time interrupt (CMDF_PRIORITY), aborting\n");
536 /* clear fifo and reset triggering circuitry */
537 outw(0, dev->iobase + FIFO_RESET_REG);
540 if (a2150_set_chanlist(dev, CR_CHAN(cmd->chanlist[0]),
541 cmd->chanlist_len) < 0)
544 /* setup ac/dc coupling */
545 if (CR_AREF(cmd->chanlist[0]) == AREF_OTHER)
546 devpriv->config_bits |= AC0_BIT;
548 devpriv->config_bits &= ~AC0_BIT;
549 if (CR_AREF(cmd->chanlist[2]) == AREF_OTHER)
550 devpriv->config_bits |= AC1_BIT;
552 devpriv->config_bits &= ~AC1_BIT;
555 a2150_get_timing(dev, &cmd->scan_begin_arg, cmd->flags);
557 /* send timing, channel, config bits */
558 outw(devpriv->config_bits, dev->iobase + CONFIG_REG);
560 /* initialize number of samples remaining */
561 devpriv->count = cmd->stop_arg * cmd->chanlist_len;
563 lock_flags = claim_dma_lock();
564 disable_dma(dma->chan);
565 release_dma_lock(lock_flags);
567 /* set size of transfer to fill in 1/3 second */
568 #define ONE_THIRD_SECOND 333333333
569 dma->size = comedi_bytes_per_sample(s) * cmd->chanlist_len *
570 ONE_THIRD_SECOND / cmd->scan_begin_arg;
571 if (dma->size > A2150_DMA_BUFFER_SIZE)
572 dma->size = A2150_DMA_BUFFER_SIZE;
573 if (dma->size < comedi_bytes_per_sample(s))
574 dma->size = comedi_bytes_per_sample(s);
575 dma->size -= dma->size % comedi_bytes_per_sample(s);
577 a2150_isadma_program(dma);
579 /* clear dma interrupt before enabling it, to try and get rid of that
580 * one spurious interrupt that has been happening */
581 outw(0x00, dev->iobase + DMA_TC_CLEAR_REG);
583 /* enable dma on card */
584 devpriv->irq_dma_bits |= DMA_INTR_EN_BIT | DMA_EN_BIT;
585 outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG);
587 /* may need to wait 72 sampling periods if timing was changed */
588 i8254_set_mode(timer_base, 0, 2, I8254_MODE0 | I8254_BINARY);
589 i8254_write(timer_base, 0, 2, 72);
591 /* setup start triggering */
593 /* decide if we need to wait 72 periods for valid data */
594 if (cmd->start_src == TRIG_NOW &&
595 (old_config_bits & CLOCK_MASK) !=
596 (devpriv->config_bits & CLOCK_MASK)) {
597 /* set trigger source to delay trigger */
598 trigger_bits |= DELAY_TRIGGER_BITS;
600 /* otherwise no delay */
601 trigger_bits |= POST_TRIGGER_BITS;
603 /* enable external hardware trigger */
604 if (cmd->start_src == TRIG_EXT) {
605 trigger_bits |= HW_TRIG_EN;
606 } else if (cmd->start_src == TRIG_OTHER) {
607 /* XXX add support for level/slope start trigger using TRIG_OTHER */
608 dev_err(dev->class_dev, "you shouldn't see this?\n");
610 /* send trigger config bits */
611 outw(trigger_bits, dev->iobase + TRIGGER_REG);
613 /* start acquisition for soft trigger */
614 if (cmd->start_src == TRIG_NOW)
615 outw(0, dev->iobase + FIFO_START_REG);
620 static int a2150_ai_eoc(struct comedi_device *dev,
621 struct comedi_subdevice *s,
622 struct comedi_insn *insn,
623 unsigned long context)
627 status = inw(dev->iobase + STATUS_REG);
628 if (status & FNE_BIT)
633 static int a2150_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
634 struct comedi_insn *insn, unsigned int *data)
636 struct a2150_private *devpriv = dev->private;
640 /* clear fifo and reset triggering circuitry */
641 outw(0, dev->iobase + FIFO_RESET_REG);
644 if (a2150_set_chanlist(dev, CR_CHAN(insn->chanspec), 1) < 0)
647 /* set dc coupling */
648 devpriv->config_bits &= ~AC0_BIT;
649 devpriv->config_bits &= ~AC1_BIT;
651 /* send timing, channel, config bits */
652 outw(devpriv->config_bits, dev->iobase + CONFIG_REG);
654 /* disable dma on card */
655 devpriv->irq_dma_bits &= ~DMA_INTR_EN_BIT & ~DMA_EN_BIT;
656 outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG);
658 /* setup start triggering */
659 outw(0, dev->iobase + TRIGGER_REG);
661 /* start acquisition for soft trigger */
662 outw(0, dev->iobase + FIFO_START_REG);
665 * there is a 35.6 sample delay for data to get through the
668 for (n = 0; n < 36; n++) {
669 ret = comedi_timeout(dev, s, insn, a2150_ai_eoc, 0);
673 inw(dev->iobase + FIFO_DATA_REG);
677 for (n = 0; n < insn->n; n++) {
678 ret = comedi_timeout(dev, s, insn, a2150_ai_eoc, 0);
682 data[n] = inw(dev->iobase + FIFO_DATA_REG);
686 /* clear fifo and reset triggering circuitry */
687 outw(0, dev->iobase + FIFO_RESET_REG);
692 static void a2150_alloc_irq_dma(struct comedi_device *dev,
693 struct comedi_devconfig *it)
695 struct a2150_private *devpriv = dev->private;
696 struct a2150_dma_desc *dma = &devpriv->dma_desc;
697 unsigned int irq_num = it->options[1];
698 unsigned int dma_chan = it->options[2];
701 * Only IRQs 15, 14, 12-9, and 7-3 are valid.
702 * Only DMA channels 7-5 and 3-0 are valid.
704 * Both must be valid for async command support.
706 if (irq_num > 15 || dma_chan > 7 ||
707 !((1 << irq_num) & 0xdef8) || !((1 << dma_chan) & 0xef))
711 * Request the IRQ and DMA channels and allocate the DMA buffer.
712 * If the requests or allocation fail async command supprt will
715 if (request_irq(irq_num, a2150_interrupt, 0, dev->board_name, dev))
717 if (request_dma(dma_chan, dev->board_name)) {
718 free_irq(irq_num, dev);
721 dma->virt_addr = dma_alloc_coherent(NULL, A2150_DMA_BUFFER_SIZE,
722 &dma->hw_addr, GFP_KERNEL);
723 if (!dma->virt_addr) {
725 free_irq(irq_num, dev);
730 dma->chan = dma_chan;
731 devpriv->irq_dma_bits = IRQ_LVL_BITS(irq_num) | DMA_CHAN_BITS(dma_chan);
733 disable_dma(dma_chan);
736 static void a2150_free_dma(struct comedi_device *dev)
738 struct a2150_private *devpriv = dev->private;
739 struct a2150_dma_desc *dma;
744 dma = &devpriv->dma_desc;
748 dma_free_coherent(NULL, A2150_DMA_BUFFER_SIZE,
749 dma->virt_addr, dma->hw_addr);
752 /* probes board type, returns offset */
753 static int a2150_probe(struct comedi_device *dev)
755 int status = inw(dev->iobase + STATUS_REG);
757 return ID_BITS(status);
760 static int a2150_attach(struct comedi_device *dev, struct comedi_devconfig *it)
762 const struct a2150_board *thisboard;
763 struct a2150_private *devpriv;
764 struct comedi_subdevice *s;
765 static const int timeout = 2000;
769 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
773 ret = comedi_request_region(dev, it->options[0], 0x1c);
777 i = a2150_probe(dev);
778 if (i >= ARRAY_SIZE(a2150_boards))
781 dev->board_ptr = a2150_boards + i;
782 thisboard = dev->board_ptr;
783 dev->board_name = thisboard->name;
785 a2150_alloc_irq_dma(dev, it);
787 ret = comedi_alloc_subdevices(dev, 1);
791 /* analog input subdevice */
792 s = &dev->subdevices[0];
793 s->type = COMEDI_SUBD_AI;
794 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_OTHER;
797 s->range_table = &range_a2150;
798 s->insn_read = a2150_ai_rinsn;
800 dev->read_subdev = s;
801 s->subdev_flags |= SDF_CMD_READ;
802 s->len_chanlist = s->n_chan;
803 s->do_cmd = a2150_ai_cmd;
804 s->do_cmdtest = a2150_ai_cmdtest;
805 s->cancel = a2150_cancel;
808 /* need to do this for software counting of completed conversions, to
809 * prevent hardware count from stopping acquisition */
810 outw(HW_COUNT_DISABLE, dev->iobase + I8253_MODE_REG);
812 /* set card's irq and dma levels */
813 outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG);
815 /* reset and sync adc clock circuitry */
816 outw_p(DPD_BIT | APD_BIT, dev->iobase + CONFIG_REG);
817 outw_p(DPD_BIT, dev->iobase + CONFIG_REG);
818 /* initialize configuration register */
819 devpriv->config_bits = 0;
820 outw(devpriv->config_bits, dev->iobase + CONFIG_REG);
821 /* wait until offset calibration is done, then enable analog inputs */
822 for (i = 0; i < timeout; i++) {
823 if ((DCAL_BIT & inw(dev->iobase + STATUS_REG)) == 0)
828 dev_err(dev->class_dev,
829 "timed out waiting for offset calibration to complete\n");
832 devpriv->config_bits |= ENABLE0_BIT | ENABLE1_BIT;
833 outw(devpriv->config_bits, dev->iobase + CONFIG_REG);
838 static void a2150_detach(struct comedi_device *dev)
841 outw(APD_BIT | DPD_BIT, dev->iobase + CONFIG_REG);
843 comedi_legacy_detach(dev);
846 static struct comedi_driver ni_at_a2150_driver = {
847 .driver_name = "ni_at_a2150",
848 .module = THIS_MODULE,
849 .attach = a2150_attach,
850 .detach = a2150_detach,
852 module_comedi_driver(ni_at_a2150_driver);
854 MODULE_AUTHOR("Comedi http://www.comedi.org");
855 MODULE_DESCRIPTION("Comedi low-level driver");
856 MODULE_LICENSE("GPL");