2 comedi/drivers/ni_atmio16d.c
3 Hardware driver for National Instruments AT-MIO16D board
4 Copyright (C) 2000 Chris R. Baugher <baugher@enteract.com>
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 Description: National Instruments AT-MIO-16D
24 Author: Chris R. Baugher <baugher@enteract.com>
26 Devices: [National Instruments] AT-MIO-16 (atmio16), AT-MIO-16D (atmio16d)
29 * I must give credit here to Michal Dobes <dobes@tesnet.cz> who
30 * wrote the driver for Advantec's pcl812 boards. I used the interrupt
31 * handling code from his driver as an example for this one.
38 #include <linux/interrupt.h>
39 #include "../comedidev.h"
41 #include <linux/ioport.h>
43 #include "comedi_fc.h"
46 /* Configuration and Status Registers */
47 #define COM_REG_1 0x00 /* wo 16 */
48 #define STAT_REG 0x00 /* ro 16 */
49 #define COM_REG_2 0x02 /* wo 16 */
50 /* Event Strobe Registers */
51 #define START_CONVERT_REG 0x08 /* wo 16 */
52 #define START_DAQ_REG 0x0A /* wo 16 */
53 #define AD_CLEAR_REG 0x0C /* wo 16 */
54 #define EXT_STROBE_REG 0x0E /* wo 16 */
55 /* Analog Output Registers */
56 #define DAC0_REG 0x10 /* wo 16 */
57 #define DAC1_REG 0x12 /* wo 16 */
58 #define INT2CLR_REG 0x14 /* wo 16 */
59 /* Analog Input Registers */
60 #define MUX_CNTR_REG 0x04 /* wo 16 */
61 #define MUX_GAIN_REG 0x06 /* wo 16 */
62 #define AD_FIFO_REG 0x16 /* ro 16 */
63 #define DMA_TC_INT_CLR_REG 0x16 /* wo 16 */
64 /* AM9513A Counter/Timer Registers */
65 #define AM9513A_DATA_REG 0x18 /* rw 16 */
66 #define AM9513A_COM_REG 0x1A /* wo 16 */
67 #define AM9513A_STAT_REG 0x1A /* ro 16 */
68 /* MIO-16 Digital I/O Registers */
69 #define MIO_16_DIG_IN_REG 0x1C /* ro 16 */
70 #define MIO_16_DIG_OUT_REG 0x1C /* wo 16 */
71 /* RTSI Switch Registers */
72 #define RTSI_SW_SHIFT_REG 0x1E /* wo 8 */
73 #define RTSI_SW_STROBE_REG 0x1F /* wo 8 */
74 /* DIO-24 Registers */
75 #define DIO_24_PORTA_REG 0x00 /* rw 8 */
76 #define DIO_24_PORTB_REG 0x01 /* rw 8 */
77 #define DIO_24_PORTC_REG 0x02 /* rw 8 */
78 #define DIO_24_CNFG_REG 0x03 /* wo 8 */
80 /* Command Register bits */
81 #define COMREG1_2SCADC 0x0001
82 #define COMREG1_1632CNT 0x0002
83 #define COMREG1_SCANEN 0x0008
84 #define COMREG1_DAQEN 0x0010
85 #define COMREG1_DMAEN 0x0020
86 #define COMREG1_CONVINTEN 0x0080
87 #define COMREG2_SCN2 0x0010
88 #define COMREG2_INTEN 0x0080
89 #define COMREG2_DOUTEN0 0x0100
90 #define COMREG2_DOUTEN1 0x0200
91 /* Status Register bits */
92 #define STAT_AD_OVERRUN 0x0100
93 #define STAT_AD_OVERFLOW 0x0200
94 #define STAT_AD_DAQPROG 0x0800
95 #define STAT_AD_CONVAVAIL 0x2000
96 #define STAT_AD_DAQSTOPINT 0x4000
97 /* AM9513A Counter/Timer defines */
98 #define CLOCK_1_MHZ 0x8B25
99 #define CLOCK_100_KHZ 0x8C25
100 #define CLOCK_10_KHZ 0x8D25
101 #define CLOCK_1_KHZ 0x8E25
102 #define CLOCK_100_HZ 0x8F25
103 /* Other miscellaneous defines */
104 #define ATMIO16D_SIZE 32 /* bus address range */
105 #define ATMIO16D_TIMEOUT 10
107 struct atmio16_board_t {
114 static const struct comedi_lrange range_atmio16d_ai_10_bipolar = { 4, {
126 static const struct comedi_lrange range_atmio16d_ai_5_bipolar = { 4, {
138 static const struct comedi_lrange range_atmio16d_ai_unipolar = { 4, {
150 /* private data struct */
151 struct atmio16d_private {
152 enum { adc_diff, adc_singleended } adc_mux;
153 enum { adc_bipolar10, adc_bipolar5, adc_unipolar10 } adc_range;
154 enum { adc_2comp, adc_straight } adc_coding;
155 enum { dac_bipolar, dac_unipolar } dac0_range, dac1_range;
156 enum { dac_internal, dac_external } dac0_reference, dac1_reference;
157 enum { dac_2comp, dac_straight } dac0_coding, dac1_coding;
158 const struct comedi_lrange *ao_range_type_list[2];
159 unsigned int ao_readback[2];
160 unsigned int com_reg_1_state; /* current state of command register 1 */
161 unsigned int com_reg_2_state; /* current state of command register 2 */
164 static void reset_counters(struct comedi_device *dev)
167 outw(0xFFC2, dev->iobase + AM9513A_COM_REG);
168 outw(0xFF02, dev->iobase + AM9513A_COM_REG);
169 outw(0x4, dev->iobase + AM9513A_DATA_REG);
170 outw(0xFF0A, dev->iobase + AM9513A_COM_REG);
171 outw(0x3, dev->iobase + AM9513A_DATA_REG);
172 outw(0xFF42, dev->iobase + AM9513A_COM_REG);
173 outw(0xFF42, dev->iobase + AM9513A_COM_REG);
175 outw(0xFFC4, dev->iobase + AM9513A_COM_REG);
176 outw(0xFF03, dev->iobase + AM9513A_COM_REG);
177 outw(0x4, dev->iobase + AM9513A_DATA_REG);
178 outw(0xFF0B, dev->iobase + AM9513A_COM_REG);
179 outw(0x3, dev->iobase + AM9513A_DATA_REG);
180 outw(0xFF44, dev->iobase + AM9513A_COM_REG);
181 outw(0xFF44, dev->iobase + AM9513A_COM_REG);
183 outw(0xFFC8, dev->iobase + AM9513A_COM_REG);
184 outw(0xFF04, dev->iobase + AM9513A_COM_REG);
185 outw(0x4, dev->iobase + AM9513A_DATA_REG);
186 outw(0xFF0C, dev->iobase + AM9513A_COM_REG);
187 outw(0x3, dev->iobase + AM9513A_DATA_REG);
188 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
189 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
191 outw(0xFFD0, dev->iobase + AM9513A_COM_REG);
192 outw(0xFF05, dev->iobase + AM9513A_COM_REG);
193 outw(0x4, dev->iobase + AM9513A_DATA_REG);
194 outw(0xFF0D, dev->iobase + AM9513A_COM_REG);
195 outw(0x3, dev->iobase + AM9513A_DATA_REG);
196 outw(0xFF50, dev->iobase + AM9513A_COM_REG);
197 outw(0xFF50, dev->iobase + AM9513A_COM_REG);
199 outw(0, dev->iobase + AD_CLEAR_REG);
202 static void reset_atmio16d(struct comedi_device *dev)
204 struct atmio16d_private *devpriv = dev->private;
207 /* now we need to initialize the board */
208 outw(0, dev->iobase + COM_REG_1);
209 outw(0, dev->iobase + COM_REG_2);
210 outw(0, dev->iobase + MUX_GAIN_REG);
211 /* init AM9513A timer */
212 outw(0xFFFF, dev->iobase + AM9513A_COM_REG);
213 outw(0xFFEF, dev->iobase + AM9513A_COM_REG);
214 outw(0xFF17, dev->iobase + AM9513A_COM_REG);
215 outw(0xF000, dev->iobase + AM9513A_DATA_REG);
216 for (i = 1; i <= 5; ++i) {
217 outw(0xFF00 + i, dev->iobase + AM9513A_COM_REG);
218 outw(0x0004, dev->iobase + AM9513A_DATA_REG);
219 outw(0xFF08 + i, dev->iobase + AM9513A_COM_REG);
220 outw(0x3, dev->iobase + AM9513A_DATA_REG);
222 outw(0xFF5F, dev->iobase + AM9513A_COM_REG);
223 /* timer init done */
224 outw(0, dev->iobase + AD_CLEAR_REG);
225 outw(0, dev->iobase + INT2CLR_REG);
226 /* select straight binary mode for Analog Input */
227 devpriv->com_reg_1_state |= 1;
228 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
229 devpriv->adc_coding = adc_straight;
230 /* zero the analog outputs */
231 outw(2048, dev->iobase + DAC0_REG);
232 outw(2048, dev->iobase + DAC1_REG);
235 static irqreturn_t atmio16d_interrupt(int irq, void *d)
237 struct comedi_device *dev = d;
238 struct comedi_subdevice *s = &dev->subdevices[0];
240 comedi_buf_put(s->async, inw(dev->iobase + AD_FIFO_REG));
242 comedi_event(dev, s);
246 static int atmio16d_ai_cmdtest(struct comedi_device *dev,
247 struct comedi_subdevice *s,
248 struct comedi_cmd *cmd)
252 /* Step 1 : check if triggers are trivially valid */
254 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
255 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
256 TRIG_FOLLOW | TRIG_TIMER);
257 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_TIMER);
258 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
259 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
264 /* Step 2a : make sure trigger sources are unique */
266 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
267 err |= cfc_check_trigger_is_unique(cmd->stop_src);
269 /* Step 2b : and mutually compatible */
274 /* Step 3: check if arguments are trivially valid */
276 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
278 if (cmd->scan_begin_src == TRIG_FOLLOW) {
279 /* internal trigger */
280 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
283 /* external trigger */
284 /* should be level/edge, hi/lo specification here */
285 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
289 err |= cfc_check_trigger_arg_min(&cmd->convert_arg, 10000);
291 err |= cfc_check_trigger_arg_max(&cmd->convert_arg, SLOWEST_TIMER);
294 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
296 if (cmd->stop_src == TRIG_COUNT) {
297 /* any count is allowed */
298 } else { /* TRIG_NONE */
299 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
308 static int atmio16d_ai_cmd(struct comedi_device *dev,
309 struct comedi_subdevice *s)
311 struct atmio16d_private *devpriv = dev->private;
312 struct comedi_cmd *cmd = &s->async->cmd;
313 unsigned int timer, base_clock;
314 unsigned int sample_count, tmp, chan, gain;
317 /* This is slowly becoming a working command interface. *
318 * It is still uber-experimental */
321 s->async->cur_chan = 0;
323 /* check if scanning multiple channels */
324 if (cmd->chanlist_len < 2) {
325 devpriv->com_reg_1_state &= ~COMREG1_SCANEN;
326 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
328 devpriv->com_reg_1_state |= COMREG1_SCANEN;
329 devpriv->com_reg_2_state |= COMREG2_SCN2;
330 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
331 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2);
334 /* Setup the Mux-Gain Counter */
335 for (i = 0; i < cmd->chanlist_len; ++i) {
336 chan = CR_CHAN(cmd->chanlist[i]);
337 gain = CR_RANGE(cmd->chanlist[i]);
338 outw(i, dev->iobase + MUX_CNTR_REG);
339 tmp = chan | (gain << 6);
340 if (i == cmd->scan_end_arg - 1)
341 tmp |= 0x0010; /* set LASTONE bit */
342 outw(tmp, dev->iobase + MUX_GAIN_REG);
345 /* Now program the sample interval timer */
346 /* Figure out which clock to use then get an
347 * appropriate timer value */
348 if (cmd->convert_arg < 65536000) {
349 base_clock = CLOCK_1_MHZ;
350 timer = cmd->convert_arg / 1000;
351 } else if (cmd->convert_arg < 655360000) {
352 base_clock = CLOCK_100_KHZ;
353 timer = cmd->convert_arg / 10000;
354 } else if (cmd->convert_arg <= 0xffffffff /* 6553600000 */) {
355 base_clock = CLOCK_10_KHZ;
356 timer = cmd->convert_arg / 100000;
357 } else if (cmd->convert_arg <= 0xffffffff /* 65536000000 */) {
358 base_clock = CLOCK_1_KHZ;
359 timer = cmd->convert_arg / 1000000;
361 outw(0xFF03, dev->iobase + AM9513A_COM_REG);
362 outw(base_clock, dev->iobase + AM9513A_DATA_REG);
363 outw(0xFF0B, dev->iobase + AM9513A_COM_REG);
364 outw(0x2, dev->iobase + AM9513A_DATA_REG);
365 outw(0xFF44, dev->iobase + AM9513A_COM_REG);
366 outw(0xFFF3, dev->iobase + AM9513A_COM_REG);
367 outw(timer, dev->iobase + AM9513A_DATA_REG);
368 outw(0xFF24, dev->iobase + AM9513A_COM_REG);
370 /* Now figure out how many samples to get */
371 /* and program the sample counter */
372 sample_count = cmd->stop_arg * cmd->scan_end_arg;
373 outw(0xFF04, dev->iobase + AM9513A_COM_REG);
374 outw(0x1025, dev->iobase + AM9513A_DATA_REG);
375 outw(0xFF0C, dev->iobase + AM9513A_COM_REG);
376 if (sample_count < 65536) {
377 /* use only Counter 4 */
378 outw(sample_count, dev->iobase + AM9513A_DATA_REG);
379 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
380 outw(0xFFF4, dev->iobase + AM9513A_COM_REG);
381 outw(0xFF28, dev->iobase + AM9513A_COM_REG);
382 devpriv->com_reg_1_state &= ~COMREG1_1632CNT;
383 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
385 /* Counter 4 and 5 are needed */
387 tmp = sample_count & 0xFFFF;
389 outw(tmp - 1, dev->iobase + AM9513A_DATA_REG);
391 outw(0xFFFF, dev->iobase + AM9513A_DATA_REG);
393 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
394 outw(0, dev->iobase + AM9513A_DATA_REG);
395 outw(0xFF28, dev->iobase + AM9513A_COM_REG);
396 outw(0xFF05, dev->iobase + AM9513A_COM_REG);
397 outw(0x25, dev->iobase + AM9513A_DATA_REG);
398 outw(0xFF0D, dev->iobase + AM9513A_COM_REG);
399 tmp = sample_count & 0xFFFF;
400 if ((tmp == 0) || (tmp == 1)) {
401 outw((sample_count >> 16) & 0xFFFF,
402 dev->iobase + AM9513A_DATA_REG);
404 outw(((sample_count >> 16) & 0xFFFF) + 1,
405 dev->iobase + AM9513A_DATA_REG);
407 outw(0xFF70, dev->iobase + AM9513A_COM_REG);
408 devpriv->com_reg_1_state |= COMREG1_1632CNT;
409 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
412 /* Program the scan interval timer ONLY IF SCANNING IS ENABLED */
413 /* Figure out which clock to use then get an
414 * appropriate timer value */
415 if (cmd->chanlist_len > 1) {
416 if (cmd->scan_begin_arg < 65536000) {
417 base_clock = CLOCK_1_MHZ;
418 timer = cmd->scan_begin_arg / 1000;
419 } else if (cmd->scan_begin_arg < 655360000) {
420 base_clock = CLOCK_100_KHZ;
421 timer = cmd->scan_begin_arg / 10000;
422 } else if (cmd->scan_begin_arg < 0xffffffff /* 6553600000 */) {
423 base_clock = CLOCK_10_KHZ;
424 timer = cmd->scan_begin_arg / 100000;
425 } else if (cmd->scan_begin_arg < 0xffffffff /* 65536000000 */) {
426 base_clock = CLOCK_1_KHZ;
427 timer = cmd->scan_begin_arg / 1000000;
429 outw(0xFF02, dev->iobase + AM9513A_COM_REG);
430 outw(base_clock, dev->iobase + AM9513A_DATA_REG);
431 outw(0xFF0A, dev->iobase + AM9513A_COM_REG);
432 outw(0x2, dev->iobase + AM9513A_DATA_REG);
433 outw(0xFF42, dev->iobase + AM9513A_COM_REG);
434 outw(0xFFF2, dev->iobase + AM9513A_COM_REG);
435 outw(timer, dev->iobase + AM9513A_DATA_REG);
436 outw(0xFF22, dev->iobase + AM9513A_COM_REG);
439 /* Clear the A/D FIFO and reset the MUX counter */
440 outw(0, dev->iobase + AD_CLEAR_REG);
441 outw(0, dev->iobase + MUX_CNTR_REG);
442 outw(0, dev->iobase + INT2CLR_REG);
443 /* enable this acquisition operation */
444 devpriv->com_reg_1_state |= COMREG1_DAQEN;
445 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
446 /* enable interrupts for conversion completion */
447 devpriv->com_reg_1_state |= COMREG1_CONVINTEN;
448 devpriv->com_reg_2_state |= COMREG2_INTEN;
449 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
450 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2);
451 /* apply a trigger. this starts the counters! */
452 outw(0, dev->iobase + START_DAQ_REG);
457 /* This will cancel a running acquisition operation */
458 static int atmio16d_ai_cancel(struct comedi_device *dev,
459 struct comedi_subdevice *s)
466 /* Mode 0 is used to get a single conversion on demand */
467 static int atmio16d_ai_insn_read(struct comedi_device *dev,
468 struct comedi_subdevice *s,
469 struct comedi_insn *insn, unsigned int *data)
471 struct atmio16d_private *devpriv = dev->private;
477 chan = CR_CHAN(insn->chanspec);
478 gain = CR_RANGE(insn->chanspec);
480 /* reset the Analog input circuitry */
481 /* outw( 0, dev->iobase+AD_CLEAR_REG ); */
482 /* reset the Analog Input MUX Counter to 0 */
483 /* outw( 0, dev->iobase+MUX_CNTR_REG ); */
485 /* set the Input MUX gain */
486 outw(chan | (gain << 6), dev->iobase + MUX_GAIN_REG);
488 for (i = 0; i < insn->n; i++) {
489 /* start the conversion */
490 outw(0, dev->iobase + START_CONVERT_REG);
491 /* wait for it to finish */
492 for (t = 0; t < ATMIO16D_TIMEOUT; t++) {
493 /* check conversion status */
494 status = inw(dev->iobase + STAT_REG);
495 if (status & STAT_AD_CONVAVAIL) {
496 /* read the data now */
497 data[i] = inw(dev->iobase + AD_FIFO_REG);
498 /* change to two's complement if need be */
499 if (devpriv->adc_coding == adc_2comp)
503 if (status & STAT_AD_OVERFLOW) {
504 printk(KERN_INFO "atmio16d: a/d FIFO overflow\n");
505 outw(0, dev->iobase + AD_CLEAR_REG);
510 /* end waiting, now check if it timed out */
511 if (t == ATMIO16D_TIMEOUT) {
512 printk(KERN_INFO "atmio16d: timeout\n");
521 static int atmio16d_ao_insn_read(struct comedi_device *dev,
522 struct comedi_subdevice *s,
523 struct comedi_insn *insn, unsigned int *data)
525 struct atmio16d_private *devpriv = dev->private;
528 for (i = 0; i < insn->n; i++)
529 data[i] = devpriv->ao_readback[CR_CHAN(insn->chanspec)];
533 static int atmio16d_ao_insn_write(struct comedi_device *dev,
534 struct comedi_subdevice *s,
535 struct comedi_insn *insn, unsigned int *data)
537 struct atmio16d_private *devpriv = dev->private;
542 chan = CR_CHAN(insn->chanspec);
544 for (i = 0; i < insn->n; i++) {
548 if (devpriv->dac0_coding == dac_2comp)
550 outw(d, dev->iobase + DAC0_REG);
553 if (devpriv->dac1_coding == dac_2comp)
555 outw(d, dev->iobase + DAC1_REG);
560 devpriv->ao_readback[chan] = data[i];
565 static int atmio16d_dio_insn_bits(struct comedi_device *dev,
566 struct comedi_subdevice *s,
567 struct comedi_insn *insn, unsigned int *data)
570 s->state &= ~data[0];
571 s->state |= (data[0] | data[1]);
572 outw(s->state, dev->iobase + MIO_16_DIG_OUT_REG);
574 data[1] = inw(dev->iobase + MIO_16_DIG_IN_REG);
579 static int atmio16d_dio_insn_config(struct comedi_device *dev,
580 struct comedi_subdevice *s,
581 struct comedi_insn *insn,
584 struct atmio16d_private *devpriv = dev->private;
588 for (i = 0; i < insn->n; i++) {
589 mask = (CR_CHAN(insn->chanspec) < 4) ? 0x0f : 0xf0;
594 devpriv->com_reg_2_state &= ~(COMREG2_DOUTEN0 | COMREG2_DOUTEN1);
595 if (s->io_bits & 0x0f)
596 devpriv->com_reg_2_state |= COMREG2_DOUTEN0;
597 if (s->io_bits & 0xf0)
598 devpriv->com_reg_2_state |= COMREG2_DOUTEN1;
599 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2);
605 options[0] - I/O port
608 N == irq N {3,4,5,6,7,9,10,11,12,14,15}
611 N == irq N {3,4,5,6,7,9}
612 options[3] - DMA1 channel
615 options[4] - DMA2 channel
620 0=differential, 1=single
621 options[6] - a/d range
622 0=bipolar10, 1=bipolar5, 2=unipolar10
624 options[7] - dac0 range
625 0=bipolar, 1=unipolar
626 options[8] - dac0 reference
627 0=internal, 1=external
628 options[9] - dac0 coding
629 0=2's comp, 1=straight binary
631 options[10] - dac1 range
632 options[11] - dac1 reference
633 options[12] - dac1 coding
636 static int atmio16d_attach(struct comedi_device *dev,
637 struct comedi_devconfig *it)
639 const struct atmio16_board_t *board = comedi_board(dev);
640 struct atmio16d_private *devpriv;
642 unsigned long iobase;
645 struct comedi_subdevice *s;
647 /* make sure the address range is free and allocate it */
648 iobase = it->options[0];
649 printk(KERN_INFO "comedi%d: atmio16d: 0x%04lx ", dev->minor, iobase);
650 if (!request_region(iobase, ATMIO16D_SIZE, "ni_atmio16d")) {
651 printk("I/O port conflict\n");
654 dev->iobase = iobase;
656 dev->board_name = board->name;
658 ret = comedi_alloc_subdevices(dev, 4);
662 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
665 dev->private = devpriv;
667 /* reset the atmio16d hardware */
670 /* check if our interrupt is available and get it */
671 irq = it->options[1];
674 ret = request_irq(irq, atmio16d_interrupt, 0, "atmio16d", dev);
676 printk(KERN_INFO "failed to allocate irq %u\n", irq);
680 printk(KERN_INFO "( irq = %u )\n", irq);
682 printk(KERN_INFO "( no irq )");
685 /* set device options */
686 devpriv->adc_mux = it->options[5];
687 devpriv->adc_range = it->options[6];
689 devpriv->dac0_range = it->options[7];
690 devpriv->dac0_reference = it->options[8];
691 devpriv->dac0_coding = it->options[9];
692 devpriv->dac1_range = it->options[10];
693 devpriv->dac1_reference = it->options[11];
694 devpriv->dac1_coding = it->options[12];
696 /* setup sub-devices */
697 s = &dev->subdevices[0];
698 dev->read_subdev = s;
700 s->type = COMEDI_SUBD_AI;
701 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_CMD_READ;
702 s->n_chan = (devpriv->adc_mux ? 16 : 8);
703 s->len_chanlist = 16;
704 s->insn_read = atmio16d_ai_insn_read;
705 s->do_cmdtest = atmio16d_ai_cmdtest;
706 s->do_cmd = atmio16d_ai_cmd;
707 s->cancel = atmio16d_ai_cancel;
708 s->maxdata = 0xfff; /* 4095 decimal */
709 switch (devpriv->adc_range) {
711 s->range_table = &range_atmio16d_ai_10_bipolar;
714 s->range_table = &range_atmio16d_ai_5_bipolar;
717 s->range_table = &range_atmio16d_ai_unipolar;
722 s = &dev->subdevices[1];
723 s->type = COMEDI_SUBD_AO;
724 s->subdev_flags = SDF_WRITABLE;
726 s->insn_read = atmio16d_ao_insn_read;
727 s->insn_write = atmio16d_ao_insn_write;
728 s->maxdata = 0xfff; /* 4095 decimal */
729 s->range_table_list = devpriv->ao_range_type_list;
730 switch (devpriv->dac0_range) {
732 devpriv->ao_range_type_list[0] = &range_bipolar10;
735 devpriv->ao_range_type_list[0] = &range_unipolar10;
738 switch (devpriv->dac1_range) {
740 devpriv->ao_range_type_list[1] = &range_bipolar10;
743 devpriv->ao_range_type_list[1] = &range_unipolar10;
748 s = &dev->subdevices[2];
749 s->type = COMEDI_SUBD_DIO;
750 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
752 s->insn_bits = atmio16d_dio_insn_bits;
753 s->insn_config = atmio16d_dio_insn_config;
755 s->range_table = &range_digital;
758 s = &dev->subdevices[3];
760 subdev_8255_init(dev, s, NULL, dev->iobase);
762 s->type = COMEDI_SUBD_UNUSED;
764 /* don't yet know how to deal with counter/timers */
766 s = &dev->subdevices[4];
768 s->type = COMEDI_SUBD_TIMER;
777 static void atmio16d_detach(struct comedi_device *dev)
779 const struct atmio16_board_t *board = comedi_board(dev);
780 struct comedi_subdevice *s;
782 if (dev->subdevices && board->has_8255) {
783 s = &dev->subdevices[3];
784 subdev_8255_cleanup(dev, s);
787 free_irq(dev->irq, dev);
790 release_region(dev->iobase, ATMIO16D_SIZE);
793 static const struct atmio16_board_t atmio16_boards[] = {
803 static struct comedi_driver atmio16d_driver = {
804 .driver_name = "atmio16",
805 .module = THIS_MODULE,
806 .attach = atmio16d_attach,
807 .detach = atmio16d_detach,
808 .board_name = &atmio16_boards[0].name,
809 .num_names = ARRAY_SIZE(atmio16_boards),
810 .offset = sizeof(struct atmio16_board_t),
812 module_comedi_driver(atmio16d_driver);
814 MODULE_AUTHOR("Comedi http://www.comedi.org");
815 MODULE_DESCRIPTION("Comedi low-level driver");
816 MODULE_LICENSE("GPL");