drivers/staging/comedi/drivers/ni_labpc.c

   1 /*
   2     comedi/drivers/ni_labpc.c
   3     Driver for National Instruments Lab-PC series boards and compatibles
   4     Copyright (C) 2001, 2002, 2003 Frank Mori Hess <fmhess@users.sourceforge.net>
   5
   6     This program is free software; you can redistribute it and/or modify
   7     it under the terms of the GNU General Public License as published by
   8     the Free Software Foundation; either version 2 of the License, or
   9     (at your option) any later version.
  10
  11     This program is distributed in the hope that it will be useful,
  12     but WITHOUT ANY WARRANTY; without even the implied warranty of
  13     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14     GNU General Public License for more details.
  15
  16     You should have received a copy of the GNU General Public License
  17     along with this program; if not, write to the Free Software
  18     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19
  20 ************************************************************************
  21 */
  22 /*
  23 Driver: ni_labpc
  24 Description: National Instruments Lab-PC (& compatibles)
  25 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
  26 Devices: [National Instruments] Lab-PC-1200 (labpc-1200),
  27   Lab-PC-1200AI (labpc-1200ai), Lab-PC+ (lab-pc+), PCI-1200 (ni_labpc)
  28 Status: works
  29
  30 Tested with lab-pc-1200.  For the older Lab-PC+, not all input ranges
  31 and analog references will work, the available ranges/arefs will
  32 depend on how you have configured the jumpers on your board
  33 (see your owner's manual).
  34
  35 Kernel-level ISA plug-and-play support for the lab-pc-1200
  36 boards has not
  37 yet been added to the driver, mainly due to the fact that
  38 I don't know the device id numbers.  If you have one
  39 of these boards,
  40 please file a bug report at http://comedi.org/
  41 so I can get the necessary information from you.
  42
  43 The 1200 series boards have onboard calibration dacs for correcting
  44 analog input/output offsets and gains.  The proper settings for these
  45 caldacs are stored on the board's eeprom.  To read the caldac values
  46 from the eeprom and store them into a file that can be then be used by
  47 comedilib, use the comedi_calibrate program.
  48
  49 Configuration options - ISA boards:
  50   [0] - I/O port base address
  51   [1] - IRQ (optional, required for timed or externally triggered conversions)
  52   [2] - DMA channel (optional)
  53
  54 Configuration options - PCI boards:
  55   [0] - bus (optional)
  56   [1] - slot (optional)
  57
  58 The Lab-pc+ has quirky chanlist requirements
  59 when scanning multiple channels.  Multiple channel scan
  60 sequence must start at highest channel, then decrement down to
  61 channel 0.  The rest of the cards can scan down like lab-pc+ or scan
  62 up from channel zero.  Chanlists consisting of all one channel
  63 are also legal, and allow you to pace conversions in bursts.
  64
  65 */
  66
  67 /*
  68
  69 NI manuals:
  70 341309a (labpc-1200 register manual)
  71 340914a (pci-1200)
  72 320502b (lab-pc+)
  73
  74 */
  75
  76 #include <linux/interrupt.h>
  77 #include <linux/slab.h>
  78 #include <linux/io.h>
  79 #include "../comedidev.h"
  80
  81 #include <linux/delay.h>
  82 #include <asm/dma.h>
  83
  84 #include "8253.h"
  85 #include "8255.h"
  86 #include "mite.h"
  87 #include "comedi_fc.h"
  88 #include "ni_labpc.h"
  89
  90 #define DRV_NAME "ni_labpc"
  91
  92 /* size of io region used by board */
  93 #define LABPC_SIZE           32
  94 /* 2 MHz master clock */
  95 #define LABPC_TIMER_BASE            500
  96
  97 /* Registers for the lab-pc+ */
  98
  99 /* write-only registers */
 100 #define COMMAND1_REG    0x0
 101 #define   ADC_GAIN_MASK (0x7 << 4)
 102 #define   ADC_CHAN_BITS(x)      ((x) & 0x7)
 103 /* enables multi channel scans */
 104 #define   ADC_SCAN_EN_BIT       0x80
 105 #define COMMAND2_REG    0x1
 106 /* enable pretriggering (used in conjunction with SWTRIG) */
 107 #define   PRETRIG_BIT   0x1
 108 /* enable paced conversions on external trigger */
 109 #define   HWTRIG_BIT    0x2
 110 /* enable paced conversions */
 111 #define   SWTRIG_BIT    0x4
 112 /* use two cascaded counters for pacing */
 113 #define   CASCADE_BIT   0x8
 114 #define   DAC_PACED_BIT(channel)        (0x40 << ((channel) & 0x1))
 115 #define COMMAND3_REG    0x2
 116 /* enable dma transfers */
 117 #define   DMA_EN_BIT    0x1
 118 /* enable interrupts for 8255 */
 119 #define   DIO_INTR_EN_BIT       0x2
 120 /* enable dma terminal count interrupt */
 121 #define   DMATC_INTR_EN_BIT     0x4
 122 /* enable timer interrupt */
 123 #define   TIMER_INTR_EN_BIT     0x8
 124 /* enable error interrupt */
 125 #define   ERR_INTR_EN_BIT       0x10
 126 /* enable fifo not empty interrupt */
 127 #define   ADC_FNE_INTR_EN_BIT   0x20
 128 #define ADC_CONVERT_REG 0x3
 129 #define DAC_LSB_REG(channel)    (0x4 + 2 * ((channel) & 0x1))
 130 #define DAC_MSB_REG(channel)    (0x5 + 2 * ((channel) & 0x1))
 131 #define ADC_CLEAR_REG   0x8
 132 #define DMATC_CLEAR_REG 0xa
 133 #define TIMER_CLEAR_REG 0xc
 134 /* 1200 boards only */
 135 #define COMMAND6_REG    0xe
 136 /* select ground or common-mode reference */
 137 #define   ADC_COMMON_BIT        0x1
 138 /*  adc unipolar */
 139 #define   ADC_UNIP_BIT  0x2
 140 /*  dac unipolar */
 141 #define   DAC_UNIP_BIT(channel) (0x4 << ((channel) & 0x1))
 142 /* enable fifo half full interrupt */
 143 #define   ADC_FHF_INTR_EN_BIT   0x20
 144 /* enable interrupt on end of hardware count */
 145 #define   A1_INTR_EN_BIT        0x40
 146 /* scan up from channel zero instead of down to zero */
 147 #define   ADC_SCAN_UP_BIT 0x80
 148 #define COMMAND4_REG    0xf
 149 /* enables 'interval' scanning */
 150 #define   INTERVAL_SCAN_EN_BIT  0x1
 151 /* enables external signal on counter b1 output to trigger scan */
 152 #define   EXT_SCAN_EN_BIT       0x2
 153 /* chooses direction (output or input) for EXTCONV* line */
 154 #define   EXT_CONVERT_OUT_BIT   0x4
 155 /* chooses differential inputs for adc (in conjunction with board jumper) */
 156 #define   ADC_DIFF_BIT  0x8
 157 #define   EXT_CONVERT_DISABLE_BIT       0x10
 158 /* 1200 boards only, calibration stuff */
 159 #define COMMAND5_REG    0x1c
 160 /* enable eeprom for write */
 161 #define   EEPROM_WRITE_UNPROTECT_BIT    0x4
 162 /* enable dithering */
 163 #define   DITHER_EN_BIT 0x8
 164 /* load calibration dac */
 165 #define   CALDAC_LOAD_BIT       0x10
 166 /* serial clock - rising edge writes, falling edge reads */
 167 #define   SCLOCK_BIT    0x20
 168 /* serial data bit for writing to eeprom or calibration dacs */
 169 #define   SDATA_BIT     0x40
 170 /* enable eeprom for read/write */
 171 #define   EEPROM_EN_BIT 0x80
 172 #define INTERVAL_COUNT_REG      0x1e
 173 #define INTERVAL_LOAD_REG       0x1f
 174 #define   INTERVAL_LOAD_BITS    0x1
 175
 176 /* read-only registers */
 177 #define STATUS1_REG     0x0
 178 /* data is available in fifo */
 179 #define   DATA_AVAIL_BIT        0x1
 180 /* overrun has occurred */
 181 #define   OVERRUN_BIT   0x2
 182 /* fifo overflow */
 183 #define   OVERFLOW_BIT  0x4
 184 /* timer interrupt has occurred */
 185 #define   TIMER_BIT     0x8
 186 /* dma terminal count has occurred */
 187 #define   DMATC_BIT     0x10
 188 /* external trigger has occurred */
 189 #define   EXT_TRIG_BIT  0x40
 190 /* 1200 boards only */
 191 #define STATUS2_REG     0x1d
 192 /* programmable eeprom serial output */
 193 #define   EEPROM_OUT_BIT        0x1
 194 /* counter A1 terminal count */
 195 #define   A1_TC_BIT     0x2
 196 /* fifo not half full */
 197 #define   FNHF_BIT      0x4
 198 #define ADC_FIFO_REG    0xa
 199
 200 #define DIO_BASE_REG    0x10
 201 #define COUNTER_A_BASE_REG      0x14
 202 #define COUNTER_A_CONTROL_REG   (COUNTER_A_BASE_REG + 0x3)
 203 /* check modes put conversion pacer output in harmless state (a0 mode 2) */
 204 #define   INIT_A0_BITS  0x14
 205 /* put hardware conversion counter output in harmless state (a1 mode 0) */
 206 #define   INIT_A1_BITS  0x70
 207 #define COUNTER_B_BASE_REG      0x18
 208
 209 enum scan_mode {
 210         MODE_SINGLE_CHAN,
 211         MODE_SINGLE_CHAN_INTERVAL,
 212         MODE_MULT_CHAN_UP,
 213         MODE_MULT_CHAN_DOWN,
 214 };
 215
 216 static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
 217 static irqreturn_t labpc_interrupt(int irq, void *d);
 218 static int labpc_drain_fifo(struct comedi_device *dev);
 219 #ifdef CONFIG_ISA_DMA_API
 220 static void labpc_drain_dma(struct comedi_device *dev);
 221 static void handle_isa_dma(struct comedi_device *dev);
 222 #endif
 223 static void labpc_drain_dregs(struct comedi_device *dev);
 224 static int labpc_ai_cmdtest(struct comedi_device *dev,
 225                             struct comedi_subdevice *s, struct comedi_cmd *cmd);
 226 static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
 227 static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
 228                           struct comedi_insn *insn, unsigned int *data);
 229 static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
 230                           struct comedi_insn *insn, unsigned int *data);
 231 static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
 232                           struct comedi_insn *insn, unsigned int *data);
 233 static int labpc_calib_read_insn(struct comedi_device *dev,
 234                                  struct comedi_subdevice *s,
 235                                  struct comedi_insn *insn, unsigned int *data);
 236 static int labpc_calib_write_insn(struct comedi_device *dev,
 237                                   struct comedi_subdevice *s,
 238                                   struct comedi_insn *insn, unsigned int *data);
 239 static int labpc_eeprom_read_insn(struct comedi_device *dev,
 240                                   struct comedi_subdevice *s,
 241                                   struct comedi_insn *insn, unsigned int *data);
 242 static int labpc_eeprom_write_insn(struct comedi_device *dev,
 243                                    struct comedi_subdevice *s,
 244                                    struct comedi_insn *insn,
 245                                    unsigned int *data);
 246 static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd,
 247                              enum scan_mode scan_mode);
 248 #ifdef CONFIG_ISA_DMA_API
 249 static unsigned int labpc_suggest_transfer_size(const struct comedi_cmd *cmd);
 250 #endif
 251 static int labpc_dio_mem_callback(int dir, int port, int data,
 252                                   unsigned long arg);
 253 static void labpc_serial_out(struct comedi_device *dev, unsigned int value,
 254                              unsigned int num_bits);
 255 static unsigned int labpc_serial_in(struct comedi_device *dev);
 256 static unsigned int labpc_eeprom_read(struct comedi_device *dev,
 257                                       unsigned int address);
 258 static unsigned int labpc_eeprom_read_status(struct comedi_device *dev);
 259 static int labpc_eeprom_write(struct comedi_device *dev,
 260                                        unsigned int address,
 261                                        unsigned int value);
 262 static void write_caldac(struct comedi_device *dev, unsigned int channel,
 263                          unsigned int value);
 264
 265 /* analog input ranges */
 266 #define NUM_LABPC_PLUS_AI_RANGES 16
 267 /* indicates unipolar ranges */
 268 static const int labpc_plus_is_unipolar[NUM_LABPC_PLUS_AI_RANGES] = {
 269         0,
 270         0,
 271         0,
 272         0,
 273         0,
 274         0,
 275         0,
 276         0,
 277         1,
 278         1,
 279         1,
 280         1,
 281         1,
 282         1,
 283         1,
 284         1,
 285 };
 286
 287 /* map range index to gain bits */
 288 static const int labpc_plus_ai_gain_bits[NUM_LABPC_PLUS_AI_RANGES] = {
 289         0x00,
 290         0x10,
 291         0x20,
 292         0x30,
 293         0x40,
 294         0x50,
 295         0x60,
 296         0x70,
 297         0x00,
 298         0x10,
 299         0x20,
 300         0x30,
 301         0x40,
 302         0x50,
 303         0x60,
 304         0x70,
 305 };
 306
 307 static const struct comedi_lrange range_labpc_plus_ai = {
 308         NUM_LABPC_PLUS_AI_RANGES,
 309         {
 310          BIP_RANGE(5),
 311          BIP_RANGE(4),
 312          BIP_RANGE(2.5),
 313          BIP_RANGE(1),
 314          BIP_RANGE(0.5),
 315          BIP_RANGE(0.25),
 316          BIP_RANGE(0.1),
 317          BIP_RANGE(0.05),
 318          UNI_RANGE(10),
 319          UNI_RANGE(8),
 320          UNI_RANGE(5),
 321          UNI_RANGE(2),
 322          UNI_RANGE(1),
 323          UNI_RANGE(0.5),
 324          UNI_RANGE(0.2),
 325          UNI_RANGE(0.1),
 326          }
 327 };
 328
 329 #define NUM_LABPC_1200_AI_RANGES 14
 330 /* indicates unipolar ranges */
 331 const int labpc_1200_is_unipolar[NUM_LABPC_1200_AI_RANGES] = {
 332         0,
 333         0,
 334         0,
 335         0,
 336         0,
 337         0,
 338         0,
 339         1,
 340         1,
 341         1,
 342         1,
 343         1,
 344         1,
 345         1,
 346 };
 347 EXPORT_SYMBOL_GPL(labpc_1200_is_unipolar);
 348
 349 /* map range index to gain bits */
 350 const int labpc_1200_ai_gain_bits[NUM_LABPC_1200_AI_RANGES] = {
 351         0x00,
 352         0x20,
 353         0x30,
 354         0x40,
 355         0x50,
 356         0x60,
 357         0x70,
 358         0x00,
 359         0x20,
 360         0x30,
 361         0x40,
 362         0x50,
 363         0x60,
 364         0x70,
 365 };
 366 EXPORT_SYMBOL_GPL(labpc_1200_ai_gain_bits);
 367
 368 const struct comedi_lrange range_labpc_1200_ai = {
 369         NUM_LABPC_1200_AI_RANGES,
 370         {
 371          BIP_RANGE(5),
 372          BIP_RANGE(2.5),
 373          BIP_RANGE(1),
 374          BIP_RANGE(0.5),
 375          BIP_RANGE(0.25),
 376          BIP_RANGE(0.1),
 377          BIP_RANGE(0.05),
 378          UNI_RANGE(10),
 379          UNI_RANGE(5),
 380          UNI_RANGE(2),
 381          UNI_RANGE(1),
 382          UNI_RANGE(0.5),
 383          UNI_RANGE(0.2),
 384          UNI_RANGE(0.1),
 385          }
 386 };
 387 EXPORT_SYMBOL_GPL(range_labpc_1200_ai);
 388
 389 /* analog output ranges */
 390 #define AO_RANGE_IS_UNIPOLAR 0x1
 391 static const struct comedi_lrange range_labpc_ao = {
 392         2,
 393         {
 394          BIP_RANGE(5),
 395          UNI_RANGE(10),
 396          }
 397 };
 398
 399 /* functions that do inb/outb and readb/writeb so we can use
 400  * function pointers to decide which to use */
 401 static inline unsigned int labpc_inb(unsigned long address)
 402 {
 403         return inb(address);
 404 }
 405
 406 static inline void labpc_outb(unsigned int byte, unsigned long address)
 407 {
 408         outb(byte, address);
 409 }
 410
 411 static inline unsigned int labpc_readb(unsigned long address)
 412 {
 413         return readb((void __iomem *)address);
 414 }
 415
 416 static inline void labpc_writeb(unsigned int byte, unsigned long address)
 417 {
 418         writeb(byte, (void __iomem *)address);
 419 }
 420
 421 static const struct labpc_board_struct labpc_boards[] = {
 422         {
 423          .name = "lab-pc-1200",
 424          .ai_speed = 10000,
 425          .bustype = isa_bustype,
 426          .register_layout = labpc_1200_layout,
 427          .has_ao = 1,
 428          .ai_range_table = &range_labpc_1200_ai,
 429          .ai_range_code = labpc_1200_ai_gain_bits,
 430          .ai_range_is_unipolar = labpc_1200_is_unipolar,
 431          .ai_scan_up = 1,
 432          .memory_mapped_io = 0,
 433          },
 434         {
 435          .name = "lab-pc-1200ai",
 436          .ai_speed = 10000,
 437          .bustype = isa_bustype,
 438          .register_layout = labpc_1200_layout,
 439          .has_ao = 0,
 440          .ai_range_table = &range_labpc_1200_ai,
 441          .ai_range_code = labpc_1200_ai_gain_bits,
 442          .ai_range_is_unipolar = labpc_1200_is_unipolar,
 443          .ai_scan_up = 1,
 444          .memory_mapped_io = 0,
 445          },
 446         {
 447          .name = "lab-pc+",
 448          .ai_speed = 12000,
 449          .bustype = isa_bustype,
 450          .register_layout = labpc_plus_layout,
 451          .has_ao = 1,
 452          .ai_range_table = &range_labpc_plus_ai,
 453          .ai_range_code = labpc_plus_ai_gain_bits,
 454          .ai_range_is_unipolar = labpc_plus_is_unipolar,
 455          .ai_scan_up = 0,
 456          .memory_mapped_io = 0,
 457          },
 458 #ifdef CONFIG_COMEDI_PCI_DRIVERS
 459         {
 460          .name = "pci-1200",
 461          .device_id = 0x161,
 462          .ai_speed = 10000,
 463          .bustype = pci_bustype,
 464          .register_layout = labpc_1200_layout,
 465          .has_ao = 1,
 466          .ai_range_table = &range_labpc_1200_ai,
 467          .ai_range_code = labpc_1200_ai_gain_bits,
 468          .ai_range_is_unipolar = labpc_1200_is_unipolar,
 469          .ai_scan_up = 1,
 470          .memory_mapped_io = 1,
 471          },
 472 /* dummy entry so pci board works when comedi_config is passed driver name */
 473         {
 474          .name = DRV_NAME,
 475          .bustype = pci_bustype,
 476          },
 477 #endif
 478 };
 479
 480 /*
 481  * Useful for shorthand access to the particular board structure
 482  */
 483 #define thisboard ((struct labpc_board_struct *)dev->board_ptr)
 484
 485 /* size in bytes of dma buffer */
 486 static const int dma_buffer_size = 0xff00;
 487 /* 2 bytes per sample */
 488 static const int sample_size = 2;
 489
 490 static inline int labpc_counter_load(struct comedi_device *dev,
 491                                      unsigned long base_address,
 492                                      unsigned int counter_number,
 493                                      unsigned int count, unsigned int mode)
 494 {
 495         if (thisboard->memory_mapped_io)
 496                 return i8254_mm_load((void __iomem *)base_address, 0,
 497                                      counter_number, count, mode);
 498         else
 499                 return i8254_load(base_address, 0, counter_number, count, mode);
 500 }
 501
 502 int labpc_common_attach(struct comedi_device *dev, unsigned long iobase,
 503                         unsigned int irq, unsigned int dma_chan)
 504 {
 505         struct labpc_private *devpriv = dev->private;
 506         struct comedi_subdevice *s;
 507         int i;
 508         unsigned long isr_flags;
 509 #ifdef CONFIG_ISA_DMA_API
 510         unsigned long dma_flags;
 511 #endif
 512         short lsb, msb;
 513         int ret;
 514
 515         dev_info(dev->class_dev, "ni_labpc: %s\n", thisboard->name);
 516         if (iobase == 0) {
 517                 dev_err(dev->class_dev, "io base address is zero!\n");
 518                 return -EINVAL;
 519         }
 520         /*  request io regions for isa boards */
 521         if (thisboard->bustype == isa_bustype) {
 522                 /* check if io addresses are available */
 523                 if (!request_region(iobase, LABPC_SIZE, DRV_NAME)) {
 524                         dev_err(dev->class_dev, "I/O port conflict\n");
 525                         return -EIO;
 526                 }
 527         }
 528         dev->iobase = iobase;
 529
 530         if (thisboard->memory_mapped_io) {
 531                 devpriv->read_byte = labpc_readb;
 532                 devpriv->write_byte = labpc_writeb;
 533         } else {
 534                 devpriv->read_byte = labpc_inb;
 535                 devpriv->write_byte = labpc_outb;
 536         }
 537         /* initialize board's command registers */
 538         devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
 539         devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
 540         devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
 541         devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
 542         if (thisboard->register_layout == labpc_1200_layout) {
 543                 devpriv->write_byte(devpriv->command5_bits,
 544                                     dev->iobase + COMMAND5_REG);
 545                 devpriv->write_byte(devpriv->command6_bits,
 546                                     dev->iobase + COMMAND6_REG);
 547         }
 548
 549         /* grab our IRQ */
 550         if (irq) {
 551                 isr_flags = 0;
 552                 if (thisboard->bustype == pci_bustype
 553                     || thisboard->bustype == pcmcia_bustype)
 554                         isr_flags |= IRQF_SHARED;
 555                 if (request_irq(irq, labpc_interrupt, isr_flags,
 556                                 DRV_NAME, dev)) {
 557                         dev_err(dev->class_dev, "unable to allocate irq %u\n",
 558                                 irq);
 559                         return -EINVAL;
 560                 }
 561         }
 562         dev->irq = irq;
 563
 564 #ifdef CONFIG_ISA_DMA_API
 565         /* grab dma channel */
 566         if (dma_chan > 3) {
 567                 dev_err(dev->class_dev, "invalid dma channel %u\n", dma_chan);
 568                 return -EINVAL;
 569         } else if (dma_chan) {
 570                 /* allocate dma buffer */
 571                 devpriv->dma_buffer =
 572                     kmalloc(dma_buffer_size, GFP_KERNEL | GFP_DMA);
 573                 if (devpriv->dma_buffer == NULL) {
 574                         dev_err(dev->class_dev,
 575                                 "failed to allocate dma buffer\n");
 576                         return -ENOMEM;
 577                 }
 578                 if (request_dma(dma_chan, DRV_NAME)) {
 579                         dev_err(dev->class_dev,
 580                                 "failed to allocate dma channel %u\n",
 581                                 dma_chan);
 582                         return -EINVAL;
 583                 }
 584                 devpriv->dma_chan = dma_chan;
 585                 dma_flags = claim_dma_lock();
 586                 disable_dma(devpriv->dma_chan);
 587                 set_dma_mode(devpriv->dma_chan, DMA_MODE_READ);
 588                 release_dma_lock(dma_flags);
 589         }
 590 #endif
 591
 592         dev->board_name = thisboard->name;
 593
 594         ret = comedi_alloc_subdevices(dev, 5);
 595         if (ret)
 596                 return ret;
 597
 598         /* analog input subdevice */
 599         s = &dev->subdevices[0];
 600         dev->read_subdev = s;
 601         s->type = COMEDI_SUBD_AI;
 602         s->subdev_flags =
 603             SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF | SDF_CMD_READ;
 604         s->n_chan = 8;
 605         s->len_chanlist = 8;
 606         s->maxdata = (1 << 12) - 1;     /* 12 bit resolution */
 607         s->range_table = thisboard->ai_range_table;
 608         s->do_cmd = labpc_ai_cmd;
 609         s->do_cmdtest = labpc_ai_cmdtest;
 610         s->insn_read = labpc_ai_rinsn;
 611         s->cancel = labpc_cancel;
 612
 613         /* analog output */
 614         s = &dev->subdevices[1];
 615         if (thisboard->has_ao) {
 616                 /*
 617                  * Could provide command support, except it only has a
 618                  * one sample hardware buffer for analog output and no
 619                  * underrun flag.
 620                  */
 621                 s->type = COMEDI_SUBD_AO;
 622                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_GROUND;
 623                 s->n_chan = NUM_AO_CHAN;
 624                 s->maxdata = (1 << 12) - 1;     /*  12 bit resolution */
 625                 s->range_table = &range_labpc_ao;
 626                 s->insn_read = labpc_ao_rinsn;
 627                 s->insn_write = labpc_ao_winsn;
 628                 /* initialize analog outputs to a known value */
 629                 for (i = 0; i < s->n_chan; i++) {
 630                         devpriv->ao_value[i] = s->maxdata / 2;
 631                         lsb = devpriv->ao_value[i] & 0xff;
 632                         msb = (devpriv->ao_value[i] >> 8) & 0xff;
 633                         devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(i));
 634                         devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(i));
 635                 }
 636         } else {
 637                 s->type = COMEDI_SUBD_UNUSED;
 638         }
 639
 640         /* 8255 dio */
 641         s = &dev->subdevices[2];
 642         /*  if board uses io memory we have to give a custom callback
 643          * function to the 8255 driver */
 644         if (thisboard->memory_mapped_io)
 645                 subdev_8255_init(dev, s, labpc_dio_mem_callback,
 646                                  (unsigned long)(dev->iobase + DIO_BASE_REG));
 647         else
 648                 subdev_8255_init(dev, s, NULL, dev->iobase + DIO_BASE_REG);
 649
 650         /*  calibration subdevices for boards that have one */
 651         s = &dev->subdevices[3];
 652         if (thisboard->register_layout == labpc_1200_layout) {
 653                 s->type = COMEDI_SUBD_CALIB;
 654                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
 655                 s->n_chan = 16;
 656                 s->maxdata = 0xff;
 657                 s->insn_read = labpc_calib_read_insn;
 658                 s->insn_write = labpc_calib_write_insn;
 659
 660                 for (i = 0; i < s->n_chan; i++)
 661                         write_caldac(dev, i, s->maxdata / 2);
 662         } else
 663                 s->type = COMEDI_SUBD_UNUSED;
 664
 665         /* EEPROM */
 666         s = &dev->subdevices[4];
 667         if (thisboard->register_layout == labpc_1200_layout) {
 668                 s->type = COMEDI_SUBD_MEMORY;
 669                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
 670                 s->n_chan = EEPROM_SIZE;
 671                 s->maxdata = 0xff;
 672                 s->insn_read = labpc_eeprom_read_insn;
 673                 s->insn_write = labpc_eeprom_write_insn;
 674
 675                 for (i = 0; i < EEPROM_SIZE; i++)
 676                         devpriv->eeprom_data[i] = labpc_eeprom_read(dev, i);
 677         } else
 678                 s->type = COMEDI_SUBD_UNUSED;
 679
 680         return 0;
 681 }
 682 EXPORT_SYMBOL_GPL(labpc_common_attach);
 683
 684 static const struct labpc_board_struct *
 685 labpc_pci_find_boardinfo(struct pci_dev *pcidev)
 686 {
 687         unsigned int device_id = pcidev->device;
 688         unsigned int n;
 689
 690         for (n = 0; n < ARRAY_SIZE(labpc_boards); n++) {
 691                 const struct labpc_board_struct *board = &labpc_boards[n];
 692                 if (board->bustype == pci_bustype &&
 693                     board->device_id == device_id)
 694                         return board;
 695         }
 696         return NULL;
 697 }
 698
 699 static int labpc_auto_attach(struct comedi_device *dev,
 700                                        unsigned long context_unused)
 701 {
 702         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
 703         struct labpc_private *devpriv;
 704         unsigned long iobase;
 705         unsigned int irq;
 706         int ret;
 707
 708         if (!IS_ENABLED(CONFIG_COMEDI_PCI_DRIVERS))
 709                 return -ENODEV;
 710
 711         devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
 712         if (!devpriv)
 713                 return -ENOMEM;
 714         dev->private = devpriv;
 715
 716         dev->board_ptr = labpc_pci_find_boardinfo(pcidev);
 717         if (!dev->board_ptr)
 718                 return -ENODEV;
 719         devpriv->mite = mite_alloc(pcidev);
 720         if (!devpriv->mite)
 721                 return -ENOMEM;
 722         ret = mite_setup(devpriv->mite);
 723         if (ret < 0)
 724                 return ret;
 725         iobase = (unsigned long)devpriv->mite->daq_io_addr;
 726         irq = mite_irq(devpriv->mite);
 727         return labpc_common_attach(dev, iobase, irq, 0);
 728 }
 729
 730 static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it)
 731 {
 732         struct labpc_private *devpriv;
 733         unsigned long iobase = 0;
 734         unsigned int irq = 0;
 735         unsigned int dma_chan = 0;
 736
 737         devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
 738         if (!devpriv)
 739                 return -ENOMEM;
 740         dev->private = devpriv;
 741
 742         /* get base address, irq etc. based on bustype */
 743         switch (thisboard->bustype) {
 744         case isa_bustype:
 745 #ifdef CONFIG_ISA_DMA_API
 746                 iobase = it->options[0];
 747                 irq = it->options[1];
 748                 dma_chan = it->options[2];
 749 #else
 750                 dev_err(dev->class_dev,
 751                         "ni_labpc driver has not been built with ISA DMA support.\n");
 752                 return -EINVAL;
 753 #endif
 754                 break;
 755         case pci_bustype:
 756 #ifdef CONFIG_COMEDI_PCI_DRIVERS
 757                 dev_err(dev->class_dev,
 758                         "manual configuration of PCI board '%s' is not supported\n",
 759                         thisboard->name);
 760                 return -EINVAL;
 761 #else
 762                 dev_err(dev->class_dev,
 763                         "ni_labpc driver has not been built with PCI support.\n");
 764                 return -EINVAL;
 765 #endif
 766                 break;
 767         default:
 768                 dev_err(dev->class_dev,
 769                         "ni_labpc: bug! couldn't determine board type\n");
 770                 return -EINVAL;
 771                 break;
 772         }
 773
 774         return labpc_common_attach(dev, iobase, irq, dma_chan);
 775 }
 776
 777 void labpc_common_detach(struct comedi_device *dev)
 778 {
 779         struct labpc_private *devpriv = dev->private;
 780         struct comedi_subdevice *s;
 781
 782         if (!thisboard)
 783                 return;
 784         if (dev->subdevices) {
 785                 s = &dev->subdevices[2];
 786                 subdev_8255_cleanup(dev, s);
 787         }
 788 #ifdef CONFIG_ISA_DMA_API
 789         /* only free stuff if it has been allocated by _attach */
 790         kfree(devpriv->dma_buffer);
 791         if (devpriv->dma_chan)
 792                 free_dma(devpriv->dma_chan);
 793 #endif
 794         if (dev->irq)
 795                 free_irq(dev->irq, dev);
 796         if (thisboard->bustype == isa_bustype && dev->iobase)
 797                 release_region(dev->iobase, LABPC_SIZE);
 798 #ifdef CONFIG_COMEDI_PCI_DRIVERS
 799         if (devpriv->mite) {
 800                 mite_unsetup(devpriv->mite);
 801                 mite_free(devpriv->mite);
 802         }
 803 #endif
 804 };
 805 EXPORT_SYMBOL_GPL(labpc_common_detach);
 806
 807 static void labpc_clear_adc_fifo(const struct comedi_device *dev)
 808 {
 809         struct labpc_private *devpriv = dev->private;
 810
 811         devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
 812         devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
 813         devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
 814 }
 815
 816 static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
 817 {
 818         struct labpc_private *devpriv = dev->private;
 819         unsigned long flags;
 820
 821         spin_lock_irqsave(&dev->spinlock, flags);
 822         devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
 823         devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
 824         spin_unlock_irqrestore(&dev->spinlock, flags);
 825
 826         devpriv->command3_bits = 0;
 827         devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
 828
 829         return 0;
 830 }
 831
 832 static enum scan_mode labpc_ai_scan_mode(const struct comedi_cmd *cmd)
 833 {
 834         if (cmd->chanlist_len == 1)
 835                 return MODE_SINGLE_CHAN;
 836
 837         /* chanlist may be NULL during cmdtest. */
 838         if (cmd->chanlist == NULL)
 839                 return MODE_MULT_CHAN_UP;
 840
 841         if (CR_CHAN(cmd->chanlist[0]) == CR_CHAN(cmd->chanlist[1]))
 842                 return MODE_SINGLE_CHAN_INTERVAL;
 843
 844         if (CR_CHAN(cmd->chanlist[0]) < CR_CHAN(cmd->chanlist[1]))
 845                 return MODE_MULT_CHAN_UP;
 846
 847         if (CR_CHAN(cmd->chanlist[0]) > CR_CHAN(cmd->chanlist[1]))
 848                 return MODE_MULT_CHAN_DOWN;
 849
 850         pr_err("ni_labpc: bug! cannot determine AI scan mode\n");
 851         return 0;
 852 }
 853
 854 static int labpc_ai_chanlist_invalid(const struct comedi_device *dev,
 855                                      const struct comedi_cmd *cmd,
 856                                      enum scan_mode mode)
 857 {
 858         int channel, range, aref, i;
 859
 860         if (cmd->chanlist == NULL)
 861                 return 0;
 862
 863         if (mode == MODE_SINGLE_CHAN)
 864                 return 0;
 865
 866         if (mode == MODE_SINGLE_CHAN_INTERVAL) {
 867                 if (cmd->chanlist_len > 0xff) {
 868                         comedi_error(dev,
 869                                      "ni_labpc: chanlist too long for single channel interval mode\n");
 870                         return 1;
 871                 }
 872         }
 873
 874         channel = CR_CHAN(cmd->chanlist[0]);
 875         range = CR_RANGE(cmd->chanlist[0]);
 876         aref = CR_AREF(cmd->chanlist[0]);
 877
 878         for (i = 0; i < cmd->chanlist_len; i++) {
 879
 880                 switch (mode) {
 881                 case MODE_SINGLE_CHAN_INTERVAL:
 882                         if (CR_CHAN(cmd->chanlist[i]) != channel) {
 883                                 comedi_error(dev,
 884                                              "channel scanning order specified in chanlist is not supported by hardware.\n");
 885                                 return 1;
 886                         }
 887                         break;
 888                 case MODE_MULT_CHAN_UP:
 889                         if (CR_CHAN(cmd->chanlist[i]) != i) {
 890                                 comedi_error(dev,
 891                                              "channel scanning order specified in chanlist is not supported by hardware.\n");
 892                                 return 1;
 893                         }
 894                         break;
 895                 case MODE_MULT_CHAN_DOWN:
 896                         if (CR_CHAN(cmd->chanlist[i]) !=
 897                             cmd->chanlist_len - i - 1) {
 898                                 comedi_error(dev,
 899                                              "channel scanning order specified in chanlist is not supported by hardware.\n");
 900                                 return 1;
 901                         }
 902                         break;
 903                 default:
 904                         dev_err(dev->class_dev,
 905                                 "ni_labpc: bug! in chanlist check\n");
 906                         return 1;
 907                         break;
 908                 }
 909
 910                 if (CR_RANGE(cmd->chanlist[i]) != range) {
 911                         comedi_error(dev,
 912                                      "entries in chanlist must all have the same range\n");
 913                         return 1;
 914                 }
 915
 916                 if (CR_AREF(cmd->chanlist[i]) != aref) {
 917                         comedi_error(dev,
 918                                      "entries in chanlist must all have the same reference\n");
 919                         return 1;
 920                 }
 921         }
 922
 923         return 0;
 924 }
 925
 926 static int labpc_use_continuous_mode(const struct comedi_cmd *cmd,
 927                                      enum scan_mode mode)
 928 {
 929         if (mode == MODE_SINGLE_CHAN)
 930                 return 1;
 931
 932         if (cmd->scan_begin_src == TRIG_FOLLOW)
 933                 return 1;
 934
 935         return 0;
 936 }
 937
 938 static unsigned int labpc_ai_convert_period(const struct comedi_cmd *cmd,
 939                                             enum scan_mode mode)
 940 {
 941         if (cmd->convert_src != TRIG_TIMER)
 942                 return 0;
 943
 944         if (mode == MODE_SINGLE_CHAN && cmd->scan_begin_src == TRIG_TIMER)
 945                 return cmd->scan_begin_arg;
 946
 947         return cmd->convert_arg;
 948 }
 949
 950 static void labpc_set_ai_convert_period(struct comedi_cmd *cmd,
 951                                         enum scan_mode mode, unsigned int ns)
 952 {
 953         if (cmd->convert_src != TRIG_TIMER)
 954                 return;
 955
 956         if (mode == MODE_SINGLE_CHAN &&
 957             cmd->scan_begin_src == TRIG_TIMER) {
 958                 cmd->scan_begin_arg = ns;
 959                 if (cmd->convert_arg > cmd->scan_begin_arg)
 960                         cmd->convert_arg = cmd->scan_begin_arg;
 961         } else
 962                 cmd->convert_arg = ns;
 963 }
 964
 965 static unsigned int labpc_ai_scan_period(const struct comedi_cmd *cmd,
 966                                         enum scan_mode mode)
 967 {
 968         if (cmd->scan_begin_src != TRIG_TIMER)
 969                 return 0;
 970
 971         if (mode == MODE_SINGLE_CHAN && cmd->convert_src == TRIG_TIMER)
 972                 return 0;
 973
 974         return cmd->scan_begin_arg;
 975 }
 976
 977 static void labpc_set_ai_scan_period(struct comedi_cmd *cmd,
 978                                      enum scan_mode mode, unsigned int ns)
 979 {
 980         if (cmd->scan_begin_src != TRIG_TIMER)
 981                 return;
 982
 983         if (mode == MODE_SINGLE_CHAN && cmd->convert_src == TRIG_TIMER)
 984                 return;
 985
 986         cmd->scan_begin_arg = ns;
 987 }
 988
 989 static int labpc_ai_cmdtest(struct comedi_device *dev,
 990                             struct comedi_subdevice *s, struct comedi_cmd *cmd)
 991 {
 992         int err = 0;
 993         int tmp, tmp2;
 994         unsigned int stop_mask;
 995         enum scan_mode mode;
 996
 997         /* Step 1 : check if triggers are trivially valid */
 998
 999         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
1000         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
1001                                         TRIG_TIMER | TRIG_FOLLOW | TRIG_EXT);
1002         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_TIMER | TRIG_EXT);
1003         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
1004
1005         stop_mask = TRIG_COUNT | TRIG_NONE;
1006         if (thisboard->register_layout == labpc_1200_layout)
1007                 stop_mask |= TRIG_EXT;
1008         err |= cfc_check_trigger_src(&cmd->stop_src, stop_mask);
1009
1010         if (err)
1011                 return 1;
1012
1013         /* Step 2a : make sure trigger sources are unique */
1014
1015         err |= cfc_check_trigger_is_unique(cmd->start_src);
1016         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
1017         err |= cfc_check_trigger_is_unique(cmd->convert_src);
1018         err |= cfc_check_trigger_is_unique(cmd->stop_src);
1019
1020         /* Step 2b : and mutually compatible */
1021
1022         /* can't have external stop and start triggers at once */
1023         if (cmd->start_src == TRIG_EXT && cmd->stop_src == TRIG_EXT)
1024                 err++;
1025
1026         if (err)
1027                 return 2;
1028
1029         /* Step 3: check if arguments are trivially valid */
1030
1031         if (cmd->start_arg == TRIG_NOW)
1032                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
1033
1034         if (!cmd->chanlist_len)
1035                 err |= -EINVAL;
1036         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
1037
1038         if (cmd->convert_src == TRIG_TIMER)
1039                 err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
1040                                                  thisboard->ai_speed);
1041
1042         /* make sure scan timing is not too fast */
1043         if (cmd->scan_begin_src == TRIG_TIMER) {
1044                 if (cmd->convert_src == TRIG_TIMER)
1045                         err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
1046                                         cmd->convert_arg * cmd->chanlist_len);
1047                 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
1048                                 thisboard->ai_speed * cmd->chanlist_len);
1049         }
1050
1051         switch (cmd->stop_src) {
1052         case TRIG_COUNT:
1053                 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
1054                 break;
1055         case TRIG_NONE:
1056                 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
1057                 break;
1058                 /*
1059                  * TRIG_EXT doesn't care since it doesn't
1060                  * trigger off a numbered channel
1061                  */
1062         default:
1063                 break;
1064         }
1065
1066         if (err)
1067                 return 3;
1068
1069         /* step 4: fix up any arguments */
1070
1071         tmp = cmd->convert_arg;
1072         tmp2 = cmd->scan_begin_arg;
1073         mode = labpc_ai_scan_mode(cmd);
1074         labpc_adc_timing(dev, cmd, mode);
1075         if (tmp != cmd->convert_arg || tmp2 != cmd->scan_begin_arg)
1076                 err++;
1077
1078         if (err)
1079                 return 4;
1080
1081         if (labpc_ai_chanlist_invalid(dev, cmd, mode))
1082                 return 5;
1083
1084         return 0;
1085 }
1086
1087 static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
1088 {
1089         struct labpc_private *devpriv = dev->private;
1090         int channel, range, aref;
1091 #ifdef CONFIG_ISA_DMA_API
1092         unsigned long irq_flags;
1093 #endif
1094         int ret;
1095         struct comedi_async *async = s->async;
1096         struct comedi_cmd *cmd = &async->cmd;
1097         enum transfer_type xfer;
1098         enum scan_mode mode;
1099         unsigned long flags;
1100
1101         if (!dev->irq) {
1102                 comedi_error(dev, "no irq assigned, cannot perform command");
1103                 return -1;
1104         }
1105
1106         range = CR_RANGE(cmd->chanlist[0]);
1107         aref = CR_AREF(cmd->chanlist[0]);
1108
1109         /* make sure board is disabled before setting up acquisition */
1110         spin_lock_irqsave(&dev->spinlock, flags);
1111         devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
1112         devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1113         spin_unlock_irqrestore(&dev->spinlock, flags);
1114
1115         devpriv->command3_bits = 0;
1116         devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1117
1118         /*  initialize software conversion count */
1119         if (cmd->stop_src == TRIG_COUNT)
1120                 devpriv->count = cmd->stop_arg * cmd->chanlist_len;
1121
1122         /*  setup hardware conversion counter */
1123         if (cmd->stop_src == TRIG_EXT) {
1124                 /*
1125                  * load counter a1 with count of 3
1126                  * (pc+ manual says this is minimum allowed) using mode 0
1127                  */
1128                 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG,
1129                                          1, 3, 0);
1130                 if (ret < 0) {
1131                         comedi_error(dev, "error loading counter a1");
1132                         return -1;
1133                 }
1134         } else                  /*
1135                                  * otherwise, just put a1 in mode 0
1136                                  * with no count to set its output low
1137                                  */
1138                 devpriv->write_byte(INIT_A1_BITS,
1139                                     dev->iobase + COUNTER_A_CONTROL_REG);
1140
1141 #ifdef CONFIG_ISA_DMA_API
1142         /*  figure out what method we will use to transfer data */
1143         if (devpriv->dma_chan &&        /*  need a dma channel allocated */
1144                 /*
1145                  * dma unsafe at RT priority,
1146                  * and too much setup time for TRIG_WAKE_EOS for
1147                  */
1148             (cmd->flags & (TRIG_WAKE_EOS | TRIG_RT)) == 0 &&
1149             /*  only available on the isa boards */
1150             thisboard->bustype == isa_bustype) {
1151                 xfer = isa_dma_transfer;
1152                 /* pc-plus has no fifo-half full interrupt */
1153         } else
1154 #endif
1155         if (thisboard->register_layout == labpc_1200_layout &&
1156                    /*  wake-end-of-scan should interrupt on fifo not empty */
1157                    (cmd->flags & TRIG_WAKE_EOS) == 0 &&
1158                    /*  make sure we are taking more than just a few points */
1159                    (cmd->stop_src != TRIG_COUNT || devpriv->count > 256)) {
1160                 xfer = fifo_half_full_transfer;
1161         } else
1162                 xfer = fifo_not_empty_transfer;
1163         devpriv->current_transfer = xfer;
1164         mode = labpc_ai_scan_mode(cmd);
1165
1166         /*  setup command6 register for 1200 boards */
1167         if (thisboard->register_layout == labpc_1200_layout) {
1168                 /*  reference inputs to ground or common? */
1169                 if (aref != AREF_GROUND)
1170                         devpriv->command6_bits |= ADC_COMMON_BIT;
1171                 else
1172                         devpriv->command6_bits &= ~ADC_COMMON_BIT;
1173                 /*  bipolar or unipolar range? */
1174                 if (thisboard->ai_range_is_unipolar[range])
1175                         devpriv->command6_bits |= ADC_UNIP_BIT;
1176                 else
1177                         devpriv->command6_bits &= ~ADC_UNIP_BIT;
1178                 /*  interrupt on fifo half full? */
1179                 if (xfer == fifo_half_full_transfer)
1180                         devpriv->command6_bits |= ADC_FHF_INTR_EN_BIT;
1181                 else
1182                         devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT;
1183                 /*  enable interrupt on counter a1 terminal count? */
1184                 if (cmd->stop_src == TRIG_EXT)
1185                         devpriv->command6_bits |= A1_INTR_EN_BIT;
1186                 else
1187                         devpriv->command6_bits &= ~A1_INTR_EN_BIT;
1188                 /*  are we scanning up or down through channels? */
1189                 if (mode == MODE_MULT_CHAN_UP)
1190                         devpriv->command6_bits |= ADC_SCAN_UP_BIT;
1191                 else
1192                         devpriv->command6_bits &= ~ADC_SCAN_UP_BIT;
1193                 /*  write to register */
1194                 devpriv->write_byte(devpriv->command6_bits,
1195                                     dev->iobase + COMMAND6_REG);
1196         }
1197
1198         /* setup channel list, etc (command1 register) */
1199         devpriv->command1_bits = 0;
1200         if (mode == MODE_MULT_CHAN_UP)
1201                 channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
1202         else
1203                 channel = CR_CHAN(cmd->chanlist[0]);
1204         /* munge channel bits for differential / scan disabled mode */
1205         if (mode != MODE_SINGLE_CHAN && aref == AREF_DIFF)
1206                 channel *= 2;
1207         devpriv->command1_bits |= ADC_CHAN_BITS(channel);
1208         devpriv->command1_bits |= thisboard->ai_range_code[range];
1209         devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
1210         /* manual says to set scan enable bit on second pass */
1211         if (mode == MODE_MULT_CHAN_UP || mode == MODE_MULT_CHAN_DOWN) {
1212                 devpriv->command1_bits |= ADC_SCAN_EN_BIT;
1213                 /* need a brief delay before enabling scan, or scan
1214                  * list will get screwed when you switch
1215                  * between scan up to scan down mode - dunno why */
1216                 udelay(1);
1217                 devpriv->write_byte(devpriv->command1_bits,
1218                                     dev->iobase + COMMAND1_REG);
1219         }
1220         /*  setup any external triggering/pacing (command4 register) */
1221         devpriv->command4_bits = 0;
1222         if (cmd->convert_src != TRIG_EXT)
1223                 devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT;
1224         /* XXX should discard first scan when using interval scanning
1225          * since manual says it is not synced with scan clock */
1226         if (labpc_use_continuous_mode(cmd, mode) == 0) {
1227                 devpriv->command4_bits |= INTERVAL_SCAN_EN_BIT;
1228                 if (cmd->scan_begin_src == TRIG_EXT)
1229                         devpriv->command4_bits |= EXT_SCAN_EN_BIT;
1230         }
1231         /*  single-ended/differential */
1232         if (aref == AREF_DIFF)
1233                 devpriv->command4_bits |= ADC_DIFF_BIT;
1234         devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
1235
1236         devpriv->write_byte(cmd->chanlist_len,
1237                             dev->iobase + INTERVAL_COUNT_REG);
1238         /*  load count */
1239         devpriv->write_byte(INTERVAL_LOAD_BITS,
1240                             dev->iobase + INTERVAL_LOAD_REG);
1241
1242         if (cmd->convert_src == TRIG_TIMER || cmd->scan_begin_src == TRIG_TIMER) {
1243                 /*  set up pacing */
1244                 labpc_adc_timing(dev, cmd, mode);
1245                 /*  load counter b0 in mode 3 */
1246                 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG,
1247                                          0, devpriv->divisor_b0, 3);
1248                 if (ret < 0) {
1249                         comedi_error(dev, "error loading counter b0");
1250                         return -1;
1251                 }
1252         }
1253         /*  set up conversion pacing */
1254         if (labpc_ai_convert_period(cmd, mode)) {
1255                 /*  load counter a0 in mode 2 */
1256                 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG,
1257                                          0, devpriv->divisor_a0, 2);
1258                 if (ret < 0) {
1259                         comedi_error(dev, "error loading counter a0");
1260                         return -1;
1261                 }
1262         } else
1263                 devpriv->write_byte(INIT_A0_BITS,
1264                                     dev->iobase + COUNTER_A_CONTROL_REG);
1265
1266         /*  set up scan pacing */
1267         if (labpc_ai_scan_period(cmd, mode)) {
1268                 /*  load counter b1 in mode 2 */
1269                 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG,
1270                                          1, devpriv->divisor_b1, 2);
1271                 if (ret < 0) {
1272                         comedi_error(dev, "error loading counter b1");
1273                         return -1;
1274                 }
1275         }
1276
1277         labpc_clear_adc_fifo(dev);
1278
1279 #ifdef CONFIG_ISA_DMA_API
1280         /*  set up dma transfer */
1281         if (xfer == isa_dma_transfer) {
1282                 irq_flags = claim_dma_lock();
1283                 disable_dma(devpriv->dma_chan);
1284                 /* clear flip-flop to make sure 2-byte registers for
1285                  * count and address get set correctly */
1286                 clear_dma_ff(devpriv->dma_chan);
1287                 set_dma_addr(devpriv->dma_chan,
1288                              virt_to_bus(devpriv->dma_buffer));
1289                 /*  set appropriate size of transfer */
1290                 devpriv->dma_transfer_size = labpc_suggest_transfer_size(cmd);
1291                 if (cmd->stop_src == TRIG_COUNT &&
1292                     devpriv->count * sample_size < devpriv->dma_transfer_size) {
1293                         devpriv->dma_transfer_size =
1294                             devpriv->count * sample_size;
1295                 }
1296                 set_dma_count(devpriv->dma_chan, devpriv->dma_transfer_size);
1297                 enable_dma(devpriv->dma_chan);
1298                 release_dma_lock(irq_flags);
1299                 /*  enable board's dma */
1300                 devpriv->command3_bits |= DMA_EN_BIT | DMATC_INTR_EN_BIT;
1301         } else
1302                 devpriv->command3_bits &= ~DMA_EN_BIT & ~DMATC_INTR_EN_BIT;
1303 #endif
1304
1305         /*  enable error interrupts */
1306         devpriv->command3_bits |= ERR_INTR_EN_BIT;
1307         /*  enable fifo not empty interrupt? */
1308         if (xfer == fifo_not_empty_transfer)
1309                 devpriv->command3_bits |= ADC_FNE_INTR_EN_BIT;
1310         else
1311                 devpriv->command3_bits &= ~ADC_FNE_INTR_EN_BIT;
1312         devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1313
1314         /*  startup acquisition */
1315
1316         /*  command2 reg */
1317         /*  use 2 cascaded counters for pacing */
1318         spin_lock_irqsave(&dev->spinlock, flags);
1319         devpriv->command2_bits |= CASCADE_BIT;
1320         switch (cmd->start_src) {
1321         case TRIG_EXT:
1322                 devpriv->command2_bits |= HWTRIG_BIT;
1323                 devpriv->command2_bits &= ~PRETRIG_BIT & ~SWTRIG_BIT;
1324                 break;
1325         case TRIG_NOW:
1326                 devpriv->command2_bits |= SWTRIG_BIT;
1327                 devpriv->command2_bits &= ~PRETRIG_BIT & ~HWTRIG_BIT;
1328                 break;
1329         default:
1330                 comedi_error(dev, "bug with start_src");
1331                 spin_unlock_irqrestore(&dev->spinlock, flags);
1332                 return -1;
1333                 break;
1334         }
1335         switch (cmd->stop_src) {
1336         case TRIG_EXT:
1337                 devpriv->command2_bits |= HWTRIG_BIT | PRETRIG_BIT;
1338                 break;
1339         case TRIG_COUNT:
1340         case TRIG_NONE:
1341                 break;
1342         default:
1343                 comedi_error(dev, "bug with stop_src");
1344                 spin_unlock_irqrestore(&dev->spinlock, flags);
1345                 return -1;
1346         }
1347         devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1348         spin_unlock_irqrestore(&dev->spinlock, flags);
1349
1350         return 0;
1351 }
1352
1353 /* interrupt service routine */
1354 static irqreturn_t labpc_interrupt(int irq, void *d)
1355 {
1356         struct comedi_device *dev = d;
1357         struct labpc_private *devpriv = dev->private;
1358         struct comedi_subdevice *s = dev->read_subdev;
1359         struct comedi_async *async;
1360         struct comedi_cmd *cmd;
1361
1362         if (dev->attached == 0) {
1363                 comedi_error(dev, "premature interrupt");
1364                 return IRQ_HANDLED;
1365         }
1366
1367         async = s->async;
1368         cmd = &async->cmd;
1369         async->events = 0;
1370
1371         /* read board status */
1372         devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG);
1373         if (thisboard->register_layout == labpc_1200_layout)
1374                 devpriv->status2_bits =
1375                     devpriv->read_byte(dev->iobase + STATUS2_REG);
1376
1377         if ((devpriv->status1_bits & (DMATC_BIT | TIMER_BIT | OVERFLOW_BIT |
1378                                       OVERRUN_BIT | DATA_AVAIL_BIT)) == 0
1379             && (devpriv->status2_bits & A1_TC_BIT) == 0
1380             && (devpriv->status2_bits & FNHF_BIT)) {
1381                 return IRQ_NONE;
1382         }
1383
1384         if (devpriv->status1_bits & OVERRUN_BIT) {
1385                 /* clear error interrupt */
1386                 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
1387                 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1388                 comedi_event(dev, s);
1389                 comedi_error(dev, "overrun");
1390                 return IRQ_HANDLED;
1391         }
1392
1393 #ifdef CONFIG_ISA_DMA_API
1394         if (devpriv->current_transfer == isa_dma_transfer) {
1395                 /*
1396                  * if a dma terminal count of external stop trigger
1397                  * has occurred
1398                  */
1399                 if (devpriv->status1_bits & DMATC_BIT ||
1400                     (thisboard->register_layout == labpc_1200_layout
1401                      && devpriv->status2_bits & A1_TC_BIT)) {
1402                         handle_isa_dma(dev);
1403                 }
1404         } else
1405 #endif
1406                 labpc_drain_fifo(dev);
1407
1408         if (devpriv->status1_bits & TIMER_BIT) {
1409                 comedi_error(dev, "handled timer interrupt?");
1410                 /*  clear it */
1411                 devpriv->write_byte(0x1, dev->iobase + TIMER_CLEAR_REG);
1412         }
1413
1414         if (devpriv->status1_bits & OVERFLOW_BIT) {
1415                 /*  clear error interrupt */
1416                 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
1417                 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1418                 comedi_event(dev, s);
1419                 comedi_error(dev, "overflow");
1420                 return IRQ_HANDLED;
1421         }
1422         /*  handle external stop trigger */
1423         if (cmd->stop_src == TRIG_EXT) {
1424                 if (devpriv->status2_bits & A1_TC_BIT) {
1425                         labpc_drain_dregs(dev);
1426                         labpc_cancel(dev, s);
1427                         async->events |= COMEDI_CB_EOA;
1428                 }
1429         }
1430
1431         /* TRIG_COUNT end of acquisition */
1432         if (cmd->stop_src == TRIG_COUNT) {
1433                 if (devpriv->count == 0) {
1434                         labpc_cancel(dev, s);
1435                         async->events |= COMEDI_CB_EOA;
1436                 }
1437         }
1438
1439         comedi_event(dev, s);
1440         return IRQ_HANDLED;
1441 }
1442
1443 /* read all available samples from ai fifo */
1444 static int labpc_drain_fifo(struct comedi_device *dev)
1445 {
1446         struct labpc_private *devpriv = dev->private;
1447         unsigned int lsb, msb;
1448         short data;
1449         struct comedi_async *async = dev->read_subdev->async;
1450         const int timeout = 10000;
1451         unsigned int i;
1452
1453         devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG);
1454
1455         for (i = 0; (devpriv->status1_bits & DATA_AVAIL_BIT) && i < timeout;
1456              i++) {
1457                 /*  quit if we have all the data we want */
1458                 if (async->cmd.stop_src == TRIG_COUNT) {
1459                         if (devpriv->count == 0)
1460                                 break;
1461                         devpriv->count--;
1462                 }
1463                 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1464                 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1465                 data = (msb << 8) | lsb;
1466                 cfc_write_to_buffer(dev->read_subdev, data);
1467                 devpriv->status1_bits =
1468                     devpriv->read_byte(dev->iobase + STATUS1_REG);
1469         }
1470         if (i == timeout) {
1471                 comedi_error(dev, "ai timeout, fifo never empties");
1472                 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1473                 return -1;
1474         }
1475
1476         return 0;
1477 }
1478
1479 #ifdef CONFIG_ISA_DMA_API
1480 static void labpc_drain_dma(struct comedi_device *dev)
1481 {
1482         struct labpc_private *devpriv = dev->private;
1483         struct comedi_subdevice *s = dev->read_subdev;
1484         struct comedi_async *async = s->async;
1485         int status;
1486         unsigned long flags;
1487         unsigned int max_points, num_points, residue, leftover;
1488         int i;
1489
1490         status = devpriv->status1_bits;
1491
1492         flags = claim_dma_lock();
1493         disable_dma(devpriv->dma_chan);
1494         /* clear flip-flop to make sure 2-byte registers for
1495          * count and address get set correctly */
1496         clear_dma_ff(devpriv->dma_chan);
1497
1498         /*  figure out how many points to read */
1499         max_points = devpriv->dma_transfer_size / sample_size;
1500         /* residue is the number of points left to be done on the dma
1501          * transfer.  It should always be zero at this point unless
1502          * the stop_src is set to external triggering.
1503          */
1504         residue = get_dma_residue(devpriv->dma_chan) / sample_size;
1505         num_points = max_points - residue;
1506         if (devpriv->count < num_points && async->cmd.stop_src == TRIG_COUNT)
1507                 num_points = devpriv->count;
1508
1509         /*  figure out how many points will be stored next time */
1510         leftover = 0;
1511         if (async->cmd.stop_src != TRIG_COUNT) {
1512                 leftover = devpriv->dma_transfer_size / sample_size;
1513         } else if (devpriv->count > num_points) {
1514                 leftover = devpriv->count - num_points;
1515                 if (leftover > max_points)
1516                         leftover = max_points;
1517         }
1518
1519         /* write data to comedi buffer */
1520         for (i = 0; i < num_points; i++)
1521                 cfc_write_to_buffer(s, devpriv->dma_buffer[i]);
1522
1523         if (async->cmd.stop_src == TRIG_COUNT)
1524                 devpriv->count -= num_points;
1525
1526         /*  set address and count for next transfer */
1527         set_dma_addr(devpriv->dma_chan, virt_to_bus(devpriv->dma_buffer));
1528         set_dma_count(devpriv->dma_chan, leftover * sample_size);
1529         release_dma_lock(flags);
1530
1531         async->events |= COMEDI_CB_BLOCK;
1532 }
1533
1534 static void handle_isa_dma(struct comedi_device *dev)
1535 {
1536         struct labpc_private *devpriv = dev->private;
1537
1538         labpc_drain_dma(dev);
1539
1540         enable_dma(devpriv->dma_chan);
1541
1542         /*  clear dma tc interrupt */
1543         devpriv->write_byte(0x1, dev->iobase + DMATC_CLEAR_REG);
1544 }
1545 #endif
1546
1547 /* makes sure all data acquired by board is transferred to comedi (used
1548  * when acquisition is terminated by stop_src == TRIG_EXT). */
1549 static void labpc_drain_dregs(struct comedi_device *dev)
1550 {
1551 #ifdef CONFIG_ISA_DMA_API
1552         struct labpc_private *devpriv = dev->private;
1553
1554         if (devpriv->current_transfer == isa_dma_transfer)
1555                 labpc_drain_dma(dev);
1556 #endif
1557
1558         labpc_drain_fifo(dev);
1559 }
1560
1561 static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1562                           struct comedi_insn *insn, unsigned int *data)
1563 {
1564         struct labpc_private *devpriv = dev->private;
1565         int i, n;
1566         int chan, range;
1567         int lsb, msb;
1568         int timeout = 1000;
1569         unsigned long flags;
1570
1571         /*  disable timed conversions */
1572         spin_lock_irqsave(&dev->spinlock, flags);
1573         devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
1574         devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1575         spin_unlock_irqrestore(&dev->spinlock, flags);
1576
1577         /*  disable interrupt generation and dma */
1578         devpriv->command3_bits = 0;
1579         devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1580
1581         /* set gain and channel */
1582         devpriv->command1_bits = 0;
1583         chan = CR_CHAN(insn->chanspec);
1584         range = CR_RANGE(insn->chanspec);
1585         devpriv->command1_bits |= thisboard->ai_range_code[range];
1586         /* munge channel bits for differential/scan disabled mode */
1587         if (CR_AREF(insn->chanspec) == AREF_DIFF)
1588                 chan *= 2;
1589         devpriv->command1_bits |= ADC_CHAN_BITS(chan);
1590         devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
1591
1592         /* setup command6 register for 1200 boards */
1593         if (thisboard->register_layout == labpc_1200_layout) {
1594                 /*  reference inputs to ground or common? */
1595                 if (CR_AREF(insn->chanspec) != AREF_GROUND)
1596                         devpriv->command6_bits |= ADC_COMMON_BIT;
1597                 else
1598                         devpriv->command6_bits &= ~ADC_COMMON_BIT;
1599                 /* bipolar or unipolar range? */
1600                 if (thisboard->ai_range_is_unipolar[range])
1601                         devpriv->command6_bits |= ADC_UNIP_BIT;
1602                 else
1603                         devpriv->command6_bits &= ~ADC_UNIP_BIT;
1604                 /* don't interrupt on fifo half full */
1605                 devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT;
1606                 /* don't enable interrupt on counter a1 terminal count? */
1607                 devpriv->command6_bits &= ~A1_INTR_EN_BIT;
1608                 /* write to register */
1609                 devpriv->write_byte(devpriv->command6_bits,
1610                                     dev->iobase + COMMAND6_REG);
1611         }
1612         /* setup command4 register */
1613         devpriv->command4_bits = 0;
1614         devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT;
1615         /* single-ended/differential */
1616         if (CR_AREF(insn->chanspec) == AREF_DIFF)
1617                 devpriv->command4_bits |= ADC_DIFF_BIT;
1618         devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
1619
1620         /*
1621          * initialize pacer counter output to make sure it doesn't
1622          * cause any problems
1623          */
1624         devpriv->write_byte(INIT_A0_BITS, dev->iobase + COUNTER_A_CONTROL_REG);
1625
1626         labpc_clear_adc_fifo(dev);
1627
1628         for (n = 0; n < insn->n; n++) {
1629                 /* trigger conversion */
1630                 devpriv->write_byte(0x1, dev->iobase + ADC_CONVERT_REG);
1631
1632                 for (i = 0; i < timeout; i++) {
1633                         if (devpriv->read_byte(dev->iobase +
1634                                                STATUS1_REG) & DATA_AVAIL_BIT)
1635                                 break;
1636                         udelay(1);
1637                 }
1638                 if (i == timeout) {
1639                         comedi_error(dev, "timeout");
1640                         return -ETIME;
1641                 }
1642                 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1643                 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1644                 data[n] = (msb << 8) | lsb;
1645         }
1646
1647         return n;
1648 }
1649
1650 /* analog output insn */
1651 static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
1652                           struct comedi_insn *insn, unsigned int *data)
1653 {
1654         struct labpc_private *devpriv = dev->private;
1655         int channel, range;
1656         unsigned long flags;
1657         int lsb, msb;
1658
1659         channel = CR_CHAN(insn->chanspec);
1660
1661         /* turn off pacing of analog output channel */
1662         /* note: hardware bug in daqcard-1200 means pacing cannot
1663          * be independently enabled/disabled for its the two channels */
1664         spin_lock_irqsave(&dev->spinlock, flags);
1665         devpriv->command2_bits &= ~DAC_PACED_BIT(channel);
1666         devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1667         spin_unlock_irqrestore(&dev->spinlock, flags);
1668
1669         /* set range */
1670         if (thisboard->register_layout == labpc_1200_layout) {
1671                 range = CR_RANGE(insn->chanspec);
1672                 if (range & AO_RANGE_IS_UNIPOLAR)
1673                         devpriv->command6_bits |= DAC_UNIP_BIT(channel);
1674                 else
1675                         devpriv->command6_bits &= ~DAC_UNIP_BIT(channel);
1676                 /*  write to register */
1677                 devpriv->write_byte(devpriv->command6_bits,
1678                                     dev->iobase + COMMAND6_REG);
1679         }
1680         /* send data */
1681         lsb = data[0] & 0xff;
1682         msb = (data[0] >> 8) & 0xff;
1683         devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(channel));
1684         devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(channel));
1685
1686         /* remember value for readback */
1687         devpriv->ao_value[channel] = data[0];
1688
1689         return 1;
1690 }
1691
1692 /* analog output readback insn */
1693 static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1694                           struct comedi_insn *insn, unsigned int *data)
1695 {
1696         struct labpc_private *devpriv = dev->private;
1697
1698         data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)];
1699
1700         return 1;
1701 }
1702
1703 static int labpc_calib_read_insn(struct comedi_device *dev,
1704                                  struct comedi_subdevice *s,
1705                                  struct comedi_insn *insn, unsigned int *data)
1706 {
1707         struct labpc_private *devpriv = dev->private;
1708
1709         data[0] = devpriv->caldac[CR_CHAN(insn->chanspec)];
1710
1711         return 1;
1712 }
1713
1714 static int labpc_calib_write_insn(struct comedi_device *dev,
1715                                   struct comedi_subdevice *s,
1716                                   struct comedi_insn *insn, unsigned int *data)
1717 {
1718         int channel = CR_CHAN(insn->chanspec);
1719
1720         write_caldac(dev, channel, data[0]);
1721         return 1;
1722 }
1723
1724 static int labpc_eeprom_read_insn(struct comedi_device *dev,
1725                                   struct comedi_subdevice *s,
1726                                   struct comedi_insn *insn, unsigned int *data)
1727 {
1728         struct labpc_private *devpriv = dev->private;
1729
1730         data[0] = devpriv->eeprom_data[CR_CHAN(insn->chanspec)];
1731
1732         return 1;
1733 }
1734
1735 static int labpc_eeprom_write_insn(struct comedi_device *dev,
1736                                    struct comedi_subdevice *s,
1737                                    struct comedi_insn *insn, unsigned int *data)
1738 {
1739         int channel = CR_CHAN(insn->chanspec);
1740         int ret;
1741
1742         /*  only allow writes to user area of eeprom */
1743         if (channel < 16 || channel > 127) {
1744                 dev_dbg(dev->class_dev,
1745                         "eeprom writes are only allowed to channels 16 through 127 (the pointer and user areas)\n");
1746                 return -EINVAL;
1747         }
1748
1749         ret = labpc_eeprom_write(dev, channel, data[0]);
1750         if (ret < 0)
1751                 return ret;
1752
1753         return 1;
1754 }
1755
1756 #ifdef CONFIG_ISA_DMA_API
1757 /* utility function that suggests a dma transfer size in bytes */
1758 static unsigned int labpc_suggest_transfer_size(const struct comedi_cmd *cmd)
1759 {
1760         unsigned int size;
1761         unsigned int freq;
1762
1763         if (cmd->convert_src == TRIG_TIMER)
1764                 freq = 1000000000 / cmd->convert_arg;
1765         /* return some default value */
1766         else
1767                 freq = 0xffffffff;
1768
1769         /* make buffer fill in no more than 1/3 second */
1770         size = (freq / 3) * sample_size;
1771
1772         /* set a minimum and maximum size allowed */
1773         if (size > dma_buffer_size)
1774                 size = dma_buffer_size - dma_buffer_size % sample_size;
1775         else if (size < sample_size)
1776                 size = sample_size;
1777
1778         return size;
1779 }
1780 #endif
1781
1782 /* figures out what counter values to use based on command */
1783 static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd,
1784                              enum scan_mode mode)
1785 {
1786         struct labpc_private *devpriv = dev->private;
1787         /* max value for 16 bit counter in mode 2 */
1788         const int max_counter_value = 0x10000;
1789         /* min value for 16 bit counter in mode 2 */
1790         const int min_counter_value = 2;
1791         unsigned int base_period;
1792         unsigned int scan_period;
1793         unsigned int convert_period;
1794
1795         /*
1796          * if both convert and scan triggers are TRIG_TIMER, then they
1797          * both rely on counter b0
1798          */
1799         convert_period = labpc_ai_convert_period(cmd, mode);
1800         scan_period = labpc_ai_scan_period(cmd, mode);
1801         if (convert_period && scan_period) {
1802                 /*
1803                  * pick the lowest b0 divisor value we can (for maximum input
1804                  * clock speed on convert and scan counters)
1805                  */
1806                 devpriv->divisor_b0 = (scan_period - 1) /
1807                     (LABPC_TIMER_BASE * max_counter_value) + 1;
1808                 if (devpriv->divisor_b0 < min_counter_value)
1809                         devpriv->divisor_b0 = min_counter_value;
1810                 if (devpriv->divisor_b0 > max_counter_value)
1811                         devpriv->divisor_b0 = max_counter_value;
1812
1813                 base_period = LABPC_TIMER_BASE * devpriv->divisor_b0;
1814
1815                 /*  set a0 for conversion frequency and b1 for scan frequency */
1816                 switch (cmd->flags & TRIG_ROUND_MASK) {
1817                 default:
1818                 case TRIG_ROUND_NEAREST:
1819                         devpriv->divisor_a0 =
1820                             (convert_period + (base_period / 2)) / base_period;
1821                         devpriv->divisor_b1 =
1822                             (scan_period + (base_period / 2)) / base_period;
1823                         break;
1824                 case TRIG_ROUND_UP:
1825                         devpriv->divisor_a0 =
1826                             (convert_period + (base_period - 1)) / base_period;
1827                         devpriv->divisor_b1 =
1828                             (scan_period + (base_period - 1)) / base_period;
1829                         break;
1830                 case TRIG_ROUND_DOWN:
1831                         devpriv->divisor_a0 = convert_period / base_period;
1832                         devpriv->divisor_b1 = scan_period / base_period;
1833                         break;
1834                 }
1835                 /*  make sure a0 and b1 values are acceptable */
1836                 if (devpriv->divisor_a0 < min_counter_value)
1837                         devpriv->divisor_a0 = min_counter_value;
1838                 if (devpriv->divisor_a0 > max_counter_value)
1839                         devpriv->divisor_a0 = max_counter_value;
1840                 if (devpriv->divisor_b1 < min_counter_value)
1841                         devpriv->divisor_b1 = min_counter_value;
1842                 if (devpriv->divisor_b1 > max_counter_value)
1843                         devpriv->divisor_b1 = max_counter_value;
1844                 /*  write corrected timings to command */
1845                 labpc_set_ai_convert_period(cmd, mode,
1846                                             base_period * devpriv->divisor_a0);
1847                 labpc_set_ai_scan_period(cmd, mode,
1848                                          base_period * devpriv->divisor_b1);
1849                 /*
1850                  * if only one TRIG_TIMER is used, we can employ the generic
1851                  * cascaded timing functions
1852                  */
1853         } else if (scan_period) {
1854                 /*
1855                  * calculate cascaded counter values
1856                  * that give desired scan timing
1857                  */
1858                 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE,
1859                                                &(devpriv->divisor_b1),
1860                                                &(devpriv->divisor_b0),
1861                                                &scan_period,
1862                                                cmd->flags & TRIG_ROUND_MASK);
1863                 labpc_set_ai_scan_period(cmd, mode, scan_period);
1864         } else if (convert_period) {
1865                 /*
1866                  * calculate cascaded counter values
1867                  * that give desired conversion timing
1868                  */
1869                 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE,
1870                                                &(devpriv->divisor_a0),
1871                                                &(devpriv->divisor_b0),
1872                                                &convert_period,
1873                                                cmd->flags & TRIG_ROUND_MASK);
1874                 labpc_set_ai_convert_period(cmd, mode, convert_period);
1875         }
1876 }
1877
1878 static int labpc_dio_mem_callback(int dir, int port, int data,
1879                                   unsigned long iobase)
1880 {
1881         if (dir) {
1882                 writeb(data, (void __iomem *)(iobase + port));
1883                 return 0;
1884         } else {
1885                 return readb((void __iomem *)(iobase + port));
1886         }
1887 }
1888
1889 /* lowlevel write to eeprom/dac */
1890 static void labpc_serial_out(struct comedi_device *dev, unsigned int value,
1891                              unsigned int value_width)
1892 {
1893         struct labpc_private *devpriv = dev->private;
1894         int i;
1895
1896         for (i = 1; i <= value_width; i++) {
1897                 /*  clear serial clock */
1898                 devpriv->command5_bits &= ~SCLOCK_BIT;
1899                 /*  send bits most significant bit first */
1900                 if (value & (1 << (value_width - i)))
1901                         devpriv->command5_bits |= SDATA_BIT;
1902                 else
1903                         devpriv->command5_bits &= ~SDATA_BIT;
1904                 udelay(1);
1905                 devpriv->write_byte(devpriv->command5_bits,
1906                                     dev->iobase + COMMAND5_REG);
1907                 /*  set clock to load bit */
1908                 devpriv->command5_bits |= SCLOCK_BIT;
1909                 udelay(1);
1910                 devpriv->write_byte(devpriv->command5_bits,
1911                                     dev->iobase + COMMAND5_REG);
1912         }
1913 }
1914
1915 /* lowlevel read from eeprom */
1916 static unsigned int labpc_serial_in(struct comedi_device *dev)
1917 {
1918         struct labpc_private *devpriv = dev->private;
1919         unsigned int value = 0;
1920         int i;
1921         const int value_width = 8;      /*  number of bits wide values are */
1922
1923         for (i = 1; i <= value_width; i++) {
1924                 /*  set serial clock */
1925                 devpriv->command5_bits |= SCLOCK_BIT;
1926                 udelay(1);
1927                 devpriv->write_byte(devpriv->command5_bits,
1928                                     dev->iobase + COMMAND5_REG);
1929                 /*  clear clock bit */
1930                 devpriv->command5_bits &= ~SCLOCK_BIT;
1931                 udelay(1);
1932                 devpriv->write_byte(devpriv->command5_bits,
1933                                     dev->iobase + COMMAND5_REG);
1934                 /*  read bits most significant bit first */
1935                 udelay(1);
1936                 devpriv->status2_bits =
1937                     devpriv->read_byte(dev->iobase + STATUS2_REG);
1938                 if (devpriv->status2_bits & EEPROM_OUT_BIT)
1939                         value |= 1 << (value_width - i);
1940         }
1941
1942         return value;
1943 }
1944
1945 static unsigned int labpc_eeprom_read(struct comedi_device *dev,
1946                                       unsigned int address)
1947 {
1948         struct labpc_private *devpriv = dev->private;
1949         unsigned int value;
1950         /*  bits to tell eeprom to expect a read */
1951         const int read_instruction = 0x3;
1952         /*  8 bit write lengths to eeprom */
1953         const int write_length = 8;
1954
1955         /*  enable read/write to eeprom */
1956         devpriv->command5_bits &= ~EEPROM_EN_BIT;
1957         udelay(1);
1958         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1959         devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
1960         udelay(1);
1961         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1962
1963         /*  send read instruction */
1964         labpc_serial_out(dev, read_instruction, write_length);
1965         /*  send 8 bit address to read from */
1966         labpc_serial_out(dev, address, write_length);
1967         /*  read result */
1968         value = labpc_serial_in(dev);
1969
1970         /*  disable read/write to eeprom */
1971         devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
1972         udelay(1);
1973         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1974
1975         return value;
1976 }
1977
1978 static int labpc_eeprom_write(struct comedi_device *dev,
1979                                 unsigned int address, unsigned int value)
1980 {
1981         struct labpc_private *devpriv = dev->private;
1982         const int write_enable_instruction = 0x6;
1983         const int write_instruction = 0x2;
1984         const int write_length = 8;     /*  8 bit write lengths to eeprom */
1985         const int write_in_progress_bit = 0x1;
1986         const int timeout = 10000;
1987         int i;
1988
1989         /*  make sure there isn't already a write in progress */
1990         for (i = 0; i < timeout; i++) {
1991                 if ((labpc_eeprom_read_status(dev) & write_in_progress_bit) ==
1992                     0)
1993                         break;
1994         }
1995         if (i == timeout) {
1996                 comedi_error(dev, "eeprom write timed out");
1997                 return -ETIME;
1998         }
1999         /*  update software copy of eeprom */
2000         devpriv->eeprom_data[address] = value;
2001
2002         /*  enable read/write to eeprom */
2003         devpriv->command5_bits &= ~EEPROM_EN_BIT;
2004         udelay(1);
2005         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2006         devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
2007         udelay(1);
2008         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2009
2010         /*  send write_enable instruction */
2011         labpc_serial_out(dev, write_enable_instruction, write_length);
2012         devpriv->command5_bits &= ~EEPROM_EN_BIT;
2013         udelay(1);
2014         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2015
2016         /*  send write instruction */
2017         devpriv->command5_bits |= EEPROM_EN_BIT;
2018         udelay(1);
2019         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2020         labpc_serial_out(dev, write_instruction, write_length);
2021         /*  send 8 bit address to write to */
2022         labpc_serial_out(dev, address, write_length);
2023         /*  write value */
2024         labpc_serial_out(dev, value, write_length);
2025         devpriv->command5_bits &= ~EEPROM_EN_BIT;
2026         udelay(1);
2027         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2028
2029         /*  disable read/write to eeprom */
2030         devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
2031         udelay(1);
2032         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2033
2034         return 0;
2035 }
2036
2037 static unsigned int labpc_eeprom_read_status(struct comedi_device *dev)
2038 {
2039         struct labpc_private *devpriv = dev->private;
2040         unsigned int value;
2041         const int read_status_instruction = 0x5;
2042         const int write_length = 8;     /*  8 bit write lengths to eeprom */
2043
2044         /*  enable read/write to eeprom */
2045         devpriv->command5_bits &= ~EEPROM_EN_BIT;
2046         udelay(1);
2047         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2048         devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
2049         udelay(1);
2050         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2051
2052         /*  send read status instruction */
2053         labpc_serial_out(dev, read_status_instruction, write_length);
2054         /*  read result */
2055         value = labpc_serial_in(dev);
2056
2057         /*  disable read/write to eeprom */
2058         devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
2059         udelay(1);
2060         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2061
2062         return value;
2063 }
2064
2065 /* writes to 8 bit calibration dacs */
2066 static void write_caldac(struct comedi_device *dev, unsigned int channel,
2067                          unsigned int value)
2068 {
2069         struct labpc_private *devpriv = dev->private;
2070
2071         if (value == devpriv->caldac[channel])
2072                 return;
2073         devpriv->caldac[channel] = value;
2074
2075         /*  clear caldac load bit and make sure we don't write to eeprom */
2076         devpriv->command5_bits &=
2077             ~CALDAC_LOAD_BIT & ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
2078         udelay(1);
2079         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2080
2081         /*  write 4 bit channel */
2082         labpc_serial_out(dev, channel, 4);
2083         /*  write 8 bit caldac value */
2084         labpc_serial_out(dev, value, 8);
2085
2086         /*  set and clear caldac bit to load caldac value */
2087         devpriv->command5_bits |= CALDAC_LOAD_BIT;
2088         udelay(1);
2089         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2090         devpriv->command5_bits &= ~CALDAC_LOAD_BIT;
2091         udelay(1);
2092         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2093 }
2094
2095 static struct comedi_driver labpc_driver = {
2096         .driver_name = DRV_NAME,
2097         .module = THIS_MODULE,
2098         .attach = labpc_attach,
2099         .auto_attach = labpc_auto_attach,
2100         .detach = labpc_common_detach,
2101         .num_names = ARRAY_SIZE(labpc_boards),
2102         .board_name = &labpc_boards[0].name,
2103         .offset = sizeof(struct labpc_board_struct),
2104 };
2105
2106 #ifdef CONFIG_COMEDI_PCI_DRIVERS
2107 static DEFINE_PCI_DEVICE_TABLE(labpc_pci_table) = {
2108         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x161)},
2109         {0}
2110 };
2111 MODULE_DEVICE_TABLE(pci, labpc_pci_table);
2112
2113 static int labpc_pci_probe(struct pci_dev *dev,
2114                                      const struct pci_device_id *ent)
2115 {
2116         return comedi_pci_auto_config(dev, &labpc_driver);
2117 }
2118
2119 static struct pci_driver labpc_pci_driver = {
2120         .name = DRV_NAME,
2121         .id_table = labpc_pci_table,
2122         .probe = labpc_pci_probe,
2123         .remove         = comedi_pci_auto_unconfig,
2124 };
2125 module_comedi_pci_driver(labpc_driver, labpc_pci_driver);
2126 #else
2127 module_comedi_driver(labpc_driver);
2128 #endif
2129
2130
2131 MODULE_AUTHOR("Comedi http://www.comedi.org");
2132 MODULE_DESCRIPTION("Comedi low-level driver");
2133 MODULE_LICENSE("GPL");