drivers/staging/comedi/drivers/ni_mio_common.c

   1 /*
   2     comedi/drivers/ni_mio_common.c
   3     Hardware driver for DAQ-STC based boards
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
   7     Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18 */
  19
  20 /*
  21         This file is meant to be included by another file, e.g.,
  22         ni_atmio.c or ni_pcimio.c.
  23
  24         Interrupt support originally added by Truxton Fulton
  25         <trux@truxton.com>
  26
  27         References (from ftp://ftp.natinst.com/support/manuals):
  28
  29            340747b.pdf  AT-MIO E series Register Level Programmer Manual
  30            341079b.pdf  PCI E Series RLPM
  31            340934b.pdf  DAQ-STC reference manual
  32         67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/)
  33         release_ni611x.pdf
  34         release_ni67xx.pdf
  35         Other possibly relevant info:
  36
  37            320517c.pdf  User manual (obsolete)
  38            320517f.pdf  User manual (new)
  39            320889a.pdf  delete
  40            320906c.pdf  maximum signal ratings
  41            321066a.pdf  about 16x
  42            321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  43            321808a.pdf  about at-mio-16e-10 rev P
  44            321837a.pdf  discontinuation of at-mio-16de-10 rev d
  45            321838a.pdf  about at-mio-16de-10 rev N
  46
  47         ISSUES:
  48
  49          - the interrupt routine needs to be cleaned up
  50
  51         2006-02-07: S-Series PCI-6143: Support has been added but is not
  52                 fully tested as yet. Terry Barnaby, BEAM Ltd.
  53 */
  54
  55 #include <linux/interrupt.h>
  56 #include <linux/sched.h>
  57 #include <linux/delay.h>
  58 #include "8255.h"
  59 #include "mite.h"
  60 #include "comedi_fc.h"
  61
  62 /* A timeout count */
  63 #define NI_TIMEOUT 1000
  64 static const unsigned old_RTSI_clock_channel = 7;
  65
  66 /* Note: this table must match the ai_gain_* definitions */
  67 static const short ni_gainlkup[][16] = {
  68         [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
  69                         0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  70         [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
  71         [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
  72                         0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  73         [ai_gain_4] = {0, 1, 4, 7},
  74         [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
  75                           0x003, 0x004, 0x005, 0x006},
  76         [ai_gain_622x] = {0, 1, 4, 5},
  77         [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
  78         [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
  79 };
  80
  81 static const struct comedi_lrange range_ni_E_ai = {
  82         16, {
  83                 BIP_RANGE(10),
  84                 BIP_RANGE(5),
  85                 BIP_RANGE(2.5),
  86                 BIP_RANGE(1),
  87                 BIP_RANGE(0.5),
  88                 BIP_RANGE(0.25),
  89                 BIP_RANGE(0.1),
  90                 BIP_RANGE(0.05),
  91                 UNI_RANGE(20),
  92                 UNI_RANGE(10),
  93                 UNI_RANGE(5),
  94                 UNI_RANGE(2),
  95                 UNI_RANGE(1),
  96                 UNI_RANGE(0.5),
  97                 UNI_RANGE(0.2),
  98                 UNI_RANGE(0.1)
  99         }
 100 };
 101
 102 static const struct comedi_lrange range_ni_E_ai_limited = {
 103         8, {
 104                 BIP_RANGE(10),
 105                 BIP_RANGE(5),
 106                 BIP_RANGE(1),
 107                 BIP_RANGE(0.1),
 108                 UNI_RANGE(10),
 109                 UNI_RANGE(5),
 110                 UNI_RANGE(1),
 111                 UNI_RANGE(0.1)
 112         }
 113 };
 114
 115 static const struct comedi_lrange range_ni_E_ai_limited14 = {
 116         14, {
 117                 BIP_RANGE(10),
 118                 BIP_RANGE(5),
 119                 BIP_RANGE(2),
 120                 BIP_RANGE(1),
 121                 BIP_RANGE(0.5),
 122                 BIP_RANGE(0.2),
 123                 BIP_RANGE(0.1),
 124                 UNI_RANGE(10),
 125                 UNI_RANGE(5),
 126                 UNI_RANGE(2),
 127                 UNI_RANGE(1),
 128                 UNI_RANGE(0.5),
 129                 UNI_RANGE(0.2),
 130                 UNI_RANGE(0.1)
 131         }
 132 };
 133
 134 static const struct comedi_lrange range_ni_E_ai_bipolar4 = {
 135         4, {
 136                 BIP_RANGE(10),
 137                 BIP_RANGE(5),
 138                 BIP_RANGE(0.5),
 139                 BIP_RANGE(0.05)
 140         }
 141 };
 142
 143 static const struct comedi_lrange range_ni_E_ai_611x = {
 144         8, {
 145                 BIP_RANGE(50),
 146                 BIP_RANGE(20),
 147                 BIP_RANGE(10),
 148                 BIP_RANGE(5),
 149                 BIP_RANGE(2),
 150                 BIP_RANGE(1),
 151                 BIP_RANGE(0.5),
 152                 BIP_RANGE(0.2)
 153         }
 154 };
 155
 156 static const struct comedi_lrange range_ni_M_ai_622x = {
 157         4, {
 158                 BIP_RANGE(10),
 159                 BIP_RANGE(5),
 160                 BIP_RANGE(1),
 161                 BIP_RANGE(0.2)
 162         }
 163 };
 164
 165 static const struct comedi_lrange range_ni_M_ai_628x = {
 166         7, {
 167                 BIP_RANGE(10),
 168                 BIP_RANGE(5),
 169                 BIP_RANGE(2),
 170                 BIP_RANGE(1),
 171                 BIP_RANGE(0.5),
 172                 BIP_RANGE(0.2),
 173                 BIP_RANGE(0.1)
 174         }
 175 };
 176
 177 static const struct comedi_lrange range_ni_E_ao_ext = {
 178         4, {
 179                 BIP_RANGE(10),
 180                 UNI_RANGE(10),
 181                 RANGE_ext(-1, 1),
 182                 RANGE_ext(0, 1)
 183         }
 184 };
 185
 186 static const struct comedi_lrange *const ni_range_lkup[] = {
 187         [ai_gain_16] = &range_ni_E_ai,
 188         [ai_gain_8] = &range_ni_E_ai_limited,
 189         [ai_gain_14] = &range_ni_E_ai_limited14,
 190         [ai_gain_4] = &range_ni_E_ai_bipolar4,
 191         [ai_gain_611x] = &range_ni_E_ai_611x,
 192         [ai_gain_622x] = &range_ni_M_ai_622x,
 193         [ai_gain_628x] = &range_ni_M_ai_628x,
 194         [ai_gain_6143] = &range_bipolar5
 195 };
 196
 197 static int ni_dio_insn_config(struct comedi_device *dev,
 198                               struct comedi_subdevice *s,
 199                               struct comedi_insn *insn, unsigned int *data);
 200 static int ni_dio_insn_bits(struct comedi_device *dev,
 201                             struct comedi_subdevice *s,
 202                             struct comedi_insn *insn, unsigned int *data);
 203 static int ni_cdio_cmdtest(struct comedi_device *dev,
 204                            struct comedi_subdevice *s, struct comedi_cmd *cmd);
 205 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
 206 static int ni_cdio_cancel(struct comedi_device *dev,
 207                           struct comedi_subdevice *s);
 208 static void handle_cdio_interrupt(struct comedi_device *dev);
 209 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
 210                           unsigned int trignum);
 211
 212 static int ni_serial_insn_config(struct comedi_device *dev,
 213                                  struct comedi_subdevice *s,
 214                                  struct comedi_insn *insn, unsigned int *data);
 215 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
 216                                    struct comedi_subdevice *s,
 217                                    unsigned char data_out,
 218                                    unsigned char *data_in);
 219 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
 220                                    struct comedi_subdevice *s,
 221                                    unsigned char data_out,
 222                                    unsigned char *data_in);
 223
 224 static int ni_calib_insn_read(struct comedi_device *dev,
 225                               struct comedi_subdevice *s,
 226                               struct comedi_insn *insn, unsigned int *data);
 227 static int ni_calib_insn_write(struct comedi_device *dev,
 228                                struct comedi_subdevice *s,
 229                                struct comedi_insn *insn, unsigned int *data);
 230
 231 static int ni_eeprom_insn_read(struct comedi_device *dev,
 232                                struct comedi_subdevice *s,
 233                                struct comedi_insn *insn, unsigned int *data);
 234 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
 235                                         struct comedi_subdevice *s,
 236                                         struct comedi_insn *insn,
 237                                         unsigned int *data);
 238
 239 static int ni_pfi_insn_bits(struct comedi_device *dev,
 240                             struct comedi_subdevice *s,
 241                             struct comedi_insn *insn, unsigned int *data);
 242 static int ni_pfi_insn_config(struct comedi_device *dev,
 243                               struct comedi_subdevice *s,
 244                               struct comedi_insn *insn, unsigned int *data);
 245 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev,
 246                                        unsigned chan);
 247
 248 static void ni_rtsi_init(struct comedi_device *dev);
 249 static int ni_rtsi_insn_bits(struct comedi_device *dev,
 250                              struct comedi_subdevice *s,
 251                              struct comedi_insn *insn, unsigned int *data);
 252 static int ni_rtsi_insn_config(struct comedi_device *dev,
 253                                struct comedi_subdevice *s,
 254                                struct comedi_insn *insn, unsigned int *data);
 255
 256 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s);
 257 static int ni_read_eeprom(struct comedi_device *dev, int addr);
 258
 259 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s);
 260 #ifndef PCIDMA
 261 static void ni_handle_fifo_half_full(struct comedi_device *dev);
 262 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
 263                                  struct comedi_subdevice *s);
 264 #endif
 265 static void ni_handle_fifo_dregs(struct comedi_device *dev);
 266 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
 267                          unsigned int trignum);
 268 static void ni_load_channelgain_list(struct comedi_device *dev,
 269                                      unsigned int n_chan, unsigned int *list);
 270 static void shutdown_ai_command(struct comedi_device *dev);
 271
 272 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
 273                          unsigned int trignum);
 274
 275 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s);
 276
 277 static int ni_8255_callback(int dir, int port, int data, unsigned long arg);
 278
 279 #ifdef PCIDMA
 280 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
 281 #endif
 282 static int ni_gpct_cancel(struct comedi_device *dev,
 283                           struct comedi_subdevice *s);
 284 static void handle_gpct_interrupt(struct comedi_device *dev,
 285                                   unsigned short counter_index);
 286
 287 static int init_cs5529(struct comedi_device *dev);
 288 static int cs5529_do_conversion(struct comedi_device *dev,
 289                                 unsigned short *data);
 290 static int cs5529_ai_insn_read(struct comedi_device *dev,
 291                                struct comedi_subdevice *s,
 292                                struct comedi_insn *insn, unsigned int *data);
 293 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
 294                                 unsigned int reg_select_bits);
 295
 296 static int ni_m_series_pwm_config(struct comedi_device *dev,
 297                                   struct comedi_subdevice *s,
 298                                   struct comedi_insn *insn, unsigned int *data);
 299 static int ni_6143_pwm_config(struct comedi_device *dev,
 300                               struct comedi_subdevice *s,
 301                               struct comedi_insn *insn, unsigned int *data);
 302
 303 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
 304                                unsigned period_ns);
 305 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status);
 306 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status);
 307
 308 enum aimodes {
 309         AIMODE_NONE = 0,
 310         AIMODE_HALF_FULL = 1,
 311         AIMODE_SCAN = 2,
 312         AIMODE_SAMPLE = 3,
 313 };
 314
 315 enum ni_common_subdevices {
 316         NI_AI_SUBDEV,
 317         NI_AO_SUBDEV,
 318         NI_DIO_SUBDEV,
 319         NI_8255_DIO_SUBDEV,
 320         NI_UNUSED_SUBDEV,
 321         NI_CALIBRATION_SUBDEV,
 322         NI_EEPROM_SUBDEV,
 323         NI_PFI_DIO_SUBDEV,
 324         NI_CS5529_CALIBRATION_SUBDEV,
 325         NI_SERIAL_SUBDEV,
 326         NI_RTSI_SUBDEV,
 327         NI_GPCT0_SUBDEV,
 328         NI_GPCT1_SUBDEV,
 329         NI_FREQ_OUT_SUBDEV,
 330         NI_NUM_SUBDEVICES
 331 };
 332 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
 333 {
 334         switch (counter_index) {
 335         case 0:
 336                 return NI_GPCT0_SUBDEV;
 337                 break;
 338         case 1:
 339                 return NI_GPCT1_SUBDEV;
 340                 break;
 341         default:
 342                 break;
 343         }
 344         BUG();
 345         return NI_GPCT0_SUBDEV;
 346 }
 347
 348 enum timebase_nanoseconds {
 349         TIMEBASE_1_NS = 50,
 350         TIMEBASE_2_NS = 10000
 351 };
 352
 353 #define SERIAL_DISABLED         0
 354 #define SERIAL_600NS            600
 355 #define SERIAL_1_2US            1200
 356 #define SERIAL_10US                     10000
 357
 358 static const int num_adc_stages_611x = 3;
 359
 360 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
 361                                unsigned ai_mite_status);
 362 static void handle_b_interrupt(struct comedi_device *dev, unsigned short status,
 363                                unsigned ao_mite_status);
 364 static void get_last_sample_611x(struct comedi_device *dev);
 365 static void get_last_sample_6143(struct comedi_device *dev);
 366
 367 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
 368                                    unsigned bit_mask, unsigned bit_values)
 369 {
 370         struct ni_private *devpriv = dev->private;
 371         unsigned long flags;
 372
 373         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 374         switch (reg) {
 375         case Interrupt_A_Enable_Register:
 376                 devpriv->int_a_enable_reg &= ~bit_mask;
 377                 devpriv->int_a_enable_reg |= bit_values & bit_mask;
 378                 devpriv->stc_writew(dev, devpriv->int_a_enable_reg,
 379                                     Interrupt_A_Enable_Register);
 380                 break;
 381         case Interrupt_B_Enable_Register:
 382                 devpriv->int_b_enable_reg &= ~bit_mask;
 383                 devpriv->int_b_enable_reg |= bit_values & bit_mask;
 384                 devpriv->stc_writew(dev, devpriv->int_b_enable_reg,
 385                                     Interrupt_B_Enable_Register);
 386                 break;
 387         case IO_Bidirection_Pin_Register:
 388                 devpriv->io_bidirection_pin_reg &= ~bit_mask;
 389                 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
 390                 devpriv->stc_writew(dev, devpriv->io_bidirection_pin_reg,
 391                                     IO_Bidirection_Pin_Register);
 392                 break;
 393         case AI_AO_Select:
 394                 devpriv->ai_ao_select_reg &= ~bit_mask;
 395                 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
 396                 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
 397                 break;
 398         case G0_G1_Select:
 399                 devpriv->g0_g1_select_reg &= ~bit_mask;
 400                 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
 401                 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
 402                 break;
 403         default:
 404                 printk("Warning %s() called with invalid register\n", __func__);
 405                 printk("reg is %d\n", reg);
 406                 break;
 407         }
 408         mmiowb();
 409         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 410 }
 411
 412 #ifdef PCIDMA
 413 static int ni_ai_drain_dma(struct comedi_device *dev);
 414
 415 /* DMA channel setup */
 416
 417 /* negative channel means no channel */
 418 static inline void ni_set_ai_dma_channel(struct comedi_device *dev, int channel)
 419 {
 420         unsigned bitfield;
 421
 422         if (channel >= 0) {
 423                 bitfield =
 424                     (ni_stc_dma_channel_select_bitfield(channel) <<
 425                      AI_DMA_Select_Shift) & AI_DMA_Select_Mask;
 426         } else {
 427                 bitfield = 0;
 428         }
 429         ni_set_bitfield(dev, AI_AO_Select, AI_DMA_Select_Mask, bitfield);
 430 }
 431
 432 /* negative channel means no channel */
 433 static inline void ni_set_ao_dma_channel(struct comedi_device *dev, int channel)
 434 {
 435         unsigned bitfield;
 436
 437         if (channel >= 0) {
 438                 bitfield =
 439                     (ni_stc_dma_channel_select_bitfield(channel) <<
 440                      AO_DMA_Select_Shift) & AO_DMA_Select_Mask;
 441         } else {
 442                 bitfield = 0;
 443         }
 444         ni_set_bitfield(dev, AI_AO_Select, AO_DMA_Select_Mask, bitfield);
 445 }
 446
 447 /* negative mite_channel means no channel */
 448 static inline void ni_set_gpct_dma_channel(struct comedi_device *dev,
 449                                            unsigned gpct_index,
 450                                            int mite_channel)
 451 {
 452         unsigned bitfield;
 453
 454         if (mite_channel >= 0) {
 455                 bitfield = GPCT_DMA_Select_Bits(gpct_index, mite_channel);
 456         } else {
 457                 bitfield = 0;
 458         }
 459         ni_set_bitfield(dev, G0_G1_Select, GPCT_DMA_Select_Mask(gpct_index),
 460                         bitfield);
 461 }
 462
 463 /* negative mite_channel means no channel */
 464 static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
 465                                           int mite_channel)
 466 {
 467         struct ni_private *devpriv = dev->private;
 468         unsigned long flags;
 469
 470         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 471         devpriv->cdio_dma_select_reg &= ~CDO_DMA_Select_Mask;
 472         if (mite_channel >= 0) {
 473                 /*XXX just guessing ni_stc_dma_channel_select_bitfield() returns the right bits,
 474                    under the assumption the cdio dma selection works just like ai/ao/gpct.
 475                    Definitely works for dma channels 0 and 1. */
 476                 devpriv->cdio_dma_select_reg |=
 477                     (ni_stc_dma_channel_select_bitfield(mite_channel) <<
 478                      CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask;
 479         }
 480         ni_writeb(devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select);
 481         mmiowb();
 482         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 483 }
 484
 485 static int ni_request_ai_mite_channel(struct comedi_device *dev)
 486 {
 487         struct ni_private *devpriv = dev->private;
 488         unsigned long flags;
 489
 490         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 491         BUG_ON(devpriv->ai_mite_chan);
 492         devpriv->ai_mite_chan =
 493             mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
 494         if (devpriv->ai_mite_chan == NULL) {
 495                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 496                 comedi_error(dev,
 497                              "failed to reserve mite dma channel for analog input.");
 498                 return -EBUSY;
 499         }
 500         devpriv->ai_mite_chan->dir = COMEDI_INPUT;
 501         ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
 502         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 503         return 0;
 504 }
 505
 506 static int ni_request_ao_mite_channel(struct comedi_device *dev)
 507 {
 508         struct ni_private *devpriv = dev->private;
 509         unsigned long flags;
 510
 511         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 512         BUG_ON(devpriv->ao_mite_chan);
 513         devpriv->ao_mite_chan =
 514             mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
 515         if (devpriv->ao_mite_chan == NULL) {
 516                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 517                 comedi_error(dev,
 518                              "failed to reserve mite dma channel for analog outut.");
 519                 return -EBUSY;
 520         }
 521         devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
 522         ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
 523         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 524         return 0;
 525 }
 526
 527 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
 528                                         unsigned gpct_index,
 529                                         enum comedi_io_direction direction)
 530 {
 531         struct ni_private *devpriv = dev->private;
 532         unsigned long flags;
 533         struct mite_channel *mite_chan;
 534
 535         BUG_ON(gpct_index >= NUM_GPCT);
 536         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 537         BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
 538         mite_chan =
 539             mite_request_channel(devpriv->mite,
 540                                  devpriv->gpct_mite_ring[gpct_index]);
 541         if (mite_chan == NULL) {
 542                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 543                 comedi_error(dev,
 544                              "failed to reserve mite dma channel for counter.");
 545                 return -EBUSY;
 546         }
 547         mite_chan->dir = direction;
 548         ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
 549                                 mite_chan);
 550         ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
 551         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 552         return 0;
 553 }
 554
 555 #endif /*  PCIDMA */
 556
 557 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
 558 {
 559 #ifdef PCIDMA
 560         struct ni_private *devpriv = dev->private;
 561         unsigned long flags;
 562
 563         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 564         BUG_ON(devpriv->cdo_mite_chan);
 565         devpriv->cdo_mite_chan =
 566             mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
 567         if (devpriv->cdo_mite_chan == NULL) {
 568                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 569                 comedi_error(dev,
 570                              "failed to reserve mite dma channel for correlated digital outut.");
 571                 return -EBUSY;
 572         }
 573         devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
 574         ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
 575         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 576 #endif /*  PCIDMA */
 577         return 0;
 578 }
 579
 580 static void ni_release_ai_mite_channel(struct comedi_device *dev)
 581 {
 582 #ifdef PCIDMA
 583         struct ni_private *devpriv = dev->private;
 584         unsigned long flags;
 585
 586         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 587         if (devpriv->ai_mite_chan) {
 588                 ni_set_ai_dma_channel(dev, -1);
 589                 mite_release_channel(devpriv->ai_mite_chan);
 590                 devpriv->ai_mite_chan = NULL;
 591         }
 592         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 593 #endif /*  PCIDMA */
 594 }
 595
 596 static void ni_release_ao_mite_channel(struct comedi_device *dev)
 597 {
 598 #ifdef PCIDMA
 599         struct ni_private *devpriv = dev->private;
 600         unsigned long flags;
 601
 602         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 603         if (devpriv->ao_mite_chan) {
 604                 ni_set_ao_dma_channel(dev, -1);
 605                 mite_release_channel(devpriv->ao_mite_chan);
 606                 devpriv->ao_mite_chan = NULL;
 607         }
 608         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 609 #endif /*  PCIDMA */
 610 }
 611
 612 #ifdef PCIDMA
 613 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
 614                                          unsigned gpct_index)
 615 {
 616         struct ni_private *devpriv = dev->private;
 617         unsigned long flags;
 618
 619         BUG_ON(gpct_index >= NUM_GPCT);
 620         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 621         if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
 622                 struct mite_channel *mite_chan =
 623                     devpriv->counter_dev->counters[gpct_index].mite_chan;
 624
 625                 ni_set_gpct_dma_channel(dev, gpct_index, -1);
 626                 ni_tio_set_mite_channel(&devpriv->
 627                                         counter_dev->counters[gpct_index],
 628                                         NULL);
 629                 mite_release_channel(mite_chan);
 630         }
 631         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 632 }
 633 #endif /*  PCIDMA */
 634
 635 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
 636 {
 637 #ifdef PCIDMA
 638         struct ni_private *devpriv = dev->private;
 639         unsigned long flags;
 640
 641         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 642         if (devpriv->cdo_mite_chan) {
 643                 ni_set_cdo_dma_channel(dev, -1);
 644                 mite_release_channel(devpriv->cdo_mite_chan);
 645                 devpriv->cdo_mite_chan = NULL;
 646         }
 647         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 648 #endif /*  PCIDMA */
 649 }
 650
 651 /* e-series boards use the second irq signals to generate dma requests for their counters */
 652 #ifdef PCIDMA
 653 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
 654                                           unsigned gpct_index, short enable)
 655 {
 656         const struct ni_board_struct *board = comedi_board(dev);
 657         struct ni_private *devpriv = dev->private;
 658
 659         if (board->reg_type & ni_reg_m_series_mask)
 660                 return;
 661         switch (gpct_index) {
 662         case 0:
 663                 if (enable) {
 664                         devpriv->stc_writew(dev, G0_Gate_Second_Irq_Enable,
 665                                             Second_IRQ_A_Enable_Register);
 666                 } else {
 667                         devpriv->stc_writew(dev, 0,
 668                                             Second_IRQ_A_Enable_Register);
 669                 }
 670                 break;
 671         case 1:
 672                 if (enable) {
 673                         devpriv->stc_writew(dev, G1_Gate_Second_Irq_Enable,
 674                                             Second_IRQ_B_Enable_Register);
 675                 } else {
 676                         devpriv->stc_writew(dev, 0,
 677                                             Second_IRQ_B_Enable_Register);
 678                 }
 679                 break;
 680         default:
 681                 BUG();
 682                 break;
 683         }
 684 }
 685 #endif /*  PCIDMA */
 686
 687 static void ni_clear_ai_fifo(struct comedi_device *dev)
 688 {
 689         const struct ni_board_struct *board = comedi_board(dev);
 690         struct ni_private *devpriv = dev->private;
 691
 692         if (board->reg_type == ni_reg_6143) {
 693                 /*  Flush the 6143 data FIFO */
 694                 ni_writel(0x10, AIFIFO_Control_6143);   /*  Flush fifo */
 695                 ni_writel(0x00, AIFIFO_Control_6143);   /*  Flush fifo */
 696                 while (ni_readl(AIFIFO_Status_6143) & 0x10) ;   /*  Wait for complete */
 697         } else {
 698                 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
 699                 if (board->reg_type == ni_reg_625x) {
 700                         ni_writeb(0, M_Offset_Static_AI_Control(0));
 701                         ni_writeb(1, M_Offset_Static_AI_Control(0));
 702 #if 0
 703                         /* the NI example code does 3 convert pulses for 625x boards,
 704                            but that appears to be wrong in practice. */
 705                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
 706                                             AI_Command_1_Register);
 707                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
 708                                             AI_Command_1_Register);
 709                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
 710                                             AI_Command_1_Register);
 711 #endif
 712                 }
 713         }
 714 }
 715
 716 static void win_out2(struct comedi_device *dev, uint32_t data, int reg)
 717 {
 718         struct ni_private *devpriv = dev->private;
 719
 720         devpriv->stc_writew(dev, data >> 16, reg);
 721         devpriv->stc_writew(dev, data & 0xffff, reg + 1);
 722 }
 723
 724 static uint32_t win_in2(struct comedi_device *dev, int reg)
 725 {
 726         struct ni_private *devpriv = dev->private;
 727         uint32_t bits;
 728
 729         bits = devpriv->stc_readw(dev, reg) << 16;
 730         bits |= devpriv->stc_readw(dev, reg + 1);
 731         return bits;
 732 }
 733
 734 #define ao_win_out(data, addr) ni_ao_win_outw(dev, data, addr)
 735 static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data,
 736                                   int addr)
 737 {
 738         struct ni_private *devpriv = dev->private;
 739         unsigned long flags;
 740
 741         spin_lock_irqsave(&devpriv->window_lock, flags);
 742         ni_writew(addr, AO_Window_Address_611x);
 743         ni_writew(data, AO_Window_Data_611x);
 744         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 745 }
 746
 747 static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data,
 748                                   int addr)
 749 {
 750         struct ni_private *devpriv = dev->private;
 751         unsigned long flags;
 752
 753         spin_lock_irqsave(&devpriv->window_lock, flags);
 754         ni_writew(addr, AO_Window_Address_611x);
 755         ni_writel(data, AO_Window_Data_611x);
 756         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 757 }
 758
 759 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
 760 {
 761         struct ni_private *devpriv = dev->private;
 762         unsigned long flags;
 763         unsigned short data;
 764
 765         spin_lock_irqsave(&devpriv->window_lock, flags);
 766         ni_writew(addr, AO_Window_Address_611x);
 767         data = ni_readw(AO_Window_Data_611x);
 768         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 769         return data;
 770 }
 771
 772 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
 773 * share registers (such as Interrupt_A_Register) without interfering with
 774 * each other.
 775 *
 776 * NOTE: the switch/case statements are optimized out for a constant argument
 777 * so this is actually quite fast---  If you must wrap another function around this
 778 * make it inline to avoid a large speed penalty.
 779 *
 780 * value should only be 1 or 0.
 781 */
 782 static inline void ni_set_bits(struct comedi_device *dev, int reg,
 783                                unsigned bits, unsigned value)
 784 {
 785         unsigned bit_values;
 786
 787         if (value)
 788                 bit_values = bits;
 789         else
 790                 bit_values = 0;
 791         ni_set_bitfield(dev, reg, bits, bit_values);
 792 }
 793
 794 static irqreturn_t ni_E_interrupt(int irq, void *d)
 795 {
 796         struct comedi_device *dev = d;
 797         struct ni_private *devpriv = dev->private;
 798         unsigned short a_status;
 799         unsigned short b_status;
 800         unsigned int ai_mite_status = 0;
 801         unsigned int ao_mite_status = 0;
 802         unsigned long flags;
 803 #ifdef PCIDMA
 804         struct mite_struct *mite = devpriv->mite;
 805 #endif
 806
 807         if (!dev->attached)
 808                 return IRQ_NONE;
 809         smp_mb();               /*  make sure dev->attached is checked before handler does anything else. */
 810
 811         /*  lock to avoid race with comedi_poll */
 812         spin_lock_irqsave(&dev->spinlock, flags);
 813         a_status = devpriv->stc_readw(dev, AI_Status_1_Register);
 814         b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
 815 #ifdef PCIDMA
 816         if (mite) {
 817                 unsigned long flags_too;
 818
 819                 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
 820                 if (devpriv->ai_mite_chan) {
 821                         ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
 822                         if (ai_mite_status & CHSR_LINKC)
 823                                 writel(CHOR_CLRLC,
 824                                        devpriv->mite->mite_io_addr +
 825                                        MITE_CHOR(devpriv->
 826                                                  ai_mite_chan->channel));
 827                 }
 828                 if (devpriv->ao_mite_chan) {
 829                         ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
 830                         if (ao_mite_status & CHSR_LINKC)
 831                                 writel(CHOR_CLRLC,
 832                                        mite->mite_io_addr +
 833                                        MITE_CHOR(devpriv->
 834                                                  ao_mite_chan->channel));
 835                 }
 836                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
 837         }
 838 #endif
 839         ack_a_interrupt(dev, a_status);
 840         ack_b_interrupt(dev, b_status);
 841         if ((a_status & Interrupt_A_St) || (ai_mite_status & CHSR_INT))
 842                 handle_a_interrupt(dev, a_status, ai_mite_status);
 843         if ((b_status & Interrupt_B_St) || (ao_mite_status & CHSR_INT))
 844                 handle_b_interrupt(dev, b_status, ao_mite_status);
 845         handle_gpct_interrupt(dev, 0);
 846         handle_gpct_interrupt(dev, 1);
 847         handle_cdio_interrupt(dev);
 848
 849         spin_unlock_irqrestore(&dev->spinlock, flags);
 850         return IRQ_HANDLED;
 851 }
 852
 853 #ifdef PCIDMA
 854 static void ni_sync_ai_dma(struct comedi_device *dev)
 855 {
 856         struct ni_private *devpriv = dev->private;
 857         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
 858         unsigned long flags;
 859
 860         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 861         if (devpriv->ai_mite_chan)
 862                 mite_sync_input_dma(devpriv->ai_mite_chan, s->async);
 863         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 864 }
 865
 866 static void mite_handle_b_linkc(struct mite_struct *mite,
 867                                 struct comedi_device *dev)
 868 {
 869         struct ni_private *devpriv = dev->private;
 870         struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
 871         unsigned long flags;
 872
 873         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 874         if (devpriv->ao_mite_chan) {
 875                 mite_sync_output_dma(devpriv->ao_mite_chan, s->async);
 876         }
 877         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 878 }
 879
 880 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
 881 {
 882         struct ni_private *devpriv = dev->private;
 883         static const int timeout = 10000;
 884         int i;
 885         for (i = 0; i < timeout; i++) {
 886                 unsigned short b_status;
 887
 888                 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
 889                 if (b_status & AO_FIFO_Half_Full_St)
 890                         break;
 891                 /* if we poll too often, the pci bus activity seems
 892                    to slow the dma transfer down */
 893                 udelay(10);
 894         }
 895         if (i == timeout) {
 896                 comedi_error(dev, "timed out waiting for dma load");
 897                 return -EPIPE;
 898         }
 899         return 0;
 900 }
 901
 902 #endif /* PCIDMA */
 903 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
 904 {
 905         struct ni_private *devpriv = dev->private;
 906
 907         if (devpriv->aimode == AIMODE_SCAN) {
 908 #ifdef PCIDMA
 909                 static const int timeout = 10;
 910                 int i;
 911
 912                 for (i = 0; i < timeout; i++) {
 913                         ni_sync_ai_dma(dev);
 914                         if ((s->async->events & COMEDI_CB_EOS))
 915                                 break;
 916                         udelay(1);
 917                 }
 918 #else
 919                 ni_handle_fifo_dregs(dev);
 920                 s->async->events |= COMEDI_CB_EOS;
 921 #endif
 922         }
 923         /* handle special case of single scan using AI_End_On_End_Of_Scan */
 924         if ((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
 925                 shutdown_ai_command(dev);
 926         }
 927 }
 928
 929 static void shutdown_ai_command(struct comedi_device *dev)
 930 {
 931         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
 932
 933 #ifdef PCIDMA
 934         ni_ai_drain_dma(dev);
 935 #endif
 936         ni_handle_fifo_dregs(dev);
 937         get_last_sample_611x(dev);
 938         get_last_sample_6143(dev);
 939
 940         s->async->events |= COMEDI_CB_EOA;
 941 }
 942
 943 static void ni_event(struct comedi_device *dev, struct comedi_subdevice *s)
 944 {
 945         if (s->
 946             async->events & (COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW |
 947                              COMEDI_CB_EOA)) {
 948                 switch (s->index) {
 949                 case NI_AI_SUBDEV:
 950                         ni_ai_reset(dev, s);
 951                         break;
 952                 case NI_AO_SUBDEV:
 953                         ni_ao_reset(dev, s);
 954                         break;
 955                 case NI_GPCT0_SUBDEV:
 956                 case NI_GPCT1_SUBDEV:
 957                         ni_gpct_cancel(dev, s);
 958                         break;
 959                 case NI_DIO_SUBDEV:
 960                         ni_cdio_cancel(dev, s);
 961                         break;
 962                 default:
 963                         break;
 964                 }
 965         }
 966         comedi_event(dev, s);
 967 }
 968
 969 static void handle_gpct_interrupt(struct comedi_device *dev,
 970                                   unsigned short counter_index)
 971 {
 972 #ifdef PCIDMA
 973         struct ni_private *devpriv = dev->private;
 974         struct comedi_subdevice *s;
 975
 976         s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
 977
 978         ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
 979                                 s);
 980         if (s->async->events)
 981                 ni_event(dev, s);
 982 #endif
 983 }
 984
 985 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
 986 {
 987         struct ni_private *devpriv = dev->private;
 988         unsigned short ack = 0;
 989
 990         if (a_status & AI_SC_TC_St) {
 991                 ack |= AI_SC_TC_Interrupt_Ack;
 992         }
 993         if (a_status & AI_START1_St) {
 994                 ack |= AI_START1_Interrupt_Ack;
 995         }
 996         if (a_status & AI_START_St) {
 997                 ack |= AI_START_Interrupt_Ack;
 998         }
 999         if (a_status & AI_STOP_St) {
1000                 /* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */
1001                 ack |= AI_STOP_Interrupt_Ack /*| AI_START_Interrupt_Ack */ ;
1002         }
1003         if (ack)
1004                 devpriv->stc_writew(dev, ack, Interrupt_A_Ack_Register);
1005 }
1006
1007 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
1008                                unsigned ai_mite_status)
1009 {
1010         struct ni_private *devpriv = dev->private;
1011         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1012
1013         /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */
1014         if (s->type == COMEDI_SUBD_UNUSED)
1015                 return;
1016
1017 #ifdef PCIDMA
1018         if (ai_mite_status & CHSR_LINKC) {
1019                 ni_sync_ai_dma(dev);
1020         }
1021
1022         if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1023                                CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1024                                CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1025                 printk
1026                     ("unknown mite interrupt, ack! (ai_mite_status=%08x)\n",
1027                      ai_mite_status);
1028                 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1029                 /* disable_irq(dev->irq); */
1030         }
1031 #endif
1032
1033         /* test for all uncommon interrupt events at the same time */
1034         if (status & (AI_Overrun_St | AI_Overflow_St | AI_SC_TC_Error_St |
1035                       AI_SC_TC_St | AI_START1_St)) {
1036                 if (status == 0xffff) {
1037                         printk
1038                             ("ni_mio_common: a_status=0xffff.  Card removed?\n");
1039                         /* we probably aren't even running a command now,
1040                          * so it's a good idea to be careful. */
1041                         if (comedi_is_subdevice_running(s)) {
1042                                 s->async->events |=
1043                                     COMEDI_CB_ERROR | COMEDI_CB_EOA;
1044                                 ni_event(dev, s);
1045                         }
1046                         return;
1047                 }
1048                 if (status & (AI_Overrun_St | AI_Overflow_St |
1049                               AI_SC_TC_Error_St)) {
1050                         printk("ni_mio_common: ai error a_status=%04x\n",
1051                                status);
1052
1053                         shutdown_ai_command(dev);
1054
1055                         s->async->events |= COMEDI_CB_ERROR;
1056                         if (status & (AI_Overrun_St | AI_Overflow_St))
1057                                 s->async->events |= COMEDI_CB_OVERFLOW;
1058
1059                         ni_event(dev, s);
1060
1061                         return;
1062                 }
1063                 if (status & AI_SC_TC_St) {
1064                         if (!devpriv->ai_continuous) {
1065                                 shutdown_ai_command(dev);
1066                         }
1067                 }
1068         }
1069 #ifndef PCIDMA
1070         if (status & AI_FIFO_Half_Full_St) {
1071                 int i;
1072                 static const int timeout = 10;
1073                 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1074                  *fail to get the fifo less than half full, so loop to be sure.*/
1075                 for (i = 0; i < timeout; ++i) {
1076                         ni_handle_fifo_half_full(dev);
1077                         if ((devpriv->stc_readw(dev,
1078                                                 AI_Status_1_Register) &
1079                              AI_FIFO_Half_Full_St) == 0)
1080                                 break;
1081                 }
1082         }
1083 #endif /*  !PCIDMA */
1084
1085         if ((status & AI_STOP_St)) {
1086                 ni_handle_eos(dev, s);
1087         }
1088
1089         ni_event(dev, s);
1090 }
1091
1092 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1093 {
1094         struct ni_private *devpriv = dev->private;
1095         unsigned short ack = 0;
1096
1097         if (b_status & AO_BC_TC_St) {
1098                 ack |= AO_BC_TC_Interrupt_Ack;
1099         }
1100         if (b_status & AO_Overrun_St) {
1101                 ack |= AO_Error_Interrupt_Ack;
1102         }
1103         if (b_status & AO_START_St) {
1104                 ack |= AO_START_Interrupt_Ack;
1105         }
1106         if (b_status & AO_START1_St) {
1107                 ack |= AO_START1_Interrupt_Ack;
1108         }
1109         if (b_status & AO_UC_TC_St) {
1110                 ack |= AO_UC_TC_Interrupt_Ack;
1111         }
1112         if (b_status & AO_UI2_TC_St) {
1113                 ack |= AO_UI2_TC_Interrupt_Ack;
1114         }
1115         if (b_status & AO_UPDATE_St) {
1116                 ack |= AO_UPDATE_Interrupt_Ack;
1117         }
1118         if (ack)
1119                 devpriv->stc_writew(dev, ack, Interrupt_B_Ack_Register);
1120 }
1121
1122 static void handle_b_interrupt(struct comedi_device *dev,
1123                                unsigned short b_status, unsigned ao_mite_status)
1124 {
1125         struct ni_private *devpriv = dev->private;
1126         struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
1127         /* unsigned short ack=0; */
1128
1129 #ifdef PCIDMA
1130         /* Currently, mite.c requires us to handle LINKC */
1131         if (ao_mite_status & CHSR_LINKC) {
1132                 mite_handle_b_linkc(devpriv->mite, dev);
1133         }
1134
1135         if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1136                                CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1137                                CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1138                 printk
1139                     ("unknown mite interrupt, ack! (ao_mite_status=%08x)\n",
1140                      ao_mite_status);
1141                 s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1142         }
1143 #endif
1144
1145         if (b_status == 0xffff)
1146                 return;
1147         if (b_status & AO_Overrun_St) {
1148                 printk
1149                     ("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n",
1150                      b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1151                 s->async->events |= COMEDI_CB_OVERFLOW;
1152         }
1153
1154         if (b_status & AO_BC_TC_St)
1155                 s->async->events |= COMEDI_CB_EOA;
1156
1157 #ifndef PCIDMA
1158         if (b_status & AO_FIFO_Request_St) {
1159                 int ret;
1160
1161                 ret = ni_ao_fifo_half_empty(dev, s);
1162                 if (!ret) {
1163                         printk("ni_mio_common: AO buffer underrun\n");
1164                         ni_set_bits(dev, Interrupt_B_Enable_Register,
1165                                     AO_FIFO_Interrupt_Enable |
1166                                     AO_Error_Interrupt_Enable, 0);
1167                         s->async->events |= COMEDI_CB_OVERFLOW;
1168                 }
1169         }
1170 #endif
1171
1172         ni_event(dev, s);
1173 }
1174
1175 #ifndef PCIDMA
1176
1177 static void ni_ao_fifo_load(struct comedi_device *dev,
1178                             struct comedi_subdevice *s, int n)
1179 {
1180         const struct ni_board_struct *board = comedi_board(dev);
1181         struct comedi_async *async = s->async;
1182         struct comedi_cmd *cmd = &async->cmd;
1183         int chan;
1184         int i;
1185         unsigned short d;
1186         u32 packed_data;
1187         int range;
1188         int err = 1;
1189
1190         chan = async->cur_chan;
1191         for (i = 0; i < n; i++) {
1192                 err &= comedi_buf_get(async, &d);
1193                 if (err == 0)
1194                         break;
1195
1196                 range = CR_RANGE(cmd->chanlist[chan]);
1197
1198                 if (board->reg_type & ni_reg_6xxx_mask) {
1199                         packed_data = d & 0xffff;
1200                         /* 6711 only has 16 bit wide ao fifo */
1201                         if (board->reg_type != ni_reg_6711) {
1202                                 err &= comedi_buf_get(async, &d);
1203                                 if (err == 0)
1204                                         break;
1205                                 chan++;
1206                                 i++;
1207                                 packed_data |= (d << 16) & 0xffff0000;
1208                         }
1209                         ni_writel(packed_data, DAC_FIFO_Data_611x);
1210                 } else {
1211                         ni_writew(d, DAC_FIFO_Data);
1212                 }
1213                 chan++;
1214                 chan %= cmd->chanlist_len;
1215         }
1216         async->cur_chan = chan;
1217         if (err == 0) {
1218                 async->events |= COMEDI_CB_OVERFLOW;
1219         }
1220 }
1221
1222 /*
1223  *  There's a small problem if the FIFO gets really low and we
1224  *  don't have the data to fill it.  Basically, if after we fill
1225  *  the FIFO with all the data available, the FIFO is _still_
1226  *  less than half full, we never clear the interrupt.  If the
1227  *  IRQ is in edge mode, we never get another interrupt, because
1228  *  this one wasn't cleared.  If in level mode, we get flooded
1229  *  with interrupts that we can't fulfill, because nothing ever
1230  *  gets put into the buffer.
1231  *
1232  *  This kind of situation is recoverable, but it is easier to
1233  *  just pretend we had a FIFO underrun, since there is a good
1234  *  chance it will happen anyway.  This is _not_ the case for
1235  *  RT code, as RT code might purposely be running close to the
1236  *  metal.  Needs to be fixed eventually.
1237  */
1238 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1239                                  struct comedi_subdevice *s)
1240 {
1241         const struct ni_board_struct *board = comedi_board(dev);
1242         int n;
1243
1244         n = comedi_buf_read_n_available(s->async);
1245         if (n == 0) {
1246                 s->async->events |= COMEDI_CB_OVERFLOW;
1247                 return 0;
1248         }
1249
1250         n /= sizeof(short);
1251         if (n > board->ao_fifo_depth / 2)
1252                 n = board->ao_fifo_depth / 2;
1253
1254         ni_ao_fifo_load(dev, s, n);
1255
1256         s->async->events |= COMEDI_CB_BLOCK;
1257
1258         return 1;
1259 }
1260
1261 static int ni_ao_prep_fifo(struct comedi_device *dev,
1262                            struct comedi_subdevice *s)
1263 {
1264         const struct ni_board_struct *board = comedi_board(dev);
1265         struct ni_private *devpriv = dev->private;
1266         int n;
1267
1268         /* reset fifo */
1269         devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
1270         if (board->reg_type & ni_reg_6xxx_mask)
1271                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
1272
1273         /* load some data */
1274         n = comedi_buf_read_n_available(s->async);
1275         if (n == 0)
1276                 return 0;
1277
1278         n /= sizeof(short);
1279         if (n > board->ao_fifo_depth)
1280                 n = board->ao_fifo_depth;
1281
1282         ni_ao_fifo_load(dev, s, n);
1283
1284         return n;
1285 }
1286
1287 static void ni_ai_fifo_read(struct comedi_device *dev,
1288                             struct comedi_subdevice *s, int n)
1289 {
1290         const struct ni_board_struct *board = comedi_board(dev);
1291         struct ni_private *devpriv = dev->private;
1292         struct comedi_async *async = s->async;
1293         int i;
1294
1295         if (board->reg_type == ni_reg_611x) {
1296                 unsigned short data[2];
1297                 u32 dl;
1298
1299                 for (i = 0; i < n / 2; i++) {
1300                         dl = ni_readl(ADC_FIFO_Data_611x);
1301                         /* This may get the hi/lo data in the wrong order */
1302                         data[0] = (dl >> 16) & 0xffff;
1303                         data[1] = dl & 0xffff;
1304                         cfc_write_array_to_buffer(s, data, sizeof(data));
1305                 }
1306                 /* Check if there's a single sample stuck in the FIFO */
1307                 if (n % 2) {
1308                         dl = ni_readl(ADC_FIFO_Data_611x);
1309                         data[0] = dl & 0xffff;
1310                         cfc_write_to_buffer(s, data[0]);
1311                 }
1312         } else if (board->reg_type == ni_reg_6143) {
1313                 unsigned short data[2];
1314                 u32 dl;
1315
1316                 /*  This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
1317                 for (i = 0; i < n / 2; i++) {
1318                         dl = ni_readl(AIFIFO_Data_6143);
1319
1320                         data[0] = (dl >> 16) & 0xffff;
1321                         data[1] = dl & 0xffff;
1322                         cfc_write_array_to_buffer(s, data, sizeof(data));
1323                 }
1324                 if (n % 2) {
1325                         /* Assume there is a single sample stuck in the FIFO */
1326                         ni_writel(0x01, AIFIFO_Control_6143);   /*  Get stranded sample into FIFO */
1327                         dl = ni_readl(AIFIFO_Data_6143);
1328                         data[0] = (dl >> 16) & 0xffff;
1329                         cfc_write_to_buffer(s, data[0]);
1330                 }
1331         } else {
1332                 if (n > sizeof(devpriv->ai_fifo_buffer) /
1333                     sizeof(devpriv->ai_fifo_buffer[0])) {
1334                         comedi_error(dev, "bug! ai_fifo_buffer too small");
1335                         async->events |= COMEDI_CB_ERROR;
1336                         return;
1337                 }
1338                 for (i = 0; i < n; i++) {
1339                         devpriv->ai_fifo_buffer[i] =
1340                             ni_readw(ADC_FIFO_Data_Register);
1341                 }
1342                 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1343                                           n *
1344                                           sizeof(devpriv->ai_fifo_buffer[0]));
1345         }
1346 }
1347
1348 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1349 {
1350         const struct ni_board_struct *board = comedi_board(dev);
1351         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1352         int n;
1353
1354         n = board->ai_fifo_depth / 2;
1355
1356         ni_ai_fifo_read(dev, s, n);
1357 }
1358 #endif
1359
1360 #ifdef PCIDMA
1361 static int ni_ai_drain_dma(struct comedi_device *dev)
1362 {
1363         struct ni_private *devpriv = dev->private;
1364         int i;
1365         static const int timeout = 10000;
1366         unsigned long flags;
1367         int retval = 0;
1368
1369         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1370         if (devpriv->ai_mite_chan) {
1371                 for (i = 0; i < timeout; i++) {
1372                         if ((devpriv->stc_readw(dev,
1373                                                 AI_Status_1_Register) &
1374                              AI_FIFO_Empty_St)
1375                             && mite_bytes_in_transit(devpriv->ai_mite_chan) ==
1376                             0)
1377                                 break;
1378                         udelay(5);
1379                 }
1380                 if (i == timeout) {
1381                         printk("ni_mio_common: wait for dma drain timed out\n");
1382                         printk
1383                             ("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
1384                              mite_bytes_in_transit(devpriv->ai_mite_chan),
1385                              devpriv->stc_readw(dev, AI_Status_1_Register));
1386                         retval = -1;
1387                 }
1388         }
1389         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1390
1391         ni_sync_ai_dma(dev);
1392
1393         return retval;
1394 }
1395 #endif
1396 /*
1397    Empties the AI fifo
1398 */
1399 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1400 {
1401         const struct ni_board_struct *board = comedi_board(dev);
1402         struct ni_private *devpriv = dev->private;
1403         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1404         unsigned short data[2];
1405         u32 dl;
1406         unsigned short fifo_empty;
1407         int i;
1408
1409         if (board->reg_type == ni_reg_611x) {
1410                 while ((devpriv->stc_readw(dev,
1411                                            AI_Status_1_Register) &
1412                         AI_FIFO_Empty_St) == 0) {
1413                         dl = ni_readl(ADC_FIFO_Data_611x);
1414
1415                         /* This may get the hi/lo data in the wrong order */
1416                         data[0] = (dl >> 16);
1417                         data[1] = (dl & 0xffff);
1418                         cfc_write_array_to_buffer(s, data, sizeof(data));
1419                 }
1420         } else if (board->reg_type == ni_reg_6143) {
1421                 i = 0;
1422                 while (ni_readl(AIFIFO_Status_6143) & 0x04) {
1423                         dl = ni_readl(AIFIFO_Data_6143);
1424
1425                         /* This may get the hi/lo data in the wrong order */
1426                         data[0] = (dl >> 16);
1427                         data[1] = (dl & 0xffff);
1428                         cfc_write_array_to_buffer(s, data, sizeof(data));
1429                         i += 2;
1430                 }
1431                 /*  Check if stranded sample is present */
1432                 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1433                         ni_writel(0x01, AIFIFO_Control_6143);   /*  Get stranded sample into FIFO */
1434                         dl = ni_readl(AIFIFO_Data_6143);
1435                         data[0] = (dl >> 16) & 0xffff;
1436                         cfc_write_to_buffer(s, data[0]);
1437                 }
1438
1439         } else {
1440                 fifo_empty =
1441                     devpriv->stc_readw(dev,
1442                                        AI_Status_1_Register) & AI_FIFO_Empty_St;
1443                 while (fifo_empty == 0) {
1444                         for (i = 0;
1445                              i <
1446                              sizeof(devpriv->ai_fifo_buffer) /
1447                              sizeof(devpriv->ai_fifo_buffer[0]); i++) {
1448                                 fifo_empty =
1449                                     devpriv->stc_readw(dev,
1450                                                        AI_Status_1_Register) &
1451                                     AI_FIFO_Empty_St;
1452                                 if (fifo_empty)
1453                                         break;
1454                                 devpriv->ai_fifo_buffer[i] =
1455                                     ni_readw(ADC_FIFO_Data_Register);
1456                         }
1457                         cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1458                                                   i *
1459                                                   sizeof(devpriv->
1460                                                          ai_fifo_buffer[0]));
1461                 }
1462         }
1463 }
1464
1465 static void get_last_sample_611x(struct comedi_device *dev)
1466 {
1467         const struct ni_board_struct *board = comedi_board(dev);
1468         struct ni_private *devpriv __maybe_unused = dev->private;
1469         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1470         unsigned short data;
1471         u32 dl;
1472
1473         if (board->reg_type != ni_reg_611x)
1474                 return;
1475
1476         /* Check if there's a single sample stuck in the FIFO */
1477         if (ni_readb(XXX_Status) & 0x80) {
1478                 dl = ni_readl(ADC_FIFO_Data_611x);
1479                 data = (dl & 0xffff);
1480                 cfc_write_to_buffer(s, data);
1481         }
1482 }
1483
1484 static void get_last_sample_6143(struct comedi_device *dev)
1485 {
1486         const struct ni_board_struct *board = comedi_board(dev);
1487         struct ni_private *devpriv __maybe_unused = dev->private;
1488         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1489         unsigned short data;
1490         u32 dl;
1491
1492         if (board->reg_type != ni_reg_6143)
1493                 return;
1494
1495         /* Check if there's a single sample stuck in the FIFO */
1496         if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1497                 ni_writel(0x01, AIFIFO_Control_6143);   /*  Get stranded sample into FIFO */
1498                 dl = ni_readl(AIFIFO_Data_6143);
1499
1500                 /* This may get the hi/lo data in the wrong order */
1501                 data = (dl >> 16) & 0xffff;
1502                 cfc_write_to_buffer(s, data);
1503         }
1504 }
1505
1506 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1507                         void *data, unsigned int num_bytes,
1508                         unsigned int chan_index)
1509 {
1510         struct ni_private *devpriv = dev->private;
1511         struct comedi_async *async = s->async;
1512         unsigned int i;
1513         unsigned int length = num_bytes / bytes_per_sample(s);
1514         unsigned short *array = data;
1515         unsigned int *larray = data;
1516
1517         for (i = 0; i < length; i++) {
1518 #ifdef PCIDMA
1519                 if (s->subdev_flags & SDF_LSAMPL)
1520                         larray[i] = le32_to_cpu(larray[i]);
1521                 else
1522                         array[i] = le16_to_cpu(array[i]);
1523 #endif
1524                 if (s->subdev_flags & SDF_LSAMPL)
1525                         larray[i] += devpriv->ai_offset[chan_index];
1526                 else
1527                         array[i] += devpriv->ai_offset[chan_index];
1528                 chan_index++;
1529                 chan_index %= async->cmd.chanlist_len;
1530         }
1531 }
1532
1533 #ifdef PCIDMA
1534
1535 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1536 {
1537         const struct ni_board_struct *board = comedi_board(dev);
1538         struct ni_private *devpriv = dev->private;
1539         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1540         int retval;
1541         unsigned long flags;
1542
1543         retval = ni_request_ai_mite_channel(dev);
1544         if (retval)
1545                 return retval;
1546 /* printk("comedi_debug: using mite channel %i for ai.\n", devpriv->ai_mite_chan->channel); */
1547
1548         /* write alloc the entire buffer */
1549         comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
1550
1551         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1552         if (devpriv->ai_mite_chan == NULL) {
1553                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1554                 return -EIO;
1555         }
1556
1557         switch (board->reg_type) {
1558         case ni_reg_611x:
1559         case ni_reg_6143:
1560                 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1561                 break;
1562         case ni_reg_628x:
1563                 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1564                 break;
1565         default:
1566                 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1567                 break;
1568         }
1569         /*start the MITE */
1570         mite_dma_arm(devpriv->ai_mite_chan);
1571         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1572
1573         return 0;
1574 }
1575
1576 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1577 {
1578         const struct ni_board_struct *board = comedi_board(dev);
1579         struct ni_private *devpriv = dev->private;
1580         struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
1581         int retval;
1582         unsigned long flags;
1583
1584         retval = ni_request_ao_mite_channel(dev);
1585         if (retval)
1586                 return retval;
1587
1588         /* read alloc the entire buffer */
1589         comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
1590
1591         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1592         if (devpriv->ao_mite_chan) {
1593                 if (board->reg_type & (ni_reg_611x | ni_reg_6713)) {
1594                         mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1595                 } else {
1596                         /* doing 32 instead of 16 bit wide transfers from memory
1597                            makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1598                         mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1599                 }
1600                 mite_dma_arm(devpriv->ao_mite_chan);
1601         } else
1602                 retval = -EIO;
1603         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1604
1605         return retval;
1606 }
1607
1608 #endif /*  PCIDMA */
1609
1610 /*
1611    used for both cancel ioctl and board initialization
1612
1613    this is pretty harsh for a cancel, but it works...
1614  */
1615
1616 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1617 {
1618         const struct ni_board_struct *board = comedi_board(dev);
1619         struct ni_private *devpriv = dev->private;
1620
1621         ni_release_ai_mite_channel(dev);
1622         /* ai configuration */
1623         devpriv->stc_writew(dev, AI_Configuration_Start | AI_Reset,
1624                             Joint_Reset_Register);
1625
1626         ni_set_bits(dev, Interrupt_A_Enable_Register,
1627                     AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable |
1628                     AI_START2_Interrupt_Enable | AI_START_Interrupt_Enable |
1629                     AI_STOP_Interrupt_Enable | AI_Error_Interrupt_Enable |
1630                     AI_FIFO_Interrupt_Enable, 0);
1631
1632         ni_clear_ai_fifo(dev);
1633
1634         if (board->reg_type != ni_reg_6143)
1635                 ni_writeb(0, Misc_Command);
1636
1637         devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register);     /* reset pulses */
1638         devpriv->stc_writew(dev,
1639                             AI_Start_Stop | AI_Mode_1_Reserved
1640                             /*| AI_Trigger_Once */ ,
1641                             AI_Mode_1_Register);
1642         devpriv->stc_writew(dev, 0x0000, AI_Mode_2_Register);
1643         /* generate FIFO interrupts on non-empty */
1644         devpriv->stc_writew(dev, (0 << 6) | 0x0000, AI_Mode_3_Register);
1645         if (board->reg_type == ni_reg_611x) {
1646                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1647                                     AI_SOC_Polarity |
1648                                     AI_LOCALMUX_CLK_Pulse_Width,
1649                                     AI_Personal_Register);
1650                 devpriv->stc_writew(dev,
1651                                     AI_SCAN_IN_PROG_Output_Select(3) |
1652                                     AI_EXTMUX_CLK_Output_Select(0) |
1653                                     AI_LOCALMUX_CLK_Output_Select(2) |
1654                                     AI_SC_TC_Output_Select(3) |
1655                                     AI_CONVERT_Output_Select
1656                                     (AI_CONVERT_Output_Enable_High),
1657                                     AI_Output_Control_Register);
1658         } else if (board->reg_type == ni_reg_6143) {
1659                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1660                                     AI_SOC_Polarity |
1661                                     AI_LOCALMUX_CLK_Pulse_Width,
1662                                     AI_Personal_Register);
1663                 devpriv->stc_writew(dev,
1664                                     AI_SCAN_IN_PROG_Output_Select(3) |
1665                                     AI_EXTMUX_CLK_Output_Select(0) |
1666                                     AI_LOCALMUX_CLK_Output_Select(2) |
1667                                     AI_SC_TC_Output_Select(3) |
1668                                     AI_CONVERT_Output_Select
1669                                     (AI_CONVERT_Output_Enable_Low),
1670                                     AI_Output_Control_Register);
1671         } else {
1672                 unsigned ai_output_control_bits;
1673                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1674                                     AI_SOC_Polarity |
1675                                     AI_CONVERT_Pulse_Width |
1676                                     AI_LOCALMUX_CLK_Pulse_Width,
1677                                     AI_Personal_Register);
1678                 ai_output_control_bits =
1679                     AI_SCAN_IN_PROG_Output_Select(3) |
1680                     AI_EXTMUX_CLK_Output_Select(0) |
1681                     AI_LOCALMUX_CLK_Output_Select(2) |
1682                     AI_SC_TC_Output_Select(3);
1683                 if (board->reg_type == ni_reg_622x)
1684                         ai_output_control_bits |=
1685                             AI_CONVERT_Output_Select
1686                             (AI_CONVERT_Output_Enable_High);
1687                 else
1688                         ai_output_control_bits |=
1689                             AI_CONVERT_Output_Select
1690                             (AI_CONVERT_Output_Enable_Low);
1691                 devpriv->stc_writew(dev, ai_output_control_bits,
1692                                     AI_Output_Control_Register);
1693         }
1694         /* the following registers should not be changed, because there
1695          * are no backup registers in devpriv.  If you want to change
1696          * any of these, add a backup register and other appropriate code:
1697          *      AI_Mode_1_Register
1698          *      AI_Mode_3_Register
1699          *      AI_Personal_Register
1700          *      AI_Output_Control_Register
1701          */
1702         devpriv->stc_writew(dev, AI_SC_TC_Error_Confirm | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack, Interrupt_A_Ack_Register);      /* clear interrupts */
1703
1704         devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
1705
1706         return 0;
1707 }
1708
1709 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1710 {
1711         unsigned long flags;
1712         int count;
1713
1714         /*  lock to avoid race with interrupt handler */
1715         spin_lock_irqsave(&dev->spinlock, flags);
1716 #ifndef PCIDMA
1717         ni_handle_fifo_dregs(dev);
1718 #else
1719         ni_sync_ai_dma(dev);
1720 #endif
1721         count = s->async->buf_write_count - s->async->buf_read_count;
1722         spin_unlock_irqrestore(&dev->spinlock, flags);
1723
1724         return count;
1725 }
1726
1727 static int ni_ai_insn_read(struct comedi_device *dev,
1728                            struct comedi_subdevice *s, struct comedi_insn *insn,
1729                            unsigned int *data)
1730 {
1731         const struct ni_board_struct *board = comedi_board(dev);
1732         struct ni_private *devpriv = dev->private;
1733         int i, n;
1734         const unsigned int mask = (1 << board->adbits) - 1;
1735         unsigned signbits;
1736         unsigned short d;
1737         unsigned long dl;
1738
1739         ni_load_channelgain_list(dev, 1, &insn->chanspec);
1740
1741         ni_clear_ai_fifo(dev);
1742
1743         signbits = devpriv->ai_offset[0];
1744         if (board->reg_type == ni_reg_611x) {
1745                 for (n = 0; n < num_adc_stages_611x; n++) {
1746                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1747                                             AI_Command_1_Register);
1748                         udelay(1);
1749                 }
1750                 for (n = 0; n < insn->n; n++) {
1751                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1752                                             AI_Command_1_Register);
1753                         /* The 611x has screwy 32-bit FIFOs. */
1754                         d = 0;
1755                         for (i = 0; i < NI_TIMEOUT; i++) {
1756                                 if (ni_readb(XXX_Status) & 0x80) {
1757                                         d = (ni_readl(ADC_FIFO_Data_611x) >> 16)
1758                                             & 0xffff;
1759                                         break;
1760                                 }
1761                                 if (!(devpriv->stc_readw(dev,
1762                                                          AI_Status_1_Register) &
1763                                       AI_FIFO_Empty_St)) {
1764                                         d = ni_readl(ADC_FIFO_Data_611x) &
1765                                             0xffff;
1766                                         break;
1767                                 }
1768                         }
1769                         if (i == NI_TIMEOUT) {
1770                                 printk
1771                                     ("ni_mio_common: timeout in 611x ni_ai_insn_read\n");
1772                                 return -ETIME;
1773                         }
1774                         d += signbits;
1775                         data[n] = d;
1776                 }
1777         } else if (board->reg_type == ni_reg_6143) {
1778                 for (n = 0; n < insn->n; n++) {
1779                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1780                                             AI_Command_1_Register);
1781
1782                         /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1783                         dl = 0;
1784                         for (i = 0; i < NI_TIMEOUT; i++) {
1785                                 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1786                                         ni_writel(0x01, AIFIFO_Control_6143);   /*  Get stranded sample into FIFO */
1787                                         dl = ni_readl(AIFIFO_Data_6143);
1788                                         break;
1789                                 }
1790                         }
1791                         if (i == NI_TIMEOUT) {
1792                                 printk
1793                                     ("ni_mio_common: timeout in 6143 ni_ai_insn_read\n");
1794                                 return -ETIME;
1795                         }
1796                         data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1797                 }
1798         } else {
1799                 for (n = 0; n < insn->n; n++) {
1800                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1801                                             AI_Command_1_Register);
1802                         for (i = 0; i < NI_TIMEOUT; i++) {
1803                                 if (!(devpriv->stc_readw(dev,
1804                                                          AI_Status_1_Register) &
1805                                       AI_FIFO_Empty_St))
1806                                         break;
1807                         }
1808                         if (i == NI_TIMEOUT) {
1809                                 printk
1810                                     ("ni_mio_common: timeout in ni_ai_insn_read\n");
1811                                 return -ETIME;
1812                         }
1813                         if (board->reg_type & ni_reg_m_series_mask) {
1814                                 data[n] =
1815                                     ni_readl(M_Offset_AI_FIFO_Data) & mask;
1816                         } else {
1817                                 d = ni_readw(ADC_FIFO_Data_Register);
1818                                 d += signbits;  /* subtle: needs to be short addition */
1819                                 data[n] = d;
1820                         }
1821                 }
1822         }
1823         return insn->n;
1824 }
1825
1826 static void ni_prime_channelgain_list(struct comedi_device *dev)
1827 {
1828         struct ni_private *devpriv = dev->private;
1829         int i;
1830
1831         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1832         for (i = 0; i < NI_TIMEOUT; ++i) {
1833                 if (!(devpriv->stc_readw(dev,
1834                                          AI_Status_1_Register) &
1835                       AI_FIFO_Empty_St)) {
1836                         devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
1837                         return;
1838                 }
1839                 udelay(1);
1840         }
1841         printk("ni_mio_common: timeout loading channel/gain list\n");
1842 }
1843
1844 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1845                                               unsigned int n_chan,
1846                                               unsigned int *list)
1847 {
1848         const struct ni_board_struct *board = comedi_board(dev);
1849         struct ni_private *devpriv = dev->private;
1850         unsigned int chan, range, aref;
1851         unsigned int i;
1852         unsigned offset;
1853         unsigned int dither;
1854         unsigned range_code;
1855
1856         devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1857
1858 /* offset = 1 << (board->adbits - 1); */
1859         if ((list[0] & CR_ALT_SOURCE)) {
1860                 unsigned bypass_bits;
1861                 chan = CR_CHAN(list[0]);
1862                 range = CR_RANGE(list[0]);
1863                 range_code = ni_gainlkup[board->gainlkup][range];
1864                 dither = ((list[0] & CR_ALT_FILTER) != 0);
1865                 bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;
1866                 bypass_bits |= chan;
1867                 bypass_bits |=
1868                     (devpriv->ai_calib_source) &
1869                     (MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
1870                      MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
1871                      MSeries_AI_Bypass_Mode_Mux_Mask |
1872                      MSeries_AO_Bypass_AO_Cal_Sel_Mask);
1873                 bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code);
1874                 if (dither)
1875                         bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
1876                 /*  don't use 2's complement encoding */
1877                 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
1878                 ni_writel(bypass_bits, M_Offset_AI_Config_FIFO_Bypass);
1879         } else {
1880                 ni_writel(0, M_Offset_AI_Config_FIFO_Bypass);
1881         }
1882         offset = 0;
1883         for (i = 0; i < n_chan; i++) {
1884                 unsigned config_bits = 0;
1885                 chan = CR_CHAN(list[i]);
1886                 aref = CR_AREF(list[i]);
1887                 range = CR_RANGE(list[i]);
1888                 dither = ((list[i] & CR_ALT_FILTER) != 0);
1889
1890                 range_code = ni_gainlkup[board->gainlkup][range];
1891                 devpriv->ai_offset[i] = offset;
1892                 switch (aref) {
1893                 case AREF_DIFF:
1894                         config_bits |=
1895                             MSeries_AI_Config_Channel_Type_Differential_Bits;
1896                         break;
1897                 case AREF_COMMON:
1898                         config_bits |=
1899                             MSeries_AI_Config_Channel_Type_Common_Ref_Bits;
1900                         break;
1901                 case AREF_GROUND:
1902                         config_bits |=
1903                             MSeries_AI_Config_Channel_Type_Ground_Ref_Bits;
1904                         break;
1905                 case AREF_OTHER:
1906                         break;
1907                 }
1908                 config_bits |= MSeries_AI_Config_Channel_Bits(chan);
1909                 config_bits |=
1910                     MSeries_AI_Config_Bank_Bits(board->reg_type, chan);
1911                 config_bits |= MSeries_AI_Config_Gain_Bits(range_code);
1912                 if (i == n_chan - 1)
1913                         config_bits |= MSeries_AI_Config_Last_Channel_Bit;
1914                 if (dither)
1915                         config_bits |= MSeries_AI_Config_Dither_Bit;
1916                 /*  don't use 2's complement encoding */
1917                 config_bits |= MSeries_AI_Config_Polarity_Bit;
1918                 ni_writew(config_bits, M_Offset_AI_Config_FIFO_Data);
1919         }
1920         ni_prime_channelgain_list(dev);
1921 }
1922
1923 /*
1924  * Notes on the 6110 and 6111:
1925  * These boards a slightly different than the rest of the series, since
1926  * they have multiple A/D converters.
1927  * From the driver side, the configuration memory is a
1928  * little different.
1929  * Configuration Memory Low:
1930  *   bits 15-9: same
1931  *   bit 8: unipolar/bipolar (should be 0 for bipolar)
1932  *   bits 0-3: gain.  This is 4 bits instead of 3 for the other boards
1933  *       1001 gain=0.1 (+/- 50)
1934  *       1010 0.2
1935  *       1011 0.1
1936  *       0001 1
1937  *       0010 2
1938  *       0011 5
1939  *       0100 10
1940  *       0101 20
1941  *       0110 50
1942  * Configuration Memory High:
1943  *   bits 12-14: Channel Type
1944  *       001 for differential
1945  *       000 for calibration
1946  *   bit 11: coupling  (this is not currently handled)
1947  *       1 AC coupling
1948  *       0 DC coupling
1949  *   bits 0-2: channel
1950  *       valid channels are 0-3
1951  */
1952 static void ni_load_channelgain_list(struct comedi_device *dev,
1953                                      unsigned int n_chan, unsigned int *list)
1954 {
1955         const struct ni_board_struct *board = comedi_board(dev);
1956         struct ni_private *devpriv = dev->private;
1957         unsigned int chan, range, aref;
1958         unsigned int i;
1959         unsigned int hi, lo;
1960         unsigned offset;
1961         unsigned int dither;
1962
1963         if (board->reg_type & ni_reg_m_series_mask) {
1964                 ni_m_series_load_channelgain_list(dev, n_chan, list);
1965                 return;
1966         }
1967         if (n_chan == 1 && (board->reg_type != ni_reg_611x)
1968             && (board->reg_type != ni_reg_6143)) {
1969                 if (devpriv->changain_state
1970                     && devpriv->changain_spec == list[0]) {
1971                         /*  ready to go. */
1972                         return;
1973                 }
1974                 devpriv->changain_state = 1;
1975                 devpriv->changain_spec = list[0];
1976         } else {
1977                 devpriv->changain_state = 0;
1978         }
1979
1980         devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1981
1982         /*  Set up Calibration mode if required */
1983         if (board->reg_type == ni_reg_6143) {
1984                 if ((list[0] & CR_ALT_SOURCE)
1985                     && !devpriv->ai_calib_source_enabled) {
1986                         /*  Strobe Relay enable bit */
1987                         ni_writew(devpriv->ai_calib_source |
1988                                   Calibration_Channel_6143_RelayOn,
1989                                   Calibration_Channel_6143);
1990                         ni_writew(devpriv->ai_calib_source,
1991                                   Calibration_Channel_6143);
1992                         devpriv->ai_calib_source_enabled = 1;
1993                         msleep_interruptible(100);      /*  Allow relays to change */
1994                 } else if (!(list[0] & CR_ALT_SOURCE)
1995                            && devpriv->ai_calib_source_enabled) {
1996                         /*  Strobe Relay disable bit */
1997                         ni_writew(devpriv->ai_calib_source |
1998                                   Calibration_Channel_6143_RelayOff,
1999                                   Calibration_Channel_6143);
2000                         ni_writew(devpriv->ai_calib_source,
2001                                   Calibration_Channel_6143);
2002                         devpriv->ai_calib_source_enabled = 0;
2003                         msleep_interruptible(100);      /*  Allow relays to change */
2004                 }
2005         }
2006
2007         offset = 1 << (board->adbits - 1);
2008         for (i = 0; i < n_chan; i++) {
2009                 if ((board->reg_type != ni_reg_6143)
2010                     && (list[i] & CR_ALT_SOURCE)) {
2011                         chan = devpriv->ai_calib_source;
2012                 } else {
2013                         chan = CR_CHAN(list[i]);
2014                 }
2015                 aref = CR_AREF(list[i]);
2016                 range = CR_RANGE(list[i]);
2017                 dither = ((list[i] & CR_ALT_FILTER) != 0);
2018
2019                 /* fix the external/internal range differences */
2020                 range = ni_gainlkup[board->gainlkup][range];
2021                 if (board->reg_type == ni_reg_611x)
2022                         devpriv->ai_offset[i] = offset;
2023                 else
2024                         devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
2025
2026                 hi = 0;
2027                 if ((list[i] & CR_ALT_SOURCE)) {
2028                         if (board->reg_type == ni_reg_611x)
2029                                 ni_writew(CR_CHAN(list[i]) & 0x0003,
2030                                           Calibration_Channel_Select_611x);
2031                 } else {
2032                         if (board->reg_type == ni_reg_611x)
2033                                 aref = AREF_DIFF;
2034                         else if (board->reg_type == ni_reg_6143)
2035                                 aref = AREF_OTHER;
2036                         switch (aref) {
2037                         case AREF_DIFF:
2038                                 hi |= AI_DIFFERENTIAL;
2039                                 break;
2040                         case AREF_COMMON:
2041                                 hi |= AI_COMMON;
2042                                 break;
2043                         case AREF_GROUND:
2044                                 hi |= AI_GROUND;
2045                                 break;
2046                         case AREF_OTHER:
2047                                 break;
2048                         }
2049                 }
2050                 hi |= AI_CONFIG_CHANNEL(chan);
2051
2052                 ni_writew(hi, Configuration_Memory_High);
2053
2054                 if (board->reg_type != ni_reg_6143) {
2055                         lo = range;
2056                         if (i == n_chan - 1)
2057                                 lo |= AI_LAST_CHANNEL;
2058                         if (dither)
2059                                 lo |= AI_DITHER;
2060
2061                         ni_writew(lo, Configuration_Memory_Low);
2062                 }
2063         }
2064
2065         /* prime the channel/gain list */
2066         if ((board->reg_type != ni_reg_611x)
2067             && (board->reg_type != ni_reg_6143)) {
2068                 ni_prime_channelgain_list(dev);
2069         }
2070 }
2071
2072 static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec,
2073                           int round_mode)
2074 {
2075         struct ni_private *devpriv = dev->private;
2076         int divider;
2077
2078         switch (round_mode) {
2079         case TRIG_ROUND_NEAREST:
2080         default:
2081                 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
2082                 break;
2083         case TRIG_ROUND_DOWN:
2084                 divider = (nanosec) / devpriv->clock_ns;
2085                 break;
2086         case TRIG_ROUND_UP:
2087                 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
2088                 break;
2089         }
2090         return divider - 1;
2091 }
2092
2093 static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer)
2094 {
2095         struct ni_private *devpriv = dev->private;
2096
2097         return devpriv->clock_ns * (timer + 1);
2098 }
2099
2100 static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev,
2101                                          unsigned num_channels)
2102 {
2103         const struct ni_board_struct *board = comedi_board(dev);
2104
2105         switch (board->reg_type) {
2106         case ni_reg_611x:
2107         case ni_reg_6143:
2108                 /*  simultaneously-sampled inputs */
2109                 return board->ai_speed;
2110                 break;
2111         default:
2112                 /*  multiplexed inputs */
2113                 break;
2114         }
2115         return board->ai_speed * num_channels;
2116 }
2117
2118 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2119                          struct comedi_cmd *cmd)
2120 {
2121         const struct ni_board_struct *board = comedi_board(dev);
2122         struct ni_private *devpriv = dev->private;
2123         int err = 0;
2124         int tmp;
2125         unsigned int sources;
2126
2127         /* Step 1 : check if triggers are trivially valid */
2128
2129         if ((cmd->flags & CMDF_WRITE))
2130                 cmd->flags &= ~CMDF_WRITE;
2131
2132         err |= cfc_check_trigger_src(&cmd->start_src,
2133                                         TRIG_NOW | TRIG_INT | TRIG_EXT);
2134         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
2135                                         TRIG_TIMER | TRIG_EXT);
2136
2137         sources = TRIG_TIMER | TRIG_EXT;
2138         if (board->reg_type == ni_reg_611x ||
2139             board->reg_type == ni_reg_6143)
2140                 sources |= TRIG_NOW;
2141         err |= cfc_check_trigger_src(&cmd->convert_src, sources);
2142
2143         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2144         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2145
2146         if (err)
2147                 return 1;
2148
2149         /* Step 2a : make sure trigger sources are unique */
2150
2151         err |= cfc_check_trigger_is_unique(cmd->start_src);
2152         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2153         err |= cfc_check_trigger_is_unique(cmd->convert_src);
2154         err |= cfc_check_trigger_is_unique(cmd->stop_src);
2155
2156         /* Step 2b : and mutually compatible */
2157
2158         if (err)
2159                 return 2;
2160
2161         /* Step 3: check if arguments are trivially valid */
2162
2163         if (cmd->start_src == TRIG_EXT) {
2164                 /* external trigger */
2165                 unsigned int tmp = CR_CHAN(cmd->start_arg);
2166
2167                 if (tmp > 16)
2168                         tmp = 16;
2169                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2170                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, tmp);
2171         } else {
2172                 /* true for both TRIG_NOW and TRIG_INT */
2173                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
2174         }
2175
2176         if (cmd->scan_begin_src == TRIG_TIMER) {
2177                 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
2178                         ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2179                 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
2180                                                  devpriv->clock_ns * 0xffffff);
2181         } else if (cmd->scan_begin_src == TRIG_EXT) {
2182                 /* external trigger */
2183                 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2184
2185                 if (tmp > 16)
2186                         tmp = 16;
2187                 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2188                 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, tmp);
2189         } else {                /* TRIG_OTHER */
2190                 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2191         }
2192
2193         if (cmd->convert_src == TRIG_TIMER) {
2194                 if ((board->reg_type == ni_reg_611x)
2195                     || (board->reg_type == ni_reg_6143)) {
2196                         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2197                 } else {
2198                         err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
2199                                                          board->ai_speed);
2200                         err |= cfc_check_trigger_arg_max(&cmd->convert_arg,
2201                                                 devpriv->clock_ns * 0xffff);
2202                 }
2203         } else if (cmd->convert_src == TRIG_EXT) {
2204                 /* external trigger */
2205                 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2206
2207                 if (tmp > 16)
2208                         tmp = 16;
2209                 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2210                 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, tmp);
2211         } else if (cmd->convert_src == TRIG_NOW) {
2212                 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2213         }
2214
2215         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
2216
2217         if (cmd->stop_src == TRIG_COUNT) {
2218                 unsigned int max_count = 0x01000000;
2219
2220                 if (board->reg_type == ni_reg_611x)
2221                         max_count -= num_adc_stages_611x;
2222                 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, max_count);
2223                 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
2224         } else {
2225                 /* TRIG_NONE */
2226                 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
2227         }
2228
2229         if (err)
2230                 return 3;
2231
2232         /* step 4: fix up any arguments */
2233
2234         if (cmd->scan_begin_src == TRIG_TIMER) {
2235                 tmp = cmd->scan_begin_arg;
2236                 cmd->scan_begin_arg =
2237                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2238                                                        cmd->scan_begin_arg,
2239                                                        cmd->
2240                                                        flags &
2241                                                        TRIG_ROUND_MASK));
2242                 if (tmp != cmd->scan_begin_arg)
2243                         err++;
2244         }
2245         if (cmd->convert_src == TRIG_TIMER) {
2246                 if ((board->reg_type != ni_reg_611x)
2247                     && (board->reg_type != ni_reg_6143)) {
2248                         tmp = cmd->convert_arg;
2249                         cmd->convert_arg =
2250                             ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2251                                                                cmd->convert_arg,
2252                                                                cmd->
2253                                                                flags &
2254                                                                TRIG_ROUND_MASK));
2255                         if (tmp != cmd->convert_arg)
2256                                 err++;
2257                         if (cmd->scan_begin_src == TRIG_TIMER &&
2258                             cmd->scan_begin_arg <
2259                             cmd->convert_arg * cmd->scan_end_arg) {
2260                                 cmd->scan_begin_arg =
2261                                     cmd->convert_arg * cmd->scan_end_arg;
2262                                 err++;
2263                         }
2264                 }
2265         }
2266
2267         if (err)
2268                 return 4;
2269
2270         return 0;
2271 }
2272
2273 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2274 {
2275         const struct ni_board_struct *board = comedi_board(dev);
2276         struct ni_private *devpriv = dev->private;
2277         const struct comedi_cmd *cmd = &s->async->cmd;
2278         int timer;
2279         int mode1 = 0;          /* mode1 is needed for both stop and convert */
2280         int mode2 = 0;
2281         int start_stop_select = 0;
2282         unsigned int stop_count;
2283         int interrupt_a_enable = 0;
2284
2285         if (dev->irq == 0) {
2286                 comedi_error(dev, "cannot run command without an irq");
2287                 return -EIO;
2288         }
2289         ni_clear_ai_fifo(dev);
2290
2291         ni_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist);
2292
2293         /* start configuration */
2294         devpriv->stc_writew(dev, AI_Configuration_Start, Joint_Reset_Register);
2295
2296         /* disable analog triggering for now, since it
2297          * interferes with the use of pfi0 */
2298         devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
2299         devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
2300                             Analog_Trigger_Etc_Register);
2301
2302         switch (cmd->start_src) {
2303         case TRIG_INT:
2304         case TRIG_NOW:
2305                 devpriv->stc_writew(dev, AI_START2_Select(0) |
2306                                     AI_START1_Sync | AI_START1_Edge |
2307                                     AI_START1_Select(0),
2308                                     AI_Trigger_Select_Register);
2309                 break;
2310         case TRIG_EXT:
2311                 {
2312                         int chan = CR_CHAN(cmd->start_arg);
2313                         unsigned int bits = AI_START2_Select(0) |
2314                             AI_START1_Sync | AI_START1_Select(chan + 1);
2315
2316                         if (cmd->start_arg & CR_INVERT)
2317                                 bits |= AI_START1_Polarity;
2318                         if (cmd->start_arg & CR_EDGE)
2319                                 bits |= AI_START1_Edge;
2320                         devpriv->stc_writew(dev, bits,
2321                                             AI_Trigger_Select_Register);
2322                         break;
2323                 }
2324         }
2325
2326         mode2 &= ~AI_Pre_Trigger;
2327         mode2 &= ~AI_SC_Initial_Load_Source;
2328         mode2 &= ~AI_SC_Reload_Mode;
2329         devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2330
2331         if (cmd->chanlist_len == 1 || (board->reg_type == ni_reg_611x)
2332             || (board->reg_type == ni_reg_6143)) {
2333                 start_stop_select |= AI_STOP_Polarity;
2334                 start_stop_select |= AI_STOP_Select(31);        /*  logic low */
2335                 start_stop_select |= AI_STOP_Sync;
2336         } else {
2337                 start_stop_select |= AI_STOP_Select(19);        /*  ai configuration memory */
2338         }
2339         devpriv->stc_writew(dev, start_stop_select,
2340                             AI_START_STOP_Select_Register);
2341
2342         devpriv->ai_cmd2 = 0;
2343         switch (cmd->stop_src) {
2344         case TRIG_COUNT:
2345                 stop_count = cmd->stop_arg - 1;
2346
2347                 if (board->reg_type == ni_reg_611x) {
2348                         /*  have to take 3 stage adc pipeline into account */
2349                         stop_count += num_adc_stages_611x;
2350                 }
2351                 /* stage number of scans */
2352                 devpriv->stc_writel(dev, stop_count, AI_SC_Load_A_Registers);
2353
2354                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once;
2355                 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2356                 /* load SC (Scan Count) */
2357                 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2358
2359                 devpriv->ai_continuous = 0;
2360                 if (stop_count == 0) {
2361                         devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
2362                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2363                         /*  this is required to get the last sample for chanlist_len > 1, not sure why */
2364                         if (cmd->chanlist_len > 1)
2365                                 start_stop_select |=
2366                                     AI_STOP_Polarity | AI_STOP_Edge;
2367                 }
2368                 break;
2369         case TRIG_NONE:
2370                 /* stage number of scans */
2371                 devpriv->stc_writel(dev, 0, AI_SC_Load_A_Registers);
2372
2373                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous;
2374                 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2375
2376                 /* load SC (Scan Count) */
2377                 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2378
2379                 devpriv->ai_continuous = 1;
2380
2381                 break;
2382         }
2383
2384         switch (cmd->scan_begin_src) {
2385         case TRIG_TIMER:
2386                 /*
2387                    stop bits for non 611x boards
2388                    AI_SI_Special_Trigger_Delay=0
2389                    AI_Pre_Trigger=0
2390                    AI_START_STOP_Select_Register:
2391                    AI_START_Polarity=0 (?)      rising edge
2392                    AI_START_Edge=1              edge triggered
2393                    AI_START_Sync=1 (?)
2394                    AI_START_Select=0            SI_TC
2395                    AI_STOP_Polarity=0           rising edge
2396                    AI_STOP_Edge=0               level
2397                    AI_STOP_Sync=1
2398                    AI_STOP_Select=19            external pin (configuration mem)
2399                  */
2400                 start_stop_select |= AI_START_Edge | AI_START_Sync;
2401                 devpriv->stc_writew(dev, start_stop_select,
2402                                     AI_START_STOP_Select_Register);
2403
2404                 mode2 |= AI_SI_Reload_Mode(0);
2405                 /* AI_SI_Initial_Load_Source=A */
2406                 mode2 &= ~AI_SI_Initial_Load_Source;
2407                 /* mode2 |= AI_SC_Reload_Mode; */
2408                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2409
2410                 /* load SI */
2411                 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2412                                        TRIG_ROUND_NEAREST);
2413                 devpriv->stc_writel(dev, timer, AI_SI_Load_A_Registers);
2414                 devpriv->stc_writew(dev, AI_SI_Load, AI_Command_1_Register);
2415                 break;
2416         case TRIG_EXT:
2417                 if (cmd->scan_begin_arg & CR_EDGE)
2418                         start_stop_select |= AI_START_Edge;
2419                 /* AI_START_Polarity==1 is falling edge */
2420                 if (cmd->scan_begin_arg & CR_INVERT)
2421                         start_stop_select |= AI_START_Polarity;
2422                 if (cmd->scan_begin_src != cmd->convert_src ||
2423                     (cmd->scan_begin_arg & ~CR_EDGE) !=
2424                     (cmd->convert_arg & ~CR_EDGE))
2425                         start_stop_select |= AI_START_Sync;
2426                 start_stop_select |=
2427                     AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg));
2428                 devpriv->stc_writew(dev, start_stop_select,
2429                                     AI_START_STOP_Select_Register);
2430                 break;
2431         }
2432
2433         switch (cmd->convert_src) {
2434         case TRIG_TIMER:
2435         case TRIG_NOW:
2436                 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2437                         timer = 1;
2438                 else
2439                         timer = ni_ns_to_timer(dev, cmd->convert_arg,
2440                                                TRIG_ROUND_NEAREST);
2441                 devpriv->stc_writew(dev, 1, AI_SI2_Load_A_Register);    /* 0,0 does not work. */
2442                 devpriv->stc_writew(dev, timer, AI_SI2_Load_B_Register);
2443
2444                 /* AI_SI2_Reload_Mode = alternate */
2445                 /* AI_SI2_Initial_Load_Source = A */
2446                 mode2 &= ~AI_SI2_Initial_Load_Source;
2447                 mode2 |= AI_SI2_Reload_Mode;
2448                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2449
2450                 /* AI_SI2_Load */
2451                 devpriv->stc_writew(dev, AI_SI2_Load, AI_Command_1_Register);
2452
2453                 mode2 |= AI_SI2_Reload_Mode;    /*  alternate */
2454                 mode2 |= AI_SI2_Initial_Load_Source;    /*  B */
2455
2456                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2457                 break;
2458         case TRIG_EXT:
2459                 mode1 |= AI_CONVERT_Source_Select(1 + cmd->convert_arg);
2460                 if ((cmd->convert_arg & CR_INVERT) == 0)
2461                         mode1 |= AI_CONVERT_Source_Polarity;
2462                 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2463
2464                 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable;
2465                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2466
2467                 break;
2468         }
2469
2470         if (dev->irq) {
2471
2472                 /* interrupt on FIFO, errors, SC_TC */
2473                 interrupt_a_enable |= AI_Error_Interrupt_Enable |
2474                     AI_SC_TC_Interrupt_Enable;
2475
2476 #ifndef PCIDMA
2477                 interrupt_a_enable |= AI_FIFO_Interrupt_Enable;
2478 #endif
2479
2480                 if (cmd->flags & TRIG_WAKE_EOS
2481                     || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
2482                         /* wake on end-of-scan */
2483                         devpriv->aimode = AIMODE_SCAN;
2484                 } else {
2485                         devpriv->aimode = AIMODE_HALF_FULL;
2486                 }
2487
2488                 switch (devpriv->aimode) {
2489                 case AIMODE_HALF_FULL:
2490                         /*generate FIFO interrupts and DMA requests on half-full */
2491 #ifdef PCIDMA
2492                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF_to_E,
2493                                             AI_Mode_3_Register);
2494 #else
2495                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2496                                             AI_Mode_3_Register);
2497 #endif
2498                         break;
2499                 case AIMODE_SAMPLE:
2500                         /*generate FIFO interrupts on non-empty */
2501                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2502                                             AI_Mode_3_Register);
2503                         break;
2504                 case AIMODE_SCAN:
2505 #ifdef PCIDMA
2506                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2507                                             AI_Mode_3_Register);
2508 #else
2509                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2510                                             AI_Mode_3_Register);
2511 #endif
2512                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2513                         break;
2514                 default:
2515                         break;
2516                 }
2517
2518                 devpriv->stc_writew(dev, AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_SC_TC_Error_Confirm, Interrupt_A_Ack_Register);      /* clear interrupts */
2519
2520                 ni_set_bits(dev, Interrupt_A_Enable_Register,
2521                             interrupt_a_enable, 1);
2522         } else {
2523                 /* interrupt on nothing */
2524                 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
2525
2526                 /* XXX start polling if necessary */
2527         }
2528
2529         /* end configuration */
2530         devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
2531
2532         switch (cmd->scan_begin_src) {
2533         case TRIG_TIMER:
2534                 devpriv->stc_writew(dev,
2535                                     AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2536                                     AI_SC_Arm, AI_Command_1_Register);
2537                 break;
2538         case TRIG_EXT:
2539                 /* XXX AI_SI_Arm? */
2540                 devpriv->stc_writew(dev,
2541                                     AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2542                                     AI_SC_Arm, AI_Command_1_Register);
2543                 break;
2544         }
2545
2546 #ifdef PCIDMA
2547         {
2548                 int retval = ni_ai_setup_MITE_dma(dev);
2549                 if (retval)
2550                         return retval;
2551         }
2552 #endif
2553
2554         switch (cmd->start_src) {
2555         case TRIG_NOW:
2556                 /* AI_START1_Pulse */
2557                 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2558                                     AI_Command_2_Register);
2559                 s->async->inttrig = NULL;
2560                 break;
2561         case TRIG_EXT:
2562                 s->async->inttrig = NULL;
2563                 break;
2564         case TRIG_INT:
2565                 s->async->inttrig = &ni_ai_inttrig;
2566                 break;
2567         }
2568
2569         return 0;
2570 }
2571
2572 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
2573                          unsigned int trignum)
2574 {
2575         struct ni_private *devpriv = dev->private;
2576
2577         if (trignum != 0)
2578                 return -EINVAL;
2579
2580         devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2581                             AI_Command_2_Register);
2582         s->async->inttrig = NULL;
2583
2584         return 1;
2585 }
2586
2587 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2588                                     struct comedi_subdevice *s,
2589                                     struct comedi_insn *insn,
2590                                     unsigned int *data);
2591
2592 static int ni_ai_insn_config(struct comedi_device *dev,
2593                              struct comedi_subdevice *s,
2594                              struct comedi_insn *insn, unsigned int *data)
2595 {
2596         const struct ni_board_struct *board = comedi_board(dev);
2597         struct ni_private *devpriv = dev->private;
2598
2599         if (insn->n < 1)
2600                 return -EINVAL;
2601
2602         switch (data[0]) {
2603         case INSN_CONFIG_ANALOG_TRIG:
2604                 return ni_ai_config_analog_trig(dev, s, insn, data);
2605         case INSN_CONFIG_ALT_SOURCE:
2606                 if (board->reg_type & ni_reg_m_series_mask) {
2607                         if (data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
2608                                         MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
2609                                         MSeries_AI_Bypass_Mode_Mux_Mask |
2610                                         MSeries_AO_Bypass_AO_Cal_Sel_Mask)) {
2611                                 return -EINVAL;
2612                         }
2613                         devpriv->ai_calib_source = data[1];
2614                 } else if (board->reg_type == ni_reg_6143) {
2615                         unsigned int calib_source;
2616
2617                         calib_source = data[1] & 0xf;
2618
2619                         if (calib_source > 0xF)
2620                                 return -EINVAL;
2621
2622                         devpriv->ai_calib_source = calib_source;
2623                         ni_writew(calib_source, Calibration_Channel_6143);
2624                 } else {
2625                         unsigned int calib_source;
2626                         unsigned int calib_source_adjust;
2627
2628                         calib_source = data[1] & 0xf;
2629                         calib_source_adjust = (data[1] >> 4) & 0xff;
2630
2631                         if (calib_source >= 8)
2632                                 return -EINVAL;
2633                         devpriv->ai_calib_source = calib_source;
2634                         if (board->reg_type == ni_reg_611x) {
2635                                 ni_writeb(calib_source_adjust,
2636                                           Cal_Gain_Select_611x);
2637                         }
2638                 }
2639                 return 2;
2640         default:
2641                 break;
2642         }
2643
2644         return -EINVAL;
2645 }
2646
2647 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2648                                     struct comedi_subdevice *s,
2649                                     struct comedi_insn *insn,
2650                                     unsigned int *data)
2651 {
2652         const struct ni_board_struct *board = comedi_board(dev);
2653         struct ni_private *devpriv = dev->private;
2654         unsigned int a, b, modebits;
2655         int err = 0;
2656
2657         /* data[1] is flags
2658          * data[2] is analog line
2659          * data[3] is set level
2660          * data[4] is reset level */
2661         if (!board->has_analog_trig)
2662                 return -EINVAL;
2663         if ((data[1] & 0xffff0000) != COMEDI_EV_SCAN_BEGIN) {
2664                 data[1] &= (COMEDI_EV_SCAN_BEGIN | 0xffff);
2665                 err++;
2666         }
2667         if (data[2] >= board->n_adchan) {
2668                 data[2] = board->n_adchan - 1;
2669                 err++;
2670         }
2671         if (data[3] > 255) {    /* a */
2672                 data[3] = 255;
2673                 err++;
2674         }
2675         if (data[4] > 255) {    /* b */
2676                 data[4] = 255;
2677                 err++;
2678         }
2679         /*
2680          * 00 ignore
2681          * 01 set
2682          * 10 reset
2683          *
2684          * modes:
2685          *   1 level:                    +b-   +a-
2686          *     high mode                00 00 01 10
2687          *     low mode                 00 00 10 01
2688          *   2 level: (a<b)
2689          *     hysteresis low mode      10 00 00 01
2690          *     hysteresis high mode     01 00 00 10
2691          *     middle mode              10 01 01 10
2692          */
2693
2694         a = data[3];
2695         b = data[4];
2696         modebits = data[1] & 0xff;
2697         if (modebits & 0xf0) {
2698                 /* two level mode */
2699                 if (b < a) {
2700                         /* swap order */
2701                         a = data[4];
2702                         b = data[3];
2703                         modebits =
2704                             ((data[1] & 0xf) << 4) | ((data[1] & 0xf0) >> 4);
2705                 }
2706                 devpriv->atrig_low = a;
2707                 devpriv->atrig_high = b;
2708                 switch (modebits) {
2709                 case 0x81:      /* low hysteresis mode */
2710                         devpriv->atrig_mode = 6;
2711                         break;
2712                 case 0x42:      /* high hysteresis mode */
2713                         devpriv->atrig_mode = 3;
2714                         break;
2715                 case 0x96:      /* middle window mode */
2716                         devpriv->atrig_mode = 2;
2717                         break;
2718                 default:
2719                         data[1] &= ~0xff;
2720                         err++;
2721                 }
2722         } else {
2723                 /* one level mode */
2724                 if (b != 0) {
2725                         data[4] = 0;
2726                         err++;
2727                 }
2728                 switch (modebits) {
2729                 case 0x06:      /* high window mode */
2730                         devpriv->atrig_high = a;
2731                         devpriv->atrig_mode = 0;
2732                         break;
2733                 case 0x09:      /* low window mode */
2734                         devpriv->atrig_low = a;
2735                         devpriv->atrig_mode = 1;
2736                         break;
2737                 default:
2738                         data[1] &= ~0xff;
2739                         err++;
2740                 }
2741         }
2742         if (err)
2743                 return -EAGAIN;
2744         return 5;
2745 }
2746
2747 /* munge data from unsigned to 2's complement for analog output bipolar modes */
2748 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2749                         void *data, unsigned int num_bytes,
2750                         unsigned int chan_index)
2751 {
2752         const struct ni_board_struct *board = comedi_board(dev);
2753         struct comedi_async *async = s->async;
2754         unsigned int range;
2755         unsigned int i;
2756         unsigned int offset;
2757         unsigned int length = num_bytes / sizeof(short);
2758         unsigned short *array = data;
2759
2760         offset = 1 << (board->aobits - 1);
2761         for (i = 0; i < length; i++) {
2762                 range = CR_RANGE(async->cmd.chanlist[chan_index]);
2763                 if (board->ao_unipolar == 0 || (range & 1) == 0)
2764                         array[i] -= offset;
2765 #ifdef PCIDMA
2766                 array[i] = cpu_to_le16(array[i]);
2767 #endif
2768                 chan_index++;
2769                 chan_index %= async->cmd.chanlist_len;
2770         }
2771 }
2772
2773 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2774                                           struct comedi_subdevice *s,
2775                                           unsigned int chanspec[],
2776                                           unsigned int n_chans, int timed)
2777 {
2778         const struct ni_board_struct *board = comedi_board(dev);
2779         struct ni_private *devpriv = dev->private;
2780         unsigned int range;
2781         unsigned int chan;
2782         unsigned int conf;
2783         int i;
2784         int invert = 0;
2785
2786         if (timed) {
2787                 for (i = 0; i < board->n_aochan; ++i) {
2788                         devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit;
2789                         ni_writeb(devpriv->ao_conf[i],
2790                                   M_Offset_AO_Config_Bank(i));
2791                         ni_writeb(0xf, M_Offset_AO_Waveform_Order(i));
2792                 }
2793         }
2794         for (i = 0; i < n_chans; i++) {
2795                 const struct comedi_krange *krange;
2796                 chan = CR_CHAN(chanspec[i]);
2797                 range = CR_RANGE(chanspec[i]);
2798                 krange = s->range_table->range + range;
2799                 invert = 0;
2800                 conf = 0;
2801                 switch (krange->max - krange->min) {
2802                 case 20000000:
2803                         conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2804                         ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2805                         break;
2806                 case 10000000:
2807                         conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2808                         ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2809                         break;
2810                 case 4000000:
2811                         conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2812                         ni_writeb(MSeries_Attenuate_x5_Bit,
2813                                   M_Offset_AO_Reference_Attenuation(chan));
2814                         break;
2815                 case 2000000:
2816                         conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2817                         ni_writeb(MSeries_Attenuate_x5_Bit,
2818                                   M_Offset_AO_Reference_Attenuation(chan));
2819                         break;
2820                 default:
2821                         printk("%s: bug! unhandled ao reference voltage\n",
2822                                __func__);
2823                         break;
2824                 }
2825                 switch (krange->max + krange->min) {
2826                 case 0:
2827                         conf |= MSeries_AO_DAC_Offset_0V_Bits;
2828                         break;
2829                 case 10000000:
2830                         conf |= MSeries_AO_DAC_Offset_5V_Bits;
2831                         break;
2832                 default:
2833                         printk("%s: bug! unhandled ao offset voltage\n",
2834                                __func__);
2835                         break;
2836                 }
2837                 if (timed)
2838                         conf |= MSeries_AO_Update_Timed_Bit;
2839                 ni_writeb(conf, M_Offset_AO_Config_Bank(chan));
2840                 devpriv->ao_conf[chan] = conf;
2841                 ni_writeb(i, M_Offset_AO_Waveform_Order(chan));
2842         }
2843         return invert;
2844 }
2845
2846 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2847                                      struct comedi_subdevice *s,
2848                                      unsigned int chanspec[],
2849                                      unsigned int n_chans)
2850 {
2851         const struct ni_board_struct *board = comedi_board(dev);
2852         struct ni_private *devpriv = dev->private;
2853         unsigned int range;
2854         unsigned int chan;
2855         unsigned int conf;
2856         int i;
2857         int invert = 0;
2858
2859         for (i = 0; i < n_chans; i++) {
2860                 chan = CR_CHAN(chanspec[i]);
2861                 range = CR_RANGE(chanspec[i]);
2862                 conf = AO_Channel(chan);
2863
2864                 if (board->ao_unipolar) {
2865                         if ((range & 1) == 0) {
2866                                 conf |= AO_Bipolar;
2867                                 invert = (1 << (board->aobits - 1));
2868                         } else {
2869                                 invert = 0;
2870                         }
2871                         if (range & 2)
2872                                 conf |= AO_Ext_Ref;
2873                 } else {
2874                         conf |= AO_Bipolar;
2875                         invert = (1 << (board->aobits - 1));
2876                 }
2877
2878                 /* not all boards can deglitch, but this shouldn't hurt */
2879                 if (chanspec[i] & CR_DEGLITCH)
2880                         conf |= AO_Deglitch;
2881
2882                 /* analog reference */
2883                 /* AREF_OTHER connects AO ground to AI ground, i think */
2884                 conf |= (CR_AREF(chanspec[i]) ==
2885                          AREF_OTHER) ? AO_Ground_Ref : 0;
2886
2887                 ni_writew(conf, AO_Configuration);
2888                 devpriv->ao_conf[chan] = conf;
2889         }
2890         return invert;
2891 }
2892
2893 static int ni_ao_config_chanlist(struct comedi_device *dev,
2894                                  struct comedi_subdevice *s,
2895                                  unsigned int chanspec[], unsigned int n_chans,
2896                                  int timed)
2897 {
2898         const struct ni_board_struct *board = comedi_board(dev);
2899
2900         if (board->reg_type & ni_reg_m_series_mask)
2901                 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
2902                                                       timed);
2903         else
2904                 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2905 }
2906
2907 static int ni_ao_insn_read(struct comedi_device *dev,
2908                            struct comedi_subdevice *s, struct comedi_insn *insn,
2909                            unsigned int *data)
2910 {
2911         struct ni_private *devpriv = dev->private;
2912
2913         data[0] = devpriv->ao[CR_CHAN(insn->chanspec)];
2914
2915         return 1;
2916 }
2917
2918 static int ni_ao_insn_write(struct comedi_device *dev,
2919                             struct comedi_subdevice *s,
2920                             struct comedi_insn *insn, unsigned int *data)
2921 {
2922         const struct ni_board_struct *board = comedi_board(dev);
2923         struct ni_private *devpriv = dev->private;
2924         unsigned int chan = CR_CHAN(insn->chanspec);
2925         unsigned int invert;
2926
2927         invert = ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2928
2929         devpriv->ao[chan] = data[0];
2930
2931         if (board->reg_type & ni_reg_m_series_mask) {
2932                 ni_writew(data[0], M_Offset_DAC_Direct_Data(chan));
2933         } else
2934                 ni_writew(data[0] ^ invert,
2935                           (chan) ? DAC1_Direct_Data : DAC0_Direct_Data);
2936
2937         return 1;
2938 }
2939
2940 static int ni_ao_insn_write_671x(struct comedi_device *dev,
2941                                  struct comedi_subdevice *s,
2942                                  struct comedi_insn *insn, unsigned int *data)
2943 {
2944         const struct ni_board_struct *board = comedi_board(dev);
2945         struct ni_private *devpriv = dev->private;
2946         unsigned int chan = CR_CHAN(insn->chanspec);
2947         unsigned int invert;
2948
2949         ao_win_out(1 << chan, AO_Immediate_671x);
2950         invert = 1 << (board->aobits - 1);
2951
2952         ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2953
2954         devpriv->ao[chan] = data[0];
2955         ao_win_out(data[0] ^ invert, DACx_Direct_Data_671x(chan));
2956
2957         return 1;
2958 }
2959
2960 static int ni_ao_insn_config(struct comedi_device *dev,
2961                              struct comedi_subdevice *s,
2962                              struct comedi_insn *insn, unsigned int *data)
2963 {
2964         const struct ni_board_struct *board = comedi_board(dev);
2965         struct ni_private *devpriv = dev->private;
2966
2967         switch (data[0]) {
2968         case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
2969                 switch (data[1]) {
2970                 case COMEDI_OUTPUT:
2971                         data[2] = 1 + board->ao_fifo_depth * sizeof(short);
2972                         if (devpriv->mite)
2973                                 data[2] += devpriv->mite->fifo_size;
2974                         break;
2975                 case COMEDI_INPUT:
2976                         data[2] = 0;
2977                         break;
2978                 default:
2979                         return -EINVAL;
2980                         break;
2981                 }
2982                 return 0;
2983         default:
2984                 break;
2985         }
2986
2987         return -EINVAL;
2988 }
2989
2990 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
2991                          unsigned int trignum)
2992 {
2993         const struct ni_board_struct *board __maybe_unused = comedi_board(dev);
2994         struct ni_private *devpriv = dev->private;
2995         int ret;
2996         int interrupt_b_bits;
2997         int i;
2998         static const int timeout = 1000;
2999
3000         if (trignum != 0)
3001                 return -EINVAL;
3002
3003         /* Null trig at beginning prevent ao start trigger from executing more than
3004            once per command (and doing things like trying to allocate the ao dma channel
3005            multiple times) */
3006         s->async->inttrig = NULL;
3007
3008         ni_set_bits(dev, Interrupt_B_Enable_Register,
3009                     AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
3010         interrupt_b_bits = AO_Error_Interrupt_Enable;
3011 #ifdef PCIDMA
3012         devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
3013         if (board->reg_type & ni_reg_6xxx_mask)
3014                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
3015         ret = ni_ao_setup_MITE_dma(dev);
3016         if (ret)
3017                 return ret;
3018         ret = ni_ao_wait_for_dma_load(dev);
3019         if (ret < 0)
3020                 return ret;
3021 #else
3022         ret = ni_ao_prep_fifo(dev, s);
3023         if (ret == 0)
3024                 return -EPIPE;
3025
3026         interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
3027 #endif
3028
3029         devpriv->stc_writew(dev, devpriv->ao_mode3 | AO_Not_An_UPDATE,
3030                             AO_Mode_3_Register);
3031         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3032         /* wait for DACs to be loaded */
3033         for (i = 0; i < timeout; i++) {
3034                 udelay(1);
3035                 if ((devpriv->stc_readw(dev,
3036                                         Joint_Status_2_Register) &
3037                      AO_TMRDACWRs_In_Progress_St) == 0)
3038                         break;
3039         }
3040         if (i == timeout) {
3041                 comedi_error(dev,
3042                              "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear");
3043                 return -EIO;
3044         }
3045         /*  stc manual says we are need to clear error interrupt after AO_TMRDACWRs_In_Progress_St clears */
3046         devpriv->stc_writew(dev, AO_Error_Interrupt_Ack,
3047                             Interrupt_B_Ack_Register);
3048
3049         ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
3050
3051         devpriv->stc_writew(dev,
3052                             devpriv->ao_cmd1 | AO_UI_Arm | AO_UC_Arm | AO_BC_Arm
3053                             | AO_DAC1_Update_Mode | AO_DAC0_Update_Mode,
3054                             AO_Command_1_Register);
3055
3056         devpriv->stc_writew(dev, devpriv->ao_cmd2 | AO_START1_Pulse,
3057                             AO_Command_2_Register);
3058
3059         return 0;
3060 }
3061
3062 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3063 {
3064         const struct ni_board_struct *board = comedi_board(dev);
3065         struct ni_private *devpriv = dev->private;
3066         const struct comedi_cmd *cmd = &s->async->cmd;
3067         int bits;
3068         int i;
3069         unsigned trigvar;
3070
3071         if (dev->irq == 0) {
3072                 comedi_error(dev, "cannot run command without an irq");
3073                 return -EIO;
3074         }
3075
3076         devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3077
3078         devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3079
3080         if (board->reg_type & ni_reg_6xxx_mask) {
3081                 ao_win_out(CLEAR_WG, AO_Misc_611x);
3082
3083                 bits = 0;
3084                 for (i = 0; i < cmd->chanlist_len; i++) {
3085                         int chan;
3086
3087                         chan = CR_CHAN(cmd->chanlist[i]);
3088                         bits |= 1 << chan;
3089                         ao_win_out(chan, AO_Waveform_Generation_611x);
3090                 }
3091                 ao_win_out(bits, AO_Timed_611x);
3092         }
3093
3094         ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3095
3096         if (cmd->stop_src == TRIG_NONE) {
3097                 devpriv->ao_mode1 |= AO_Continuous;
3098                 devpriv->ao_mode1 &= ~AO_Trigger_Once;
3099         } else {
3100                 devpriv->ao_mode1 &= ~AO_Continuous;
3101                 devpriv->ao_mode1 |= AO_Trigger_Once;
3102         }
3103         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3104         switch (cmd->start_src) {
3105         case TRIG_INT:
3106         case TRIG_NOW:
3107                 devpriv->ao_trigger_select &=
3108                     ~(AO_START1_Polarity | AO_START1_Select(-1));
3109                 devpriv->ao_trigger_select |= AO_START1_Edge | AO_START1_Sync;
3110                 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3111                                     AO_Trigger_Select_Register);
3112                 break;
3113         case TRIG_EXT:
3114                 devpriv->ao_trigger_select =
3115                     AO_START1_Select(CR_CHAN(cmd->start_arg) + 1);
3116                 if (cmd->start_arg & CR_INVERT)
3117                         devpriv->ao_trigger_select |= AO_START1_Polarity;       /*  0=active high, 1=active low. see daq-stc 3-24 (p186) */
3118                 if (cmd->start_arg & CR_EDGE)
3119                         devpriv->ao_trigger_select |= AO_START1_Edge;   /*  0=edge detection disabled, 1=enabled */
3120                 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3121                                     AO_Trigger_Select_Register);
3122                 break;
3123         default:
3124                 BUG();
3125                 break;
3126         }
3127         devpriv->ao_mode3 &= ~AO_Trigger_Length;
3128         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3129
3130         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3131         devpriv->ao_mode2 &= ~AO_BC_Initial_Load_Source;
3132         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3133         if (cmd->stop_src == TRIG_NONE) {
3134                 devpriv->stc_writel(dev, 0xffffff, AO_BC_Load_A_Register);
3135         } else {
3136                 devpriv->stc_writel(dev, 0, AO_BC_Load_A_Register);
3137         }
3138         devpriv->stc_writew(dev, AO_BC_Load, AO_Command_1_Register);
3139         devpriv->ao_mode2 &= ~AO_UC_Initial_Load_Source;
3140         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3141         switch (cmd->stop_src) {
3142         case TRIG_COUNT:
3143                 if (board->reg_type & ni_reg_m_series_mask) {
3144                         /*  this is how the NI example code does it for m-series boards, verified correct with 6259 */
3145                         devpriv->stc_writel(dev, cmd->stop_arg - 1,
3146                                             AO_UC_Load_A_Register);
3147                         devpriv->stc_writew(dev, AO_UC_Load,
3148                                             AO_Command_1_Register);
3149                 } else {
3150                         devpriv->stc_writel(dev, cmd->stop_arg,
3151                                             AO_UC_Load_A_Register);
3152                         devpriv->stc_writew(dev, AO_UC_Load,
3153                                             AO_Command_1_Register);
3154                         devpriv->stc_writel(dev, cmd->stop_arg - 1,
3155                                             AO_UC_Load_A_Register);
3156                 }
3157                 break;
3158         case TRIG_NONE:
3159                 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3160                 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3161                 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3162                 break;
3163         default:
3164                 devpriv->stc_writel(dev, 0, AO_UC_Load_A_Register);
3165                 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3166                 devpriv->stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register);
3167         }
3168
3169         devpriv->ao_mode1 &=
3170             ~(AO_UI_Source_Select(0x1f) | AO_UI_Source_Polarity |
3171               AO_UPDATE_Source_Select(0x1f) | AO_UPDATE_Source_Polarity);
3172         switch (cmd->scan_begin_src) {
3173         case TRIG_TIMER:
3174                 devpriv->ao_cmd2 &= ~AO_BC_Gate_Enable;
3175                 trigvar =
3176                     ni_ns_to_timer(dev, cmd->scan_begin_arg,
3177                                    TRIG_ROUND_NEAREST);
3178                 devpriv->stc_writel(dev, 1, AO_UI_Load_A_Register);
3179                 devpriv->stc_writew(dev, AO_UI_Load, AO_Command_1_Register);
3180                 devpriv->stc_writel(dev, trigvar, AO_UI_Load_A_Register);
3181                 break;
3182         case TRIG_EXT:
3183                 devpriv->ao_mode1 |=
3184                     AO_UPDATE_Source_Select(cmd->scan_begin_arg);
3185                 if (cmd->scan_begin_arg & CR_INVERT)
3186                         devpriv->ao_mode1 |= AO_UPDATE_Source_Polarity;
3187                 devpriv->ao_cmd2 |= AO_BC_Gate_Enable;
3188                 break;
3189         default:
3190                 BUG();
3191                 break;
3192         }
3193         devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3194         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3195         devpriv->ao_mode2 &=
3196             ~(AO_UI_Reload_Mode(3) | AO_UI_Initial_Load_Source);
3197         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3198
3199         if (cmd->scan_end_arg > 1) {
3200                 devpriv->ao_mode1 |= AO_Multiple_Channels;
3201                 devpriv->stc_writew(dev,
3202                                     AO_Number_Of_Channels(cmd->scan_end_arg -
3203                                                           1) |
3204                                     AO_UPDATE_Output_Select
3205                                     (AO_Update_Output_High_Z),
3206                                     AO_Output_Control_Register);
3207         } else {
3208                 unsigned bits;
3209                 devpriv->ao_mode1 &= ~AO_Multiple_Channels;
3210                 bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z);
3211                 if (board->reg_type &
3212                     (ni_reg_m_series_mask | ni_reg_6xxx_mask)) {
3213                         bits |= AO_Number_Of_Channels(0);
3214                 } else {
3215                         bits |=
3216                             AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0]));
3217                 }
3218                 devpriv->stc_writew(dev, bits, AO_Output_Control_Register);
3219         }
3220         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3221
3222         devpriv->stc_writew(dev, AO_DAC0_Update_Mode | AO_DAC1_Update_Mode,
3223                             AO_Command_1_Register);
3224
3225         devpriv->ao_mode3 |= AO_Stop_On_Overrun_Error;
3226         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3227
3228         devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask;
3229 #ifdef PCIDMA
3230         devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;
3231 #else
3232         devpriv->ao_mode2 |= AO_FIFO_Mode_HF;
3233 #endif
3234         devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;
3235         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3236
3237         bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3238             AO_TMRDACWR_Pulse_Width;
3239         if (board->ao_fifo_depth)
3240                 bits |= AO_FIFO_Enable;
3241         else
3242                 bits |= AO_DMA_PIO_Control;
3243 #if 0
3244         /* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281,
3245            verified with bus analyzer. */
3246         if (board->reg_type & ni_reg_m_series_mask)
3247                 bits |= AO_Number_Of_DAC_Packages;
3248 #endif
3249         devpriv->stc_writew(dev, bits, AO_Personal_Register);
3250         /*  enable sending of ao dma requests */
3251         devpriv->stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
3252
3253         devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3254
3255         if (cmd->stop_src == TRIG_COUNT) {
3256                 devpriv->stc_writew(dev, AO_BC_TC_Interrupt_Ack,
3257                                     Interrupt_B_Ack_Register);
3258                 ni_set_bits(dev, Interrupt_B_Enable_Register,
3259                             AO_BC_TC_Interrupt_Enable, 1);
3260         }
3261
3262         s->async->inttrig = &ni_ao_inttrig;
3263
3264         return 0;
3265 }
3266
3267 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3268                          struct comedi_cmd *cmd)
3269 {
3270         const struct ni_board_struct *board = comedi_board(dev);
3271         struct ni_private *devpriv = dev->private;
3272         int err = 0;
3273         int tmp;
3274
3275         /* Step 1 : check if triggers are trivially valid */
3276
3277         if ((cmd->flags & CMDF_WRITE) == 0)
3278                 cmd->flags |= CMDF_WRITE;
3279
3280         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3281         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
3282                                         TRIG_TIMER | TRIG_EXT);
3283         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3284         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3285         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3286
3287         if (err)
3288                 return 1;
3289
3290         /* Step 2a : make sure trigger sources are unique */
3291
3292         err |= cfc_check_trigger_is_unique(cmd->start_src);
3293         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
3294         err |= cfc_check_trigger_is_unique(cmd->stop_src);
3295
3296         /* Step 2b : and mutually compatible */
3297
3298         if (err)
3299                 return 2;
3300
3301         /* Step 3: check if arguments are trivially valid */
3302
3303         if (cmd->start_src == TRIG_EXT) {
3304                 /* external trigger */
3305                 unsigned int tmp = CR_CHAN(cmd->start_arg);
3306
3307                 if (tmp > 18)
3308                         tmp = 18;
3309                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3310                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, tmp);
3311         } else {
3312                 /* true for both TRIG_NOW and TRIG_INT */
3313                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3314         }
3315
3316         if (cmd->scan_begin_src == TRIG_TIMER) {
3317                 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
3318                                                  board->ao_speed);
3319                 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
3320                                                  devpriv->clock_ns * 0xffffff);
3321         }
3322
3323         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
3324         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3325
3326         if (cmd->stop_src == TRIG_COUNT)
3327                 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3328         else    /* TRIG_NONE */
3329                 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
3330
3331         if (err)
3332                 return 3;
3333
3334         /* step 4: fix up any arguments */
3335         if (cmd->scan_begin_src == TRIG_TIMER) {
3336                 tmp = cmd->scan_begin_arg;
3337                 cmd->scan_begin_arg =
3338                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3339                                                        cmd->scan_begin_arg,
3340                                                        cmd->
3341                                                        flags &
3342                                                        TRIG_ROUND_MASK));
3343                 if (tmp != cmd->scan_begin_arg)
3344                         err++;
3345         }
3346         if (err)
3347                 return 4;
3348
3349         /* step 5: fix up chanlist */
3350
3351         if (err)
3352                 return 5;
3353
3354         return 0;
3355 }
3356
3357 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3358 {
3359         const struct ni_board_struct *board = comedi_board(dev);
3360         struct ni_private *devpriv = dev->private;
3361
3362         /* devpriv->ao0p=0x0000; */
3363         /* ni_writew(devpriv->ao0p,AO_Configuration); */
3364
3365         /* devpriv->ao1p=AO_Channel(1); */
3366         /* ni_writew(devpriv->ao1p,AO_Configuration); */
3367
3368         ni_release_ao_mite_channel(dev);
3369
3370         devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3371         devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3372         ni_set_bits(dev, Interrupt_B_Enable_Register, ~0, 0);
3373         devpriv->stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
3374         devpriv->stc_writew(dev, 0x3f98, Interrupt_B_Ack_Register);
3375         devpriv->stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3376                             AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
3377         devpriv->stc_writew(dev, 0, AO_Output_Control_Register);
3378         devpriv->stc_writew(dev, 0, AO_Start_Select_Register);
3379         devpriv->ao_cmd1 = 0;
3380         devpriv->stc_writew(dev, devpriv->ao_cmd1, AO_Command_1_Register);
3381         devpriv->ao_cmd2 = 0;
3382         devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3383         devpriv->ao_mode1 = 0;
3384         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3385         devpriv->ao_mode2 = 0;
3386         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3387         if (board->reg_type & ni_reg_m_series_mask)
3388                 devpriv->ao_mode3 = AO_Last_Gate_Disable;
3389         else
3390                 devpriv->ao_mode3 = 0;
3391         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3392         devpriv->ao_trigger_select = 0;
3393         devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3394                             AO_Trigger_Select_Register);
3395         if (board->reg_type & ni_reg_6xxx_mask) {
3396                 unsigned immediate_bits = 0;
3397                 unsigned i;
3398                 for (i = 0; i < s->n_chan; ++i) {
3399                         immediate_bits |= 1 << i;
3400                 }
3401                 ao_win_out(immediate_bits, AO_Immediate_671x);
3402                 ao_win_out(CLEAR_WG, AO_Misc_611x);
3403         }
3404         devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3405
3406         return 0;
3407 }
3408
3409 /* digital io */
3410
3411 static int ni_dio_insn_config(struct comedi_device *dev,
3412                               struct comedi_subdevice *s,
3413                               struct comedi_insn *insn,
3414                               unsigned int *data)
3415 {
3416         struct ni_private *devpriv = dev->private;
3417         int ret;
3418
3419         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3420         if (ret)
3421                 return ret;
3422
3423         devpriv->dio_control &= ~DIO_Pins_Dir_Mask;
3424         devpriv->dio_control |= DIO_Pins_Dir(s->io_bits);
3425         devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3426
3427         return insn->n;
3428 }
3429
3430 static int ni_dio_insn_bits(struct comedi_device *dev,
3431                             struct comedi_subdevice *s,
3432                             struct comedi_insn *insn,
3433                             unsigned int *data)
3434 {
3435         struct ni_private *devpriv = dev->private;
3436
3437         /* Make sure we're not using the serial part of the dio */
3438         if ((data[0] & (DIO_SDIN | DIO_SDOUT)) && devpriv->serial_interval_ns)
3439                 return -EBUSY;
3440
3441         if (comedi_dio_update_state(s, data)) {
3442                 devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
3443                 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
3444                 devpriv->stc_writew(dev, devpriv->dio_output,
3445                                     DIO_Output_Register);
3446         }
3447
3448         data[1] = devpriv->stc_readw(dev, DIO_Parallel_Input_Register);
3449
3450         return insn->n;
3451 }
3452
3453 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3454                                        struct comedi_subdevice *s,
3455                                        struct comedi_insn *insn,
3456                                        unsigned int *data)
3457 {
3458         struct ni_private *devpriv __maybe_unused = dev->private;
3459         int ret;
3460
3461         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3462         if (ret)
3463                 return ret;
3464
3465         ni_writel(s->io_bits, M_Offset_DIO_Direction);
3466
3467         return insn->n;
3468 }
3469
3470 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3471                                      struct comedi_subdevice *s,
3472                                      struct comedi_insn *insn,
3473                                      unsigned int *data)
3474 {
3475         struct ni_private *devpriv __maybe_unused = dev->private;
3476
3477         if (comedi_dio_update_state(s, data))
3478                 ni_writel(s->state, M_Offset_Static_Digital_Output);
3479
3480         data[1] = ni_readl(M_Offset_Static_Digital_Input);
3481
3482         return insn->n;
3483 }
3484
3485 static int ni_cdio_cmdtest(struct comedi_device *dev,
3486                            struct comedi_subdevice *s, struct comedi_cmd *cmd)
3487 {
3488         int err = 0;
3489         int tmp;
3490         unsigned i;
3491
3492         /* Step 1 : check if triggers are trivially valid */
3493
3494         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT);
3495         err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3496         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3497         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3498         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3499
3500         if (err)
3501                 return 1;
3502
3503         /* Step 2a : make sure trigger sources are unique */
3504         /* Step 2b : and mutually compatible */
3505
3506         if (err)
3507                 return 2;
3508
3509         /* Step 3: check if arguments are trivially valid */
3510
3511         err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3512
3513         tmp = cmd->scan_begin_arg;
3514         tmp &= CR_PACK_FLAGS(CDO_Sample_Source_Select_Mask, 0, 0, CR_INVERT);
3515         if (tmp != cmd->scan_begin_arg)
3516                 err |= -EINVAL;
3517
3518         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
3519         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3520         err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
3521
3522         if (err)
3523                 return 3;
3524
3525         /* step 4: fix up any arguments */
3526
3527         if (err)
3528                 return 4;
3529
3530         /* step 5: check chanlist */
3531
3532         for (i = 0; i < cmd->chanlist_len; ++i) {
3533                 if (cmd->chanlist[i] != i)
3534                         err = 1;
3535         }
3536
3537         if (err)
3538                 return 5;
3539
3540         return 0;
3541 }
3542
3543 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3544 {
3545         struct ni_private *devpriv __maybe_unused = dev->private;
3546         const struct comedi_cmd *cmd = &s->async->cmd;
3547         unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit;
3548         int retval;
3549
3550         ni_writel(CDO_Reset_Bit, M_Offset_CDIO_Command);
3551         switch (cmd->scan_begin_src) {
3552         case TRIG_EXT:
3553                 cdo_mode_bits |=
3554                     CR_CHAN(cmd->scan_begin_arg) &
3555                     CDO_Sample_Source_Select_Mask;
3556                 break;
3557         default:
3558                 BUG();
3559                 break;
3560         }
3561         if (cmd->scan_begin_arg & CR_INVERT)
3562                 cdo_mode_bits |= CDO_Polarity_Bit;
3563         ni_writel(cdo_mode_bits, M_Offset_CDO_Mode);
3564         if (s->io_bits) {
3565                 ni_writel(s->state, M_Offset_CDO_FIFO_Data);
3566                 ni_writel(CDO_SW_Update_Bit, M_Offset_CDIO_Command);
3567                 ni_writel(s->io_bits, M_Offset_CDO_Mask_Enable);
3568         } else {
3569                 comedi_error(dev,
3570                              "attempted to run digital output command with no lines configured as outputs");
3571                 return -EIO;
3572         }
3573         retval = ni_request_cdo_mite_channel(dev);
3574         if (retval < 0) {
3575                 return retval;
3576         }
3577         s->async->inttrig = &ni_cdo_inttrig;
3578         return 0;
3579 }
3580
3581 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3582                           unsigned int trignum)
3583 {
3584 #ifdef PCIDMA
3585         struct ni_private *devpriv = dev->private;
3586         unsigned long flags;
3587 #endif
3588         int retval = 0;
3589         unsigned i;
3590         const unsigned timeout = 1000;
3591
3592         s->async->inttrig = NULL;
3593
3594         /* read alloc the entire buffer */
3595         comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
3596
3597 #ifdef PCIDMA
3598         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3599         if (devpriv->cdo_mite_chan) {
3600                 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3601                 mite_dma_arm(devpriv->cdo_mite_chan);
3602         } else {
3603                 comedi_error(dev, "BUG: no cdo mite channel?");
3604                 retval = -EIO;
3605         }
3606         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3607         if (retval < 0)
3608                 return retval;
3609 #endif
3610 /*
3611 * XXX not sure what interrupt C group does
3612 * ni_writeb(Interrupt_Group_C_Enable_Bit,
3613 * M_Offset_Interrupt_C_Enable); wait for dma to fill output fifo
3614 */
3615         for (i = 0; i < timeout; ++i) {
3616                 if (ni_readl(M_Offset_CDIO_Status) & CDO_FIFO_Full_Bit)
3617                         break;
3618                 udelay(10);
3619         }
3620         if (i == timeout) {
3621                 comedi_error(dev, "dma failed to fill cdo fifo!");
3622                 ni_cdio_cancel(dev, s);
3623                 return -EIO;
3624         }
3625         ni_writel(CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit |
3626                   CDO_Empty_FIFO_Interrupt_Enable_Set_Bit,
3627                   M_Offset_CDIO_Command);
3628         return retval;
3629 }
3630
3631 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3632 {
3633         struct ni_private *devpriv __maybe_unused = dev->private;
3634
3635         ni_writel(CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit |
3636                   CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit |
3637                   CDO_FIFO_Request_Interrupt_Enable_Clear_Bit,
3638                   M_Offset_CDIO_Command);
3639 /*
3640 * XXX not sure what interrupt C group does ni_writeb(0,
3641 * M_Offset_Interrupt_C_Enable);
3642 */
3643         ni_writel(0, M_Offset_CDO_Mask_Enable);
3644         ni_release_cdo_mite_channel(dev);
3645         return 0;
3646 }
3647
3648 static void handle_cdio_interrupt(struct comedi_device *dev)
3649 {
3650         const struct ni_board_struct *board = comedi_board(dev);
3651         struct ni_private *devpriv __maybe_unused = dev->private;
3652         unsigned cdio_status;
3653         struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3654 #ifdef PCIDMA
3655         unsigned long flags;
3656 #endif
3657
3658         if ((board->reg_type & ni_reg_m_series_mask) == 0) {
3659                 return;
3660         }
3661 #ifdef PCIDMA
3662         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3663         if (devpriv->cdo_mite_chan) {
3664                 unsigned cdo_mite_status =
3665                     mite_get_status(devpriv->cdo_mite_chan);
3666                 if (cdo_mite_status & CHSR_LINKC) {
3667                         writel(CHOR_CLRLC,
3668                                devpriv->mite->mite_io_addr +
3669                                MITE_CHOR(devpriv->cdo_mite_chan->channel));
3670                 }
3671                 mite_sync_output_dma(devpriv->cdo_mite_chan, s->async);
3672         }
3673         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3674 #endif
3675
3676         cdio_status = ni_readl(M_Offset_CDIO_Status);
3677         if (cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit)) {
3678 /* printk("cdio error: statux=0x%x\n", cdio_status); */
3679                 ni_writel(CDO_Error_Interrupt_Confirm_Bit, M_Offset_CDIO_Command);      /*  XXX just guessing this is needed and does something useful */
3680                 s->async->events |= COMEDI_CB_OVERFLOW;
3681         }
3682         if (cdio_status & CDO_FIFO_Empty_Bit) {
3683 /* printk("cdio fifo empty\n"); */
3684                 ni_writel(CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit,
3685                           M_Offset_CDIO_Command);
3686 /* s->async->events |= COMEDI_CB_EOA; */
3687         }
3688         ni_event(dev, s);
3689 }
3690
3691 static int ni_serial_insn_config(struct comedi_device *dev,
3692                                  struct comedi_subdevice *s,
3693                                  struct comedi_insn *insn, unsigned int *data)
3694 {
3695         struct ni_private *devpriv = dev->private;
3696         int err = insn->n;
3697         unsigned char byte_out, byte_in = 0;
3698
3699         if (insn->n != 2)
3700                 return -EINVAL;
3701
3702         switch (data[0]) {
3703         case INSN_CONFIG_SERIAL_CLOCK:
3704                 devpriv->serial_hw_mode = 1;
3705                 devpriv->dio_control |= DIO_HW_Serial_Enable;
3706
3707                 if (data[1] == SERIAL_DISABLED) {
3708                         devpriv->serial_hw_mode = 0;
3709                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3710                                                   DIO_Software_Serial_Control);
3711                         data[1] = SERIAL_DISABLED;
3712                         devpriv->serial_interval_ns = data[1];
3713                 } else if (data[1] <= SERIAL_600NS) {
3714                         /* Warning: this clock speed is too fast to reliably
3715                            control SCXI. */
3716                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3717                         devpriv->clock_and_fout |= Slow_Internal_Timebase;
3718                         devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
3719                         data[1] = SERIAL_600NS;
3720                         devpriv->serial_interval_ns = data[1];
3721                 } else if (data[1] <= SERIAL_1_2US) {
3722                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3723                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
3724                             DIO_Serial_Out_Divide_By_2;
3725                         data[1] = SERIAL_1_2US;
3726                         devpriv->serial_interval_ns = data[1];
3727                 } else if (data[1] <= SERIAL_10US) {
3728                         devpriv->dio_control |= DIO_HW_Serial_Timebase;
3729                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
3730                             DIO_Serial_Out_Divide_By_2;
3731                         /* Note: DIO_Serial_Out_Divide_By_2 only affects
3732                            600ns/1.2us. If you turn divide_by_2 off with the
3733                            slow clock, you will still get 10us, except then
3734                            all your delays are wrong. */
3735                         data[1] = SERIAL_10US;
3736                         devpriv->serial_interval_ns = data[1];
3737                 } else {
3738                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3739                                                   DIO_Software_Serial_Control);
3740                         devpriv->serial_hw_mode = 0;
3741                         data[1] = (data[1] / 1000) * 1000;
3742                         devpriv->serial_interval_ns = data[1];
3743                 }
3744
3745                 devpriv->stc_writew(dev, devpriv->dio_control,
3746                                     DIO_Control_Register);
3747                 devpriv->stc_writew(dev, devpriv->clock_and_fout,
3748                                     Clock_and_FOUT_Register);
3749                 return 1;
3750
3751                 break;
3752
3753         case INSN_CONFIG_BIDIRECTIONAL_DATA:
3754
3755                 if (devpriv->serial_interval_ns == 0) {
3756                         return -EINVAL;
3757                 }
3758
3759                 byte_out = data[1] & 0xFF;
3760
3761                 if (devpriv->serial_hw_mode) {
3762                         err = ni_serial_hw_readwrite8(dev, s, byte_out,
3763                                                       &byte_in);
3764                 } else if (devpriv->serial_interval_ns > 0) {
3765                         err = ni_serial_sw_readwrite8(dev, s, byte_out,
3766                                                       &byte_in);
3767                 } else {
3768                         printk("ni_serial_insn_config: serial disabled!\n");
3769                         return -EINVAL;
3770                 }
3771                 if (err < 0)
3772                         return err;
3773                 data[1] = byte_in & 0xFF;
3774                 return insn->n;
3775
3776                 break;
3777         default:
3778                 return -EINVAL;
3779         }
3780
3781 }
3782
3783 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3784                                    struct comedi_subdevice *s,
3785                                    unsigned char data_out,
3786                                    unsigned char *data_in)
3787 {
3788         struct ni_private *devpriv = dev->private;
3789         unsigned int status1;
3790         int err = 0, count = 20;
3791
3792         devpriv->dio_output &= ~DIO_Serial_Data_Mask;
3793         devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
3794         devpriv->stc_writew(dev, devpriv->dio_output, DIO_Output_Register);
3795
3796         status1 = devpriv->stc_readw(dev, Joint_Status_1_Register);
3797         if (status1 & DIO_Serial_IO_In_Progress_St) {
3798                 err = -EBUSY;
3799                 goto Error;
3800         }
3801
3802         devpriv->dio_control |= DIO_HW_Serial_Start;
3803         devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3804         devpriv->dio_control &= ~DIO_HW_Serial_Start;
3805
3806         /* Wait until STC says we're done, but don't loop infinitely. */
3807         while ((status1 =
3808                 devpriv->stc_readw(dev,
3809                                    Joint_Status_1_Register)) &
3810                DIO_Serial_IO_In_Progress_St) {
3811                 /* Delay one bit per loop */
3812                 udelay((devpriv->serial_interval_ns + 999) / 1000);
3813                 if (--count < 0) {
3814                         printk
3815                             ("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n");
3816                         err = -ETIME;
3817                         goto Error;
3818                 }
3819         }
3820
3821         /* Delay for last bit. This delay is absolutely necessary, because
3822            DIO_Serial_IO_In_Progress_St goes high one bit too early. */
3823         udelay((devpriv->serial_interval_ns + 999) / 1000);
3824
3825         if (data_in != NULL)
3826                 *data_in = devpriv->stc_readw(dev, DIO_Serial_Input_Register);
3827
3828 Error:
3829         devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3830
3831         return err;
3832 }
3833
3834 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
3835                                    struct comedi_subdevice *s,
3836                                    unsigned char data_out,
3837                                    unsigned char *data_in)
3838 {
3839         struct ni_private *devpriv = dev->private;
3840         unsigned char mask, input = 0;
3841
3842         /* Wait for one bit before transfer */
3843         udelay((devpriv->serial_interval_ns + 999) / 1000);
3844
3845         for (mask = 0x80; mask; mask >>= 1) {
3846                 /* Output current bit; note that we cannot touch s->state
3847                    because it is a per-subdevice field, and serial is
3848                    a separate subdevice from DIO. */
3849                 devpriv->dio_output &= ~DIO_SDOUT;
3850                 if (data_out & mask) {
3851                         devpriv->dio_output |= DIO_SDOUT;
3852                 }
3853                 devpriv->stc_writew(dev, devpriv->dio_output,
3854                                     DIO_Output_Register);
3855
3856                 /* Assert SDCLK (active low, inverted), wait for half of
3857                    the delay, deassert SDCLK, and wait for the other half. */
3858                 devpriv->dio_control |= DIO_Software_Serial_Control;
3859                 devpriv->stc_writew(dev, devpriv->dio_control,
3860                                     DIO_Control_Register);
3861
3862                 udelay((devpriv->serial_interval_ns + 999) / 2000);
3863
3864                 devpriv->dio_control &= ~DIO_Software_Serial_Control;
3865                 devpriv->stc_writew(dev, devpriv->dio_control,
3866                                     DIO_Control_Register);
3867
3868                 udelay((devpriv->serial_interval_ns + 999) / 2000);
3869
3870                 /* Input current bit */
3871                 if (devpriv->stc_readw(dev,
3872                                        DIO_Parallel_Input_Register) & DIO_SDIN)
3873                 {
3874 /*                      printk("DIO_P_I_R: 0x%x\n", devpriv->stc_readw(dev, DIO_Parallel_Input_Register)); */
3875                         input |= mask;
3876                 }
3877         }
3878
3879         if (data_in)
3880                 *data_in = input;
3881
3882         return 0;
3883 }
3884
3885 static void mio_common_detach(struct comedi_device *dev)
3886 {
3887         struct ni_private *devpriv = dev->private;
3888
3889         if (devpriv) {
3890                 if (devpriv->counter_dev) {
3891                         ni_gpct_device_destroy(devpriv->counter_dev);
3892                 }
3893         }
3894 }
3895
3896 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
3897 {
3898         int i;
3899
3900         for (i = 0; i < s->n_chan; i++) {
3901                 ni_ao_win_outw(dev, AO_Channel(i) | 0x0,
3902                                AO_Configuration_2_67xx);
3903         }
3904         ao_win_out(0x0, AO_Later_Single_Point_Updates);
3905 }
3906
3907 static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg)
3908 {
3909         unsigned stc_register;
3910         switch (reg) {
3911         case NITIO_G0_AUTO_INC:
3912                 stc_register = G_Autoincrement_Register(0);
3913                 break;
3914         case NITIO_G1_AUTO_INC:
3915                 stc_register = G_Autoincrement_Register(1);
3916                 break;
3917         case NITIO_G0_CMD:
3918                 stc_register = G_Command_Register(0);
3919                 break;
3920         case NITIO_G1_CMD:
3921                 stc_register = G_Command_Register(1);
3922                 break;
3923         case NITIO_G0_HW_SAVE:
3924                 stc_register = G_HW_Save_Register(0);
3925                 break;
3926         case NITIO_G1_HW_SAVE:
3927                 stc_register = G_HW_Save_Register(1);
3928                 break;
3929         case NITIO_G0_SW_SAVE:
3930                 stc_register = G_Save_Register(0);
3931                 break;
3932         case NITIO_G1_SW_SAVE:
3933                 stc_register = G_Save_Register(1);
3934                 break;
3935         case NITIO_G0_MODE:
3936                 stc_register = G_Mode_Register(0);
3937                 break;
3938         case NITIO_G1_MODE:
3939                 stc_register = G_Mode_Register(1);
3940                 break;
3941         case NITIO_G0_LOADA:
3942                 stc_register = G_Load_A_Register(0);
3943                 break;
3944         case NITIO_G1_LOADA:
3945                 stc_register = G_Load_A_Register(1);
3946                 break;
3947         case NITIO_G0_LOADB:
3948                 stc_register = G_Load_B_Register(0);
3949                 break;
3950         case NITIO_G1_LOADB:
3951                 stc_register = G_Load_B_Register(1);
3952                 break;
3953         case NITIO_G0_INPUT_SEL:
3954                 stc_register = G_Input_Select_Register(0);
3955                 break;
3956         case NITIO_G1_INPUT_SEL:
3957                 stc_register = G_Input_Select_Register(1);
3958                 break;
3959         case NITIO_G01_STATUS:
3960                 stc_register = G_Status_Register;
3961                 break;
3962         case NITIO_G01_RESET:
3963                 stc_register = Joint_Reset_Register;
3964                 break;
3965         case NITIO_G01_STATUS1:
3966                 stc_register = Joint_Status_1_Register;
3967                 break;
3968         case NITIO_G01_STATUS2:
3969                 stc_register = Joint_Status_2_Register;
3970                 break;
3971         case NITIO_G0_INT_ACK:
3972                 stc_register = Interrupt_A_Ack_Register;
3973                 break;
3974         case NITIO_G1_INT_ACK:
3975                 stc_register = Interrupt_B_Ack_Register;
3976                 break;
3977         case NITIO_G0_STATUS:
3978                 stc_register = AI_Status_1_Register;
3979                 break;
3980         case NITIO_G1_STATUS:
3981                 stc_register = AO_Status_1_Register;
3982                 break;
3983         case NITIO_G0_INT_ENA:
3984                 stc_register = Interrupt_A_Enable_Register;
3985                 break;
3986         case NITIO_G1_INT_ENA:
3987                 stc_register = Interrupt_B_Enable_Register;
3988                 break;
3989         default:
3990                 printk("%s: unhandled register 0x%x in switch.\n",
3991                        __func__, reg);
3992                 BUG();
3993                 return 0;
3994                 break;
3995         }
3996         return stc_register;
3997 }
3998
3999 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
4000                                    enum ni_gpct_register reg)
4001 {
4002         struct comedi_device *dev = counter->counter_dev->dev;
4003         struct ni_private *devpriv = dev->private;
4004         unsigned stc_register;
4005         /* bits in the join reset register which are relevant to counters */
4006         static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset;
4007         static const unsigned gpct_interrupt_a_enable_mask =
4008             G0_Gate_Interrupt_Enable | G0_TC_Interrupt_Enable;
4009         static const unsigned gpct_interrupt_b_enable_mask =
4010             G1_Gate_Interrupt_Enable | G1_TC_Interrupt_Enable;
4011
4012         switch (reg) {
4013                 /* m-series-only registers */
4014         case NITIO_G0_CNT_MODE:
4015                 ni_writew(bits, M_Offset_G0_Counting_Mode);
4016                 break;
4017         case NITIO_G1_CNT_MODE:
4018                 ni_writew(bits, M_Offset_G1_Counting_Mode);
4019                 break;
4020         case NITIO_G0_GATE2:
4021                 ni_writew(bits, M_Offset_G0_Second_Gate);
4022                 break;
4023         case NITIO_G1_GATE2:
4024                 ni_writew(bits, M_Offset_G1_Second_Gate);
4025                 break;
4026         case NITIO_G0_DMA_CFG:
4027                 ni_writew(bits, M_Offset_G0_DMA_Config);
4028                 break;
4029         case NITIO_G1_DMA_CFG:
4030                 ni_writew(bits, M_Offset_G1_DMA_Config);
4031                 break;
4032         case NITIO_G0_ABZ:
4033                 ni_writew(bits, M_Offset_G0_MSeries_ABZ);
4034                 break;
4035         case NITIO_G1_ABZ:
4036                 ni_writew(bits, M_Offset_G1_MSeries_ABZ);
4037                 break;
4038
4039                 /* 32 bit registers */
4040         case NITIO_G0_LOADA:
4041         case NITIO_G1_LOADA:
4042         case NITIO_G0_LOADB:
4043         case NITIO_G1_LOADB:
4044                 stc_register = ni_gpct_to_stc_register(reg);
4045                 devpriv->stc_writel(dev, bits, stc_register);
4046                 break;
4047
4048                 /* 16 bit registers */
4049         case NITIO_G0_INT_ENA:
4050                 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
4051                 ni_set_bitfield(dev, Interrupt_A_Enable_Register,
4052                                 gpct_interrupt_a_enable_mask, bits);
4053                 break;
4054         case NITIO_G1_INT_ENA:
4055                 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
4056                 ni_set_bitfield(dev, Interrupt_B_Enable_Register,
4057                                 gpct_interrupt_b_enable_mask, bits);
4058                 break;
4059         case NITIO_G01_RESET:
4060                 BUG_ON(bits & ~gpct_joint_reset_mask);
4061                 /* fall-through */
4062         default:
4063                 stc_register = ni_gpct_to_stc_register(reg);
4064                 devpriv->stc_writew(dev, bits, stc_register);
4065         }
4066 }
4067
4068 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
4069                                       enum ni_gpct_register reg)
4070 {
4071         struct comedi_device *dev = counter->counter_dev->dev;
4072         struct ni_private *devpriv = dev->private;
4073         unsigned stc_register;
4074
4075         switch (reg) {
4076                 /* m-series only registers */
4077         case NITIO_G0_DMA_STATUS:
4078                 return ni_readw(M_Offset_G0_DMA_Status);
4079         case NITIO_G1_DMA_STATUS:
4080                 return ni_readw(M_Offset_G1_DMA_Status);
4081
4082                 /* 32 bit registers */
4083         case NITIO_G0_HW_SAVE:
4084         case NITIO_G1_HW_SAVE:
4085         case NITIO_G0_SW_SAVE:
4086         case NITIO_G1_SW_SAVE:
4087                 stc_register = ni_gpct_to_stc_register(reg);
4088                 return devpriv->stc_readl(dev, stc_register);
4089
4090                 /* 16 bit registers */
4091         default:
4092                 stc_register = ni_gpct_to_stc_register(reg);
4093                 return devpriv->stc_readw(dev, stc_register);
4094                 break;
4095         }
4096         return 0;
4097 }
4098
4099 static int ni_freq_out_insn_read(struct comedi_device *dev,
4100                                  struct comedi_subdevice *s,
4101                                  struct comedi_insn *insn, unsigned int *data)
4102 {
4103         struct ni_private *devpriv = dev->private;
4104
4105         data[0] = devpriv->clock_and_fout & FOUT_Divider_mask;
4106         return 1;
4107 }
4108
4109 static int ni_freq_out_insn_write(struct comedi_device *dev,
4110                                   struct comedi_subdevice *s,
4111                                   struct comedi_insn *insn, unsigned int *data)
4112 {
4113         struct ni_private *devpriv = dev->private;
4114
4115         devpriv->clock_and_fout &= ~FOUT_Enable;
4116         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4117                             Clock_and_FOUT_Register);
4118         devpriv->clock_and_fout &= ~FOUT_Divider_mask;
4119         devpriv->clock_and_fout |= FOUT_Divider(data[0]);
4120         devpriv->clock_and_fout |= FOUT_Enable;
4121         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4122                             Clock_and_FOUT_Register);
4123         return insn->n;
4124 }
4125
4126 static int ni_set_freq_out_clock(struct comedi_device *dev,
4127                                  unsigned int clock_source)
4128 {
4129         struct ni_private *devpriv = dev->private;
4130
4131         switch (clock_source) {
4132         case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4133                 devpriv->clock_and_fout &= ~FOUT_Timebase_Select;
4134                 break;
4135         case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4136                 devpriv->clock_and_fout |= FOUT_Timebase_Select;
4137                 break;
4138         default:
4139                 return -EINVAL;
4140         }
4141         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4142                             Clock_and_FOUT_Register);
4143         return 3;
4144 }
4145
4146 static void ni_get_freq_out_clock(struct comedi_device *dev,
4147                                   unsigned int *clock_source,
4148                                   unsigned int *clock_period_ns)
4149 {
4150         struct ni_private *devpriv = dev->private;
4151
4152         if (devpriv->clock_and_fout & FOUT_Timebase_Select) {
4153                 *clock_source = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4154                 *clock_period_ns = TIMEBASE_2_NS;
4155         } else {
4156                 *clock_source = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4157                 *clock_period_ns = TIMEBASE_1_NS * 2;
4158         }
4159 }
4160
4161 static int ni_freq_out_insn_config(struct comedi_device *dev,
4162                                    struct comedi_subdevice *s,
4163                                    struct comedi_insn *insn, unsigned int *data)
4164 {
4165         switch (data[0]) {
4166         case INSN_CONFIG_SET_CLOCK_SRC:
4167                 return ni_set_freq_out_clock(dev, data[1]);
4168                 break;
4169         case INSN_CONFIG_GET_CLOCK_SRC:
4170                 ni_get_freq_out_clock(dev, &data[1], &data[2]);
4171                 return 3;
4172         default:
4173                 break;
4174         }
4175         return -EINVAL;
4176 }
4177
4178 static int ni_alloc_private(struct comedi_device *dev)
4179 {
4180         struct ni_private *devpriv;
4181
4182         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
4183         if (!devpriv)
4184                 return -ENOMEM;
4185
4186         spin_lock_init(&devpriv->window_lock);
4187         spin_lock_init(&devpriv->soft_reg_copy_lock);
4188         spin_lock_init(&devpriv->mite_channel_lock);
4189
4190         return 0;
4191 };
4192
4193 static int ni_E_init(struct comedi_device *dev)
4194 {
4195         const struct ni_board_struct *board = comedi_board(dev);
4196         struct ni_private *devpriv = dev->private;
4197         struct comedi_subdevice *s;
4198         unsigned j;
4199         enum ni_gpct_variant counter_variant;
4200         int ret;
4201
4202         if (board->n_aochan > MAX_N_AO_CHAN) {
4203                 printk("bug! n_aochan > MAX_N_AO_CHAN\n");
4204                 return -EINVAL;
4205         }
4206
4207         ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
4208         if (ret)
4209                 return ret;
4210
4211         /* analog input subdevice */
4212
4213         s = &dev->subdevices[NI_AI_SUBDEV];
4214         dev->read_subdev = s;
4215         if (board->n_adchan) {
4216                 s->type = COMEDI_SUBD_AI;
4217                 s->subdev_flags =
4218                     SDF_READABLE | SDF_DIFF | SDF_DITHER | SDF_CMD_READ;
4219                 if (board->reg_type != ni_reg_611x)
4220                         s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
4221                 if (board->adbits > 16)
4222                         s->subdev_flags |= SDF_LSAMPL;
4223                 if (board->reg_type & ni_reg_m_series_mask)
4224                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
4225                 s->n_chan = board->n_adchan;
4226                 s->len_chanlist = 512;
4227                 s->maxdata = (1 << board->adbits) - 1;
4228                 s->range_table = ni_range_lkup[board->gainlkup];
4229                 s->insn_read = &ni_ai_insn_read;
4230                 s->insn_config = &ni_ai_insn_config;
4231                 s->do_cmdtest = &ni_ai_cmdtest;
4232                 s->do_cmd = &ni_ai_cmd;
4233                 s->cancel = &ni_ai_reset;
4234                 s->poll = &ni_ai_poll;
4235                 s->munge = &ni_ai_munge;
4236 #ifdef PCIDMA
4237                 s->async_dma_dir = DMA_FROM_DEVICE;
4238 #endif
4239         } else {
4240                 s->type = COMEDI_SUBD_UNUSED;
4241         }
4242
4243         /* analog output subdevice */
4244
4245         s = &dev->subdevices[NI_AO_SUBDEV];
4246         if (board->n_aochan) {
4247                 s->type = COMEDI_SUBD_AO;
4248                 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
4249                 if (board->reg_type & ni_reg_m_series_mask)
4250                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
4251                 s->n_chan = board->n_aochan;
4252                 s->maxdata = (1 << board->aobits) - 1;
4253                 s->range_table = board->ao_range_table;
4254                 s->insn_read = &ni_ao_insn_read;
4255                 if (board->reg_type & ni_reg_6xxx_mask) {
4256                         s->insn_write = &ni_ao_insn_write_671x;
4257                 } else {
4258                         s->insn_write = &ni_ao_insn_write;
4259                 }
4260                 s->insn_config = &ni_ao_insn_config;
4261 #ifdef PCIDMA
4262                 if (board->n_aochan) {
4263                         s->async_dma_dir = DMA_TO_DEVICE;
4264 #else
4265                 if (board->ao_fifo_depth) {
4266 #endif
4267                         dev->write_subdev = s;
4268                         s->subdev_flags |= SDF_CMD_WRITE;
4269                         s->do_cmd = &ni_ao_cmd;
4270                         s->do_cmdtest = &ni_ao_cmdtest;
4271                         s->len_chanlist = board->n_aochan;
4272                         if ((board->reg_type & ni_reg_m_series_mask) == 0)
4273                                 s->munge = ni_ao_munge;
4274                 }
4275                 s->cancel = &ni_ao_reset;
4276         } else {
4277                 s->type = COMEDI_SUBD_UNUSED;
4278         }
4279         if ((board->reg_type & ni_reg_67xx_mask))
4280                 init_ao_67xx(dev, s);
4281
4282         /* digital i/o subdevice */
4283
4284         s = &dev->subdevices[NI_DIO_SUBDEV];
4285         s->type = COMEDI_SUBD_DIO;
4286         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
4287         s->maxdata = 1;
4288         s->io_bits = 0;         /* all bits input */
4289         s->range_table = &range_digital;
4290         s->n_chan = board->num_p0_dio_channels;
4291         if (board->reg_type & ni_reg_m_series_mask) {
4292                 s->subdev_flags |=
4293                     SDF_LSAMPL | SDF_CMD_WRITE /* | SDF_CMD_READ */ ;
4294                 s->insn_bits = &ni_m_series_dio_insn_bits;
4295                 s->insn_config = &ni_m_series_dio_insn_config;
4296                 s->do_cmd = &ni_cdio_cmd;
4297                 s->do_cmdtest = &ni_cdio_cmdtest;
4298                 s->cancel = &ni_cdio_cancel;
4299                 s->async_dma_dir = DMA_BIDIRECTIONAL;
4300                 s->len_chanlist = s->n_chan;
4301
4302                 ni_writel(CDO_Reset_Bit | CDI_Reset_Bit, M_Offset_CDIO_Command);
4303                 ni_writel(s->io_bits, M_Offset_DIO_Direction);
4304         } else {
4305                 s->insn_bits = &ni_dio_insn_bits;
4306                 s->insn_config = &ni_dio_insn_config;
4307                 devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
4308                 ni_writew(devpriv->dio_control, DIO_Control_Register);
4309         }
4310
4311         /* 8255 device */
4312         s = &dev->subdevices[NI_8255_DIO_SUBDEV];
4313         if (board->has_8255) {
4314                 subdev_8255_init(dev, s, ni_8255_callback, (unsigned long)dev);
4315         } else {
4316                 s->type = COMEDI_SUBD_UNUSED;
4317         }
4318
4319         /* formerly general purpose counter/timer device, but no longer used */
4320         s = &dev->subdevices[NI_UNUSED_SUBDEV];
4321         s->type = COMEDI_SUBD_UNUSED;
4322
4323         /* calibration subdevice -- ai and ao */
4324         s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
4325         s->type = COMEDI_SUBD_CALIB;
4326         if (board->reg_type & ni_reg_m_series_mask) {
4327                 /*  internal PWM analog output used for AI nonlinearity calibration */
4328                 s->subdev_flags = SDF_INTERNAL;
4329                 s->insn_config = &ni_m_series_pwm_config;
4330                 s->n_chan = 1;
4331                 s->maxdata = 0;
4332                 ni_writel(0x0, M_Offset_Cal_PWM);
4333         } else if (board->reg_type == ni_reg_6143) {
4334                 /*  internal PWM analog output used for AI nonlinearity calibration */
4335                 s->subdev_flags = SDF_INTERNAL;
4336                 s->insn_config = &ni_6143_pwm_config;
4337                 s->n_chan = 1;
4338                 s->maxdata = 0;
4339         } else {
4340                 s->subdev_flags = SDF_WRITABLE | SDF_INTERNAL;
4341                 s->insn_read = &ni_calib_insn_read;
4342                 s->insn_write = &ni_calib_insn_write;
4343                 caldac_setup(dev, s);
4344         }
4345
4346         /* EEPROM */
4347         s = &dev->subdevices[NI_EEPROM_SUBDEV];
4348         s->type = COMEDI_SUBD_MEMORY;
4349         s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
4350         s->maxdata = 0xff;
4351         if (board->reg_type & ni_reg_m_series_mask) {
4352                 s->n_chan = M_SERIES_EEPROM_SIZE;
4353                 s->insn_read = &ni_m_series_eeprom_insn_read;
4354         } else {
4355                 s->n_chan = 512;
4356                 s->insn_read = &ni_eeprom_insn_read;
4357         }
4358
4359         /* PFI */
4360         s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
4361         s->type = COMEDI_SUBD_DIO;
4362         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4363         if (board->reg_type & ni_reg_m_series_mask) {
4364                 unsigned i;
4365                 s->n_chan = 16;
4366                 ni_writew(s->state, M_Offset_PFI_DO);
4367                 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
4368                         ni_writew(devpriv->pfi_output_select_reg[i],
4369                                   M_Offset_PFI_Output_Select(i + 1));
4370                 }
4371         } else {
4372                 s->n_chan = 10;
4373         }
4374         s->maxdata = 1;
4375         if (board->reg_type & ni_reg_m_series_mask) {
4376                 s->insn_bits = &ni_pfi_insn_bits;
4377         }
4378         s->insn_config = &ni_pfi_insn_config;
4379         ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
4380
4381         /* cs5529 calibration adc */
4382         s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
4383         if (board->reg_type & ni_reg_67xx_mask) {
4384                 s->type = COMEDI_SUBD_AI;
4385                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
4386                 /*  one channel for each analog output channel */
4387                 s->n_chan = board->n_aochan;
4388                 s->maxdata = (1 << 16) - 1;
4389                 s->range_table = &range_unknown;        /* XXX */
4390                 s->insn_read = cs5529_ai_insn_read;
4391                 s->insn_config = NULL;
4392                 init_cs5529(dev);
4393         } else {
4394                 s->type = COMEDI_SUBD_UNUSED;
4395         }
4396
4397         /* Serial */
4398         s = &dev->subdevices[NI_SERIAL_SUBDEV];
4399         s->type = COMEDI_SUBD_SERIAL;
4400         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4401         s->n_chan = 1;
4402         s->maxdata = 0xff;
4403         s->insn_config = ni_serial_insn_config;
4404         devpriv->serial_interval_ns = 0;
4405         devpriv->serial_hw_mode = 0;
4406
4407         /* RTSI */
4408         s = &dev->subdevices[NI_RTSI_SUBDEV];
4409         s->type = COMEDI_SUBD_DIO;
4410         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4411         s->n_chan = 8;
4412         s->maxdata = 1;
4413         s->insn_bits = ni_rtsi_insn_bits;
4414         s->insn_config = ni_rtsi_insn_config;
4415         ni_rtsi_init(dev);
4416
4417         if (board->reg_type & ni_reg_m_series_mask) {
4418                 counter_variant = ni_gpct_variant_m_series;
4419         } else {
4420                 counter_variant = ni_gpct_variant_e_series;
4421         }
4422         devpriv->counter_dev = ni_gpct_device_construct(dev,
4423                                                         &ni_gpct_write_register,
4424                                                         &ni_gpct_read_register,
4425                                                         counter_variant,
4426                                                         NUM_GPCT);
4427         /* General purpose counters */
4428         for (j = 0; j < NUM_GPCT; ++j) {
4429                 s = &dev->subdevices[NI_GPCT_SUBDEV(j)];
4430                 s->type = COMEDI_SUBD_COUNTER;
4431                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL;
4432                 s->n_chan = 3;
4433                 if (board->reg_type & ni_reg_m_series_mask)
4434                         s->maxdata = 0xffffffff;
4435                 else
4436                         s->maxdata = 0xffffff;
4437                 s->insn_read = ni_tio_insn_read;
4438                 s->insn_write = ni_tio_insn_read;
4439                 s->insn_config = ni_tio_insn_config;
4440 #ifdef PCIDMA
4441                 s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */;
4442                 s->do_cmd = &ni_gpct_cmd;
4443                 s->len_chanlist = 1;
4444                 s->do_cmdtest = ni_tio_cmdtest;
4445                 s->cancel = &ni_gpct_cancel;
4446                 s->async_dma_dir = DMA_BIDIRECTIONAL;
4447 #endif
4448                 s->private = &devpriv->counter_dev->counters[j];
4449
4450                 devpriv->counter_dev->counters[j].chip_index = 0;
4451                 devpriv->counter_dev->counters[j].counter_index = j;
4452                 ni_tio_init_counter(&devpriv->counter_dev->counters[j]);
4453         }
4454
4455         /* Frequency output */
4456         s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
4457         s->type = COMEDI_SUBD_COUNTER;
4458         s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
4459         s->n_chan = 1;
4460         s->maxdata = 0xf;
4461         s->insn_read = &ni_freq_out_insn_read;
4462         s->insn_write = &ni_freq_out_insn_write;
4463         s->insn_config = &ni_freq_out_insn_config;
4464
4465         /* ai configuration */
4466         s = &dev->subdevices[NI_AI_SUBDEV];
4467         ni_ai_reset(dev, s);
4468         if ((board->reg_type & ni_reg_6xxx_mask) == 0) {
4469                 /*  BEAM is this needed for PCI-6143 ?? */
4470                 devpriv->clock_and_fout =
4471                     Slow_Internal_Time_Divide_By_2 |
4472                     Slow_Internal_Timebase |
4473                     Clock_To_Board_Divide_By_2 |
4474                     Clock_To_Board |
4475                     AI_Output_Divide_By_2 | AO_Output_Divide_By_2;
4476         } else {
4477                 devpriv->clock_and_fout =
4478                     Slow_Internal_Time_Divide_By_2 |
4479                     Slow_Internal_Timebase |
4480                     Clock_To_Board_Divide_By_2 | Clock_To_Board;
4481         }
4482         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4483                             Clock_and_FOUT_Register);
4484
4485         /* analog output configuration */
4486         s = &dev->subdevices[NI_AO_SUBDEV];
4487         ni_ao_reset(dev, s);
4488
4489         if (dev->irq) {
4490                 devpriv->stc_writew(dev,
4491                                     (IRQ_POLARITY ? Interrupt_Output_Polarity :
4492                                      0) | (Interrupt_Output_On_3_Pins & 0) |
4493                                     Interrupt_A_Enable | Interrupt_B_Enable |
4494                                     Interrupt_A_Output_Select(interrupt_pin
4495                                                               (dev->irq)) |
4496                                     Interrupt_B_Output_Select(interrupt_pin
4497                                                               (dev->irq)),
4498                                     Interrupt_Control_Register);
4499         }
4500
4501         /* DMA setup */
4502         ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
4503         ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
4504
4505         if (board->reg_type & ni_reg_6xxx_mask) {
4506                 ni_writeb(0, Magic_611x);
4507         } else if (board->reg_type & ni_reg_m_series_mask) {
4508                 int channel;
4509                 for (channel = 0; channel < board->n_aochan; ++channel) {
4510                         ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel));
4511                         ni_writeb(0x0,
4512                                   M_Offset_AO_Reference_Attenuation(channel));
4513                 }
4514                 ni_writeb(0x0, M_Offset_AO_Calibration);
4515         }
4516
4517         printk("\n");
4518         return 0;
4519 }
4520
4521 static int ni_8255_callback(int dir, int port, int data, unsigned long arg)
4522 {
4523         struct comedi_device *dev = (struct comedi_device *)arg;
4524         struct ni_private *devpriv __maybe_unused = dev->private;
4525
4526         if (dir) {
4527                 ni_writeb(data, Port_A + 2 * port);
4528                 return 0;
4529         } else {
4530                 return ni_readb(Port_A + 2 * port);
4531         }
4532 }
4533
4534 /*
4535         presents the EEPROM as a subdevice
4536 */
4537
4538 static int ni_eeprom_insn_read(struct comedi_device *dev,
4539                                struct comedi_subdevice *s,
4540                                struct comedi_insn *insn, unsigned int *data)
4541 {
4542         data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4543
4544         return 1;
4545 }
4546
4547 /*
4548         reads bytes out of eeprom
4549 */
4550
4551 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4552 {
4553         struct ni_private *devpriv __maybe_unused = dev->private;
4554         int bit;
4555         int bitstring;
4556
4557         bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4558         ni_writeb(0x04, Serial_Command);
4559         for (bit = 0x8000; bit; bit >>= 1) {
4560                 ni_writeb(0x04 | ((bit & bitstring) ? 0x02 : 0),
4561                           Serial_Command);
4562                 ni_writeb(0x05 | ((bit & bitstring) ? 0x02 : 0),
4563                           Serial_Command);
4564         }
4565         bitstring = 0;
4566         for (bit = 0x80; bit; bit >>= 1) {
4567                 ni_writeb(0x04, Serial_Command);
4568                 ni_writeb(0x05, Serial_Command);
4569                 bitstring |= ((ni_readb(XXX_Status) & PROMOUT) ? bit : 0);
4570         }
4571         ni_writeb(0x00, Serial_Command);
4572
4573         return bitstring;
4574 }
4575
4576 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4577                                         struct comedi_subdevice *s,
4578                                         struct comedi_insn *insn,
4579                                         unsigned int *data)
4580 {
4581         struct ni_private *devpriv = dev->private;
4582
4583         data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4584
4585         return 1;
4586 }
4587
4588 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
4589 {
4590         struct ni_private *devpriv = dev->private;
4591
4592         data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4593         data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4594         return 3;
4595 }
4596
4597 static int ni_m_series_pwm_config(struct comedi_device *dev,
4598                                   struct comedi_subdevice *s,
4599                                   struct comedi_insn *insn, unsigned int *data)
4600 {
4601         struct ni_private *devpriv = dev->private;
4602         unsigned up_count, down_count;
4603
4604         switch (data[0]) {
4605         case INSN_CONFIG_PWM_OUTPUT:
4606                 switch (data[1]) {
4607                 case TRIG_ROUND_NEAREST:
4608                         up_count =
4609                             (data[2] +
4610                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4611                         break;
4612                 case TRIG_ROUND_DOWN:
4613                         up_count = data[2] / devpriv->clock_ns;
4614                         break;
4615                 case TRIG_ROUND_UP:
4616                         up_count =
4617                             (data[2] + devpriv->clock_ns -
4618                              1) / devpriv->clock_ns;
4619                         break;
4620                 default:
4621                         return -EINVAL;
4622                         break;
4623                 }
4624                 switch (data[3]) {
4625                 case TRIG_ROUND_NEAREST:
4626                         down_count =
4627                             (data[4] +
4628                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4629                         break;
4630                 case TRIG_ROUND_DOWN:
4631                         down_count = data[4] / devpriv->clock_ns;
4632                         break;
4633                 case TRIG_ROUND_UP:
4634                         down_count =
4635                             (data[4] + devpriv->clock_ns -
4636                              1) / devpriv->clock_ns;
4637                         break;
4638                 default:
4639                         return -EINVAL;
4640                         break;
4641                 }
4642                 if (up_count * devpriv->clock_ns != data[2] ||
4643                     down_count * devpriv->clock_ns != data[4]) {
4644                         data[2] = up_count * devpriv->clock_ns;
4645                         data[4] = down_count * devpriv->clock_ns;
4646                         return -EAGAIN;
4647                 }
4648                 ni_writel(MSeries_Cal_PWM_High_Time_Bits(up_count) |
4649                           MSeries_Cal_PWM_Low_Time_Bits(down_count),
4650                           M_Offset_Cal_PWM);
4651                 devpriv->pwm_up_count = up_count;
4652                 devpriv->pwm_down_count = down_count;
4653                 return 5;
4654                 break;
4655         case INSN_CONFIG_GET_PWM_OUTPUT:
4656                 return ni_get_pwm_config(dev, data);
4657                 break;
4658         default:
4659                 return -EINVAL;
4660                 break;
4661         }
4662         return 0;
4663 }
4664
4665 static int ni_6143_pwm_config(struct comedi_device *dev,
4666                               struct comedi_subdevice *s,
4667                               struct comedi_insn *insn, unsigned int *data)
4668 {
4669         struct ni_private *devpriv = dev->private;
4670         unsigned up_count, down_count;
4671
4672         switch (data[0]) {
4673         case INSN_CONFIG_PWM_OUTPUT:
4674                 switch (data[1]) {
4675                 case TRIG_ROUND_NEAREST:
4676                         up_count =
4677                             (data[2] +
4678                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4679                         break;
4680                 case TRIG_ROUND_DOWN:
4681                         up_count = data[2] / devpriv->clock_ns;
4682                         break;
4683                 case TRIG_ROUND_UP:
4684                         up_count =
4685                             (data[2] + devpriv->clock_ns -
4686                              1) / devpriv->clock_ns;
4687                         break;
4688                 default:
4689                         return -EINVAL;
4690                         break;
4691                 }
4692                 switch (data[3]) {
4693                 case TRIG_ROUND_NEAREST:
4694                         down_count =
4695                             (data[4] +
4696                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4697                         break;
4698                 case TRIG_ROUND_DOWN:
4699                         down_count = data[4] / devpriv->clock_ns;
4700                         break;
4701                 case TRIG_ROUND_UP:
4702                         down_count =
4703                             (data[4] + devpriv->clock_ns -
4704                              1) / devpriv->clock_ns;
4705                         break;
4706                 default:
4707                         return -EINVAL;
4708                         break;
4709                 }
4710                 if (up_count * devpriv->clock_ns != data[2] ||
4711                     down_count * devpriv->clock_ns != data[4]) {
4712                         data[2] = up_count * devpriv->clock_ns;
4713                         data[4] = down_count * devpriv->clock_ns;
4714                         return -EAGAIN;
4715                 }
4716                 ni_writel(up_count, Calibration_HighTime_6143);
4717                 devpriv->pwm_up_count = up_count;
4718                 ni_writel(down_count, Calibration_LowTime_6143);
4719                 devpriv->pwm_down_count = down_count;
4720                 return 5;
4721                 break;
4722         case INSN_CONFIG_GET_PWM_OUTPUT:
4723                 return ni_get_pwm_config(dev, data);
4724         default:
4725                 return -EINVAL;
4726                 break;
4727         }
4728         return 0;
4729 }
4730
4731 static void ni_write_caldac(struct comedi_device *dev, int addr, int val);
4732 /*
4733         calibration subdevice
4734 */
4735 static int ni_calib_insn_write(struct comedi_device *dev,
4736                                struct comedi_subdevice *s,
4737                                struct comedi_insn *insn, unsigned int *data)
4738 {
4739         ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4740
4741         return 1;
4742 }
4743
4744 static int ni_calib_insn_read(struct comedi_device *dev,
4745                               struct comedi_subdevice *s,
4746                               struct comedi_insn *insn, unsigned int *data)
4747 {
4748         struct ni_private *devpriv = dev->private;
4749
4750         data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4751
4752         return 1;
4753 }
4754
4755 static int pack_mb88341(int addr, int val, int *bitstring);
4756 static int pack_dac8800(int addr, int val, int *bitstring);
4757 static int pack_dac8043(int addr, int val, int *bitstring);
4758 static int pack_ad8522(int addr, int val, int *bitstring);
4759 static int pack_ad8804(int addr, int val, int *bitstring);
4760 static int pack_ad8842(int addr, int val, int *bitstring);
4761
4762 struct caldac_struct {
4763         int n_chans;
4764         int n_bits;
4765         int (*packbits) (int, int, int *);
4766 };
4767
4768 static struct caldac_struct caldacs[] = {
4769         [mb88341] = {12, 8, pack_mb88341},
4770         [dac8800] = {8, 8, pack_dac8800},
4771         [dac8043] = {1, 12, pack_dac8043},
4772         [ad8522] = {2, 12, pack_ad8522},
4773         [ad8804] = {12, 8, pack_ad8804},
4774         [ad8842] = {8, 8, pack_ad8842},
4775         [ad8804_debug] = {16, 8, pack_ad8804},
4776 };
4777
4778 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4779 {
4780         const struct ni_board_struct *board = comedi_board(dev);
4781         struct ni_private *devpriv = dev->private;
4782         int i, j;
4783         int n_dacs;
4784         int n_chans = 0;
4785         int n_bits;
4786         int diffbits = 0;
4787         int type;
4788         int chan;
4789
4790         type = board->caldac[0];
4791         if (type == caldac_none)
4792                 return;
4793         n_bits = caldacs[type].n_bits;
4794         for (i = 0; i < 3; i++) {
4795                 type = board->caldac[i];
4796                 if (type == caldac_none)
4797                         break;
4798                 if (caldacs[type].n_bits != n_bits)
4799                         diffbits = 1;
4800                 n_chans += caldacs[type].n_chans;
4801         }
4802         n_dacs = i;
4803         s->n_chan = n_chans;
4804
4805         if (diffbits) {
4806                 unsigned int *maxdata_list;
4807
4808                 if (n_chans > MAX_N_CALDACS) {
4809                         printk("BUG! MAX_N_CALDACS too small\n");
4810                 }
4811                 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
4812                 chan = 0;
4813                 for (i = 0; i < n_dacs; i++) {
4814                         type = board->caldac[i];
4815                         for (j = 0; j < caldacs[type].n_chans; j++) {
4816                                 maxdata_list[chan] =
4817                                     (1 << caldacs[type].n_bits) - 1;
4818                                 chan++;
4819                         }
4820                 }
4821
4822                 for (chan = 0; chan < s->n_chan; chan++)
4823                         ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
4824         } else {
4825                 type = board->caldac[0];
4826                 s->maxdata = (1 << caldacs[type].n_bits) - 1;
4827
4828                 for (chan = 0; chan < s->n_chan; chan++)
4829                         ni_write_caldac(dev, i, s->maxdata / 2);
4830         }
4831 }
4832
4833 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
4834 {
4835         const struct ni_board_struct *board = comedi_board(dev);
4836         struct ni_private *devpriv = dev->private;
4837         unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
4838         int i;
4839         int type;
4840
4841         /* printk("ni_write_caldac: chan=%d val=%d\n",addr,val); */
4842         if (devpriv->caldacs[addr] == val)
4843                 return;
4844         devpriv->caldacs[addr] = val;
4845
4846         for (i = 0; i < 3; i++) {
4847                 type = board->caldac[i];
4848                 if (type == caldac_none)
4849                         break;
4850                 if (addr < caldacs[type].n_chans) {
4851                         bits = caldacs[type].packbits(addr, val, &bitstring);
4852                         loadbit = SerDacLd(i);
4853                         /* printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring); */
4854                         break;
4855                 }
4856                 addr -= caldacs[type].n_chans;
4857         }
4858
4859         for (bit = 1 << (bits - 1); bit; bit >>= 1) {
4860                 ni_writeb(((bit & bitstring) ? 0x02 : 0), Serial_Command);
4861                 udelay(1);
4862                 ni_writeb(1 | ((bit & bitstring) ? 0x02 : 0), Serial_Command);
4863                 udelay(1);
4864         }
4865         ni_writeb(loadbit, Serial_Command);
4866         udelay(1);
4867         ni_writeb(0, Serial_Command);
4868 }
4869
4870 static int pack_mb88341(int addr, int val, int *bitstring)
4871 {
4872         /*
4873            Fujitsu MB 88341
4874            Note that address bits are reversed.  Thanks to
4875            Ingo Keen for noticing this.
4876
4877            Note also that the 88341 expects address values from
4878            1-12, whereas we use channel numbers 0-11.  The NI
4879            docs use 1-12, also, so be careful here.
4880          */
4881         addr++;
4882         *bitstring = ((addr & 0x1) << 11) |
4883             ((addr & 0x2) << 9) |
4884             ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
4885         return 12;
4886 }
4887
4888 static int pack_dac8800(int addr, int val, int *bitstring)
4889 {
4890         *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
4891         return 11;
4892 }
4893
4894 static int pack_dac8043(int addr, int val, int *bitstring)
4895 {
4896         *bitstring = val & 0xfff;
4897         return 12;
4898 }
4899
4900 static int pack_ad8522(int addr, int val, int *bitstring)
4901 {
4902         *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
4903         return 16;
4904 }
4905
4906 static int pack_ad8804(int addr, int val, int *bitstring)
4907 {
4908         *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
4909         return 12;
4910 }
4911
4912 static int pack_ad8842(int addr, int val, int *bitstring)
4913 {
4914         *bitstring = ((addr + 1) << 8) | (val & 0xff);
4915         return 12;
4916 }
4917
4918 #if 0
4919 /*
4920  *      Read the GPCTs current value.
4921  */
4922 static int GPCT_G_Watch(struct comedi_device *dev, int chan)
4923 {
4924         unsigned int hi1, hi2, lo;
4925
4926         devpriv->gpct_command[chan] &= ~G_Save_Trace;
4927         devpriv->stc_writew(dev, devpriv->gpct_command[chan],
4928                             G_Command_Register(chan));
4929
4930         devpriv->gpct_command[chan] |= G_Save_Trace;
4931         devpriv->stc_writew(dev, devpriv->gpct_command[chan],
4932                             G_Command_Register(chan));
4933
4934         /* This procedure is used because the two registers cannot
4935          * be read atomically. */
4936         do {
4937                 hi1 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
4938                 lo = devpriv->stc_readw(dev, G_Save_Register_Low(chan));
4939                 hi2 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
4940         } while (hi1 != hi2);
4941
4942         return (hi1 << 16) | lo;
4943 }
4944
4945 static void GPCT_Reset(struct comedi_device *dev, int chan)
4946 {
4947         int temp_ack_reg = 0;
4948
4949         /* printk("GPCT_Reset..."); */
4950         devpriv->gpct_cur_operation[chan] = GPCT_RESET;
4951
4952         switch (chan) {
4953         case 0:
4954                 devpriv->stc_writew(dev, G0_Reset, Joint_Reset_Register);
4955                 ni_set_bits(dev, Interrupt_A_Enable_Register,
4956                             G0_TC_Interrupt_Enable, 0);
4957                 ni_set_bits(dev, Interrupt_A_Enable_Register,
4958                             G0_Gate_Interrupt_Enable, 0);
4959                 temp_ack_reg |= G0_Gate_Error_Confirm;
4960                 temp_ack_reg |= G0_TC_Error_Confirm;
4961                 temp_ack_reg |= G0_TC_Interrupt_Ack;
4962                 temp_ack_reg |= G0_Gate_Interrupt_Ack;
4963                 devpriv->stc_writew(dev, temp_ack_reg,
4964                                     Interrupt_A_Ack_Register);
4965
4966                 /* problem...this interferes with the other ctr... */
4967                 devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
4968                 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
4969                                     Analog_Trigger_Etc_Register);
4970                 break;
4971         case 1:
4972                 devpriv->stc_writew(dev, G1_Reset, Joint_Reset_Register);
4973                 ni_set_bits(dev, Interrupt_B_Enable_Register,
4974                             G1_TC_Interrupt_Enable, 0);
4975                 ni_set_bits(dev, Interrupt_B_Enable_Register,
4976                             G0_Gate_Interrupt_Enable, 0);
4977                 temp_ack_reg |= G1_Gate_Error_Confirm;
4978                 temp_ack_reg |= G1_TC_Error_Confirm;
4979                 temp_ack_reg |= G1_TC_Interrupt_Ack;
4980                 temp_ack_reg |= G1_Gate_Interrupt_Ack;
4981                 devpriv->stc_writew(dev, temp_ack_reg,
4982                                     Interrupt_B_Ack_Register);
4983
4984                 devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
4985                 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
4986                                     Analog_Trigger_Etc_Register);
4987                 break;
4988         }
4989
4990         devpriv->gpct_mode[chan] = 0;
4991         devpriv->gpct_input_select[chan] = 0;
4992         devpriv->gpct_command[chan] = 0;
4993
4994         devpriv->gpct_command[chan] |= G_Synchronized_Gate;
4995
4996         devpriv->stc_writew(dev, devpriv->gpct_mode[chan],
4997                             G_Mode_Register(chan));
4998         devpriv->stc_writew(dev, devpriv->gpct_input_select[chan],
4999                             G_Input_Select_Register(chan));
5000         devpriv->stc_writew(dev, 0, G_Autoincrement_Register(chan));
5001
5002         /* printk("exit GPCT_Reset\n"); */
5003 }
5004
5005 #endif
5006
5007 #ifdef PCIDMA
5008 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
5009 {
5010         struct ni_gpct *counter = s->private;
5011         int retval;
5012
5013         retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
5014                                               COMEDI_INPUT);
5015         if (retval) {
5016                 comedi_error(dev,
5017                              "no dma channel available for use by counter");
5018                 return retval;
5019         }
5020         ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
5021         ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5022
5023         return ni_tio_cmd(dev, s);
5024 }
5025 #endif
5026
5027 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
5028 {
5029 #ifdef PCIDMA
5030         struct ni_gpct *counter = s->private;
5031         int retval;
5032
5033         retval = ni_tio_cancel(counter);
5034         ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5035         ni_release_gpct_mite_channel(dev, counter->counter_index);
5036         return retval;
5037 #else
5038         return 0;
5039 #endif
5040 }
5041
5042 /*
5043  *
5044  *  Programmable Function Inputs
5045  *
5046  */
5047
5048 static int ni_m_series_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5049                                        unsigned source)
5050 {
5051         struct ni_private *devpriv = dev->private;
5052         unsigned pfi_reg_index;
5053         unsigned array_offset;
5054
5055         if ((source & 0x1f) != source)
5056                 return -EINVAL;
5057         pfi_reg_index = 1 + chan / 3;
5058         array_offset = pfi_reg_index - 1;
5059         devpriv->pfi_output_select_reg[array_offset] &=
5060             ~MSeries_PFI_Output_Select_Mask(chan);
5061         devpriv->pfi_output_select_reg[array_offset] |=
5062             MSeries_PFI_Output_Select_Bits(chan, source);
5063         ni_writew(devpriv->pfi_output_select_reg[array_offset],
5064                   M_Offset_PFI_Output_Select(pfi_reg_index));
5065         return 2;
5066 }
5067
5068 static int ni_old_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5069                                   unsigned source)
5070 {
5071         /*  pre-m-series boards have fixed signals on pfi pins */
5072         if (source != ni_old_get_pfi_routing(dev, chan))
5073                 return -EINVAL;
5074         return 2;
5075 }
5076
5077 static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5078                               unsigned source)
5079 {
5080         const struct ni_board_struct *board = comedi_board(dev);
5081
5082         if (board->reg_type & ni_reg_m_series_mask)
5083                 return ni_m_series_set_pfi_routing(dev, chan, source);
5084         else
5085                 return ni_old_set_pfi_routing(dev, chan, source);
5086 }
5087
5088 static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev,
5089                                             unsigned chan)
5090 {
5091         struct ni_private *devpriv = dev->private;
5092         const unsigned array_offset = chan / 3;
5093
5094         return MSeries_PFI_Output_Select_Source(chan,
5095                                                 devpriv->
5096                                                 pfi_output_select_reg
5097                                                 [array_offset]);
5098 }
5099
5100 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5101 {
5102         /*  pre-m-series boards have fixed signals on pfi pins */
5103         switch (chan) {
5104         case 0:
5105                 return NI_PFI_OUTPUT_AI_START1;
5106                 break;
5107         case 1:
5108                 return NI_PFI_OUTPUT_AI_START2;
5109                 break;
5110         case 2:
5111                 return NI_PFI_OUTPUT_AI_CONVERT;
5112                 break;
5113         case 3:
5114                 return NI_PFI_OUTPUT_G_SRC1;
5115                 break;
5116         case 4:
5117                 return NI_PFI_OUTPUT_G_GATE1;
5118                 break;
5119         case 5:
5120                 return NI_PFI_OUTPUT_AO_UPDATE_N;
5121                 break;
5122         case 6:
5123                 return NI_PFI_OUTPUT_AO_START1;
5124                 break;
5125         case 7:
5126                 return NI_PFI_OUTPUT_AI_START_PULSE;
5127                 break;
5128         case 8:
5129                 return NI_PFI_OUTPUT_G_SRC0;
5130                 break;
5131         case 9:
5132                 return NI_PFI_OUTPUT_G_GATE0;
5133                 break;
5134         default:
5135                 printk("%s: bug, unhandled case in switch.\n", __func__);
5136                 break;
5137         }
5138         return 0;
5139 }
5140
5141 static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5142 {
5143         const struct ni_board_struct *board = comedi_board(dev);
5144
5145         if (board->reg_type & ni_reg_m_series_mask)
5146                 return ni_m_series_get_pfi_routing(dev, chan);
5147         else
5148                 return ni_old_get_pfi_routing(dev, chan);
5149 }
5150
5151 static int ni_config_filter(struct comedi_device *dev, unsigned pfi_channel,
5152                             enum ni_pfi_filter_select filter)
5153 {
5154         const struct ni_board_struct *board = comedi_board(dev);
5155         struct ni_private *devpriv __maybe_unused = dev->private;
5156         unsigned bits;
5157
5158         if ((board->reg_type & ni_reg_m_series_mask) == 0) {
5159                 return -ENOTSUPP;
5160         }
5161         bits = ni_readl(M_Offset_PFI_Filter);
5162         bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel);
5163         bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter);
5164         ni_writel(bits, M_Offset_PFI_Filter);
5165         return 0;
5166 }
5167
5168 static int ni_pfi_insn_bits(struct comedi_device *dev,
5169                             struct comedi_subdevice *s,
5170                             struct comedi_insn *insn,
5171                             unsigned int *data)
5172 {
5173         const struct ni_board_struct *board = comedi_board(dev);
5174         struct ni_private *devpriv __maybe_unused = dev->private;
5175
5176         if (!(board->reg_type & ni_reg_m_series_mask))
5177                 return -ENOTSUPP;
5178
5179         if (comedi_dio_update_state(s, data))
5180                 ni_writew(s->state, M_Offset_PFI_DO);
5181
5182         data[1] = ni_readw(M_Offset_PFI_DI);
5183
5184         return insn->n;
5185 }
5186
5187 static int ni_pfi_insn_config(struct comedi_device *dev,
5188                               struct comedi_subdevice *s,
5189                               struct comedi_insn *insn, unsigned int *data)
5190 {
5191         struct ni_private *devpriv = dev->private;
5192         unsigned int chan;
5193
5194         if (insn->n < 1)
5195                 return -EINVAL;
5196
5197         chan = CR_CHAN(insn->chanspec);
5198
5199         switch (data[0]) {
5200         case COMEDI_OUTPUT:
5201                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 1);
5202                 break;
5203         case COMEDI_INPUT:
5204                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 0);
5205                 break;
5206         case INSN_CONFIG_DIO_QUERY:
5207                 data[1] =
5208                     (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
5209                     COMEDI_OUTPUT : COMEDI_INPUT;
5210                 return 0;
5211                 break;
5212         case INSN_CONFIG_SET_ROUTING:
5213                 return ni_set_pfi_routing(dev, chan, data[1]);
5214                 break;
5215         case INSN_CONFIG_GET_ROUTING:
5216                 data[1] = ni_get_pfi_routing(dev, chan);
5217                 break;
5218         case INSN_CONFIG_FILTER:
5219                 return ni_config_filter(dev, chan, data[1]);
5220                 break;
5221         default:
5222                 return -EINVAL;
5223         }
5224         return 0;
5225 }
5226
5227 /*
5228  *
5229  *  NI RTSI Bus Functions
5230  *
5231  */
5232 static void ni_rtsi_init(struct comedi_device *dev)
5233 {
5234         const struct ni_board_struct *board = comedi_board(dev);
5235         struct ni_private *devpriv = dev->private;
5236
5237         /*  Initialises the RTSI bus signal switch to a default state */
5238
5239         /*  Set clock mode to internal */
5240         devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit;
5241         if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0) {
5242                 printk("ni_set_master_clock failed, bug?");
5243         }
5244         /*  default internal lines routing to RTSI bus lines */
5245         devpriv->rtsi_trig_a_output_reg =
5246             RTSI_Trig_Output_Bits(0,
5247                                   NI_RTSI_OUTPUT_ADR_START1) |
5248             RTSI_Trig_Output_Bits(1,
5249                                   NI_RTSI_OUTPUT_ADR_START2) |
5250             RTSI_Trig_Output_Bits(2,
5251                                   NI_RTSI_OUTPUT_SCLKG) |
5252             RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN);
5253         devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5254                             RTSI_Trig_A_Output_Register);
5255         devpriv->rtsi_trig_b_output_reg =
5256             RTSI_Trig_Output_Bits(4,
5257                                   NI_RTSI_OUTPUT_DA_START1) |
5258             RTSI_Trig_Output_Bits(5,
5259                                   NI_RTSI_OUTPUT_G_SRC0) |
5260             RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0);
5261         if (board->reg_type & ni_reg_m_series_mask)
5262                 devpriv->rtsi_trig_b_output_reg |=
5263                     RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
5264         devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5265                             RTSI_Trig_B_Output_Register);
5266
5267 /*
5268 * Sets the source and direction of the 4 on board lines
5269 * devpriv->stc_writew(dev, 0x0000, RTSI_Board_Register);
5270 */
5271 }
5272
5273 static int ni_rtsi_insn_bits(struct comedi_device *dev,
5274                              struct comedi_subdevice *s,
5275                              struct comedi_insn *insn, unsigned int *data)
5276 {
5277         data[1] = 0;
5278
5279         return insn->n;
5280 }
5281
5282 /* Find best multiplier/divider to try and get the PLL running at 80 MHz
5283  * given an arbitrary frequency input clock */
5284 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
5285                                          unsigned *freq_divider,
5286                                          unsigned *freq_multiplier,
5287                                          unsigned *actual_period_ns)
5288 {
5289         unsigned div;
5290         unsigned best_div = 1;
5291         static const unsigned max_div = 0x10;
5292         unsigned mult;
5293         unsigned best_mult = 1;
5294         static const unsigned max_mult = 0x100;
5295         static const unsigned pico_per_nano = 1000;
5296
5297         const unsigned reference_picosec = reference_period_ns * pico_per_nano;
5298         /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
5299          * 20 MHz for most timing clocks */
5300         static const unsigned target_picosec = 12500;
5301         static const unsigned fudge_factor_80_to_20Mhz = 4;
5302         int best_period_picosec = 0;
5303         for (div = 1; div <= max_div; ++div) {
5304                 for (mult = 1; mult <= max_mult; ++mult) {
5305                         unsigned new_period_ps =
5306                             (reference_picosec * div) / mult;
5307                         if (abs(new_period_ps - target_picosec) <
5308                             abs(best_period_picosec - target_picosec)) {
5309                                 best_period_picosec = new_period_ps;
5310                                 best_div = div;
5311                                 best_mult = mult;
5312                         }
5313                 }
5314         }
5315         if (best_period_picosec == 0) {
5316                 printk("%s: bug, failed to find pll parameters\n", __func__);
5317                 return -EIO;
5318         }
5319         *freq_divider = best_div;
5320         *freq_multiplier = best_mult;
5321         *actual_period_ns =
5322             (best_period_picosec * fudge_factor_80_to_20Mhz +
5323              (pico_per_nano / 2)) / pico_per_nano;
5324         return 0;
5325 }
5326
5327 static inline unsigned num_configurable_rtsi_channels(struct comedi_device *dev)
5328 {
5329         const struct ni_board_struct *board = comedi_board(dev);
5330
5331         if (board->reg_type & ni_reg_m_series_mask)
5332                 return 8;
5333         else
5334                 return 7;
5335 }
5336
5337 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
5338                                            unsigned source, unsigned period_ns)
5339 {
5340         struct ni_private *devpriv = dev->private;
5341         static const unsigned min_period_ns = 50;
5342         static const unsigned max_period_ns = 1000;
5343         static const unsigned timeout = 1000;
5344         unsigned pll_control_bits;
5345         unsigned freq_divider;
5346         unsigned freq_multiplier;
5347         unsigned i;
5348         int retval;
5349
5350         if (source == NI_MIO_PLL_PXI10_CLOCK)
5351                 period_ns = 100;
5352         /*  these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
5353         if (period_ns < min_period_ns || period_ns > max_period_ns) {
5354                 printk
5355                     ("%s: you must specify an input clock frequency between %i and %i nanosec "
5356                      "for the phased-lock loop.\n", __func__,
5357                      min_period_ns, max_period_ns);
5358                 return -EINVAL;
5359         }
5360         devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5361         devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5362                             RTSI_Trig_Direction_Register);
5363         pll_control_bits =
5364             MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
5365         devpriv->clock_and_fout2 |=
5366             MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit;
5367         devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
5368         switch (source) {
5369         case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
5370                 devpriv->clock_and_fout2 |=
5371                     MSeries_PLL_In_Source_Select_Star_Trigger_Bits;
5372                 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5373                                                        &freq_multiplier,
5374                                                        &devpriv->clock_ns);
5375                 if (retval < 0)
5376                         return retval;
5377                 break;
5378         case NI_MIO_PLL_PXI10_CLOCK:
5379                 /* pxi clock is 10MHz */
5380                 devpriv->clock_and_fout2 |=
5381                     MSeries_PLL_In_Source_Select_PXI_Clock10;
5382                 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5383                                                        &freq_multiplier,
5384                                                        &devpriv->clock_ns);
5385                 if (retval < 0)
5386                         return retval;
5387                 break;
5388         default:
5389                 {
5390                         unsigned rtsi_channel;
5391                         static const unsigned max_rtsi_channel = 7;
5392                         for (rtsi_channel = 0; rtsi_channel <= max_rtsi_channel;
5393                              ++rtsi_channel) {
5394                                 if (source ==
5395                                     NI_MIO_PLL_RTSI_CLOCK(rtsi_channel)) {
5396                                         devpriv->clock_and_fout2 |=
5397                                             MSeries_PLL_In_Source_Select_RTSI_Bits
5398                                             (rtsi_channel);
5399                                         break;
5400                                 }
5401                         }
5402                         if (rtsi_channel > max_rtsi_channel)
5403                                 return -EINVAL;
5404                         retval = ni_mseries_get_pll_parameters(period_ns,
5405                                                                &freq_divider,
5406                                                                &freq_multiplier,
5407                                                                &devpriv->
5408                                                                clock_ns);
5409                         if (retval < 0)
5410                                 return retval;
5411                 }
5412                 break;
5413         }
5414         ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
5415         pll_control_bits |=
5416             MSeries_PLL_Divisor_Bits(freq_divider) |
5417             MSeries_PLL_Multiplier_Bits(freq_multiplier);
5418
5419         /* printk("using divider=%i, multiplier=%i for PLL. pll_control_bits = 0x%x\n",
5420          * freq_divider, freq_multiplier, pll_control_bits); */
5421         /* printk("clock_ns=%d\n", devpriv->clock_ns); */
5422         ni_writew(pll_control_bits, M_Offset_PLL_Control);
5423         devpriv->clock_source = source;
5424         /* it seems to typically take a few hundred microseconds for PLL to lock */
5425         for (i = 0; i < timeout; ++i) {
5426                 if (ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit) {
5427                         break;
5428                 }
5429                 udelay(1);
5430         }
5431         if (i == timeout) {
5432                 printk
5433                     ("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n",
5434                      __func__, source, period_ns);
5435                 return -ETIMEDOUT;
5436         }
5437         return 3;
5438 }
5439
5440 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
5441                                unsigned period_ns)
5442 {
5443         const struct ni_board_struct *board = comedi_board(dev);
5444         struct ni_private *devpriv = dev->private;
5445
5446         if (source == NI_MIO_INTERNAL_CLOCK) {
5447                 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5448                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5449                                     RTSI_Trig_Direction_Register);
5450                 devpriv->clock_ns = TIMEBASE_1_NS;
5451                 if (board->reg_type & ni_reg_m_series_mask) {
5452                         devpriv->clock_and_fout2 &=
5453                             ~(MSeries_Timebase1_Select_Bit |
5454                               MSeries_Timebase3_Select_Bit);
5455                         ni_writew(devpriv->clock_and_fout2,
5456                                   M_Offset_Clock_and_Fout2);
5457                         ni_writew(0, M_Offset_PLL_Control);
5458                 }
5459                 devpriv->clock_source = source;
5460         } else {
5461                 if (board->reg_type & ni_reg_m_series_mask) {
5462                         return ni_mseries_set_pll_master_clock(dev, source,
5463                                                                period_ns);
5464                 } else {
5465                         if (source == NI_MIO_RTSI_CLOCK) {
5466                                 devpriv->rtsi_trig_direction_reg |=
5467                                     Use_RTSI_Clock_Bit;
5468                                 devpriv->stc_writew(dev,
5469                                                     devpriv->
5470                                                     rtsi_trig_direction_reg,
5471                                                     RTSI_Trig_Direction_Register);
5472                                 if (period_ns == 0) {
5473                                         printk
5474                                             ("%s: we don't handle an unspecified clock period correctly yet, returning error.\n",
5475                                              __func__);
5476                                         return -EINVAL;
5477                                 } else {
5478                                         devpriv->clock_ns = period_ns;
5479                                 }
5480                                 devpriv->clock_source = source;
5481                         } else
5482                                 return -EINVAL;
5483                 }
5484         }
5485         return 3;
5486 }
5487
5488 static int ni_valid_rtsi_output_source(struct comedi_device *dev, unsigned chan,
5489                                        unsigned source)
5490 {
5491         const struct ni_board_struct *board = comedi_board(dev);
5492
5493         if (chan >= num_configurable_rtsi_channels(dev)) {
5494                 if (chan == old_RTSI_clock_channel) {
5495                         if (source == NI_RTSI_OUTPUT_RTSI_OSC)
5496                                 return 1;
5497                         else {
5498                                 printk
5499                                     ("%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards.\n",
5500                                      __func__, chan, old_RTSI_clock_channel);
5501                                 return 0;
5502                         }
5503                 }
5504                 return 0;
5505         }
5506         switch (source) {
5507         case NI_RTSI_OUTPUT_ADR_START1:
5508         case NI_RTSI_OUTPUT_ADR_START2:
5509         case NI_RTSI_OUTPUT_SCLKG:
5510         case NI_RTSI_OUTPUT_DACUPDN:
5511         case NI_RTSI_OUTPUT_DA_START1:
5512         case NI_RTSI_OUTPUT_G_SRC0:
5513         case NI_RTSI_OUTPUT_G_GATE0:
5514         case NI_RTSI_OUTPUT_RGOUT0:
5515         case NI_RTSI_OUTPUT_RTSI_BRD_0:
5516                 return 1;
5517                 break;
5518         case NI_RTSI_OUTPUT_RTSI_OSC:
5519                 if (board->reg_type & ni_reg_m_series_mask)
5520                         return 1;
5521                 else
5522                         return 0;
5523                 break;
5524         default:
5525                 return 0;
5526                 break;
5527         }
5528 }
5529
5530 static int ni_set_rtsi_routing(struct comedi_device *dev, unsigned chan,
5531                                unsigned source)
5532 {
5533         struct ni_private *devpriv = dev->private;
5534
5535         if (ni_valid_rtsi_output_source(dev, chan, source) == 0)
5536                 return -EINVAL;
5537         if (chan < 4) {
5538                 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5539                 devpriv->rtsi_trig_a_output_reg |=
5540                     RTSI_Trig_Output_Bits(chan, source);
5541                 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5542                                     RTSI_Trig_A_Output_Register);
5543         } else if (chan < 8) {
5544                 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5545                 devpriv->rtsi_trig_b_output_reg |=
5546                     RTSI_Trig_Output_Bits(chan, source);
5547                 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5548                                     RTSI_Trig_B_Output_Register);
5549         }
5550         return 2;
5551 }
5552
5553 static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan)
5554 {
5555         struct ni_private *devpriv = dev->private;
5556
5557         if (chan < 4) {
5558                 return RTSI_Trig_Output_Source(chan,
5559                                                devpriv->rtsi_trig_a_output_reg);
5560         } else if (chan < num_configurable_rtsi_channels(dev)) {
5561                 return RTSI_Trig_Output_Source(chan,
5562                                                devpriv->rtsi_trig_b_output_reg);
5563         } else {
5564                 if (chan == old_RTSI_clock_channel)
5565                         return NI_RTSI_OUTPUT_RTSI_OSC;
5566                 printk("%s: bug! should never get here?\n", __func__);
5567                 return 0;
5568         }
5569 }
5570
5571 static int ni_rtsi_insn_config(struct comedi_device *dev,
5572                                struct comedi_subdevice *s,
5573                                struct comedi_insn *insn, unsigned int *data)
5574 {
5575         const struct ni_board_struct *board = comedi_board(dev);
5576         struct ni_private *devpriv = dev->private;
5577         unsigned int chan = CR_CHAN(insn->chanspec);
5578
5579         switch (data[0]) {
5580         case INSN_CONFIG_DIO_OUTPUT:
5581                 if (chan < num_configurable_rtsi_channels(dev)) {
5582                         devpriv->rtsi_trig_direction_reg |=
5583                             RTSI_Output_Bit(chan,
5584                                 (board->reg_type & ni_reg_m_series_mask) != 0);
5585                 } else if (chan == old_RTSI_clock_channel) {
5586                         devpriv->rtsi_trig_direction_reg |=
5587                             Drive_RTSI_Clock_Bit;
5588                 }
5589                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5590                                     RTSI_Trig_Direction_Register);
5591                 break;
5592         case INSN_CONFIG_DIO_INPUT:
5593                 if (chan < num_configurable_rtsi_channels(dev)) {
5594                         devpriv->rtsi_trig_direction_reg &=
5595                             ~RTSI_Output_Bit(chan,
5596                                 (board->reg_type & ni_reg_m_series_mask) != 0);
5597                 } else if (chan == old_RTSI_clock_channel) {
5598                         devpriv->rtsi_trig_direction_reg &=
5599                             ~Drive_RTSI_Clock_Bit;
5600                 }
5601                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5602                                     RTSI_Trig_Direction_Register);
5603                 break;
5604         case INSN_CONFIG_DIO_QUERY:
5605                 if (chan < num_configurable_rtsi_channels(dev)) {
5606                         data[1] =
5607                             (devpriv->rtsi_trig_direction_reg &
5608                              RTSI_Output_Bit(chan,
5609                                 (board->reg_type & ni_reg_m_series_mask) != 0))
5610                                 ? INSN_CONFIG_DIO_OUTPUT
5611                                 : INSN_CONFIG_DIO_INPUT;
5612                 } else if (chan == old_RTSI_clock_channel) {
5613                         data[1] =
5614                             (devpriv->rtsi_trig_direction_reg &
5615                              Drive_RTSI_Clock_Bit)
5616                             ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
5617                 }
5618                 return 2;
5619                 break;
5620         case INSN_CONFIG_SET_CLOCK_SRC:
5621                 return ni_set_master_clock(dev, data[1], data[2]);
5622                 break;
5623         case INSN_CONFIG_GET_CLOCK_SRC:
5624                 data[1] = devpriv->clock_source;
5625                 data[2] = devpriv->clock_ns;
5626                 return 3;
5627                 break;
5628         case INSN_CONFIG_SET_ROUTING:
5629                 return ni_set_rtsi_routing(dev, chan, data[1]);
5630                 break;
5631         case INSN_CONFIG_GET_ROUTING:
5632                 data[1] = ni_get_rtsi_routing(dev, chan);
5633                 return 2;
5634                 break;
5635         default:
5636                 return -EINVAL;
5637                 break;
5638         }
5639         return 1;
5640 }
5641
5642 static int cs5529_wait_for_idle(struct comedi_device *dev)
5643 {
5644         unsigned short status;
5645         const int timeout = HZ;
5646         int i;
5647
5648         for (i = 0; i < timeout; i++) {
5649                 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5650                 if ((status & CSS_ADC_BUSY) == 0) {
5651                         break;
5652                 }
5653                 set_current_state(TASK_INTERRUPTIBLE);
5654                 if (schedule_timeout(1)) {
5655                         return -EIO;
5656                 }
5657         }
5658 /* printk("looped %i times waiting for idle\n", i); */
5659         if (i == timeout) {
5660                 printk("%s: %s: timeout\n", __FILE__, __func__);
5661                 return -ETIME;
5662         }
5663         return 0;
5664 }
5665
5666 static void cs5529_command(struct comedi_device *dev, unsigned short value)
5667 {
5668         static const int timeout = 100;
5669         int i;
5670
5671         ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
5672         /* give time for command to start being serially clocked into cs5529.
5673          * this insures that the CSS_ADC_BUSY bit will get properly
5674          * set before we exit this function.
5675          */
5676         for (i = 0; i < timeout; i++) {
5677                 if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
5678                         break;
5679                 udelay(1);
5680         }
5681 /* printk("looped %i times writing command to cs5529\n", i); */
5682         if (i == timeout) {
5683                 comedi_error(dev, "possible problem - never saw adc go busy?");
5684         }
5685 }
5686
5687 /* write to cs5529 register */
5688 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
5689                                 unsigned int reg_select_bits)
5690 {
5691         ni_ao_win_outw(dev, ((value >> 16) & 0xff),
5692                        CAL_ADC_Config_Data_High_Word_67xx);
5693         ni_ao_win_outw(dev, (value & 0xffff),
5694                        CAL_ADC_Config_Data_Low_Word_67xx);
5695         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5696         cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
5697         if (cs5529_wait_for_idle(dev))
5698                 comedi_error(dev, "time or signal in cs5529_config_write()");
5699 }
5700
5701 static int cs5529_do_conversion(struct comedi_device *dev, unsigned short *data)
5702 {
5703         int retval;
5704         unsigned short status;
5705
5706         cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
5707         retval = cs5529_wait_for_idle(dev);
5708         if (retval) {
5709                 comedi_error(dev,
5710                              "timeout or signal in cs5529_do_conversion()");
5711                 return -ETIME;
5712         }
5713         status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5714         if (status & CSS_OSC_DETECT) {
5715                 printk
5716                     ("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n");
5717                 return -EIO;
5718         }
5719         if (status & CSS_OVERRANGE) {
5720                 printk
5721                     ("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n");
5722         }
5723         if (data) {
5724                 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
5725                 /* cs5529 returns 16 bit signed data in bipolar mode */
5726                 *data ^= (1 << 15);
5727         }
5728         return 0;
5729 }
5730
5731 static int cs5529_ai_insn_read(struct comedi_device *dev,
5732                                struct comedi_subdevice *s,
5733                                struct comedi_insn *insn, unsigned int *data)
5734 {
5735         int n, retval;
5736         unsigned short sample;
5737         unsigned int channel_select;
5738         const unsigned int INTERNAL_REF = 0x1000;
5739
5740         /* Set calibration adc source.  Docs lie, reference select bits 8 to 11
5741          * do nothing. bit 12 seems to chooses internal reference voltage, bit
5742          * 13 causes the adc input to go overrange (maybe reads external reference?) */
5743         if (insn->chanspec & CR_ALT_SOURCE)
5744                 channel_select = INTERNAL_REF;
5745         else
5746                 channel_select = CR_CHAN(insn->chanspec);
5747         ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
5748
5749         for (n = 0; n < insn->n; n++) {
5750                 retval = cs5529_do_conversion(dev, &sample);
5751                 if (retval < 0)
5752                         return retval;
5753                 data[n] = sample;
5754         }
5755         return insn->n;
5756 }
5757
5758 static int init_cs5529(struct comedi_device *dev)
5759 {
5760         unsigned int config_bits =
5761             CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
5762
5763 #if 1
5764         /* do self-calibration */
5765         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN,
5766                             CSCMD_CONFIG_REGISTER);
5767         /* need to force a conversion for calibration to run */
5768         cs5529_do_conversion(dev, NULL);
5769 #else
5770         /* force gain calibration to 1 */
5771         cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
5772         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET,
5773                             CSCMD_CONFIG_REGISTER);
5774         if (cs5529_wait_for_idle(dev))
5775                 comedi_error(dev, "timeout or signal in init_cs5529()\n");
5776 #endif
5777         return 0;
5778 }