drivers/staging/comedi/drivers/ni_mio_common.c

   1 /*
   2     comedi/drivers/ni_mio_common.c
   3     Hardware driver for DAQ-STC based boards
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
   7     Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18 */
  19
  20 /*
  21         This file is meant to be included by another file, e.g.,
  22         ni_atmio.c or ni_pcimio.c.
  23
  24         Interrupt support originally added by Truxton Fulton
  25         <trux@truxton.com>
  26
  27         References (from ftp://ftp.natinst.com/support/manuals):
  28
  29            340747b.pdf  AT-MIO E series Register Level Programmer Manual
  30            341079b.pdf  PCI E Series RLPM
  31            340934b.pdf  DAQ-STC reference manual
  32         67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/)
  33         release_ni611x.pdf
  34         release_ni67xx.pdf
  35         Other possibly relevant info:
  36
  37            320517c.pdf  User manual (obsolete)
  38            320517f.pdf  User manual (new)
  39            320889a.pdf  delete
  40            320906c.pdf  maximum signal ratings
  41            321066a.pdf  about 16x
  42            321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  43            321808a.pdf  about at-mio-16e-10 rev P
  44            321837a.pdf  discontinuation of at-mio-16de-10 rev d
  45            321838a.pdf  about at-mio-16de-10 rev N
  46
  47         ISSUES:
  48
  49          - the interrupt routine needs to be cleaned up
  50
  51         2006-02-07: S-Series PCI-6143: Support has been added but is not
  52                 fully tested as yet. Terry Barnaby, BEAM Ltd.
  53 */
  54
  55 #include <linux/interrupt.h>
  56 #include <linux/sched.h>
  57 #include <linux/delay.h>
  58 #include "8255.h"
  59 #include "mite.h"
  60
  61 /* A timeout count */
  62 #define NI_TIMEOUT 1000
  63 static const unsigned old_RTSI_clock_channel = 7;
  64
  65 /* Note: this table must match the ai_gain_* definitions */
  66 static const short ni_gainlkup[][16] = {
  67         [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
  68                         0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  69         [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
  70         [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
  71                         0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  72         [ai_gain_4] = {0, 1, 4, 7},
  73         [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
  74                           0x003, 0x004, 0x005, 0x006},
  75         [ai_gain_622x] = {0, 1, 4, 5},
  76         [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
  77         [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
  78 };
  79
  80 static const struct comedi_lrange range_ni_E_ai = {
  81         16, {
  82                 BIP_RANGE(10),
  83                 BIP_RANGE(5),
  84                 BIP_RANGE(2.5),
  85                 BIP_RANGE(1),
  86                 BIP_RANGE(0.5),
  87                 BIP_RANGE(0.25),
  88                 BIP_RANGE(0.1),
  89                 BIP_RANGE(0.05),
  90                 UNI_RANGE(20),
  91                 UNI_RANGE(10),
  92                 UNI_RANGE(5),
  93                 UNI_RANGE(2),
  94                 UNI_RANGE(1),
  95                 UNI_RANGE(0.5),
  96                 UNI_RANGE(0.2),
  97                 UNI_RANGE(0.1)
  98         }
  99 };
 100
 101 static const struct comedi_lrange range_ni_E_ai_limited = {
 102         8, {
 103                 BIP_RANGE(10),
 104                 BIP_RANGE(5),
 105                 BIP_RANGE(1),
 106                 BIP_RANGE(0.1),
 107                 UNI_RANGE(10),
 108                 UNI_RANGE(5),
 109                 UNI_RANGE(1),
 110                 UNI_RANGE(0.1)
 111         }
 112 };
 113
 114 static const struct comedi_lrange range_ni_E_ai_limited14 = {
 115         14, {
 116                 BIP_RANGE(10),
 117                 BIP_RANGE(5),
 118                 BIP_RANGE(2),
 119                 BIP_RANGE(1),
 120                 BIP_RANGE(0.5),
 121                 BIP_RANGE(0.2),
 122                 BIP_RANGE(0.1),
 123                 UNI_RANGE(10),
 124                 UNI_RANGE(5),
 125                 UNI_RANGE(2),
 126                 UNI_RANGE(1),
 127                 UNI_RANGE(0.5),
 128                 UNI_RANGE(0.2),
 129                 UNI_RANGE(0.1)
 130         }
 131 };
 132
 133 static const struct comedi_lrange range_ni_E_ai_bipolar4 = {
 134         4, {
 135                 BIP_RANGE(10),
 136                 BIP_RANGE(5),
 137                 BIP_RANGE(0.5),
 138                 BIP_RANGE(0.05)
 139         }
 140 };
 141
 142 static const struct comedi_lrange range_ni_E_ai_611x = {
 143         8, {
 144                 BIP_RANGE(50),
 145                 BIP_RANGE(20),
 146                 BIP_RANGE(10),
 147                 BIP_RANGE(5),
 148                 BIP_RANGE(2),
 149                 BIP_RANGE(1),
 150                 BIP_RANGE(0.5),
 151                 BIP_RANGE(0.2)
 152         }
 153 };
 154
 155 static const struct comedi_lrange range_ni_M_ai_622x = {
 156         4, {
 157                 BIP_RANGE(10),
 158                 BIP_RANGE(5),
 159                 BIP_RANGE(1),
 160                 BIP_RANGE(0.2)
 161         }
 162 };
 163
 164 static const struct comedi_lrange range_ni_M_ai_628x = {
 165         7, {
 166                 BIP_RANGE(10),
 167                 BIP_RANGE(5),
 168                 BIP_RANGE(2),
 169                 BIP_RANGE(1),
 170                 BIP_RANGE(0.5),
 171                 BIP_RANGE(0.2),
 172                 BIP_RANGE(0.1)
 173         }
 174 };
 175
 176 static const struct comedi_lrange range_ni_E_ao_ext = {
 177         4, {
 178                 BIP_RANGE(10),
 179                 UNI_RANGE(10),
 180                 RANGE_ext(-1, 1),
 181                 RANGE_ext(0, 1)
 182         }
 183 };
 184
 185 static const struct comedi_lrange *const ni_range_lkup[] = {
 186         [ai_gain_16] = &range_ni_E_ai,
 187         [ai_gain_8] = &range_ni_E_ai_limited,
 188         [ai_gain_14] = &range_ni_E_ai_limited14,
 189         [ai_gain_4] = &range_ni_E_ai_bipolar4,
 190         [ai_gain_611x] = &range_ni_E_ai_611x,
 191         [ai_gain_622x] = &range_ni_M_ai_622x,
 192         [ai_gain_628x] = &range_ni_M_ai_628x,
 193         [ai_gain_6143] = &range_bipolar5
 194 };
 195
 196 enum aimodes {
 197         AIMODE_NONE = 0,
 198         AIMODE_HALF_FULL = 1,
 199         AIMODE_SCAN = 2,
 200         AIMODE_SAMPLE = 3,
 201 };
 202
 203 enum ni_common_subdevices {
 204         NI_AI_SUBDEV,
 205         NI_AO_SUBDEV,
 206         NI_DIO_SUBDEV,
 207         NI_8255_DIO_SUBDEV,
 208         NI_UNUSED_SUBDEV,
 209         NI_CALIBRATION_SUBDEV,
 210         NI_EEPROM_SUBDEV,
 211         NI_PFI_DIO_SUBDEV,
 212         NI_CS5529_CALIBRATION_SUBDEV,
 213         NI_SERIAL_SUBDEV,
 214         NI_RTSI_SUBDEV,
 215         NI_GPCT0_SUBDEV,
 216         NI_GPCT1_SUBDEV,
 217         NI_FREQ_OUT_SUBDEV,
 218         NI_NUM_SUBDEVICES
 219 };
 220 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
 221 {
 222         switch (counter_index) {
 223         case 0:
 224                 return NI_GPCT0_SUBDEV;
 225         case 1:
 226                 return NI_GPCT1_SUBDEV;
 227         default:
 228                 break;
 229         }
 230         BUG();
 231         return NI_GPCT0_SUBDEV;
 232 }
 233
 234 enum timebase_nanoseconds {
 235         TIMEBASE_1_NS = 50,
 236         TIMEBASE_2_NS = 10000
 237 };
 238
 239 #define SERIAL_DISABLED         0
 240 #define SERIAL_600NS            600
 241 #define SERIAL_1_2US            1200
 242 #define SERIAL_10US                     10000
 243
 244 static const int num_adc_stages_611x = 3;
 245
 246 static void ni_writel(struct comedi_device *dev, uint32_t data, int reg)
 247 {
 248         if (dev->mmio)
 249                 writel(data, dev->mmio + reg);
 250
 251         outl(data, dev->iobase + reg);
 252 }
 253
 254 static void ni_writew(struct comedi_device *dev, uint16_t data, int reg)
 255 {
 256         if (dev->mmio)
 257                 writew(data, dev->mmio + reg);
 258
 259         outw(data, dev->iobase + reg);
 260 }
 261
 262 static void ni_writeb(struct comedi_device *dev, uint8_t data, int reg)
 263 {
 264         if (dev->mmio)
 265                 writeb(data, dev->mmio + reg);
 266
 267         outb(data, dev->iobase + reg);
 268 }
 269
 270 static uint32_t ni_readl(struct comedi_device *dev, int reg)
 271 {
 272         if (dev->mmio)
 273                 return readl(dev->mmio + reg);
 274
 275         return inl(dev->iobase + reg);
 276 }
 277
 278 static uint16_t ni_readw(struct comedi_device *dev, int reg)
 279 {
 280         if (dev->mmio)
 281                 return readw(dev->mmio + reg);
 282
 283         return inw(dev->iobase + reg);
 284 }
 285
 286 static uint8_t ni_readb(struct comedi_device *dev, int reg)
 287 {
 288         if (dev->mmio)
 289                 return readb(dev->mmio + reg);
 290
 291         return inb(dev->iobase + reg);
 292 }
 293
 294 /*
 295  * We automatically take advantage of STC registers that can be
 296  * read/written directly in the I/O space of the board.
 297  *
 298  * The AT-MIO and DAQCard devices map the low 8 STC registers to
 299  * iobase+reg*2.
 300  *
 301  * Most PCIMIO devices also map the low 8 STC registers but the
 302  * 611x devices map the read registers to iobase+(addr-1)*2.
 303  * For now non-windowed STC access is disabled if a PCIMIO device
 304  * is detected (devpriv->mite has been initialized).
 305  *
 306  * The M series devices do not used windowed registers for the
 307  * STC registers. The functions below handle the mapping of the
 308  * windowed STC registers to the m series register offsets.
 309  */
 310
 311 struct mio_regmap {
 312         unsigned int mio_reg;
 313         int size;
 314 };
 315
 316 static const struct mio_regmap m_series_stc_write_regmap[] = {
 317         [NISTC_INTA_ACK_REG]            = { 0x104, 2 },
 318         [NISTC_INTB_ACK_REG]            = { 0x106, 2 },
 319         [NISTC_AI_CMD2_REG]             = { 0x108, 2 },
 320         [NISTC_AO_CMD2_REG]             = { 0x10a, 2 },
 321         [NISTC_G0_CMD_REG]              = { 0x10c, 2 },
 322         [NISTC_G1_CMD_REG]              = { 0x10e, 2 },
 323         [NISTC_AI_CMD1_REG]             = { 0x110, 2 },
 324         [NISTC_AO_CMD1_REG]             = { 0x112, 2 },
 325         /*
 326          * NISTC_DIO_OUT_REG maps to:
 327          * { NI_M_DIO_REG, 4 } and { NI_M_SCXI_SER_DO_REG, 1 }
 328          */
 329         [NISTC_DIO_OUT_REG]             = { 0, 0 }, /* DOES NOT MAP CLEANLY */
 330         [NISTC_DIO_CTRL_REG]            = { 0, 0 }, /* DOES NOT MAP CLEANLY */
 331         [NISTC_AI_MODE1_REG]            = { 0x118, 2 },
 332         [NISTC_AI_MODE2_REG]            = { 0x11a, 2 },
 333         [NISTC_AI_SI_LOADA_REG]         = { 0x11c, 4 },
 334         [NISTC_AI_SI_LOADB_REG]         = { 0x120, 4 },
 335         [NISTC_AI_SC_LOADA_REG]         = { 0x124, 4 },
 336         [NISTC_AI_SC_LOADB_REG]         = { 0x128, 4 },
 337         [NISTC_AI_SI2_LOADA_REG]        = { 0x12c, 4 },
 338         [NISTC_AI_SI2_LOADB_REG]        = { 0x130, 4 },
 339         [NISTC_G0_MODE_REG]             = { 0x134, 2 },
 340         [NISTC_G1_MODE_REG]             = { 0x136, 2 },
 341         [NISTC_G0_LOADA_REG]            = { 0x138, 4 },
 342         [NISTC_G0_LOADB_REG]            = { 0x13c, 4 },
 343         [NISTC_G1_LOADA_REG]            = { 0x140, 4 },
 344         [NISTC_G1_LOADB_REG]            = { 0x144, 4 },
 345         [NISTC_G0_INPUT_SEL_REG]        = { 0x148, 2 },
 346         [NISTC_G1_INPUT_SEL_REG]        = { 0x14a, 2 },
 347         [NISTC_AO_MODE1_REG]            = { 0x14c, 2 },
 348         [NISTC_AO_MODE2_REG]            = { 0x14e, 2 },
 349         [NISTC_AO_UI_LOADA_REG]         = { 0x150, 4 },
 350         [NISTC_AO_UI_LOADB_REG]         = { 0x154, 4 },
 351         [NISTC_AO_BC_LOADA_REG]         = { 0x158, 4 },
 352         [NISTC_AO_BC_LOADB_REG]         = { 0x15c, 4 },
 353         [NISTC_AO_UC_LOADA_REG]         = { 0x160, 4 },
 354         [NISTC_AO_UC_LOADB_REG]         = { 0x164, 4 },
 355         [Clock_and_FOUT_Register]       = { 0x170, 2 },
 356         [IO_Bidirection_Pin_Register]   = { 0x172, 2 },
 357         [RTSI_Trig_Direction_Register]  = { 0x174, 2 },
 358         [Interrupt_Control_Register]    = { 0x176, 2 },
 359         [AI_Output_Control_Register]    = { 0x178, 2 },
 360         [Analog_Trigger_Etc_Register]   = { 0x17a, 2 },
 361         [AI_START_STOP_Select_Register] = { 0x17c, 2 },
 362         [AI_Trigger_Select_Register]    = { 0x17e, 2 },
 363         [AI_DIV_Load_A_Register]        = { 0x180, 4 },
 364         [AO_Start_Select_Register]      = { 0x184, 2 },
 365         [AO_Trigger_Select_Register]    = { 0x186, 2 },
 366         [G_Autoincrement_Register(0)]   = { 0x188, 2 },
 367         [G_Autoincrement_Register(1)]   = { 0x18a, 2 },
 368         [AO_Mode_3_Register]            = { 0x18c, 2 },
 369         [Joint_Reset_Register]          = { 0x190, 2 },
 370         [Interrupt_A_Enable_Register]   = { 0x192, 2 },
 371         [Second_IRQ_A_Enable_Register]  = { 0, 0 }, /* E-Series only */
 372         [Interrupt_B_Enable_Register]   = { 0x196, 2 },
 373         [Second_IRQ_B_Enable_Register]  = { 0, 0 }, /* E-Series only */
 374         [AI_Personal_Register]          = { 0x19a, 2 },
 375         [AO_Personal_Register]          = { 0x19c, 2 },
 376         [RTSI_Trig_A_Output_Register]   = { 0x19e, 2 },
 377         [RTSI_Trig_B_Output_Register]   = { 0x1a0, 2 },
 378         [RTSI_Board_Register]           = { 0, 0 }, /* Unknown */
 379         [Configuration_Memory_Clear]    = { 0x1a4, 2 },
 380         [ADC_FIFO_Clear]                = { 0x1a6, 2 },
 381         [DAC_FIFO_Clear]                = { 0x1a8, 2 },
 382         [AO_Output_Control_Register]    = { 0x1ac, 2 },
 383         [AI_Mode_3_Register]            = { 0x1ae, 2 },
 384 };
 385
 386 static void m_series_stc_write(struct comedi_device *dev,
 387                                unsigned int data, unsigned int reg)
 388 {
 389         const struct mio_regmap *regmap;
 390
 391         if (reg < ARRAY_SIZE(m_series_stc_write_regmap)) {
 392                 regmap = &m_series_stc_write_regmap[reg];
 393         } else {
 394                 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
 395                          __func__, reg);
 396                 return;
 397         }
 398
 399         switch (regmap->size) {
 400         case 4:
 401                 ni_writel(dev, data, regmap->mio_reg);
 402                 break;
 403         case 2:
 404                 ni_writew(dev, data, regmap->mio_reg);
 405                 break;
 406         default:
 407                 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
 408                          __func__, reg);
 409                 break;
 410         }
 411 }
 412
 413 static const struct mio_regmap m_series_stc_read_regmap[] = {
 414         [AI_Status_1_Register]          = { 0x104, 2 },
 415         [AO_Status_1_Register]          = { 0x106, 2 },
 416         [G_Status_Register]             = { 0x108, 2 },
 417         [AI_Status_2_Register]          = { 0, 0 }, /* Unknown */
 418         [AO_Status_2_Register]          = { 0x10c, 2 },
 419         [DIO_Parallel_Input_Register]   = { 0, 0 }, /* Unknown */
 420         [G_HW_Save_Register(0)]         = { 0x110, 4 },
 421         [G_HW_Save_Register(1)]         = { 0x114, 4 },
 422         [G_Save_Register(0)]            = { 0x118, 4 },
 423         [G_Save_Register(1)]            = { 0x11c, 4 },
 424         [AO_UI_Save_Registers]          = { 0x120, 4 },
 425         [AO_BC_Save_Registers]          = { 0x124, 4 },
 426         [AO_UC_Save_Registers]          = { 0x128, 4 },
 427         [Joint_Status_1_Register]       = { 0x136, 2 },
 428         [DIO_Serial_Input_Register]     = { 0x009, 1 },
 429         [Joint_Status_2_Register]       = { 0x13a, 2 },
 430         [AI_SI_Save_Registers]          = { 0x180, 4 },
 431         [AI_SC_Save_Registers]          = { 0x184, 4 },
 432 };
 433
 434 static unsigned int m_series_stc_read(struct comedi_device *dev,
 435                                       unsigned int reg)
 436 {
 437         const struct mio_regmap *regmap;
 438
 439         if (reg < ARRAY_SIZE(m_series_stc_read_regmap)) {
 440                 regmap = &m_series_stc_read_regmap[reg];
 441         } else {
 442                 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
 443                          __func__, reg);
 444                 return 0;
 445         }
 446
 447         switch (regmap->size) {
 448         case 4:
 449                 return ni_readl(dev, regmap->mio_reg);
 450         case 2:
 451                 return ni_readw(dev, regmap->mio_reg);
 452         case 1:
 453                 return ni_readb(dev, regmap->mio_reg);
 454         default:
 455                 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
 456                          __func__, reg);
 457                 return 0;
 458         }
 459 }
 460
 461 static void ni_stc_writew(struct comedi_device *dev, uint16_t data, int reg)
 462 {
 463         struct ni_private *devpriv = dev->private;
 464         unsigned long flags;
 465
 466         if (devpriv->is_m_series) {
 467                 m_series_stc_write(dev, data, reg);
 468         } else {
 469                 spin_lock_irqsave(&devpriv->window_lock, flags);
 470                 if (!devpriv->mite && reg < 8) {
 471                         ni_writew(dev, data, reg * 2);
 472                 } else {
 473                         ni_writew(dev, reg, Window_Address);
 474                         ni_writew(dev, data, Window_Data);
 475                 }
 476                 spin_unlock_irqrestore(&devpriv->window_lock, flags);
 477         }
 478 }
 479
 480 static void ni_stc_writel(struct comedi_device *dev, uint32_t data, int reg)
 481 {
 482         struct ni_private *devpriv = dev->private;
 483
 484         if (devpriv->is_m_series) {
 485                 m_series_stc_write(dev, data, reg);
 486         } else {
 487                 ni_stc_writew(dev, data >> 16, reg);
 488                 ni_stc_writew(dev, data & 0xffff, reg + 1);
 489         }
 490 }
 491
 492 static uint16_t ni_stc_readw(struct comedi_device *dev, int reg)
 493 {
 494         struct ni_private *devpriv = dev->private;
 495         unsigned long flags;
 496         uint16_t val;
 497
 498         if (devpriv->is_m_series) {
 499                 val = m_series_stc_read(dev, reg);
 500         } else {
 501                 spin_lock_irqsave(&devpriv->window_lock, flags);
 502                 if (!devpriv->mite && reg < 8) {
 503                         val = ni_readw(dev, reg * 2);
 504                 } else {
 505                         ni_writew(dev, reg, Window_Address);
 506                         val = ni_readw(dev, Window_Data);
 507                 }
 508                 spin_unlock_irqrestore(&devpriv->window_lock, flags);
 509         }
 510         return val;
 511 }
 512
 513 static uint32_t ni_stc_readl(struct comedi_device *dev, int reg)
 514 {
 515         struct ni_private *devpriv = dev->private;
 516         uint32_t val;
 517
 518         if (devpriv->is_m_series) {
 519                 val = m_series_stc_read(dev, reg);
 520         } else {
 521                 val = ni_stc_readw(dev, reg) << 16;
 522                 val |= ni_stc_readw(dev, reg + 1);
 523         }
 524         return val;
 525 }
 526
 527 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
 528                                    unsigned bit_mask, unsigned bit_values)
 529 {
 530         struct ni_private *devpriv = dev->private;
 531         unsigned long flags;
 532
 533         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 534         switch (reg) {
 535         case Interrupt_A_Enable_Register:
 536                 devpriv->int_a_enable_reg &= ~bit_mask;
 537                 devpriv->int_a_enable_reg |= bit_values & bit_mask;
 538                 ni_stc_writew(dev, devpriv->int_a_enable_reg,
 539                               Interrupt_A_Enable_Register);
 540                 break;
 541         case Interrupt_B_Enable_Register:
 542                 devpriv->int_b_enable_reg &= ~bit_mask;
 543                 devpriv->int_b_enable_reg |= bit_values & bit_mask;
 544                 ni_stc_writew(dev, devpriv->int_b_enable_reg,
 545                               Interrupt_B_Enable_Register);
 546                 break;
 547         case IO_Bidirection_Pin_Register:
 548                 devpriv->io_bidirection_pin_reg &= ~bit_mask;
 549                 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
 550                 ni_stc_writew(dev, devpriv->io_bidirection_pin_reg,
 551                               IO_Bidirection_Pin_Register);
 552                 break;
 553         case AI_AO_Select:
 554                 devpriv->ai_ao_select_reg &= ~bit_mask;
 555                 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
 556                 ni_writeb(dev, devpriv->ai_ao_select_reg, AI_AO_Select);
 557                 break;
 558         case G0_G1_Select:
 559                 devpriv->g0_g1_select_reg &= ~bit_mask;
 560                 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
 561                 ni_writeb(dev, devpriv->g0_g1_select_reg, G0_G1_Select);
 562                 break;
 563         default:
 564                 dev_err(dev->class_dev, "called with invalid register %d\n",
 565                         reg);
 566                 break;
 567         }
 568         mmiowb();
 569         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 570 }
 571
 572 #ifdef PCIDMA
 573 /* DMA channel setup */
 574
 575 /* negative channel means no channel */
 576 static inline void ni_set_ai_dma_channel(struct comedi_device *dev, int channel)
 577 {
 578         unsigned bitfield;
 579
 580         if (channel >= 0)
 581                 bitfield =
 582                     (ni_stc_dma_channel_select_bitfield(channel) <<
 583                      AI_DMA_Select_Shift) & AI_DMA_Select_Mask;
 584         else
 585                 bitfield = 0;
 586         ni_set_bitfield(dev, AI_AO_Select, AI_DMA_Select_Mask, bitfield);
 587 }
 588
 589 /* negative channel means no channel */
 590 static inline void ni_set_ao_dma_channel(struct comedi_device *dev, int channel)
 591 {
 592         unsigned bitfield;
 593
 594         if (channel >= 0)
 595                 bitfield =
 596                     (ni_stc_dma_channel_select_bitfield(channel) <<
 597                      AO_DMA_Select_Shift) & AO_DMA_Select_Mask;
 598         else
 599                 bitfield = 0;
 600         ni_set_bitfield(dev, AI_AO_Select, AO_DMA_Select_Mask, bitfield);
 601 }
 602
 603 /* negative mite_channel means no channel */
 604 static inline void ni_set_gpct_dma_channel(struct comedi_device *dev,
 605                                            unsigned gpct_index,
 606                                            int mite_channel)
 607 {
 608         unsigned bitfield;
 609
 610         if (mite_channel >= 0)
 611                 bitfield = GPCT_DMA_Select_Bits(gpct_index, mite_channel);
 612         else
 613                 bitfield = 0;
 614         ni_set_bitfield(dev, G0_G1_Select, GPCT_DMA_Select_Mask(gpct_index),
 615                         bitfield);
 616 }
 617
 618 /* negative mite_channel means no channel */
 619 static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
 620                                           int mite_channel)
 621 {
 622         struct ni_private *devpriv = dev->private;
 623         unsigned long flags;
 624         unsigned bits;
 625
 626         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 627         devpriv->cdio_dma_select_reg &= ~NI_M_CDIO_DMA_SEL_CDO_MASK;
 628         if (mite_channel >= 0) {
 629                 /*
 630                  * XXX just guessing ni_stc_dma_channel_select_bitfield()
 631                  * returns the right bits, under the assumption the cdio dma
 632                  * selection works just like ai/ao/gpct.
 633                  * Definitely works for dma channels 0 and 1.
 634                  */
 635                 bits = ni_stc_dma_channel_select_bitfield(mite_channel);
 636                 devpriv->cdio_dma_select_reg |= NI_M_CDIO_DMA_SEL_CDO(bits);
 637         }
 638         ni_writeb(dev, devpriv->cdio_dma_select_reg, NI_M_CDIO_DMA_SEL_REG);
 639         mmiowb();
 640         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 641 }
 642
 643 static int ni_request_ai_mite_channel(struct comedi_device *dev)
 644 {
 645         struct ni_private *devpriv = dev->private;
 646         unsigned long flags;
 647
 648         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 649         BUG_ON(devpriv->ai_mite_chan);
 650         devpriv->ai_mite_chan =
 651             mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
 652         if (!devpriv->ai_mite_chan) {
 653                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 654                 dev_err(dev->class_dev,
 655                         "failed to reserve mite dma channel for analog input\n");
 656                 return -EBUSY;
 657         }
 658         devpriv->ai_mite_chan->dir = COMEDI_INPUT;
 659         ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
 660         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 661         return 0;
 662 }
 663
 664 static int ni_request_ao_mite_channel(struct comedi_device *dev)
 665 {
 666         struct ni_private *devpriv = dev->private;
 667         unsigned long flags;
 668
 669         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 670         BUG_ON(devpriv->ao_mite_chan);
 671         devpriv->ao_mite_chan =
 672             mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
 673         if (!devpriv->ao_mite_chan) {
 674                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 675                 dev_err(dev->class_dev,
 676                         "failed to reserve mite dma channel for analog outut\n");
 677                 return -EBUSY;
 678         }
 679         devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
 680         ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
 681         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 682         return 0;
 683 }
 684
 685 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
 686                                         unsigned gpct_index,
 687                                         enum comedi_io_direction direction)
 688 {
 689         struct ni_private *devpriv = dev->private;
 690         unsigned long flags;
 691         struct mite_channel *mite_chan;
 692
 693         BUG_ON(gpct_index >= NUM_GPCT);
 694         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 695         BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
 696         mite_chan =
 697             mite_request_channel(devpriv->mite,
 698                                  devpriv->gpct_mite_ring[gpct_index]);
 699         if (!mite_chan) {
 700                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 701                 dev_err(dev->class_dev,
 702                         "failed to reserve mite dma channel for counter\n");
 703                 return -EBUSY;
 704         }
 705         mite_chan->dir = direction;
 706         ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
 707                                 mite_chan);
 708         ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
 709         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 710         return 0;
 711 }
 712
 713 #endif /*  PCIDMA */
 714
 715 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
 716 {
 717 #ifdef PCIDMA
 718         struct ni_private *devpriv = dev->private;
 719         unsigned long flags;
 720
 721         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 722         BUG_ON(devpriv->cdo_mite_chan);
 723         devpriv->cdo_mite_chan =
 724             mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
 725         if (!devpriv->cdo_mite_chan) {
 726                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 727                 dev_err(dev->class_dev,
 728                         "failed to reserve mite dma channel for correlated digital output\n");
 729                 return -EBUSY;
 730         }
 731         devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
 732         ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
 733         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 734 #endif /*  PCIDMA */
 735         return 0;
 736 }
 737
 738 static void ni_release_ai_mite_channel(struct comedi_device *dev)
 739 {
 740 #ifdef PCIDMA
 741         struct ni_private *devpriv = dev->private;
 742         unsigned long flags;
 743
 744         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 745         if (devpriv->ai_mite_chan) {
 746                 ni_set_ai_dma_channel(dev, -1);
 747                 mite_release_channel(devpriv->ai_mite_chan);
 748                 devpriv->ai_mite_chan = NULL;
 749         }
 750         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 751 #endif /*  PCIDMA */
 752 }
 753
 754 static void ni_release_ao_mite_channel(struct comedi_device *dev)
 755 {
 756 #ifdef PCIDMA
 757         struct ni_private *devpriv = dev->private;
 758         unsigned long flags;
 759
 760         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 761         if (devpriv->ao_mite_chan) {
 762                 ni_set_ao_dma_channel(dev, -1);
 763                 mite_release_channel(devpriv->ao_mite_chan);
 764                 devpriv->ao_mite_chan = NULL;
 765         }
 766         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 767 #endif /*  PCIDMA */
 768 }
 769
 770 #ifdef PCIDMA
 771 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
 772                                          unsigned gpct_index)
 773 {
 774         struct ni_private *devpriv = dev->private;
 775         unsigned long flags;
 776
 777         BUG_ON(gpct_index >= NUM_GPCT);
 778         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 779         if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
 780                 struct mite_channel *mite_chan =
 781                     devpriv->counter_dev->counters[gpct_index].mite_chan;
 782
 783                 ni_set_gpct_dma_channel(dev, gpct_index, -1);
 784                 ni_tio_set_mite_channel(&devpriv->
 785                                         counter_dev->counters[gpct_index],
 786                                         NULL);
 787                 mite_release_channel(mite_chan);
 788         }
 789         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 790 }
 791 #endif /*  PCIDMA */
 792
 793 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
 794 {
 795 #ifdef PCIDMA
 796         struct ni_private *devpriv = dev->private;
 797         unsigned long flags;
 798
 799         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 800         if (devpriv->cdo_mite_chan) {
 801                 ni_set_cdo_dma_channel(dev, -1);
 802                 mite_release_channel(devpriv->cdo_mite_chan);
 803                 devpriv->cdo_mite_chan = NULL;
 804         }
 805         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 806 #endif /*  PCIDMA */
 807 }
 808
 809 #ifdef PCIDMA
 810 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
 811                                           unsigned gpct_index, short enable)
 812 {
 813         struct ni_private *devpriv = dev->private;
 814         uint16_t val = 0;
 815         int reg;
 816
 817         if (devpriv->is_m_series || gpct_index > 1)
 818                 return;
 819
 820         /*
 821          * e-series boards use the second irq signals to generate
 822          * dma requests for their counters
 823          */
 824         if (gpct_index == 0) {
 825                 reg = Second_IRQ_A_Enable_Register;
 826                 if (enable)
 827                         val = G0_Gate_Second_Irq_Enable;
 828         } else {
 829                 reg = Second_IRQ_B_Enable_Register;
 830                 if (enable)
 831                         val = G1_Gate_Second_Irq_Enable;
 832         }
 833         ni_stc_writew(dev, val, reg);
 834 }
 835 #endif /*  PCIDMA */
 836
 837 static void ni_clear_ai_fifo(struct comedi_device *dev)
 838 {
 839         struct ni_private *devpriv = dev->private;
 840         static const int timeout = 10000;
 841         int i;
 842
 843         if (devpriv->is_6143) {
 844                 /*  Flush the 6143 data FIFO */
 845                 ni_writel(dev, 0x10, AIFIFO_Control_6143);
 846                 ni_writel(dev, 0x00, AIFIFO_Control_6143);
 847                 /*  Wait for complete */
 848                 for (i = 0; i < timeout; i++) {
 849                         if (!(ni_readl(dev, AIFIFO_Status_6143) & 0x10))
 850                                 break;
 851                         udelay(1);
 852                 }
 853                 if (i == timeout)
 854                         dev_err(dev->class_dev, "FIFO flush timeout\n");
 855         } else {
 856                 ni_stc_writew(dev, 1, ADC_FIFO_Clear);
 857                 if (devpriv->is_625x) {
 858                         ni_writeb(dev, 0, NI_M_STATIC_AI_CTRL_REG(0));
 859                         ni_writeb(dev, 1, NI_M_STATIC_AI_CTRL_REG(0));
 860 #if 0
 861                         /* the NI example code does 3 convert pulses for 625x boards,
 862                            but that appears to be wrong in practice. */
 863                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
 864                                       NISTC_AI_CMD1_REG);
 865                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
 866                                       NISTC_AI_CMD1_REG);
 867                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
 868                                       NISTC_AI_CMD1_REG);
 869 #endif
 870                 }
 871         }
 872 }
 873
 874 static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data,
 875                                   int addr)
 876 {
 877         struct ni_private *devpriv = dev->private;
 878         unsigned long flags;
 879
 880         spin_lock_irqsave(&devpriv->window_lock, flags);
 881         ni_writew(dev, addr, AO_Window_Address_611x);
 882         ni_writew(dev, data, AO_Window_Data_611x);
 883         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 884 }
 885
 886 static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data,
 887                                   int addr)
 888 {
 889         struct ni_private *devpriv = dev->private;
 890         unsigned long flags;
 891
 892         spin_lock_irqsave(&devpriv->window_lock, flags);
 893         ni_writew(dev, addr, AO_Window_Address_611x);
 894         ni_writel(dev, data, AO_Window_Data_611x);
 895         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 896 }
 897
 898 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
 899 {
 900         struct ni_private *devpriv = dev->private;
 901         unsigned long flags;
 902         unsigned short data;
 903
 904         spin_lock_irqsave(&devpriv->window_lock, flags);
 905         ni_writew(dev, addr, AO_Window_Address_611x);
 906         data = ni_readw(dev, AO_Window_Data_611x);
 907         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 908         return data;
 909 }
 910
 911 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
 912 * share registers (such as Interrupt_A_Register) without interfering with
 913 * each other.
 914 *
 915 * NOTE: the switch/case statements are optimized out for a constant argument
 916 * so this is actually quite fast---  If you must wrap another function around this
 917 * make it inline to avoid a large speed penalty.
 918 *
 919 * value should only be 1 or 0.
 920 */
 921 static inline void ni_set_bits(struct comedi_device *dev, int reg,
 922                                unsigned bits, unsigned value)
 923 {
 924         unsigned bit_values;
 925
 926         if (value)
 927                 bit_values = bits;
 928         else
 929                 bit_values = 0;
 930         ni_set_bitfield(dev, reg, bits, bit_values);
 931 }
 932
 933 #ifdef PCIDMA
 934 static void ni_sync_ai_dma(struct comedi_device *dev)
 935 {
 936         struct ni_private *devpriv = dev->private;
 937         struct comedi_subdevice *s = dev->read_subdev;
 938         unsigned long flags;
 939
 940         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 941         if (devpriv->ai_mite_chan)
 942                 mite_sync_input_dma(devpriv->ai_mite_chan, s);
 943         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 944 }
 945
 946 static int ni_ai_drain_dma(struct comedi_device *dev)
 947 {
 948         struct ni_private *devpriv = dev->private;
 949         int i;
 950         static const int timeout = 10000;
 951         unsigned long flags;
 952         int retval = 0;
 953
 954         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 955         if (devpriv->ai_mite_chan) {
 956                 for (i = 0; i < timeout; i++) {
 957                         if ((ni_stc_readw(dev, AI_Status_1_Register) &
 958                              AI_FIFO_Empty_St)
 959                             && mite_bytes_in_transit(devpriv->ai_mite_chan) ==
 960                             0)
 961                                 break;
 962                         udelay(5);
 963                 }
 964                 if (i == timeout) {
 965                         dev_err(dev->class_dev, "timed out\n");
 966                         dev_err(dev->class_dev,
 967                                 "mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
 968                                 mite_bytes_in_transit(devpriv->ai_mite_chan),
 969                                 ni_stc_readw(dev, AI_Status_1_Register));
 970                         retval = -1;
 971                 }
 972         }
 973         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 974
 975         ni_sync_ai_dma(dev);
 976
 977         return retval;
 978 }
 979
 980 static void mite_handle_b_linkc(struct mite_struct *mite,
 981                                 struct comedi_device *dev)
 982 {
 983         struct ni_private *devpriv = dev->private;
 984         struct comedi_subdevice *s = dev->write_subdev;
 985         unsigned long flags;
 986
 987         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 988         if (devpriv->ao_mite_chan)
 989                 mite_sync_output_dma(devpriv->ao_mite_chan, s);
 990         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 991 }
 992
 993 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
 994 {
 995         static const int timeout = 10000;
 996         int i;
 997
 998         for (i = 0; i < timeout; i++) {
 999                 unsigned short b_status;
1000
1001                 b_status = ni_stc_readw(dev, AO_Status_1_Register);
1002                 if (b_status & AO_FIFO_Half_Full_St)
1003                         break;
1004                 /* if we poll too often, the pci bus activity seems
1005                    to slow the dma transfer down */
1006                 udelay(10);
1007         }
1008         if (i == timeout) {
1009                 dev_err(dev->class_dev, "timed out waiting for dma load\n");
1010                 return -EPIPE;
1011         }
1012         return 0;
1013 }
1014 #endif /* PCIDMA */
1015
1016 #ifndef PCIDMA
1017
1018 static void ni_ao_fifo_load(struct comedi_device *dev,
1019                             struct comedi_subdevice *s, int n)
1020 {
1021         struct ni_private *devpriv = dev->private;
1022         int i;
1023         unsigned short d;
1024         u32 packed_data;
1025
1026         for (i = 0; i < n; i++) {
1027                 comedi_buf_read_samples(s, &d, 1);
1028
1029                 if (devpriv->is_6xxx) {
1030                         packed_data = d & 0xffff;
1031                         /* 6711 only has 16 bit wide ao fifo */
1032                         if (!devpriv->is_6711) {
1033                                 comedi_buf_read_samples(s, &d, 1);
1034                                 i++;
1035                                 packed_data |= (d << 16) & 0xffff0000;
1036                         }
1037                         ni_writel(dev, packed_data, DAC_FIFO_Data_611x);
1038                 } else {
1039                         ni_writew(dev, d, DAC_FIFO_Data);
1040                 }
1041         }
1042 }
1043
1044 /*
1045  *  There's a small problem if the FIFO gets really low and we
1046  *  don't have the data to fill it.  Basically, if after we fill
1047  *  the FIFO with all the data available, the FIFO is _still_
1048  *  less than half full, we never clear the interrupt.  If the
1049  *  IRQ is in edge mode, we never get another interrupt, because
1050  *  this one wasn't cleared.  If in level mode, we get flooded
1051  *  with interrupts that we can't fulfill, because nothing ever
1052  *  gets put into the buffer.
1053  *
1054  *  This kind of situation is recoverable, but it is easier to
1055  *  just pretend we had a FIFO underrun, since there is a good
1056  *  chance it will happen anyway.  This is _not_ the case for
1057  *  RT code, as RT code might purposely be running close to the
1058  *  metal.  Needs to be fixed eventually.
1059  */
1060 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1061                                  struct comedi_subdevice *s)
1062 {
1063         const struct ni_board_struct *board = dev->board_ptr;
1064         unsigned int nbytes;
1065         unsigned int nsamples;
1066
1067         nbytes = comedi_buf_read_n_available(s);
1068         if (nbytes == 0) {
1069                 s->async->events |= COMEDI_CB_OVERFLOW;
1070                 return 0;
1071         }
1072
1073         nsamples = comedi_bytes_to_samples(s, nbytes);
1074         if (nsamples > board->ao_fifo_depth / 2)
1075                 nsamples = board->ao_fifo_depth / 2;
1076
1077         ni_ao_fifo_load(dev, s, nsamples);
1078
1079         return 1;
1080 }
1081
1082 static int ni_ao_prep_fifo(struct comedi_device *dev,
1083                            struct comedi_subdevice *s)
1084 {
1085         const struct ni_board_struct *board = dev->board_ptr;
1086         struct ni_private *devpriv = dev->private;
1087         unsigned int nbytes;
1088         unsigned int nsamples;
1089
1090         /* reset fifo */
1091         ni_stc_writew(dev, 1, DAC_FIFO_Clear);
1092         if (devpriv->is_6xxx)
1093                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
1094
1095         /* load some data */
1096         nbytes = comedi_buf_read_n_available(s);
1097         if (nbytes == 0)
1098                 return 0;
1099
1100         nsamples = comedi_bytes_to_samples(s, nbytes);
1101         if (nsamples > board->ao_fifo_depth)
1102                 nsamples = board->ao_fifo_depth;
1103
1104         ni_ao_fifo_load(dev, s, nsamples);
1105
1106         return nsamples;
1107 }
1108
1109 static void ni_ai_fifo_read(struct comedi_device *dev,
1110                             struct comedi_subdevice *s, int n)
1111 {
1112         struct ni_private *devpriv = dev->private;
1113         struct comedi_async *async = s->async;
1114         u32 dl;
1115         unsigned short data;
1116         int i;
1117
1118         if (devpriv->is_611x) {
1119                 for (i = 0; i < n / 2; i++) {
1120                         dl = ni_readl(dev, ADC_FIFO_Data_611x);
1121                         /* This may get the hi/lo data in the wrong order */
1122                         data = (dl >> 16) & 0xffff;
1123                         comedi_buf_write_samples(s, &data, 1);
1124                         data = dl & 0xffff;
1125                         comedi_buf_write_samples(s, &data, 1);
1126                 }
1127                 /* Check if there's a single sample stuck in the FIFO */
1128                 if (n % 2) {
1129                         dl = ni_readl(dev, ADC_FIFO_Data_611x);
1130                         data = dl & 0xffff;
1131                         comedi_buf_write_samples(s, &data, 1);
1132                 }
1133         } else if (devpriv->is_6143) {
1134                 /*  This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
1135                 for (i = 0; i < n / 2; i++) {
1136                         dl = ni_readl(dev, AIFIFO_Data_6143);
1137
1138                         data = (dl >> 16) & 0xffff;
1139                         comedi_buf_write_samples(s, &data, 1);
1140                         data = dl & 0xffff;
1141                         comedi_buf_write_samples(s, &data, 1);
1142                 }
1143                 if (n % 2) {
1144                         /* Assume there is a single sample stuck in the FIFO */
1145                         /* Get stranded sample into FIFO */
1146                         ni_writel(dev, 0x01, AIFIFO_Control_6143);
1147                         dl = ni_readl(dev, AIFIFO_Data_6143);
1148                         data = (dl >> 16) & 0xffff;
1149                         comedi_buf_write_samples(s, &data, 1);
1150                 }
1151         } else {
1152                 if (n > sizeof(devpriv->ai_fifo_buffer) /
1153                     sizeof(devpriv->ai_fifo_buffer[0])) {
1154                         dev_err(dev->class_dev,
1155                                 "bug! ai_fifo_buffer too small\n");
1156                         async->events |= COMEDI_CB_ERROR;
1157                         return;
1158                 }
1159                 for (i = 0; i < n; i++) {
1160                         devpriv->ai_fifo_buffer[i] =
1161                             ni_readw(dev, ADC_FIFO_Data_Register);
1162                 }
1163                 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, n);
1164         }
1165 }
1166
1167 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1168 {
1169         const struct ni_board_struct *board = dev->board_ptr;
1170         struct comedi_subdevice *s = dev->read_subdev;
1171         int n;
1172
1173         n = board->ai_fifo_depth / 2;
1174
1175         ni_ai_fifo_read(dev, s, n);
1176 }
1177 #endif
1178
1179 /*
1180    Empties the AI fifo
1181 */
1182 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1183 {
1184         struct ni_private *devpriv = dev->private;
1185         struct comedi_subdevice *s = dev->read_subdev;
1186         u32 dl;
1187         unsigned short data;
1188         unsigned short fifo_empty;
1189         int i;
1190
1191         if (devpriv->is_611x) {
1192                 while ((ni_stc_readw(dev, AI_Status_1_Register) &
1193                         AI_FIFO_Empty_St) == 0) {
1194                         dl = ni_readl(dev, ADC_FIFO_Data_611x);
1195
1196                         /* This may get the hi/lo data in the wrong order */
1197                         data = dl >> 16;
1198                         comedi_buf_write_samples(s, &data, 1);
1199                         data = dl & 0xffff;
1200                         comedi_buf_write_samples(s, &data, 1);
1201                 }
1202         } else if (devpriv->is_6143) {
1203                 i = 0;
1204                 while (ni_readl(dev, AIFIFO_Status_6143) & 0x04) {
1205                         dl = ni_readl(dev, AIFIFO_Data_6143);
1206
1207                         /* This may get the hi/lo data in the wrong order */
1208                         data = dl >> 16;
1209                         comedi_buf_write_samples(s, &data, 1);
1210                         data = dl & 0xffff;
1211                         comedi_buf_write_samples(s, &data, 1);
1212                         i += 2;
1213                 }
1214                 /*  Check if stranded sample is present */
1215                 if (ni_readl(dev, AIFIFO_Status_6143) & 0x01) {
1216                         /* Get stranded sample into FIFO */
1217                         ni_writel(dev, 0x01, AIFIFO_Control_6143);
1218                         dl = ni_readl(dev, AIFIFO_Data_6143);
1219                         data = (dl >> 16) & 0xffff;
1220                         comedi_buf_write_samples(s, &data, 1);
1221                 }
1222
1223         } else {
1224                 fifo_empty = ni_stc_readw(dev, AI_Status_1_Register) &
1225                              AI_FIFO_Empty_St;
1226                 while (fifo_empty == 0) {
1227                         for (i = 0;
1228                              i <
1229                              sizeof(devpriv->ai_fifo_buffer) /
1230                              sizeof(devpriv->ai_fifo_buffer[0]); i++) {
1231                                 fifo_empty = ni_stc_readw(dev,
1232                                                           AI_Status_1_Register) &
1233                                                 AI_FIFO_Empty_St;
1234                                 if (fifo_empty)
1235                                         break;
1236                                 devpriv->ai_fifo_buffer[i] =
1237                                     ni_readw(dev, ADC_FIFO_Data_Register);
1238                         }
1239                         comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, i);
1240                 }
1241         }
1242 }
1243
1244 static void get_last_sample_611x(struct comedi_device *dev)
1245 {
1246         struct ni_private *devpriv = dev->private;
1247         struct comedi_subdevice *s = dev->read_subdev;
1248         unsigned short data;
1249         u32 dl;
1250
1251         if (!devpriv->is_611x)
1252                 return;
1253
1254         /* Check if there's a single sample stuck in the FIFO */
1255         if (ni_readb(dev, XXX_Status) & 0x80) {
1256                 dl = ni_readl(dev, ADC_FIFO_Data_611x);
1257                 data = dl & 0xffff;
1258                 comedi_buf_write_samples(s, &data, 1);
1259         }
1260 }
1261
1262 static void get_last_sample_6143(struct comedi_device *dev)
1263 {
1264         struct ni_private *devpriv = dev->private;
1265         struct comedi_subdevice *s = dev->read_subdev;
1266         unsigned short data;
1267         u32 dl;
1268
1269         if (!devpriv->is_6143)
1270                 return;
1271
1272         /* Check if there's a single sample stuck in the FIFO */
1273         if (ni_readl(dev, AIFIFO_Status_6143) & 0x01) {
1274                 /* Get stranded sample into FIFO */
1275                 ni_writel(dev, 0x01, AIFIFO_Control_6143);
1276                 dl = ni_readl(dev, AIFIFO_Data_6143);
1277
1278                 /* This may get the hi/lo data in the wrong order */
1279                 data = (dl >> 16) & 0xffff;
1280                 comedi_buf_write_samples(s, &data, 1);
1281         }
1282 }
1283
1284 static void shutdown_ai_command(struct comedi_device *dev)
1285 {
1286         struct comedi_subdevice *s = dev->read_subdev;
1287
1288 #ifdef PCIDMA
1289         ni_ai_drain_dma(dev);
1290 #endif
1291         ni_handle_fifo_dregs(dev);
1292         get_last_sample_611x(dev);
1293         get_last_sample_6143(dev);
1294
1295         s->async->events |= COMEDI_CB_EOA;
1296 }
1297
1298 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
1299 {
1300         struct ni_private *devpriv = dev->private;
1301
1302         if (devpriv->aimode == AIMODE_SCAN) {
1303 #ifdef PCIDMA
1304                 static const int timeout = 10;
1305                 int i;
1306
1307                 for (i = 0; i < timeout; i++) {
1308                         ni_sync_ai_dma(dev);
1309                         if ((s->async->events & COMEDI_CB_EOS))
1310                                 break;
1311                         udelay(1);
1312                 }
1313 #else
1314                 ni_handle_fifo_dregs(dev);
1315                 s->async->events |= COMEDI_CB_EOS;
1316 #endif
1317         }
1318         /* handle special case of single scan */
1319         if (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)
1320                 shutdown_ai_command(dev);
1321 }
1322
1323 static void handle_gpct_interrupt(struct comedi_device *dev,
1324                                   unsigned short counter_index)
1325 {
1326 #ifdef PCIDMA
1327         struct ni_private *devpriv = dev->private;
1328         struct comedi_subdevice *s;
1329
1330         s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
1331
1332         ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
1333                                 s);
1334         comedi_handle_events(dev, s);
1335 #endif
1336 }
1337
1338 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
1339 {
1340         unsigned short ack = 0;
1341
1342         if (a_status & AI_SC_TC_St)
1343                 ack |= NISTC_INTA_ACK_AI_SC_TC;
1344         if (a_status & AI_START1_St)
1345                 ack |= NISTC_INTA_ACK_AI_START1;
1346         if (a_status & AI_START_St)
1347                 ack |= NISTC_INTA_ACK_AI_START;
1348         if (a_status & AI_STOP_St)
1349                 ack |= NISTC_INTA_ACK_AI_STOP;
1350         if (ack)
1351                 ni_stc_writew(dev, ack, NISTC_INTA_ACK_REG);
1352 }
1353
1354 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
1355                                unsigned ai_mite_status)
1356 {
1357         struct comedi_subdevice *s = dev->read_subdev;
1358         struct comedi_cmd *cmd = &s->async->cmd;
1359
1360         /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */
1361         if (s->type == COMEDI_SUBD_UNUSED)
1362                 return;
1363
1364 #ifdef PCIDMA
1365         if (ai_mite_status & CHSR_LINKC)
1366                 ni_sync_ai_dma(dev);
1367
1368         if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1369                                CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1370                                CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1371                 dev_err(dev->class_dev,
1372                         "unknown mite interrupt (ai_mite_status=%08x)\n",
1373                         ai_mite_status);
1374                 s->async->events |= COMEDI_CB_ERROR;
1375                 /* disable_irq(dev->irq); */
1376         }
1377 #endif
1378
1379         /* test for all uncommon interrupt events at the same time */
1380         if (status & (AI_Overrun_St | AI_Overflow_St | AI_SC_TC_Error_St |
1381                       AI_SC_TC_St | AI_START1_St)) {
1382                 if (status == 0xffff) {
1383                         dev_err(dev->class_dev, "Card removed?\n");
1384                         /* we probably aren't even running a command now,
1385                          * so it's a good idea to be careful. */
1386                         if (comedi_is_subdevice_running(s)) {
1387                                 s->async->events |= COMEDI_CB_ERROR;
1388                                 comedi_handle_events(dev, s);
1389                         }
1390                         return;
1391                 }
1392                 if (status & (AI_Overrun_St | AI_Overflow_St |
1393                               AI_SC_TC_Error_St)) {
1394                         dev_err(dev->class_dev, "ai error a_status=%04x\n",
1395                                 status);
1396
1397                         shutdown_ai_command(dev);
1398
1399                         s->async->events |= COMEDI_CB_ERROR;
1400                         if (status & (AI_Overrun_St | AI_Overflow_St))
1401                                 s->async->events |= COMEDI_CB_OVERFLOW;
1402
1403                         comedi_handle_events(dev, s);
1404                         return;
1405                 }
1406                 if (status & AI_SC_TC_St) {
1407                         if (cmd->stop_src == TRIG_COUNT)
1408                                 shutdown_ai_command(dev);
1409                 }
1410         }
1411 #ifndef PCIDMA
1412         if (status & AI_FIFO_Half_Full_St) {
1413                 int i;
1414                 static const int timeout = 10;
1415                 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1416                  *fail to get the fifo less than half full, so loop to be sure.*/
1417                 for (i = 0; i < timeout; ++i) {
1418                         ni_handle_fifo_half_full(dev);
1419                         if ((ni_stc_readw(dev, AI_Status_1_Register) &
1420                              AI_FIFO_Half_Full_St) == 0)
1421                                 break;
1422                 }
1423         }
1424 #endif /*  !PCIDMA */
1425
1426         if ((status & AI_STOP_St))
1427                 ni_handle_eos(dev, s);
1428
1429         comedi_handle_events(dev, s);
1430 }
1431
1432 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1433 {
1434         unsigned short ack = 0;
1435
1436         if (b_status & AO_BC_TC_St)
1437                 ack |= NISTC_INTB_ACK_AO_BC_TC;
1438         if (b_status & AO_Overrun_St)
1439                 ack |= NISTC_INTB_ACK_AO_ERR;
1440         if (b_status & AO_START_St)
1441                 ack |= NISTC_INTB_ACK_AO_START;
1442         if (b_status & AO_START1_St)
1443                 ack |= NISTC_INTB_ACK_AO_START1;
1444         if (b_status & AO_UC_TC_St)
1445                 ack |= NISTC_INTB_ACK_AO_UC_TC;
1446         if (b_status & AO_UI2_TC_St)
1447                 ack |= NISTC_INTB_ACK_AO_UI2_TC;
1448         if (b_status & AO_UPDATE_St)
1449                 ack |= NISTC_INTB_ACK_AO_UPDATE;
1450         if (ack)
1451                 ni_stc_writew(dev, ack, NISTC_INTB_ACK_REG);
1452 }
1453
1454 static void handle_b_interrupt(struct comedi_device *dev,
1455                                unsigned short b_status, unsigned ao_mite_status)
1456 {
1457         struct comedi_subdevice *s = dev->write_subdev;
1458         /* unsigned short ack=0; */
1459
1460 #ifdef PCIDMA
1461         /* Currently, mite.c requires us to handle LINKC */
1462         if (ao_mite_status & CHSR_LINKC) {
1463                 struct ni_private *devpriv = dev->private;
1464
1465                 mite_handle_b_linkc(devpriv->mite, dev);
1466         }
1467
1468         if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1469                                CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1470                                CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1471                 dev_err(dev->class_dev,
1472                         "unknown mite interrupt (ao_mite_status=%08x)\n",
1473                         ao_mite_status);
1474                 s->async->events |= COMEDI_CB_ERROR;
1475         }
1476 #endif
1477
1478         if (b_status == 0xffff)
1479                 return;
1480         if (b_status & AO_Overrun_St) {
1481                 dev_err(dev->class_dev,
1482                         "AO FIFO underrun status=0x%04x status2=0x%04x\n",
1483                         b_status, ni_stc_readw(dev, AO_Status_2_Register));
1484                 s->async->events |= COMEDI_CB_OVERFLOW;
1485         }
1486
1487         if (b_status & AO_BC_TC_St)
1488                 s->async->events |= COMEDI_CB_EOA;
1489
1490 #ifndef PCIDMA
1491         if (b_status & AO_FIFO_Request_St) {
1492                 int ret;
1493
1494                 ret = ni_ao_fifo_half_empty(dev, s);
1495                 if (!ret) {
1496                         dev_err(dev->class_dev, "AO buffer underrun\n");
1497                         ni_set_bits(dev, Interrupt_B_Enable_Register,
1498                                     AO_FIFO_Interrupt_Enable |
1499                                     AO_Error_Interrupt_Enable, 0);
1500                         s->async->events |= COMEDI_CB_OVERFLOW;
1501                 }
1502         }
1503 #endif
1504
1505         comedi_handle_events(dev, s);
1506 }
1507
1508 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1509                         void *data, unsigned int num_bytes,
1510                         unsigned int chan_index)
1511 {
1512         struct ni_private *devpriv = dev->private;
1513         struct comedi_async *async = s->async;
1514         struct comedi_cmd *cmd = &async->cmd;
1515         unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
1516         unsigned short *array = data;
1517         unsigned int *larray = data;
1518         unsigned int i;
1519
1520         for (i = 0; i < nsamples; i++) {
1521 #ifdef PCIDMA
1522                 if (s->subdev_flags & SDF_LSAMPL)
1523                         larray[i] = le32_to_cpu(larray[i]);
1524                 else
1525                         array[i] = le16_to_cpu(array[i]);
1526 #endif
1527                 if (s->subdev_flags & SDF_LSAMPL)
1528                         larray[i] += devpriv->ai_offset[chan_index];
1529                 else
1530                         array[i] += devpriv->ai_offset[chan_index];
1531                 chan_index++;
1532                 chan_index %= cmd->chanlist_len;
1533         }
1534 }
1535
1536 #ifdef PCIDMA
1537
1538 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1539 {
1540         struct ni_private *devpriv = dev->private;
1541         struct comedi_subdevice *s = dev->read_subdev;
1542         int retval;
1543         unsigned long flags;
1544
1545         retval = ni_request_ai_mite_channel(dev);
1546         if (retval)
1547                 return retval;
1548
1549         /* write alloc the entire buffer */
1550         comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
1551
1552         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1553         if (!devpriv->ai_mite_chan) {
1554                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1555                 return -EIO;
1556         }
1557
1558         if (devpriv->is_611x || devpriv->is_6143)
1559                 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1560         else if (devpriv->is_628x)
1561                 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1562         else
1563                 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1564
1565         /*start the MITE */
1566         mite_dma_arm(devpriv->ai_mite_chan);
1567         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1568
1569         return 0;
1570 }
1571
1572 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1573 {
1574         struct ni_private *devpriv = dev->private;
1575         struct comedi_subdevice *s = dev->write_subdev;
1576         int retval;
1577         unsigned long flags;
1578
1579         retval = ni_request_ao_mite_channel(dev);
1580         if (retval)
1581                 return retval;
1582
1583         /* read alloc the entire buffer */
1584         comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
1585
1586         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1587         if (devpriv->ao_mite_chan) {
1588                 if (devpriv->is_611x || devpriv->is_6713) {
1589                         mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1590                 } else {
1591                         /* doing 32 instead of 16 bit wide transfers from memory
1592                            makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1593                         mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1594                 }
1595                 mite_dma_arm(devpriv->ao_mite_chan);
1596         } else {
1597                 retval = -EIO;
1598         }
1599         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1600
1601         return retval;
1602 }
1603
1604 #endif /*  PCIDMA */
1605
1606 /*
1607    used for both cancel ioctl and board initialization
1608
1609    this is pretty harsh for a cancel, but it works...
1610  */
1611
1612 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1613 {
1614         struct ni_private *devpriv = dev->private;
1615
1616         ni_release_ai_mite_channel(dev);
1617         /* ai configuration */
1618         ni_stc_writew(dev, AI_Configuration_Start | AI_Reset,
1619                       Joint_Reset_Register);
1620
1621         ni_set_bits(dev, Interrupt_A_Enable_Register,
1622                     AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable |
1623                     AI_START2_Interrupt_Enable | AI_START_Interrupt_Enable |
1624                     AI_STOP_Interrupt_Enable | AI_Error_Interrupt_Enable |
1625                     AI_FIFO_Interrupt_Enable, 0);
1626
1627         ni_clear_ai_fifo(dev);
1628
1629         if (!devpriv->is_6143)
1630                 ni_writeb(dev, 0, Misc_Command);
1631
1632         ni_stc_writew(dev, NISTC_AI_CMD1_DISARM, NISTC_AI_CMD1_REG);
1633         ni_stc_writew(dev, NISTC_AI_MODE1_START_STOP |
1634                            NISTC_AI_MODE1_RSVD
1635                             /*| NISTC_AI_MODE1_TRIGGER_ONCE */,
1636                       NISTC_AI_MODE1_REG);
1637         ni_stc_writew(dev, 0, NISTC_AI_MODE2_REG);
1638         /* generate FIFO interrupts on non-empty */
1639         ni_stc_writew(dev, (0 << 6) | 0x0000, AI_Mode_3_Register);
1640         if (devpriv->is_611x) {
1641                 ni_stc_writew(dev,
1642                               AI_SHIFTIN_Pulse_Width |
1643                               AI_SOC_Polarity |
1644                               AI_LOCALMUX_CLK_Pulse_Width,
1645                               AI_Personal_Register);
1646                 ni_stc_writew(dev,
1647                               AI_SCAN_IN_PROG_Output_Select(3) |
1648                               AI_EXTMUX_CLK_Output_Select(0) |
1649                               AI_LOCALMUX_CLK_Output_Select(2) |
1650                               AI_SC_TC_Output_Select(3) |
1651                               AI_CONVERT_Output_Select
1652                               (AI_CONVERT_Output_Enable_High),
1653                               AI_Output_Control_Register);
1654         } else if (devpriv->is_6143) {
1655                 ni_stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1656                                    AI_SOC_Polarity |
1657                                    AI_LOCALMUX_CLK_Pulse_Width,
1658                               AI_Personal_Register);
1659                 ni_stc_writew(dev,
1660                               AI_SCAN_IN_PROG_Output_Select(3) |
1661                               AI_EXTMUX_CLK_Output_Select(0) |
1662                               AI_LOCALMUX_CLK_Output_Select(2) |
1663                               AI_SC_TC_Output_Select(3) |
1664                               AI_CONVERT_Output_Select
1665                               (AI_CONVERT_Output_Enable_Low),
1666                               AI_Output_Control_Register);
1667         } else {
1668                 unsigned ai_output_control_bits;
1669
1670                 ni_stc_writew(dev,
1671                               AI_SHIFTIN_Pulse_Width |
1672                               AI_SOC_Polarity |
1673                               AI_CONVERT_Pulse_Width |
1674                               AI_LOCALMUX_CLK_Pulse_Width,
1675                               AI_Personal_Register);
1676                 ai_output_control_bits =
1677                     AI_SCAN_IN_PROG_Output_Select(3) |
1678                     AI_EXTMUX_CLK_Output_Select(0) |
1679                     AI_LOCALMUX_CLK_Output_Select(2) |
1680                     AI_SC_TC_Output_Select(3);
1681                 if (devpriv->is_622x)
1682                         ai_output_control_bits |=
1683                             AI_CONVERT_Output_Select
1684                             (AI_CONVERT_Output_Enable_High);
1685                 else
1686                         ai_output_control_bits |=
1687                             AI_CONVERT_Output_Select
1688                             (AI_CONVERT_Output_Enable_Low);
1689                 ni_stc_writew(dev, ai_output_control_bits,
1690                               AI_Output_Control_Register);
1691         }
1692         /* the following registers should not be changed, because there
1693          * are no backup registers in devpriv.  If you want to change
1694          * any of these, add a backup register and other appropriate code:
1695          *      NISTC_AI_MODE1_REG
1696          *      AI_Mode_3_Register
1697          *      AI_Personal_Register
1698          *      AI_Output_Control_Register
1699          */
1700
1701         /* clear interrupts */
1702         ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
1703
1704         ni_stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
1705
1706         return 0;
1707 }
1708
1709 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1710 {
1711         unsigned long flags;
1712         int count;
1713
1714         /*  lock to avoid race with interrupt handler */
1715         spin_lock_irqsave(&dev->spinlock, flags);
1716 #ifndef PCIDMA
1717         ni_handle_fifo_dregs(dev);
1718 #else
1719         ni_sync_ai_dma(dev);
1720 #endif
1721         count = comedi_buf_n_bytes_ready(s);
1722         spin_unlock_irqrestore(&dev->spinlock, flags);
1723
1724         return count;
1725 }
1726
1727 static void ni_prime_channelgain_list(struct comedi_device *dev)
1728 {
1729         int i;
1730
1731         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, NISTC_AI_CMD1_REG);
1732         for (i = 0; i < NI_TIMEOUT; ++i) {
1733                 if (!(ni_stc_readw(dev, AI_Status_1_Register) &
1734                       AI_FIFO_Empty_St)) {
1735                         ni_stc_writew(dev, 1, ADC_FIFO_Clear);
1736                         return;
1737                 }
1738                 udelay(1);
1739         }
1740         dev_err(dev->class_dev, "timeout loading channel/gain list\n");
1741 }
1742
1743 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1744                                               unsigned int n_chan,
1745                                               unsigned int *list)
1746 {
1747         const struct ni_board_struct *board = dev->board_ptr;
1748         struct ni_private *devpriv = dev->private;
1749         unsigned int chan, range, aref;
1750         unsigned int i;
1751         unsigned int dither;
1752         unsigned range_code;
1753
1754         ni_stc_writew(dev, 1, Configuration_Memory_Clear);
1755
1756         if ((list[0] & CR_ALT_SOURCE)) {
1757                 unsigned bypass_bits;
1758
1759                 chan = CR_CHAN(list[0]);
1760                 range = CR_RANGE(list[0]);
1761                 range_code = ni_gainlkup[board->gainlkup][range];
1762                 dither = (list[0] & CR_ALT_FILTER) != 0;
1763                 bypass_bits = NI_M_CFG_BYPASS_FIFO |
1764                               NI_M_CFG_BYPASS_AI_CHAN(chan) |
1765                               NI_M_CFG_BYPASS_AI_GAIN(range_code) |
1766                               devpriv->ai_calib_source;
1767                 if (dither)
1768                         bypass_bits |= NI_M_CFG_BYPASS_AI_DITHER;
1769                 /*  don't use 2's complement encoding */
1770                 bypass_bits |= NI_M_CFG_BYPASS_AI_POLARITY;
1771                 ni_writel(dev, bypass_bits, NI_M_CFG_BYPASS_FIFO_REG);
1772         } else {
1773                 ni_writel(dev, 0, NI_M_CFG_BYPASS_FIFO_REG);
1774         }
1775         for (i = 0; i < n_chan; i++) {
1776                 unsigned config_bits = 0;
1777
1778                 chan = CR_CHAN(list[i]);
1779                 aref = CR_AREF(list[i]);
1780                 range = CR_RANGE(list[i]);
1781                 dither = (list[i] & CR_ALT_FILTER) != 0;
1782
1783                 range_code = ni_gainlkup[board->gainlkup][range];
1784                 devpriv->ai_offset[i] = 0;
1785                 switch (aref) {
1786                 case AREF_DIFF:
1787                         config_bits |= NI_M_AI_CFG_CHAN_TYPE_DIFF;
1788                         break;
1789                 case AREF_COMMON:
1790                         config_bits |= NI_M_AI_CFG_CHAN_TYPE_COMMON;
1791                         break;
1792                 case AREF_GROUND:
1793                         config_bits |= NI_M_AI_CFG_CHAN_TYPE_GROUND;
1794                         break;
1795                 case AREF_OTHER:
1796                         break;
1797                 }
1798                 config_bits |= NI_M_AI_CFG_CHAN_SEL(chan);
1799                 config_bits |= NI_M_AI_CFG_BANK_SEL(chan);
1800                 config_bits |= NI_M_AI_CFG_GAIN(range_code);
1801                 if (i == n_chan - 1)
1802                         config_bits |= NI_M_AI_CFG_LAST_CHAN;
1803                 if (dither)
1804                         config_bits |= NI_M_AI_CFG_DITHER;
1805                 /*  don't use 2's complement encoding */
1806                 config_bits |= NI_M_AI_CFG_POLARITY;
1807                 ni_writew(dev, config_bits, NI_M_AI_CFG_FIFO_DATA_REG);
1808         }
1809         ni_prime_channelgain_list(dev);
1810 }
1811
1812 /*
1813  * Notes on the 6110 and 6111:
1814  * These boards a slightly different than the rest of the series, since
1815  * they have multiple A/D converters.
1816  * From the driver side, the configuration memory is a
1817  * little different.
1818  * Configuration Memory Low:
1819  *   bits 15-9: same
1820  *   bit 8: unipolar/bipolar (should be 0 for bipolar)
1821  *   bits 0-3: gain.  This is 4 bits instead of 3 for the other boards
1822  *       1001 gain=0.1 (+/- 50)
1823  *       1010 0.2
1824  *       1011 0.1
1825  *       0001 1
1826  *       0010 2
1827  *       0011 5
1828  *       0100 10
1829  *       0101 20
1830  *       0110 50
1831  * Configuration Memory High:
1832  *   bits 12-14: Channel Type
1833  *       001 for differential
1834  *       000 for calibration
1835  *   bit 11: coupling  (this is not currently handled)
1836  *       1 AC coupling
1837  *       0 DC coupling
1838  *   bits 0-2: channel
1839  *       valid channels are 0-3
1840  */
1841 static void ni_load_channelgain_list(struct comedi_device *dev,
1842                                      struct comedi_subdevice *s,
1843                                      unsigned int n_chan, unsigned int *list)
1844 {
1845         const struct ni_board_struct *board = dev->board_ptr;
1846         struct ni_private *devpriv = dev->private;
1847         unsigned int offset = (s->maxdata + 1) >> 1;
1848         unsigned int chan, range, aref;
1849         unsigned int i;
1850         unsigned int hi, lo;
1851         unsigned int dither;
1852
1853         if (devpriv->is_m_series) {
1854                 ni_m_series_load_channelgain_list(dev, n_chan, list);
1855                 return;
1856         }
1857         if (n_chan == 1 && !devpriv->is_611x && !devpriv->is_6143) {
1858                 if (devpriv->changain_state
1859                     && devpriv->changain_spec == list[0]) {
1860                         /*  ready to go. */
1861                         return;
1862                 }
1863                 devpriv->changain_state = 1;
1864                 devpriv->changain_spec = list[0];
1865         } else {
1866                 devpriv->changain_state = 0;
1867         }
1868
1869         ni_stc_writew(dev, 1, Configuration_Memory_Clear);
1870
1871         /*  Set up Calibration mode if required */
1872         if (devpriv->is_6143) {
1873                 if ((list[0] & CR_ALT_SOURCE)
1874                     && !devpriv->ai_calib_source_enabled) {
1875                         /*  Strobe Relay enable bit */
1876                         ni_writew(dev, devpriv->ai_calib_source |
1877                                        Calibration_Channel_6143_RelayOn,
1878                                   Calibration_Channel_6143);
1879                         ni_writew(dev, devpriv->ai_calib_source,
1880                                   Calibration_Channel_6143);
1881                         devpriv->ai_calib_source_enabled = 1;
1882                         msleep_interruptible(100);      /*  Allow relays to change */
1883                 } else if (!(list[0] & CR_ALT_SOURCE)
1884                            && devpriv->ai_calib_source_enabled) {
1885                         /*  Strobe Relay disable bit */
1886                         ni_writew(dev, devpriv->ai_calib_source |
1887                                        Calibration_Channel_6143_RelayOff,
1888                                   Calibration_Channel_6143);
1889                         ni_writew(dev, devpriv->ai_calib_source,
1890                                   Calibration_Channel_6143);
1891                         devpriv->ai_calib_source_enabled = 0;
1892                         msleep_interruptible(100);      /*  Allow relays to change */
1893                 }
1894         }
1895
1896         for (i = 0; i < n_chan; i++) {
1897                 if (!devpriv->is_6143 && (list[i] & CR_ALT_SOURCE))
1898                         chan = devpriv->ai_calib_source;
1899                 else
1900                         chan = CR_CHAN(list[i]);
1901                 aref = CR_AREF(list[i]);
1902                 range = CR_RANGE(list[i]);
1903                 dither = (list[i] & CR_ALT_FILTER) != 0;
1904
1905                 /* fix the external/internal range differences */
1906                 range = ni_gainlkup[board->gainlkup][range];
1907                 if (devpriv->is_611x)
1908                         devpriv->ai_offset[i] = offset;
1909                 else
1910                         devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
1911
1912                 hi = 0;
1913                 if ((list[i] & CR_ALT_SOURCE)) {
1914                         if (devpriv->is_611x)
1915                                 ni_writew(dev, CR_CHAN(list[i]) & 0x0003,
1916                                           Calibration_Channel_Select_611x);
1917                 } else {
1918                         if (devpriv->is_611x)
1919                                 aref = AREF_DIFF;
1920                         else if (devpriv->is_6143)
1921                                 aref = AREF_OTHER;
1922                         switch (aref) {
1923                         case AREF_DIFF:
1924                                 hi |= AI_DIFFERENTIAL;
1925                                 break;
1926                         case AREF_COMMON:
1927                                 hi |= AI_COMMON;
1928                                 break;
1929                         case AREF_GROUND:
1930                                 hi |= AI_GROUND;
1931                                 break;
1932                         case AREF_OTHER:
1933                                 break;
1934                         }
1935                 }
1936                 hi |= AI_CONFIG_CHANNEL(chan);
1937
1938                 ni_writew(dev, hi, Configuration_Memory_High);
1939
1940                 if (!devpriv->is_6143) {
1941                         lo = range;
1942                         if (i == n_chan - 1)
1943                                 lo |= AI_LAST_CHANNEL;
1944                         if (dither)
1945                                 lo |= AI_DITHER;
1946
1947                         ni_writew(dev, lo, Configuration_Memory_Low);
1948                 }
1949         }
1950
1951         /* prime the channel/gain list */
1952         if (!devpriv->is_611x && !devpriv->is_6143)
1953                 ni_prime_channelgain_list(dev);
1954 }
1955
1956 static int ni_ai_insn_read(struct comedi_device *dev,
1957                            struct comedi_subdevice *s,
1958                            struct comedi_insn *insn,
1959                            unsigned int *data)
1960 {
1961         struct ni_private *devpriv = dev->private;
1962         unsigned int mask = (s->maxdata + 1) >> 1;
1963         int i, n;
1964         unsigned signbits;
1965         unsigned int d;
1966         unsigned long dl;
1967
1968         ni_load_channelgain_list(dev, s, 1, &insn->chanspec);
1969
1970         ni_clear_ai_fifo(dev);
1971
1972         signbits = devpriv->ai_offset[0];
1973         if (devpriv->is_611x) {
1974                 for (n = 0; n < num_adc_stages_611x; n++) {
1975                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1976                                       NISTC_AI_CMD1_REG);
1977                         udelay(1);
1978                 }
1979                 for (n = 0; n < insn->n; n++) {
1980                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1981                                       NISTC_AI_CMD1_REG);
1982                         /* The 611x has screwy 32-bit FIFOs. */
1983                         d = 0;
1984                         for (i = 0; i < NI_TIMEOUT; i++) {
1985                                 if (ni_readb(dev, XXX_Status) & 0x80) {
1986                                         d = ni_readl(dev, ADC_FIFO_Data_611x);
1987                                         d >>= 16;
1988                                         d &= 0xffff;
1989                                         break;
1990                                 }
1991                                 if (!(ni_stc_readw(dev, AI_Status_1_Register) &
1992                                       AI_FIFO_Empty_St)) {
1993                                         d = ni_readl(dev, ADC_FIFO_Data_611x);
1994                                         d &= 0xffff;
1995                                         break;
1996                                 }
1997                         }
1998                         if (i == NI_TIMEOUT) {
1999                                 dev_err(dev->class_dev, "timeout\n");
2000                                 return -ETIME;
2001                         }
2002                         d += signbits;
2003                         data[n] = d;
2004                 }
2005         } else if (devpriv->is_6143) {
2006                 for (n = 0; n < insn->n; n++) {
2007                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
2008                                       NISTC_AI_CMD1_REG);
2009
2010                         /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
2011                         dl = 0;
2012                         for (i = 0; i < NI_TIMEOUT; i++) {
2013                                 if (ni_readl(dev, AIFIFO_Status_6143) & 0x01) {
2014                                         /* Get stranded sample into FIFO */
2015                                         ni_writel(dev, 0x01,
2016                                                   AIFIFO_Control_6143);
2017                                         dl = ni_readl(dev, AIFIFO_Data_6143);
2018                                         break;
2019                                 }
2020                         }
2021                         if (i == NI_TIMEOUT) {
2022                                 dev_err(dev->class_dev, "timeout\n");
2023                                 return -ETIME;
2024                         }
2025                         data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
2026                 }
2027         } else {
2028                 for (n = 0; n < insn->n; n++) {
2029                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
2030                                       NISTC_AI_CMD1_REG);
2031                         for (i = 0; i < NI_TIMEOUT; i++) {
2032                                 if (!(ni_stc_readw(dev, AI_Status_1_Register) &
2033                                       AI_FIFO_Empty_St))
2034                                         break;
2035                         }
2036                         if (i == NI_TIMEOUT) {
2037                                 dev_err(dev->class_dev, "timeout\n");
2038                                 return -ETIME;
2039                         }
2040                         if (devpriv->is_m_series) {
2041                                 dl = ni_readl(dev, NI_M_AI_FIFO_DATA_REG);
2042                                 dl &= mask;
2043                                 data[n] = dl;
2044                         } else {
2045                                 d = ni_readw(dev, ADC_FIFO_Data_Register);
2046                                 d += signbits;  /* subtle: needs to be short addition */
2047                                 data[n] = d;
2048                         }
2049                 }
2050         }
2051         return insn->n;
2052 }
2053
2054 static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec,
2055                           unsigned int flags)
2056 {
2057         struct ni_private *devpriv = dev->private;
2058         int divider;
2059
2060         switch (flags & CMDF_ROUND_MASK) {
2061         case CMDF_ROUND_NEAREST:
2062         default:
2063                 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
2064                 break;
2065         case CMDF_ROUND_DOWN:
2066                 divider = (nanosec) / devpriv->clock_ns;
2067                 break;
2068         case CMDF_ROUND_UP:
2069                 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
2070                 break;
2071         }
2072         return divider - 1;
2073 }
2074
2075 static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer)
2076 {
2077         struct ni_private *devpriv = dev->private;
2078
2079         return devpriv->clock_ns * (timer + 1);
2080 }
2081
2082 static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev,
2083                                          unsigned num_channels)
2084 {
2085         const struct ni_board_struct *board = dev->board_ptr;
2086         struct ni_private *devpriv = dev->private;
2087
2088         /* simultaneously-sampled inputs */
2089         if (devpriv->is_611x || devpriv->is_6143)
2090                 return board->ai_speed;
2091
2092         /* multiplexed inputs */
2093         return board->ai_speed * num_channels;
2094 }
2095
2096 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2097                          struct comedi_cmd *cmd)
2098 {
2099         const struct ni_board_struct *board = dev->board_ptr;
2100         struct ni_private *devpriv = dev->private;
2101         int err = 0;
2102         unsigned int tmp;
2103         unsigned int sources;
2104
2105         /* Step 1 : check if triggers are trivially valid */
2106
2107         err |= comedi_check_trigger_src(&cmd->start_src,
2108                                         TRIG_NOW | TRIG_INT | TRIG_EXT);
2109         err |= comedi_check_trigger_src(&cmd->scan_begin_src,
2110                                         TRIG_TIMER | TRIG_EXT);
2111
2112         sources = TRIG_TIMER | TRIG_EXT;
2113         if (devpriv->is_611x || devpriv->is_6143)
2114                 sources |= TRIG_NOW;
2115         err |= comedi_check_trigger_src(&cmd->convert_src, sources);
2116
2117         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2118         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2119
2120         if (err)
2121                 return 1;
2122
2123         /* Step 2a : make sure trigger sources are unique */
2124
2125         err |= comedi_check_trigger_is_unique(cmd->start_src);
2126         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
2127         err |= comedi_check_trigger_is_unique(cmd->convert_src);
2128         err |= comedi_check_trigger_is_unique(cmd->stop_src);
2129
2130         /* Step 2b : and mutually compatible */
2131
2132         if (err)
2133                 return 2;
2134
2135         /* Step 3: check if arguments are trivially valid */
2136
2137         switch (cmd->start_src) {
2138         case TRIG_NOW:
2139         case TRIG_INT:
2140                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
2141                 break;
2142         case TRIG_EXT:
2143                 tmp = CR_CHAN(cmd->start_arg);
2144
2145                 if (tmp > 16)
2146                         tmp = 16;
2147                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2148                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
2149                 break;
2150         }
2151
2152         if (cmd->scan_begin_src == TRIG_TIMER) {
2153                 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
2154                         ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2155                 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
2156                                                     devpriv->clock_ns *
2157                                                     0xffffff);
2158         } else if (cmd->scan_begin_src == TRIG_EXT) {
2159                 /* external trigger */
2160                 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2161
2162                 if (tmp > 16)
2163                         tmp = 16;
2164                 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2165                 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, tmp);
2166         } else {                /* TRIG_OTHER */
2167                 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2168         }
2169
2170         if (cmd->convert_src == TRIG_TIMER) {
2171                 if (devpriv->is_611x || devpriv->is_6143) {
2172                         err |= comedi_check_trigger_arg_is(&cmd->convert_arg,
2173                                                            0);
2174                 } else {
2175                         err |= comedi_check_trigger_arg_min(&cmd->convert_arg,
2176                                                             board->ai_speed);
2177                         err |= comedi_check_trigger_arg_max(&cmd->convert_arg,
2178                                                             devpriv->clock_ns *
2179                                                             0xffff);
2180                 }
2181         } else if (cmd->convert_src == TRIG_EXT) {
2182                 /* external trigger */
2183                 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2184
2185                 if (tmp > 16)
2186                         tmp = 16;
2187                 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2188                 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, tmp);
2189         } else if (cmd->convert_src == TRIG_NOW) {
2190                 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
2191         }
2192
2193         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
2194                                            cmd->chanlist_len);
2195
2196         if (cmd->stop_src == TRIG_COUNT) {
2197                 unsigned int max_count = 0x01000000;
2198
2199                 if (devpriv->is_611x)
2200                         max_count -= num_adc_stages_611x;
2201                 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, max_count);
2202                 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
2203         } else {
2204                 /* TRIG_NONE */
2205                 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
2206         }
2207
2208         if (err)
2209                 return 3;
2210
2211         /* step 4: fix up any arguments */
2212
2213         if (cmd->scan_begin_src == TRIG_TIMER) {
2214                 tmp = cmd->scan_begin_arg;
2215                 cmd->scan_begin_arg =
2216                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2217                                                        cmd->scan_begin_arg,
2218                                                        cmd->flags));
2219                 if (tmp != cmd->scan_begin_arg)
2220                         err++;
2221         }
2222         if (cmd->convert_src == TRIG_TIMER) {
2223                 if (!devpriv->is_611x && !devpriv->is_6143) {
2224                         tmp = cmd->convert_arg;
2225                         cmd->convert_arg =
2226                             ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2227                                                                cmd->convert_arg,
2228                                                                cmd->flags));
2229                         if (tmp != cmd->convert_arg)
2230                                 err++;
2231                         if (cmd->scan_begin_src == TRIG_TIMER &&
2232                             cmd->scan_begin_arg <
2233                             cmd->convert_arg * cmd->scan_end_arg) {
2234                                 cmd->scan_begin_arg =
2235                                     cmd->convert_arg * cmd->scan_end_arg;
2236                                 err++;
2237                         }
2238                 }
2239         }
2240
2241         if (err)
2242                 return 4;
2243
2244         return 0;
2245 }
2246
2247 static int ni_ai_inttrig(struct comedi_device *dev,
2248                          struct comedi_subdevice *s,
2249                          unsigned int trig_num)
2250 {
2251         struct ni_private *devpriv = dev->private;
2252         struct comedi_cmd *cmd = &s->async->cmd;
2253
2254         if (trig_num != cmd->start_arg)
2255                 return -EINVAL;
2256
2257         ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE | devpriv->ai_cmd2,
2258                       NISTC_AI_CMD2_REG);
2259         s->async->inttrig = NULL;
2260
2261         return 1;
2262 }
2263
2264 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2265 {
2266         struct ni_private *devpriv = dev->private;
2267         const struct comedi_cmd *cmd = &s->async->cmd;
2268         int timer;
2269         int mode1 = 0;          /* mode1 is needed for both stop and convert */
2270         int mode2 = 0;
2271         int start_stop_select = 0;
2272         unsigned int stop_count;
2273         int interrupt_a_enable = 0;
2274
2275         if (dev->irq == 0) {
2276                 dev_err(dev->class_dev, "cannot run command without an irq\n");
2277                 return -EIO;
2278         }
2279         ni_clear_ai_fifo(dev);
2280
2281         ni_load_channelgain_list(dev, s, cmd->chanlist_len, cmd->chanlist);
2282
2283         /* start configuration */
2284         ni_stc_writew(dev, AI_Configuration_Start, Joint_Reset_Register);
2285
2286         /* disable analog triggering for now, since it
2287          * interferes with the use of pfi0 */
2288         devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
2289         ni_stc_writew(dev, devpriv->an_trig_etc_reg,
2290                       Analog_Trigger_Etc_Register);
2291
2292         switch (cmd->start_src) {
2293         case TRIG_INT:
2294         case TRIG_NOW:
2295                 ni_stc_writew(dev,
2296                               AI_START2_Select(0) |
2297                               AI_START1_Sync | AI_START1_Edge |
2298                               AI_START1_Select(0),
2299                               AI_Trigger_Select_Register);
2300                 break;
2301         case TRIG_EXT:
2302                 {
2303                         int chan = CR_CHAN(cmd->start_arg);
2304                         unsigned int bits = AI_START2_Select(0) |
2305                             AI_START1_Sync | AI_START1_Select(chan + 1);
2306
2307                         if (cmd->start_arg & CR_INVERT)
2308                                 bits |= AI_START1_Polarity;
2309                         if (cmd->start_arg & CR_EDGE)
2310                                 bits |= AI_START1_Edge;
2311                         ni_stc_writew(dev, bits, AI_Trigger_Select_Register);
2312                         break;
2313                 }
2314         }
2315
2316         mode2 &= ~NISTC_AI_MODE2_PRE_TRIGGER;
2317         mode2 &= ~NISTC_AI_MODE2_SC_INIT_LOAD_SRC;
2318         mode2 &= ~NISTC_AI_MODE2_SC_RELOAD_MODE;
2319         ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2320
2321         if (cmd->chanlist_len == 1 || devpriv->is_611x || devpriv->is_6143) {
2322                 start_stop_select |= AI_STOP_Polarity;
2323                 start_stop_select |= AI_STOP_Select(31);        /*  logic low */
2324                 start_stop_select |= AI_STOP_Sync;
2325         } else {
2326                 start_stop_select |= AI_STOP_Select(19);        /*  ai configuration memory */
2327         }
2328         ni_stc_writew(dev, start_stop_select, AI_START_STOP_Select_Register);
2329
2330         devpriv->ai_cmd2 = 0;
2331         switch (cmd->stop_src) {
2332         case TRIG_COUNT:
2333                 stop_count = cmd->stop_arg - 1;
2334
2335                 if (devpriv->is_611x) {
2336                         /*  have to take 3 stage adc pipeline into account */
2337                         stop_count += num_adc_stages_611x;
2338                 }
2339                 /* stage number of scans */
2340                 ni_stc_writel(dev, stop_count, NISTC_AI_SC_LOADA_REG);
2341
2342                 mode1 |= NISTC_AI_MODE1_START_STOP |
2343                          NISTC_AI_MODE1_RSVD |
2344                          NISTC_AI_MODE1_TRIGGER_ONCE;
2345                 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2346                 /* load SC (Scan Count) */
2347                 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2348
2349                 if (stop_count == 0) {
2350                         devpriv->ai_cmd2 |= NISTC_AI_CMD2_END_ON_EOS;
2351                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2352                         /*  this is required to get the last sample for chanlist_len > 1, not sure why */
2353                         if (cmd->chanlist_len > 1)
2354                                 start_stop_select |=
2355                                     AI_STOP_Polarity | AI_STOP_Edge;
2356                 }
2357                 break;
2358         case TRIG_NONE:
2359                 /* stage number of scans */
2360                 ni_stc_writel(dev, 0, NISTC_AI_SC_LOADA_REG);
2361
2362                 mode1 |= NISTC_AI_MODE1_START_STOP |
2363                          NISTC_AI_MODE1_RSVD |
2364                          NISTC_AI_MODE1_CONTINUOUS;
2365                 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2366
2367                 /* load SC (Scan Count) */
2368                 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2369                 break;
2370         }
2371
2372         switch (cmd->scan_begin_src) {
2373         case TRIG_TIMER:
2374                 /*
2375                    stop bits for non 611x boards
2376                    AI_SI_Special_Trigger_Delay=0
2377                    NISTC_AI_MODE2_PRE_TRIGGER=0
2378                    AI_START_STOP_Select_Register:
2379                    AI_START_Polarity=0 (?)      rising edge
2380                    AI_START_Edge=1              edge triggered
2381                    AI_START_Sync=1 (?)
2382                    AI_START_Select=0            SI_TC
2383                    AI_STOP_Polarity=0           rising edge
2384                    AI_STOP_Edge=0               level
2385                    AI_STOP_Sync=1
2386                    AI_STOP_Select=19            external pin (configuration mem)
2387                  */
2388                 start_stop_select |= AI_START_Edge | AI_START_Sync;
2389                 ni_stc_writew(dev, start_stop_select,
2390                               AI_START_STOP_Select_Register);
2391
2392                 mode2 &= ~NISTC_AI_MODE2_SI_INIT_LOAD_SRC;      /* A */
2393                 mode2 |= NISTC_AI_MODE2_SI_RELOAD_MODE(0);
2394                 /* mode2 |= NISTC_AI_MODE2_SC_RELOAD_MODE; */
2395                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2396
2397                 /* load SI */
2398                 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2399                                        CMDF_ROUND_NEAREST);
2400                 ni_stc_writel(dev, timer, NISTC_AI_SI_LOADA_REG);
2401                 ni_stc_writew(dev, NISTC_AI_CMD1_SI_LOAD, NISTC_AI_CMD1_REG);
2402                 break;
2403         case TRIG_EXT:
2404                 if (cmd->scan_begin_arg & CR_EDGE)
2405                         start_stop_select |= AI_START_Edge;
2406                 /* AI_START_Polarity==1 is falling edge */
2407                 if (cmd->scan_begin_arg & CR_INVERT)
2408                         start_stop_select |= AI_START_Polarity;
2409                 if (cmd->scan_begin_src != cmd->convert_src ||
2410                     (cmd->scan_begin_arg & ~CR_EDGE) !=
2411                     (cmd->convert_arg & ~CR_EDGE))
2412                         start_stop_select |= AI_START_Sync;
2413                 start_stop_select |=
2414                     AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg));
2415                 ni_stc_writew(dev, start_stop_select,
2416                               AI_START_STOP_Select_Register);
2417                 break;
2418         }
2419
2420         switch (cmd->convert_src) {
2421         case TRIG_TIMER:
2422         case TRIG_NOW:
2423                 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2424                         timer = 1;
2425                 else
2426                         timer = ni_ns_to_timer(dev, cmd->convert_arg,
2427                                                CMDF_ROUND_NEAREST);
2428                 /* 0,0 does not work */
2429                 ni_stc_writew(dev, 1, NISTC_AI_SI2_LOADA_REG);
2430                 ni_stc_writew(dev, timer, NISTC_AI_SI2_LOADB_REG);
2431
2432                 mode2 &= ~NISTC_AI_MODE2_SI2_INIT_LOAD_SRC;     /* A */
2433                 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE;        /* alternate */
2434                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2435
2436                 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_LOAD, NISTC_AI_CMD1_REG);
2437
2438                 mode2 |= NISTC_AI_MODE2_SI2_INIT_LOAD_SRC;      /* B */
2439                 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE;        /* alternate */
2440                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2441                 break;
2442         case TRIG_EXT:
2443                 mode1 |= NISTC_AI_MODE1_CONVERT_SRC(1 + cmd->convert_arg);
2444                 if ((cmd->convert_arg & CR_INVERT) == 0)
2445                         mode1 |= NISTC_AI_MODE1_CONVERT_POLARITY;
2446                 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2447
2448                 mode2 |= NISTC_AI_MODE2_SC_GATE_ENA |
2449                          NISTC_AI_MODE2_START_STOP_GATE_ENA;
2450                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2451
2452                 break;
2453         }
2454
2455         if (dev->irq) {
2456                 /* interrupt on FIFO, errors, SC_TC */
2457                 interrupt_a_enable |= AI_Error_Interrupt_Enable |
2458                     AI_SC_TC_Interrupt_Enable;
2459
2460 #ifndef PCIDMA
2461                 interrupt_a_enable |= AI_FIFO_Interrupt_Enable;
2462 #endif
2463
2464                 if ((cmd->flags & CMDF_WAKE_EOS) ||
2465                     (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)) {
2466                         /* wake on end-of-scan */
2467                         devpriv->aimode = AIMODE_SCAN;
2468                 } else {
2469                         devpriv->aimode = AIMODE_HALF_FULL;
2470                 }
2471
2472                 switch (devpriv->aimode) {
2473                 case AIMODE_HALF_FULL:
2474                         /*generate FIFO interrupts and DMA requests on half-full */
2475 #ifdef PCIDMA
2476                         ni_stc_writew(dev, AI_FIFO_Mode_HF_to_E,
2477                                       AI_Mode_3_Register);
2478 #else
2479                         ni_stc_writew(dev, AI_FIFO_Mode_HF,
2480                                       AI_Mode_3_Register);
2481 #endif
2482                         break;
2483                 case AIMODE_SAMPLE:
2484                         /*generate FIFO interrupts on non-empty */
2485                         ni_stc_writew(dev, AI_FIFO_Mode_NE,
2486                                       AI_Mode_3_Register);
2487                         break;
2488                 case AIMODE_SCAN:
2489 #ifdef PCIDMA
2490                         ni_stc_writew(dev, AI_FIFO_Mode_NE,
2491                                       AI_Mode_3_Register);
2492 #else
2493                         ni_stc_writew(dev, AI_FIFO_Mode_HF,
2494                                       AI_Mode_3_Register);
2495 #endif
2496                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2497                         break;
2498                 default:
2499                         break;
2500                 }
2501
2502                 /* clear interrupts */
2503                 ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
2504
2505                 ni_set_bits(dev, Interrupt_A_Enable_Register,
2506                             interrupt_a_enable, 1);
2507         } else {
2508                 /* interrupt on nothing */
2509                 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
2510
2511                 /* XXX start polling if necessary */
2512         }
2513
2514         /* end configuration */
2515         ni_stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
2516
2517         switch (cmd->scan_begin_src) {
2518         case TRIG_TIMER:
2519                 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2520                                    NISTC_AI_CMD1_SI_ARM |
2521                                    NISTC_AI_CMD1_DIV_ARM |
2522                                    NISTC_AI_CMD1_SC_ARM,
2523                               NISTC_AI_CMD1_REG);
2524                 break;
2525         case TRIG_EXT:
2526                 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2527                                    NISTC_AI_CMD1_SI_ARM |       /* XXX ? */
2528                                    NISTC_AI_CMD1_DIV_ARM |
2529                                    NISTC_AI_CMD1_SC_ARM,
2530                               NISTC_AI_CMD1_REG);
2531                 break;
2532         }
2533
2534 #ifdef PCIDMA
2535         {
2536                 int retval = ni_ai_setup_MITE_dma(dev);
2537
2538                 if (retval)
2539                         return retval;
2540         }
2541 #endif
2542
2543         if (cmd->start_src == TRIG_NOW) {
2544                 ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE |
2545                                    devpriv->ai_cmd2,
2546                               NISTC_AI_CMD2_REG);
2547                 s->async->inttrig = NULL;
2548         } else if (cmd->start_src == TRIG_EXT) {
2549                 s->async->inttrig = NULL;
2550         } else {        /* TRIG_INT */
2551                 s->async->inttrig = ni_ai_inttrig;
2552         }
2553
2554         return 0;
2555 }
2556
2557 static int ni_ai_insn_config(struct comedi_device *dev,
2558                              struct comedi_subdevice *s,
2559                              struct comedi_insn *insn, unsigned int *data)
2560 {
2561         struct ni_private *devpriv = dev->private;
2562
2563         if (insn->n < 1)
2564                 return -EINVAL;
2565
2566         switch (data[0]) {
2567         case INSN_CONFIG_ALT_SOURCE:
2568                 if (devpriv->is_m_series) {
2569                         if (data[1] & ~NI_M_CFG_BYPASS_AI_CAL_MASK)
2570                                 return -EINVAL;
2571                         devpriv->ai_calib_source = data[1];
2572                 } else if (devpriv->is_6143) {
2573                         unsigned int calib_source;
2574
2575                         calib_source = data[1] & 0xf;
2576
2577                         devpriv->ai_calib_source = calib_source;
2578                         ni_writew(dev, calib_source, Calibration_Channel_6143);
2579                 } else {
2580                         unsigned int calib_source;
2581                         unsigned int calib_source_adjust;
2582
2583                         calib_source = data[1] & 0xf;
2584                         calib_source_adjust = (data[1] >> 4) & 0xff;
2585
2586                         if (calib_source >= 8)
2587                                 return -EINVAL;
2588                         devpriv->ai_calib_source = calib_source;
2589                         if (devpriv->is_611x) {
2590                                 ni_writeb(dev, calib_source_adjust,
2591                                           Cal_Gain_Select_611x);
2592                         }
2593                 }
2594                 return 2;
2595         default:
2596                 break;
2597         }
2598
2599         return -EINVAL;
2600 }
2601
2602 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2603                         void *data, unsigned int num_bytes,
2604                         unsigned int chan_index)
2605 {
2606         struct comedi_cmd *cmd = &s->async->cmd;
2607         unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
2608         unsigned short *array = data;
2609         unsigned int i;
2610
2611         for (i = 0; i < nsamples; i++) {
2612                 unsigned int range = CR_RANGE(cmd->chanlist[chan_index]);
2613                 unsigned short val = array[i];
2614
2615                 /*
2616                  * Munge data from unsigned to two's complement for
2617                  * bipolar ranges.
2618                  */
2619                 if (comedi_range_is_bipolar(s, range))
2620                         val = comedi_offset_munge(s, val);
2621 #ifdef PCIDMA
2622                 val = cpu_to_le16(val);
2623 #endif
2624                 array[i] = val;
2625
2626                 chan_index++;
2627                 chan_index %= cmd->chanlist_len;
2628         }
2629 }
2630
2631 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2632                                           struct comedi_subdevice *s,
2633                                           unsigned int chanspec[],
2634                                           unsigned int n_chans, int timed)
2635 {
2636         struct ni_private *devpriv = dev->private;
2637         unsigned int range;
2638         unsigned int chan;
2639         unsigned int conf;
2640         int i;
2641         int invert = 0;
2642
2643         if (timed) {
2644                 for (i = 0; i < s->n_chan; ++i) {
2645                         devpriv->ao_conf[i] &= ~NI_M_AO_CFG_BANK_UPDATE_TIMED;
2646                         ni_writeb(dev, devpriv->ao_conf[i],
2647                                   NI_M_AO_CFG_BANK_REG(i));
2648                         ni_writeb(dev, 0xf, NI_M_AO_WAVEFORM_ORDER_REG(i));
2649                 }
2650         }
2651         for (i = 0; i < n_chans; i++) {
2652                 const struct comedi_krange *krange;
2653
2654                 chan = CR_CHAN(chanspec[i]);
2655                 range = CR_RANGE(chanspec[i]);
2656                 krange = s->range_table->range + range;
2657                 invert = 0;
2658                 conf = 0;
2659                 switch (krange->max - krange->min) {
2660                 case 20000000:
2661                         conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2662                         ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2663                         break;
2664                 case 10000000:
2665                         conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2666                         ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2667                         break;
2668                 case 4000000:
2669                         conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2670                         ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2671                                   NI_M_AO_REF_ATTENUATION_REG(chan));
2672                         break;
2673                 case 2000000:
2674                         conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2675                         ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2676                                   NI_M_AO_REF_ATTENUATION_REG(chan));
2677                         break;
2678                 default:
2679                         dev_err(dev->class_dev,
2680                                 "bug! unhandled ao reference voltage\n");
2681                         break;
2682                 }
2683                 switch (krange->max + krange->min) {
2684                 case 0:
2685                         conf |= NI_M_AO_CFG_BANK_OFFSET_0V;
2686                         break;
2687                 case 10000000:
2688                         conf |= NI_M_AO_CFG_BANK_OFFSET_5V;
2689                         break;
2690                 default:
2691                         dev_err(dev->class_dev,
2692                                 "bug! unhandled ao offset voltage\n");
2693                         break;
2694                 }
2695                 if (timed)
2696                         conf |= NI_M_AO_CFG_BANK_UPDATE_TIMED;
2697                 ni_writeb(dev, conf, NI_M_AO_CFG_BANK_REG(chan));
2698                 devpriv->ao_conf[chan] = conf;
2699                 ni_writeb(dev, i, NI_M_AO_WAVEFORM_ORDER_REG(chan));
2700         }
2701         return invert;
2702 }
2703
2704 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2705                                      struct comedi_subdevice *s,
2706                                      unsigned int chanspec[],
2707                                      unsigned int n_chans)
2708 {
2709         struct ni_private *devpriv = dev->private;
2710         unsigned int range;
2711         unsigned int chan;
2712         unsigned int conf;
2713         int i;
2714         int invert = 0;
2715
2716         for (i = 0; i < n_chans; i++) {
2717                 chan = CR_CHAN(chanspec[i]);
2718                 range = CR_RANGE(chanspec[i]);
2719                 conf = AO_Channel(chan);
2720
2721                 if (comedi_range_is_bipolar(s, range)) {
2722                         conf |= AO_Bipolar;
2723                         invert = (s->maxdata + 1) >> 1;
2724                 } else {
2725                         invert = 0;
2726                 }
2727                 if (comedi_range_is_external(s, range))
2728                         conf |= AO_Ext_Ref;
2729
2730                 /* not all boards can deglitch, but this shouldn't hurt */
2731                 if (chanspec[i] & CR_DEGLITCH)
2732                         conf |= AO_Deglitch;
2733
2734                 /* analog reference */
2735                 /* AREF_OTHER connects AO ground to AI ground, i think */
2736                 conf |= (CR_AREF(chanspec[i]) ==
2737                          AREF_OTHER) ? AO_Ground_Ref : 0;
2738
2739                 ni_writew(dev, conf, AO_Configuration);
2740                 devpriv->ao_conf[chan] = conf;
2741         }
2742         return invert;
2743 }
2744
2745 static int ni_ao_config_chanlist(struct comedi_device *dev,
2746                                  struct comedi_subdevice *s,
2747                                  unsigned int chanspec[], unsigned int n_chans,
2748                                  int timed)
2749 {
2750         struct ni_private *devpriv = dev->private;
2751
2752         if (devpriv->is_m_series)
2753                 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
2754                                                       timed);
2755         else
2756                 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2757 }
2758
2759 static int ni_ao_insn_write(struct comedi_device *dev,
2760                             struct comedi_subdevice *s,
2761                             struct comedi_insn *insn,
2762                             unsigned int *data)
2763 {
2764         struct ni_private *devpriv = dev->private;
2765         unsigned int chan = CR_CHAN(insn->chanspec);
2766         unsigned int range = CR_RANGE(insn->chanspec);
2767         int reg;
2768         int i;
2769
2770         if (devpriv->is_6xxx) {
2771                 ni_ao_win_outw(dev, 1 << chan, AO_Immediate_671x);
2772
2773                 reg = DACx_Direct_Data_671x(chan);
2774         } else if (devpriv->is_m_series) {
2775                 reg = NI_M_DAC_DIRECT_DATA_REG(chan);
2776         } else {
2777                 reg = (chan) ? DAC1_Direct_Data : DAC0_Direct_Data;
2778         }
2779
2780         ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2781
2782         for (i = 0; i < insn->n; i++) {
2783                 unsigned int val = data[i];
2784
2785                 s->readback[chan] = val;
2786
2787                 if (devpriv->is_6xxx) {
2788                         /*
2789                          * 6xxx boards have bipolar outputs, munge the
2790                          * unsigned comedi values to 2's complement
2791                          */
2792                         val = comedi_offset_munge(s, val);
2793
2794                         ni_ao_win_outw(dev, val, reg);
2795                 } else if (devpriv->is_m_series) {
2796                         /*
2797                          * M-series boards use offset binary values for
2798                          * bipolar and uinpolar outputs
2799                          */
2800                         ni_writew(dev, val, reg);
2801                 } else {
2802                         /*
2803                          * Non-M series boards need two's complement values
2804                          * for bipolar ranges.
2805                          */
2806                         if (comedi_range_is_bipolar(s, range))
2807                                 val = comedi_offset_munge(s, val);
2808
2809                         ni_writew(dev, val, reg);
2810                 }
2811         }
2812
2813         return insn->n;
2814 }
2815
2816 static int ni_ao_insn_config(struct comedi_device *dev,
2817                              struct comedi_subdevice *s,
2818                              struct comedi_insn *insn, unsigned int *data)
2819 {
2820         const struct ni_board_struct *board = dev->board_ptr;
2821         struct ni_private *devpriv = dev->private;
2822         unsigned int nbytes;
2823
2824         switch (data[0]) {
2825         case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
2826                 switch (data[1]) {
2827                 case COMEDI_OUTPUT:
2828                         nbytes = comedi_samples_to_bytes(s,
2829                                                          board->ao_fifo_depth);
2830                         data[2] = 1 + nbytes;
2831                         if (devpriv->mite)
2832                                 data[2] += devpriv->mite->fifo_size;
2833                         break;
2834                 case COMEDI_INPUT:
2835                         data[2] = 0;
2836                         break;
2837                 default:
2838                         return -EINVAL;
2839                 }
2840                 return 0;
2841         default:
2842                 break;
2843         }
2844
2845         return -EINVAL;
2846 }
2847
2848 static int ni_ao_inttrig(struct comedi_device *dev,
2849                          struct comedi_subdevice *s,
2850                          unsigned int trig_num)
2851 {
2852         struct ni_private *devpriv = dev->private;
2853         struct comedi_cmd *cmd = &s->async->cmd;
2854         int ret;
2855         int interrupt_b_bits;
2856         int i;
2857         static const int timeout = 1000;
2858
2859         if (trig_num != cmd->start_arg)
2860                 return -EINVAL;
2861
2862         /* Null trig at beginning prevent ao start trigger from executing more than
2863            once per command (and doing things like trying to allocate the ao dma channel
2864            multiple times) */
2865         s->async->inttrig = NULL;
2866
2867         ni_set_bits(dev, Interrupt_B_Enable_Register,
2868                     AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
2869         interrupt_b_bits = AO_Error_Interrupt_Enable;
2870 #ifdef PCIDMA
2871         ni_stc_writew(dev, 1, DAC_FIFO_Clear);
2872         if (devpriv->is_6xxx)
2873                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
2874         ret = ni_ao_setup_MITE_dma(dev);
2875         if (ret)
2876                 return ret;
2877         ret = ni_ao_wait_for_dma_load(dev);
2878         if (ret < 0)
2879                 return ret;
2880 #else
2881         ret = ni_ao_prep_fifo(dev, s);
2882         if (ret == 0)
2883                 return -EPIPE;
2884
2885         interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
2886 #endif
2887
2888         ni_stc_writew(dev, devpriv->ao_mode3 | AO_Not_An_UPDATE,
2889                       AO_Mode_3_Register);
2890         ni_stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
2891         /* wait for DACs to be loaded */
2892         for (i = 0; i < timeout; i++) {
2893                 udelay(1);
2894                 if ((ni_stc_readw(dev, Joint_Status_2_Register) &
2895                      AO_TMRDACWRs_In_Progress_St) == 0)
2896                         break;
2897         }
2898         if (i == timeout) {
2899                 dev_err(dev->class_dev,
2900                         "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear\n");
2901                 return -EIO;
2902         }
2903         /*
2904          * stc manual says we are need to clear error interrupt after
2905          * AO_TMRDACWRs_In_Progress_St clears
2906          */
2907         ni_stc_writew(dev, NISTC_INTB_ACK_AO_ERR, NISTC_INTB_ACK_REG);
2908
2909         ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
2910
2911         ni_stc_writew(dev, NISTC_AO_CMD1_UI_ARM |
2912                            NISTC_AO_CMD1_UC_ARM |
2913                            NISTC_AO_CMD1_BC_ARM |
2914                            NISTC_AO_CMD1_DAC1_UPDATE_MODE |
2915                            NISTC_AO_CMD1_DAC0_UPDATE_MODE |
2916                            devpriv->ao_cmd1,
2917                       NISTC_AO_CMD1_REG);
2918
2919         ni_stc_writew(dev, NISTC_AO_CMD2_START1_PULSE | devpriv->ao_cmd2,
2920                       NISTC_AO_CMD2_REG);
2921
2922         return 0;
2923 }
2924
2925 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2926 {
2927         const struct ni_board_struct *board = dev->board_ptr;
2928         struct ni_private *devpriv = dev->private;
2929         const struct comedi_cmd *cmd = &s->async->cmd;
2930         int bits;
2931         int i;
2932         unsigned trigvar;
2933
2934         if (dev->irq == 0) {
2935                 dev_err(dev->class_dev, "cannot run command without an irq\n");
2936                 return -EIO;
2937         }
2938
2939         ni_stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
2940
2941         ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);
2942
2943         if (devpriv->is_6xxx) {
2944                 ni_ao_win_outw(dev, CLEAR_WG, AO_Misc_611x);
2945
2946                 bits = 0;
2947                 for (i = 0; i < cmd->chanlist_len; i++) {
2948                         int chan;
2949
2950                         chan = CR_CHAN(cmd->chanlist[i]);
2951                         bits |= 1 << chan;
2952                         ni_ao_win_outw(dev, chan, AO_Waveform_Generation_611x);
2953                 }
2954                 ni_ao_win_outw(dev, bits, AO_Timed_611x);
2955         }
2956
2957         ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
2958
2959         if (cmd->stop_src == TRIG_NONE) {
2960                 devpriv->ao_mode1 |= NISTC_AO_MODE1_CONTINUOUS;
2961                 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_TRIGGER_ONCE;
2962         } else {
2963                 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_CONTINUOUS;
2964                 devpriv->ao_mode1 |= NISTC_AO_MODE1_TRIGGER_ONCE;
2965         }
2966         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
2967         switch (cmd->start_src) {
2968         case TRIG_INT:
2969         case TRIG_NOW:
2970                 devpriv->ao_trigger_select &=
2971                     ~(AO_START1_Polarity | AO_START1_Select(-1));
2972                 devpriv->ao_trigger_select |= AO_START1_Edge | AO_START1_Sync;
2973                 ni_stc_writew(dev, devpriv->ao_trigger_select,
2974                               AO_Trigger_Select_Register);
2975                 break;
2976         case TRIG_EXT:
2977                 devpriv->ao_trigger_select =
2978                     AO_START1_Select(CR_CHAN(cmd->start_arg) + 1);
2979                 if (cmd->start_arg & CR_INVERT)
2980                         devpriv->ao_trigger_select |= AO_START1_Polarity;       /*  0=active high, 1=active low. see daq-stc 3-24 (p186) */
2981                 if (cmd->start_arg & CR_EDGE)
2982                         devpriv->ao_trigger_select |= AO_START1_Edge;   /*  0=edge detection disabled, 1=enabled */
2983                 ni_stc_writew(dev, devpriv->ao_trigger_select,
2984                               AO_Trigger_Select_Register);
2985                 break;
2986         default:
2987                 BUG();
2988                 break;
2989         }
2990         devpriv->ao_mode3 &= ~AO_Trigger_Length;
2991         ni_stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
2992
2993         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
2994         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_BC_INIT_LOAD_SRC;
2995         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
2996         if (cmd->stop_src == TRIG_NONE)
2997                 ni_stc_writel(dev, 0xffffff, NISTC_AO_BC_LOADA_REG);
2998         else
2999                 ni_stc_writel(dev, 0, NISTC_AO_BC_LOADA_REG);
3000         ni_stc_writew(dev, NISTC_AO_CMD1_BC_LOAD, NISTC_AO_CMD1_REG);
3001         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_UC_INIT_LOAD_SRC;
3002         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3003         switch (cmd->stop_src) {
3004         case TRIG_COUNT:
3005                 if (devpriv->is_m_series) {
3006                         /*  this is how the NI example code does it for m-series boards, verified correct with 6259 */
3007                         ni_stc_writel(dev, cmd->stop_arg - 1,
3008                                       NISTC_AO_UC_LOADA_REG);
3009                         ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
3010                                       NISTC_AO_CMD1_REG);
3011                 } else {
3012                         ni_stc_writel(dev, cmd->stop_arg,
3013                                       NISTC_AO_UC_LOADA_REG);
3014                         ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
3015                                       NISTC_AO_CMD1_REG);
3016                         ni_stc_writel(dev, cmd->stop_arg - 1,
3017                                       NISTC_AO_UC_LOADA_REG);
3018                 }
3019                 break;
3020         case TRIG_NONE:
3021                 ni_stc_writel(dev, 0xffffff, NISTC_AO_UC_LOADA_REG);
3022                 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD, NISTC_AO_CMD1_REG);
3023                 ni_stc_writel(dev, 0xffffff, NISTC_AO_UC_LOADA_REG);
3024                 break;
3025         default:
3026                 ni_stc_writel(dev, 0, NISTC_AO_UC_LOADA_REG);
3027                 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD, NISTC_AO_CMD1_REG);
3028                 ni_stc_writel(dev, cmd->stop_arg, NISTC_AO_UC_LOADA_REG);
3029         }
3030
3031         devpriv->ao_mode1 &= ~(NISTC_AO_MODE1_UPDATE_SRC_MASK |
3032                                NISTC_AO_MODE1_UI_SRC_MASK |
3033                                NISTC_AO_MODE1_UPDATE_SRC_POLARITY |
3034                                NISTC_AO_MODE1_UI_SRC_POLARITY);
3035         switch (cmd->scan_begin_src) {
3036         case TRIG_TIMER:
3037                 devpriv->ao_cmd2 &= ~NISTC_AO_CMD2_BC_GATE_ENA;
3038                 trigvar =
3039                     ni_ns_to_timer(dev, cmd->scan_begin_arg,
3040                                    CMDF_ROUND_NEAREST);
3041                 ni_stc_writel(dev, 1, NISTC_AO_UI_LOADA_REG);
3042                 ni_stc_writew(dev, NISTC_AO_CMD1_UI_LOAD, NISTC_AO_CMD1_REG);
3043                 ni_stc_writel(dev, trigvar, NISTC_AO_UI_LOADA_REG);
3044                 break;
3045         case TRIG_EXT:
3046                 devpriv->ao_mode1 |=
3047                     NISTC_AO_MODE1_UPDATE_SRC(cmd->scan_begin_arg);
3048                 if (cmd->scan_begin_arg & CR_INVERT)
3049                         devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC_POLARITY;
3050                 devpriv->ao_cmd2 |= NISTC_AO_CMD2_BC_GATE_ENA;
3051                 break;
3052         default:
3053                 BUG();
3054                 break;
3055         }
3056         ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG);
3057         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3058         devpriv->ao_mode2 &= ~(NISTC_AO_MODE2_UI_RELOAD_MODE(3) |
3059                                NISTC_AO_MODE2_UI_INIT_LOAD_SRC);
3060         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3061
3062         if (cmd->scan_end_arg > 1) {
3063                 devpriv->ao_mode1 |= NISTC_AO_MODE1_MULTI_CHAN;
3064                 ni_stc_writew(dev,
3065                               AO_Number_Of_Channels(cmd->scan_end_arg - 1) |
3066                               AO_UPDATE_Output_Select(AO_Update_Output_High_Z),
3067                               AO_Output_Control_Register);
3068         } else {
3069                 unsigned bits;
3070
3071                 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_MULTI_CHAN;
3072                 bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z);
3073                 if (devpriv->is_m_series || devpriv->is_6xxx) {
3074                         bits |= AO_Number_Of_Channels(0);
3075                 } else {
3076                         bits |=
3077                             AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0]));
3078                 }
3079                 ni_stc_writew(dev, bits, AO_Output_Control_Register);
3080         }
3081         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3082
3083         ni_stc_writew(dev, NISTC_AO_CMD1_DAC1_UPDATE_MODE |
3084                            NISTC_AO_CMD1_DAC0_UPDATE_MODE,
3085                       NISTC_AO_CMD1_REG);
3086
3087         devpriv->ao_mode3 |= AO_Stop_On_Overrun_Error;
3088         ni_stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3089
3090         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_MODE_MASK;
3091 #ifdef PCIDMA
3092         devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF_F;
3093 #else
3094         devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF;
3095 #endif
3096         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_REXMIT_ENA;
3097         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3098
3099         bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3100             AO_TMRDACWR_Pulse_Width;
3101         if (board->ao_fifo_depth)
3102                 bits |= AO_FIFO_Enable;
3103         else
3104                 bits |= AO_DMA_PIO_Control;
3105 #if 0
3106         /* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281,
3107            verified with bus analyzer. */
3108         if (devpriv->is_m_series)
3109                 bits |= AO_Number_Of_DAC_Packages;
3110 #endif
3111         ni_stc_writew(dev, bits, AO_Personal_Register);
3112         /*  enable sending of ao dma requests */
3113         ni_stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
3114
3115         ni_stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3116
3117         if (cmd->stop_src == TRIG_COUNT) {
3118                 ni_stc_writew(dev, NISTC_INTB_ACK_AO_BC_TC,
3119                               NISTC_INTB_ACK_REG);
3120                 ni_set_bits(dev, Interrupt_B_Enable_Register,
3121                             AO_BC_TC_Interrupt_Enable, 1);
3122         }
3123
3124         s->async->inttrig = ni_ao_inttrig;
3125
3126         return 0;
3127 }
3128
3129 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3130                          struct comedi_cmd *cmd)
3131 {
3132         const struct ni_board_struct *board = dev->board_ptr;
3133         struct ni_private *devpriv = dev->private;
3134         int err = 0;
3135         unsigned int tmp;
3136
3137         /* Step 1 : check if triggers are trivially valid */
3138
3139         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3140         err |= comedi_check_trigger_src(&cmd->scan_begin_src,
3141                                         TRIG_TIMER | TRIG_EXT);
3142         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3143         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3144         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3145
3146         if (err)
3147                 return 1;
3148
3149         /* Step 2a : make sure trigger sources are unique */
3150
3151         err |= comedi_check_trigger_is_unique(cmd->start_src);
3152         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
3153         err |= comedi_check_trigger_is_unique(cmd->stop_src);
3154
3155         /* Step 2b : and mutually compatible */
3156
3157         if (err)
3158                 return 2;
3159
3160         /* Step 3: check if arguments are trivially valid */
3161
3162         switch (cmd->start_src) {
3163         case TRIG_INT:
3164                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3165                 break;
3166         case TRIG_EXT:
3167                 tmp = CR_CHAN(cmd->start_arg);
3168
3169                 if (tmp > 18)
3170                         tmp = 18;
3171                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3172                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
3173                 break;
3174         }
3175
3176         if (cmd->scan_begin_src == TRIG_TIMER) {
3177                 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
3178                                                     board->ao_speed);
3179                 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
3180                                                     devpriv->clock_ns *
3181                                                     0xffffff);
3182         }
3183
3184         err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3185         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3186                                            cmd->chanlist_len);
3187
3188         if (cmd->stop_src == TRIG_COUNT)
3189                 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3190         else    /* TRIG_NONE */
3191                 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
3192
3193         if (err)
3194                 return 3;
3195
3196         /* step 4: fix up any arguments */
3197         if (cmd->scan_begin_src == TRIG_TIMER) {
3198                 tmp = cmd->scan_begin_arg;
3199                 cmd->scan_begin_arg =
3200                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3201                                                        cmd->scan_begin_arg,
3202                                                        cmd->flags));
3203                 if (tmp != cmd->scan_begin_arg)
3204                         err++;
3205         }
3206         if (err)
3207                 return 4;
3208
3209         return 0;
3210 }
3211
3212 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3213 {
3214         struct ni_private *devpriv = dev->private;
3215
3216         ni_release_ao_mite_channel(dev);
3217
3218         ni_stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3219         ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);
3220         ni_set_bits(dev, Interrupt_B_Enable_Register, ~0, 0);
3221         ni_stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
3222         ni_stc_writew(dev, NISTC_INTB_ACK_AO_ALL, NISTC_INTB_ACK_REG);
3223         ni_stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3224                       AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
3225         ni_stc_writew(dev, 0, AO_Output_Control_Register);
3226         ni_stc_writew(dev, 0, AO_Start_Select_Register);
3227         devpriv->ao_cmd1 = 0;
3228         ni_stc_writew(dev, devpriv->ao_cmd1, NISTC_AO_CMD1_REG);
3229         devpriv->ao_cmd2 = 0;
3230         ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG);
3231         devpriv->ao_mode1 = 0;
3232         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3233         devpriv->ao_mode2 = 0;
3234         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3235         if (devpriv->is_m_series)
3236                 devpriv->ao_mode3 = AO_Last_Gate_Disable;
3237         else
3238                 devpriv->ao_mode3 = 0;
3239         ni_stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3240         devpriv->ao_trigger_select = 0;
3241         ni_stc_writew(dev, devpriv->ao_trigger_select,
3242                       AO_Trigger_Select_Register);
3243         if (devpriv->is_6xxx) {
3244                 unsigned immediate_bits = 0;
3245                 unsigned i;
3246
3247                 for (i = 0; i < s->n_chan; ++i)
3248                         immediate_bits |= 1 << i;
3249                 ni_ao_win_outw(dev, immediate_bits, AO_Immediate_671x);
3250                 ni_ao_win_outw(dev, CLEAR_WG, AO_Misc_611x);
3251         }
3252         ni_stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3253
3254         return 0;
3255 }
3256
3257 /* digital io */
3258
3259 static int ni_dio_insn_config(struct comedi_device *dev,
3260                               struct comedi_subdevice *s,
3261                               struct comedi_insn *insn,
3262                               unsigned int *data)
3263 {
3264         struct ni_private *devpriv = dev->private;
3265         int ret;
3266
3267         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3268         if (ret)
3269                 return ret;
3270
3271         devpriv->dio_control &= ~NISTC_DIO_CTRL_DIR_MASK;
3272         devpriv->dio_control |= NISTC_DIO_CTRL_DIR(s->io_bits);
3273         ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3274
3275         return insn->n;
3276 }
3277
3278 static int ni_dio_insn_bits(struct comedi_device *dev,
3279                             struct comedi_subdevice *s,
3280                             struct comedi_insn *insn,
3281                             unsigned int *data)
3282 {
3283         struct ni_private *devpriv = dev->private;
3284
3285         /* Make sure we're not using the serial part of the dio */
3286         if ((data[0] & (NISTC_DIO_SDIN | NISTC_DIO_SDOUT)) &&
3287             devpriv->serial_interval_ns)
3288                 return -EBUSY;
3289
3290         if (comedi_dio_update_state(s, data)) {
3291                 devpriv->dio_output &= ~NISTC_DIO_OUT_PARALLEL_MASK;
3292                 devpriv->dio_output |= NISTC_DIO_OUT_PARALLEL(s->state);
3293                 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3294         }
3295
3296         data[1] = ni_stc_readw(dev, DIO_Parallel_Input_Register);
3297
3298         return insn->n;
3299 }
3300
3301 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3302                                        struct comedi_subdevice *s,
3303                                        struct comedi_insn *insn,
3304                                        unsigned int *data)
3305 {
3306         int ret;
3307
3308         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3309         if (ret)
3310                 return ret;
3311
3312         ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
3313
3314         return insn->n;
3315 }
3316
3317 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3318                                      struct comedi_subdevice *s,
3319                                      struct comedi_insn *insn,
3320                                      unsigned int *data)
3321 {
3322         if (comedi_dio_update_state(s, data))
3323                 ni_writel(dev, s->state, NI_M_DIO_REG);
3324
3325         data[1] = ni_readl(dev, NI_M_DIO_REG);
3326
3327         return insn->n;
3328 }
3329
3330 static int ni_cdio_check_chanlist(struct comedi_device *dev,
3331                                   struct comedi_subdevice *s,
3332                                   struct comedi_cmd *cmd)
3333 {
3334         int i;
3335
3336         for (i = 0; i < cmd->chanlist_len; ++i) {
3337                 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3338
3339                 if (chan != i)
3340                         return -EINVAL;
3341         }
3342
3343         return 0;
3344 }
3345
3346 static int ni_cdio_cmdtest(struct comedi_device *dev,
3347                            struct comedi_subdevice *s, struct comedi_cmd *cmd)
3348 {
3349         int err = 0;
3350         int tmp;
3351
3352         /* Step 1 : check if triggers are trivially valid */
3353
3354         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT);
3355         err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3356         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3357         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3358         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3359
3360         if (err)
3361                 return 1;
3362
3363         /* Step 2a : make sure trigger sources are unique */
3364         /* Step 2b : and mutually compatible */
3365
3366         /* Step 3: check if arguments are trivially valid */
3367
3368         err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3369
3370         tmp = cmd->scan_begin_arg;
3371         tmp &= CR_PACK_FLAGS(NI_M_CDO_MODE_SAMPLE_SRC_MASK, 0, 0, CR_INVERT);
3372         if (tmp != cmd->scan_begin_arg)
3373                 err |= -EINVAL;
3374
3375         err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3376         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3377                                            cmd->chanlist_len);
3378         err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
3379
3380         if (err)
3381                 return 3;
3382
3383         /* Step 4: fix up any arguments */
3384
3385         /* Step 5: check channel list if it exists */
3386
3387         if (cmd->chanlist && cmd->chanlist_len > 0)
3388                 err |= ni_cdio_check_chanlist(dev, s, cmd);
3389
3390         if (err)
3391                 return 5;
3392
3393         return 0;
3394 }
3395
3396 static int ni_cdo_inttrig(struct comedi_device *dev,
3397                           struct comedi_subdevice *s,
3398                           unsigned int trig_num)
3399 {
3400         struct comedi_cmd *cmd = &s->async->cmd;
3401         const unsigned timeout = 1000;
3402         int retval = 0;
3403         unsigned i;
3404 #ifdef PCIDMA
3405         struct ni_private *devpriv = dev->private;
3406         unsigned long flags;
3407 #endif
3408
3409         if (trig_num != cmd->start_arg)
3410                 return -EINVAL;
3411
3412         s->async->inttrig = NULL;
3413
3414         /* read alloc the entire buffer */
3415         comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
3416
3417 #ifdef PCIDMA
3418         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3419         if (devpriv->cdo_mite_chan) {
3420                 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3421                 mite_dma_arm(devpriv->cdo_mite_chan);
3422         } else {
3423                 dev_err(dev->class_dev, "BUG: no cdo mite channel?\n");
3424                 retval = -EIO;
3425         }
3426         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3427         if (retval < 0)
3428                 return retval;
3429 #endif
3430         /*
3431          * XXX not sure what interrupt C group does
3432          * wait for dma to fill output fifo
3433          * ni_writeb(dev, NI_M_INTC_ENA, NI_M_INTC_ENA_REG);
3434          */
3435         for (i = 0; i < timeout; ++i) {
3436                 if (ni_readl(dev, NI_M_CDIO_STATUS_REG) &
3437                     NI_M_CDIO_STATUS_CDO_FIFO_FULL)
3438                         break;
3439                 udelay(10);
3440         }
3441         if (i == timeout) {
3442                 dev_err(dev->class_dev, "dma failed to fill cdo fifo!\n");
3443                 s->cancel(dev, s);
3444                 return -EIO;
3445         }
3446         ni_writel(dev, NI_M_CDO_CMD_ARM |
3447                        NI_M_CDO_CMD_ERR_INT_ENA_SET |
3448                        NI_M_CDO_CMD_F_E_INT_ENA_SET,
3449                   NI_M_CDIO_CMD_REG);
3450         return retval;
3451 }
3452
3453 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3454 {
3455         const struct comedi_cmd *cmd = &s->async->cmd;
3456         unsigned cdo_mode_bits;
3457         int retval;
3458
3459         ni_writel(dev, NI_M_CDO_CMD_RESET, NI_M_CDIO_CMD_REG);
3460         cdo_mode_bits = NI_M_CDO_MODE_FIFO_MODE |
3461                         NI_M_CDO_MODE_HALT_ON_ERROR |
3462                         NI_M_CDO_MODE_SAMPLE_SRC(CR_CHAN(cmd->scan_begin_arg));
3463         if (cmd->scan_begin_arg & CR_INVERT)
3464                 cdo_mode_bits |= NI_M_CDO_MODE_POLARITY;
3465         ni_writel(dev, cdo_mode_bits, NI_M_CDO_MODE_REG);
3466         if (s->io_bits) {
3467                 ni_writel(dev, s->state, NI_M_CDO_FIFO_DATA_REG);
3468                 ni_writel(dev, NI_M_CDO_CMD_SW_UPDATE, NI_M_CDIO_CMD_REG);
3469                 ni_writel(dev, s->io_bits, NI_M_CDO_MASK_ENA_REG);
3470         } else {
3471                 dev_err(dev->class_dev,
3472                         "attempted to run digital output command with no lines configured as outputs\n");
3473                 return -EIO;
3474         }
3475         retval = ni_request_cdo_mite_channel(dev);
3476         if (retval < 0)
3477                 return retval;
3478
3479         s->async->inttrig = ni_cdo_inttrig;
3480
3481         return 0;
3482 }
3483
3484 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3485 {
3486         ni_writel(dev, NI_M_CDO_CMD_DISARM |
3487                        NI_M_CDO_CMD_ERR_INT_ENA_CLR |
3488                        NI_M_CDO_CMD_F_E_INT_ENA_CLR |
3489                        NI_M_CDO_CMD_F_REQ_INT_ENA_CLR,
3490                   NI_M_CDIO_CMD_REG);
3491         /*
3492          * XXX not sure what interrupt C group does
3493          * ni_writeb(dev, 0, NI_M_INTC_ENA_REG);
3494          */
3495         ni_writel(dev, 0, NI_M_CDO_MASK_ENA_REG);
3496         ni_release_cdo_mite_channel(dev);
3497         return 0;
3498 }
3499
3500 static void handle_cdio_interrupt(struct comedi_device *dev)
3501 {
3502         struct ni_private *devpriv = dev->private;
3503         unsigned cdio_status;
3504         struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3505 #ifdef PCIDMA
3506         unsigned long flags;
3507 #endif
3508
3509         if (!devpriv->is_m_series)
3510                 return;
3511 #ifdef PCIDMA
3512         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3513         if (devpriv->cdo_mite_chan) {
3514                 unsigned cdo_mite_status =
3515                     mite_get_status(devpriv->cdo_mite_chan);
3516                 if (cdo_mite_status & CHSR_LINKC) {
3517                         writel(CHOR_CLRLC,
3518                                devpriv->mite->mite_io_addr +
3519                                MITE_CHOR(devpriv->cdo_mite_chan->channel));
3520                 }
3521                 mite_sync_output_dma(devpriv->cdo_mite_chan, s);
3522         }
3523         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3524 #endif
3525
3526         cdio_status = ni_readl(dev, NI_M_CDIO_STATUS_REG);
3527         if (cdio_status & NI_M_CDIO_STATUS_CDO_ERROR) {
3528                 /* XXX just guessing this is needed and does something useful */
3529                 ni_writel(dev, NI_M_CDO_CMD_ERR_INT_CONFIRM,
3530                           NI_M_CDIO_CMD_REG);
3531                 s->async->events |= COMEDI_CB_OVERFLOW;
3532         }
3533         if (cdio_status & NI_M_CDIO_STATUS_CDO_FIFO_EMPTY) {
3534                 ni_writel(dev, NI_M_CDO_CMD_F_E_INT_ENA_CLR,
3535                           NI_M_CDIO_CMD_REG);
3536                 /* s->async->events |= COMEDI_CB_EOA; */
3537         }
3538         comedi_handle_events(dev, s);
3539 }
3540
3541 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3542                                    struct comedi_subdevice *s,
3543                                    unsigned char data_out,
3544                                    unsigned char *data_in)
3545 {
3546         struct ni_private *devpriv = dev->private;
3547         unsigned int status1;
3548         int err = 0, count = 20;
3549
3550         devpriv->dio_output &= ~NISTC_DIO_OUT_SERIAL_MASK;
3551         devpriv->dio_output |= NISTC_DIO_OUT_SERIAL(data_out);
3552         ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3553
3554         status1 = ni_stc_readw(dev, Joint_Status_1_Register);
3555         if (status1 & DIO_Serial_IO_In_Progress_St) {
3556                 err = -EBUSY;
3557                 goto Error;
3558         }
3559
3560         devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_START;
3561         ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3562         devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_START;
3563
3564         /* Wait until STC says we're done, but don't loop infinitely. */
3565         while ((status1 = ni_stc_readw(dev, Joint_Status_1_Register)) &
3566                DIO_Serial_IO_In_Progress_St) {
3567                 /* Delay one bit per loop */
3568                 udelay((devpriv->serial_interval_ns + 999) / 1000);
3569                 if (--count < 0) {
3570                         dev_err(dev->class_dev,
3571                                 "SPI serial I/O didn't finish in time!\n");
3572                         err = -ETIME;
3573                         goto Error;
3574                 }
3575         }
3576
3577         /* Delay for last bit. This delay is absolutely necessary, because
3578            DIO_Serial_IO_In_Progress_St goes high one bit too early. */
3579         udelay((devpriv->serial_interval_ns + 999) / 1000);
3580
3581         if (data_in)
3582                 *data_in = ni_stc_readw(dev, DIO_Serial_Input_Register);
3583
3584 Error:
3585         ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3586
3587         return err;
3588 }
3589
3590 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
3591                                    struct comedi_subdevice *s,
3592                                    unsigned char data_out,
3593                                    unsigned char *data_in)
3594 {
3595         struct ni_private *devpriv = dev->private;
3596         unsigned char mask, input = 0;
3597
3598         /* Wait for one bit before transfer */
3599         udelay((devpriv->serial_interval_ns + 999) / 1000);
3600
3601         for (mask = 0x80; mask; mask >>= 1) {
3602                 /* Output current bit; note that we cannot touch s->state
3603                    because it is a per-subdevice field, and serial is
3604                    a separate subdevice from DIO. */
3605                 devpriv->dio_output &= ~NISTC_DIO_SDOUT;
3606                 if (data_out & mask)
3607                         devpriv->dio_output |= NISTC_DIO_SDOUT;
3608                 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3609
3610                 /* Assert SDCLK (active low, inverted), wait for half of
3611                    the delay, deassert SDCLK, and wait for the other half. */
3612                 devpriv->dio_control |= NISTC_DIO_SDCLK;
3613                 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3614
3615                 udelay((devpriv->serial_interval_ns + 999) / 2000);
3616
3617                 devpriv->dio_control &= ~NISTC_DIO_SDCLK;
3618                 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3619
3620                 udelay((devpriv->serial_interval_ns + 999) / 2000);
3621
3622                 /* Input current bit */
3623                 if (ni_stc_readw(dev, DIO_Parallel_Input_Register) &
3624                     NISTC_DIO_SDIN)
3625                         input |= mask;
3626         }
3627
3628         if (data_in)
3629                 *data_in = input;
3630
3631         return 0;
3632 }
3633
3634 static int ni_serial_insn_config(struct comedi_device *dev,
3635                                  struct comedi_subdevice *s,
3636                                  struct comedi_insn *insn,
3637                                  unsigned int *data)
3638 {
3639         struct ni_private *devpriv = dev->private;
3640         int err = insn->n;
3641         unsigned char byte_out, byte_in = 0;
3642
3643         if (insn->n != 2)
3644                 return -EINVAL;
3645
3646         switch (data[0]) {
3647         case INSN_CONFIG_SERIAL_CLOCK:
3648                 devpriv->serial_hw_mode = 1;
3649                 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_ENA;
3650
3651                 if (data[1] == SERIAL_DISABLED) {
3652                         devpriv->serial_hw_mode = 0;
3653                         devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3654                                                   NISTC_DIO_SDCLK);
3655                         data[1] = SERIAL_DISABLED;
3656                         devpriv->serial_interval_ns = data[1];
3657                 } else if (data[1] <= SERIAL_600NS) {
3658                         /* Warning: this clock speed is too fast to reliably
3659                            control SCXI. */
3660                         devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3661                         devpriv->clock_and_fout |= Slow_Internal_Timebase;
3662                         devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
3663                         data[1] = SERIAL_600NS;
3664                         devpriv->serial_interval_ns = data[1];
3665                 } else if (data[1] <= SERIAL_1_2US) {
3666                         devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3667                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
3668                             DIO_Serial_Out_Divide_By_2;
3669                         data[1] = SERIAL_1_2US;
3670                         devpriv->serial_interval_ns = data[1];
3671                 } else if (data[1] <= SERIAL_10US) {
3672                         devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3673                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
3674                             DIO_Serial_Out_Divide_By_2;
3675                         /* Note: DIO_Serial_Out_Divide_By_2 only affects
3676                            600ns/1.2us. If you turn divide_by_2 off with the
3677                            slow clock, you will still get 10us, except then
3678                            all your delays are wrong. */
3679                         data[1] = SERIAL_10US;
3680                         devpriv->serial_interval_ns = data[1];
3681                 } else {
3682                         devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3683                                                   NISTC_DIO_SDCLK);
3684                         devpriv->serial_hw_mode = 0;
3685                         data[1] = (data[1] / 1000) * 1000;
3686                         devpriv->serial_interval_ns = data[1];
3687                 }
3688
3689                 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3690                 ni_stc_writew(dev, devpriv->clock_and_fout,
3691                               Clock_and_FOUT_Register);
3692                 return 1;
3693
3694         case INSN_CONFIG_BIDIRECTIONAL_DATA:
3695
3696                 if (devpriv->serial_interval_ns == 0)
3697                         return -EINVAL;
3698
3699                 byte_out = data[1] & 0xFF;
3700
3701                 if (devpriv->serial_hw_mode) {
3702                         err = ni_serial_hw_readwrite8(dev, s, byte_out,
3703                                                       &byte_in);
3704                 } else if (devpriv->serial_interval_ns > 0) {
3705                         err = ni_serial_sw_readwrite8(dev, s, byte_out,
3706                                                       &byte_in);
3707                 } else {
3708                         dev_err(dev->class_dev, "serial disabled!\n");
3709                         return -EINVAL;
3710                 }
3711                 if (err < 0)
3712                         return err;
3713                 data[1] = byte_in & 0xFF;
3714                 return insn->n;
3715
3716                 break;
3717         default:
3718                 return -EINVAL;
3719         }
3720 }
3721
3722 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
3723 {
3724         int i;
3725
3726         for (i = 0; i < s->n_chan; i++) {
3727                 ni_ao_win_outw(dev, AO_Channel(i) | 0x0,
3728                                AO_Configuration_2_67xx);
3729         }
3730         ni_ao_win_outw(dev, 0x0, AO_Later_Single_Point_Updates);
3731 }
3732
3733 static const struct mio_regmap ni_gpct_to_stc_regmap[] = {
3734         [NITIO_G0_AUTO_INC]     = { G_Autoincrement_Register(0), 2 },
3735         [NITIO_G1_AUTO_INC]     = { G_Autoincrement_Register(1), 2 },
3736         [NITIO_G0_CMD]          = { NISTC_G0_CMD_REG, 2 },
3737         [NITIO_G1_CMD]          = { NISTC_G1_CMD_REG, 2 },
3738         [NITIO_G0_HW_SAVE]      = { G_HW_Save_Register(0), 4 },
3739         [NITIO_G1_HW_SAVE]      = { G_HW_Save_Register(1), 4 },
3740         [NITIO_G0_SW_SAVE]      = { G_Save_Register(0), 4 },
3741         [NITIO_G1_SW_SAVE]      = { G_Save_Register(1), 4 },
3742         [NITIO_G0_MODE]         = { NISTC_G0_MODE_REG, 2 },
3743         [NITIO_G1_MODE]         = { NISTC_G1_MODE_REG, 2 },
3744         [NITIO_G0_LOADA]        = { NISTC_G0_LOADA_REG, 4 },
3745         [NITIO_G1_LOADA]        = { NISTC_G1_LOADA_REG, 4 },
3746         [NITIO_G0_LOADB]        = { NISTC_G0_LOADB_REG, 4 },
3747         [NITIO_G1_LOADB]        = { NISTC_G1_LOADB_REG, 4 },
3748         [NITIO_G0_INPUT_SEL]    = { NISTC_G0_INPUT_SEL_REG, 2 },
3749         [NITIO_G1_INPUT_SEL]    = { NISTC_G1_INPUT_SEL_REG, 2 },
3750         [NITIO_G0_CNT_MODE]     = { 0x1b0, 2 }, /* M-Series only */
3751         [NITIO_G1_CNT_MODE]     = { 0x1b2, 2 }, /* M-Series only */
3752         [NITIO_G0_GATE2]        = { 0x1b4, 2 }, /* M-Series only */
3753         [NITIO_G1_GATE2]        = { 0x1b6, 2 }, /* M-Series only */
3754         [NITIO_G01_STATUS]      = { G_Status_Register, 2 },
3755         [NITIO_G01_RESET]       = { Joint_Reset_Register, 2 },
3756         [NITIO_G01_STATUS1]     = { Joint_Status_1_Register, 2 },
3757         [NITIO_G01_STATUS2]     = { Joint_Status_2_Register, 2 },
3758         [NITIO_G0_DMA_CFG]      = { 0x1b8, 2 }, /* M-Series only */
3759         [NITIO_G1_DMA_CFG]      = { 0x1ba, 2 }, /* M-Series only */
3760         [NITIO_G0_DMA_STATUS]   = { 0x1b8, 2 }, /* M-Series only */
3761         [NITIO_G1_DMA_STATUS]   = { 0x1ba, 2 }, /* M-Series only */
3762         [NITIO_G0_ABZ]          = { 0x1c0, 2 }, /* M-Series only */
3763         [NITIO_G1_ABZ]          = { 0x1c2, 2 }, /* M-Series only */
3764         [NITIO_G0_INT_ACK]      = { NISTC_INTA_ACK_REG, 2 },
3765         [NITIO_G1_INT_ACK]      = { NISTC_INTB_ACK_REG, 2 },
3766         [NITIO_G0_STATUS]       = { AI_Status_1_Register, 2 },
3767         [NITIO_G1_STATUS]       = { AO_Status_1_Register, 2 },
3768         [NITIO_G0_INT_ENA]      = { Interrupt_A_Enable_Register, 2 },
3769         [NITIO_G1_INT_ENA]      = { Interrupt_B_Enable_Register, 2 },
3770 };
3771
3772 static unsigned int ni_gpct_to_stc_register(struct comedi_device *dev,
3773                                             enum ni_gpct_register reg)
3774 {
3775         const struct mio_regmap *regmap;
3776
3777         if (reg < ARRAY_SIZE(ni_gpct_to_stc_regmap)) {
3778                 regmap = &ni_gpct_to_stc_regmap[reg];
3779         } else {
3780                 dev_warn(dev->class_dev,"%s: unhandled register 0x%x\n",
3781                          __func__, reg);
3782                 return 0;
3783         }
3784
3785         return regmap->mio_reg;
3786 }
3787
3788 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
3789                                    enum ni_gpct_register reg)
3790 {
3791         struct comedi_device *dev = counter->counter_dev->dev;
3792         unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
3793         /* bits in the join reset register which are relevant to counters */
3794         static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset;
3795         static const unsigned gpct_interrupt_a_enable_mask =
3796             G0_Gate_Interrupt_Enable | G0_TC_Interrupt_Enable;
3797         static const unsigned gpct_interrupt_b_enable_mask =
3798             G1_Gate_Interrupt_Enable | G1_TC_Interrupt_Enable;
3799
3800         if (stc_register == 0)
3801                 return;
3802
3803         switch (reg) {
3804                 /* m-series only registers */
3805         case NITIO_G0_CNT_MODE:
3806         case NITIO_G1_CNT_MODE:
3807         case NITIO_G0_GATE2:
3808         case NITIO_G1_GATE2:
3809         case NITIO_G0_DMA_CFG:
3810         case NITIO_G1_DMA_CFG:
3811         case NITIO_G0_ABZ:
3812         case NITIO_G1_ABZ:
3813                 ni_writew(dev, bits, stc_register);
3814                 break;
3815
3816                 /* 32 bit registers */
3817         case NITIO_G0_LOADA:
3818         case NITIO_G1_LOADA:
3819         case NITIO_G0_LOADB:
3820         case NITIO_G1_LOADB:
3821                 ni_stc_writel(dev, bits, stc_register);
3822                 break;
3823
3824                 /* 16 bit registers */
3825         case NITIO_G0_INT_ENA:
3826                 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
3827                 ni_set_bitfield(dev, stc_register,
3828                                 gpct_interrupt_a_enable_mask, bits);
3829                 break;
3830         case NITIO_G1_INT_ENA:
3831                 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
3832                 ni_set_bitfield(dev, stc_register,
3833                                 gpct_interrupt_b_enable_mask, bits);
3834                 break;
3835         case NITIO_G01_RESET:
3836                 BUG_ON(bits & ~gpct_joint_reset_mask);
3837                 /* fall-through */
3838         default:
3839                 ni_stc_writew(dev, bits, stc_register);
3840         }
3841 }
3842
3843 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
3844                                       enum ni_gpct_register reg)
3845 {
3846         struct comedi_device *dev = counter->counter_dev->dev;
3847         unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
3848
3849         if (stc_register == 0)
3850                 return 0;
3851
3852         switch (reg) {
3853                 /* m-series only registers */
3854         case NITIO_G0_DMA_STATUS:
3855         case NITIO_G1_DMA_STATUS:
3856                 return ni_readw(dev, stc_register);
3857
3858                 /* 32 bit registers */
3859         case NITIO_G0_HW_SAVE:
3860         case NITIO_G1_HW_SAVE:
3861         case NITIO_G0_SW_SAVE:
3862         case NITIO_G1_SW_SAVE:
3863                 return ni_stc_readl(dev, stc_register);
3864
3865                 /* 16 bit registers */
3866         default:
3867                 return ni_stc_readw(dev, stc_register);
3868         }
3869 }
3870
3871 static int ni_freq_out_insn_read(struct comedi_device *dev,
3872                                  struct comedi_subdevice *s,
3873                                  struct comedi_insn *insn,
3874                                  unsigned int *data)
3875 {
3876         struct ni_private *devpriv = dev->private;
3877         unsigned int val = devpriv->clock_and_fout & FOUT_Divider_mask;
3878         int i;
3879
3880         for (i = 0; i < insn->n; i++)
3881                 data[i] = val;
3882
3883         return insn->n;
3884 }
3885
3886 static int ni_freq_out_insn_write(struct comedi_device *dev,
3887                                   struct comedi_subdevice *s,
3888                                   struct comedi_insn *insn,
3889                                   unsigned int *data)
3890 {
3891         struct ni_private *devpriv = dev->private;
3892
3893         if (insn->n) {
3894                 devpriv->clock_and_fout &= ~FOUT_Enable;
3895                 ni_stc_writew(dev, devpriv->clock_and_fout,
3896                               Clock_and_FOUT_Register);
3897                 devpriv->clock_and_fout &= ~FOUT_Divider_mask;
3898
3899                 /* use the last data value to set the fout divider */
3900                 devpriv->clock_and_fout |= FOUT_Divider(data[insn->n - 1]);
3901
3902                 devpriv->clock_and_fout |= FOUT_Enable;
3903                 ni_stc_writew(dev, devpriv->clock_and_fout,
3904                               Clock_and_FOUT_Register);
3905         }
3906         return insn->n;
3907 }
3908
3909 static int ni_freq_out_insn_config(struct comedi_device *dev,
3910                                    struct comedi_subdevice *s,
3911                                    struct comedi_insn *insn,
3912                                    unsigned int *data)
3913 {
3914         struct ni_private *devpriv = dev->private;
3915
3916         switch (data[0]) {
3917         case INSN_CONFIG_SET_CLOCK_SRC:
3918                 switch (data[1]) {
3919                 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
3920                         devpriv->clock_and_fout &= ~FOUT_Timebase_Select;
3921                         break;
3922                 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
3923                         devpriv->clock_and_fout |= FOUT_Timebase_Select;
3924                         break;
3925                 default:
3926                         return -EINVAL;
3927                 }
3928                 ni_stc_writew(dev, devpriv->clock_and_fout,
3929                               Clock_and_FOUT_Register);
3930                 break;
3931         case INSN_CONFIG_GET_CLOCK_SRC:
3932                 if (devpriv->clock_and_fout & FOUT_Timebase_Select) {
3933                         data[1] = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
3934                         data[2] = TIMEBASE_2_NS;
3935                 } else {
3936                         data[1] = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
3937                         data[2] = TIMEBASE_1_NS * 2;
3938                 }
3939                 break;
3940         default:
3941                 return -EINVAL;
3942         }
3943         return insn->n;
3944 }
3945
3946 static int ni_8255_callback(struct comedi_device *dev,
3947                             int dir, int port, int data, unsigned long iobase)
3948 {
3949         if (dir) {
3950                 ni_writeb(dev, data, iobase + 2 * port);
3951                 return 0;
3952         }
3953
3954         return ni_readb(dev, iobase + 2 * port);
3955 }
3956
3957 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
3958 {
3959         struct ni_private *devpriv = dev->private;
3960
3961         data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
3962         data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
3963         return 3;
3964 }
3965
3966 static int ni_m_series_pwm_config(struct comedi_device *dev,
3967                                   struct comedi_subdevice *s,
3968                                   struct comedi_insn *insn,
3969                                   unsigned int *data)
3970 {
3971         struct ni_private *devpriv = dev->private;
3972         unsigned up_count, down_count;
3973
3974         switch (data[0]) {
3975         case INSN_CONFIG_PWM_OUTPUT:
3976                 switch (data[1]) {
3977                 case CMDF_ROUND_NEAREST:
3978                         up_count =
3979                             (data[2] +
3980                              devpriv->clock_ns / 2) / devpriv->clock_ns;
3981                         break;
3982                 case CMDF_ROUND_DOWN:
3983                         up_count = data[2] / devpriv->clock_ns;
3984                         break;
3985                 case CMDF_ROUND_UP:
3986                         up_count =
3987                             (data[2] + devpriv->clock_ns -
3988                              1) / devpriv->clock_ns;
3989                         break;
3990                 default:
3991                         return -EINVAL;
3992                 }
3993                 switch (data[3]) {
3994                 case CMDF_ROUND_NEAREST:
3995                         down_count =
3996                             (data[4] +
3997                              devpriv->clock_ns / 2) / devpriv->clock_ns;
3998                         break;
3999                 case CMDF_ROUND_DOWN:
4000                         down_count = data[4] / devpriv->clock_ns;
4001                         break;
4002                 case CMDF_ROUND_UP:
4003                         down_count =
4004                             (data[4] + devpriv->clock_ns -
4005                              1) / devpriv->clock_ns;
4006                         break;
4007                 default:
4008                         return -EINVAL;
4009                 }
4010                 if (up_count * devpriv->clock_ns != data[2] ||
4011                     down_count * devpriv->clock_ns != data[4]) {
4012                         data[2] = up_count * devpriv->clock_ns;
4013                         data[4] = down_count * devpriv->clock_ns;
4014                         return -EAGAIN;
4015                 }
4016                 ni_writel(dev, NI_M_CAL_PWM_HIGH_TIME(up_count) |
4017                                NI_M_CAL_PWM_LOW_TIME(down_count),
4018                           NI_M_CAL_PWM_REG);
4019                 devpriv->pwm_up_count = up_count;
4020                 devpriv->pwm_down_count = down_count;
4021                 return 5;
4022         case INSN_CONFIG_GET_PWM_OUTPUT:
4023                 return ni_get_pwm_config(dev, data);
4024         default:
4025                 return -EINVAL;
4026         }
4027         return 0;
4028 }
4029
4030 static int ni_6143_pwm_config(struct comedi_device *dev,
4031                               struct comedi_subdevice *s,
4032                               struct comedi_insn *insn,
4033                               unsigned int *data)
4034 {
4035         struct ni_private *devpriv = dev->private;
4036         unsigned up_count, down_count;
4037
4038         switch (data[0]) {
4039         case INSN_CONFIG_PWM_OUTPUT:
4040                 switch (data[1]) {
4041                 case CMDF_ROUND_NEAREST:
4042                         up_count =
4043                             (data[2] +
4044                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4045                         break;
4046                 case CMDF_ROUND_DOWN:
4047                         up_count = data[2] / devpriv->clock_ns;
4048                         break;
4049                 case CMDF_ROUND_UP:
4050                         up_count =
4051                             (data[2] + devpriv->clock_ns -
4052                              1) / devpriv->clock_ns;
4053                         break;
4054                 default:
4055                         return -EINVAL;
4056                 }
4057                 switch (data[3]) {
4058                 case CMDF_ROUND_NEAREST:
4059                         down_count =
4060                             (data[4] +
4061                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4062                         break;
4063                 case CMDF_ROUND_DOWN:
4064                         down_count = data[4] / devpriv->clock_ns;
4065                         break;
4066                 case CMDF_ROUND_UP:
4067                         down_count =
4068                             (data[4] + devpriv->clock_ns -
4069                              1) / devpriv->clock_ns;
4070                         break;
4071                 default:
4072                         return -EINVAL;
4073                 }
4074                 if (up_count * devpriv->clock_ns != data[2] ||
4075                     down_count * devpriv->clock_ns != data[4]) {
4076                         data[2] = up_count * devpriv->clock_ns;
4077                         data[4] = down_count * devpriv->clock_ns;
4078                         return -EAGAIN;
4079                 }
4080                 ni_writel(dev, up_count, Calibration_HighTime_6143);
4081                 devpriv->pwm_up_count = up_count;
4082                 ni_writel(dev, down_count, Calibration_LowTime_6143);
4083                 devpriv->pwm_down_count = down_count;
4084                 return 5;
4085         case INSN_CONFIG_GET_PWM_OUTPUT:
4086                 return ni_get_pwm_config(dev, data);
4087         default:
4088                 return -EINVAL;
4089         }
4090         return 0;
4091 }
4092
4093 static int pack_mb88341(int addr, int val, int *bitstring)
4094 {
4095         /*
4096            Fujitsu MB 88341
4097            Note that address bits are reversed.  Thanks to
4098            Ingo Keen for noticing this.
4099
4100            Note also that the 88341 expects address values from
4101            1-12, whereas we use channel numbers 0-11.  The NI
4102            docs use 1-12, also, so be careful here.
4103          */
4104         addr++;
4105         *bitstring = ((addr & 0x1) << 11) |
4106             ((addr & 0x2) << 9) |
4107             ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
4108         return 12;
4109 }
4110
4111 static int pack_dac8800(int addr, int val, int *bitstring)
4112 {
4113         *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
4114         return 11;
4115 }
4116
4117 static int pack_dac8043(int addr, int val, int *bitstring)
4118 {
4119         *bitstring = val & 0xfff;
4120         return 12;
4121 }
4122
4123 static int pack_ad8522(int addr, int val, int *bitstring)
4124 {
4125         *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
4126         return 16;
4127 }
4128
4129 static int pack_ad8804(int addr, int val, int *bitstring)
4130 {
4131         *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
4132         return 12;
4133 }
4134
4135 static int pack_ad8842(int addr, int val, int *bitstring)
4136 {
4137         *bitstring = ((addr + 1) << 8) | (val & 0xff);
4138         return 12;
4139 }
4140
4141 struct caldac_struct {
4142         int n_chans;
4143         int n_bits;
4144         int (*packbits)(int, int, int *);
4145 };
4146
4147 static struct caldac_struct caldacs[] = {
4148         [mb88341] = {12, 8, pack_mb88341},
4149         [dac8800] = {8, 8, pack_dac8800},
4150         [dac8043] = {1, 12, pack_dac8043},
4151         [ad8522] = {2, 12, pack_ad8522},
4152         [ad8804] = {12, 8, pack_ad8804},
4153         [ad8842] = {8, 8, pack_ad8842},
4154         [ad8804_debug] = {16, 8, pack_ad8804},
4155 };
4156
4157 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
4158 {
4159         const struct ni_board_struct *board = dev->board_ptr;
4160         struct ni_private *devpriv = dev->private;
4161         unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
4162         int i;
4163         int type;
4164
4165         if (devpriv->caldacs[addr] == val)
4166                 return;
4167         devpriv->caldacs[addr] = val;
4168
4169         for (i = 0; i < 3; i++) {
4170                 type = board->caldac[i];
4171                 if (type == caldac_none)
4172                         break;
4173                 if (addr < caldacs[type].n_chans) {
4174                         bits = caldacs[type].packbits(addr, val, &bitstring);
4175                         loadbit = SerDacLd(i);
4176                         break;
4177                 }
4178                 addr -= caldacs[type].n_chans;
4179         }
4180
4181         /* bits will be 0 if there is no caldac for the given addr */
4182         if (bits == 0)
4183                 return;
4184
4185         for (bit = 1 << (bits - 1); bit; bit >>= 1) {
4186                 ni_writeb(dev, ((bit & bitstring) ? 0x02 : 0), Serial_Command);
4187                 udelay(1);
4188                 ni_writeb(dev, 1 | ((bit & bitstring) ? 0x02 : 0),
4189                           Serial_Command);
4190                 udelay(1);
4191         }
4192         ni_writeb(dev, loadbit, Serial_Command);
4193         udelay(1);
4194         ni_writeb(dev, 0, Serial_Command);
4195 }
4196
4197 static int ni_calib_insn_write(struct comedi_device *dev,
4198                                struct comedi_subdevice *s,
4199                                struct comedi_insn *insn,
4200                                unsigned int *data)
4201 {
4202         ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4203
4204         return 1;
4205 }
4206
4207 static int ni_calib_insn_read(struct comedi_device *dev,
4208                               struct comedi_subdevice *s,
4209                               struct comedi_insn *insn,
4210                               unsigned int *data)
4211 {
4212         struct ni_private *devpriv = dev->private;
4213
4214         data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4215
4216         return 1;
4217 }
4218
4219 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4220 {
4221         const struct ni_board_struct *board = dev->board_ptr;
4222         struct ni_private *devpriv = dev->private;
4223         int i, j;
4224         int n_dacs;
4225         int n_chans = 0;
4226         int n_bits;
4227         int diffbits = 0;
4228         int type;
4229         int chan;
4230
4231         type = board->caldac[0];
4232         if (type == caldac_none)
4233                 return;
4234         n_bits = caldacs[type].n_bits;
4235         for (i = 0; i < 3; i++) {
4236                 type = board->caldac[i];
4237                 if (type == caldac_none)
4238                         break;
4239                 if (caldacs[type].n_bits != n_bits)
4240                         diffbits = 1;
4241                 n_chans += caldacs[type].n_chans;
4242         }
4243         n_dacs = i;
4244         s->n_chan = n_chans;
4245
4246         if (diffbits) {
4247                 unsigned int *maxdata_list;
4248
4249                 if (n_chans > MAX_N_CALDACS)
4250                         dev_err(dev->class_dev,
4251                                 "BUG! MAX_N_CALDACS too small\n");
4252                 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
4253                 chan = 0;
4254                 for (i = 0; i < n_dacs; i++) {
4255                         type = board->caldac[i];
4256                         for (j = 0; j < caldacs[type].n_chans; j++) {
4257                                 maxdata_list[chan] =
4258                                     (1 << caldacs[type].n_bits) - 1;
4259                                 chan++;
4260                         }
4261                 }
4262
4263                 for (chan = 0; chan < s->n_chan; chan++)
4264                         ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
4265         } else {
4266                 type = board->caldac[0];
4267                 s->maxdata = (1 << caldacs[type].n_bits) - 1;
4268
4269                 for (chan = 0; chan < s->n_chan; chan++)
4270                         ni_write_caldac(dev, i, s->maxdata / 2);
4271         }
4272 }
4273
4274 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4275 {
4276         int bit;
4277         int bitstring;
4278
4279         bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4280         ni_writeb(dev, 0x04, Serial_Command);
4281         for (bit = 0x8000; bit; bit >>= 1) {
4282                 ni_writeb(dev, 0x04 | ((bit & bitstring) ? 0x02 : 0),
4283                           Serial_Command);
4284                 ni_writeb(dev, 0x05 | ((bit & bitstring) ? 0x02 : 0),
4285                           Serial_Command);
4286         }
4287         bitstring = 0;
4288         for (bit = 0x80; bit; bit >>= 1) {
4289                 ni_writeb(dev, 0x04, Serial_Command);
4290                 ni_writeb(dev, 0x05, Serial_Command);
4291                 bitstring |= ((ni_readb(dev, XXX_Status) & PROMOUT) ? bit : 0);
4292         }
4293         ni_writeb(dev, 0x00, Serial_Command);
4294
4295         return bitstring;
4296 }
4297
4298 static int ni_eeprom_insn_read(struct comedi_device *dev,
4299                                struct comedi_subdevice *s,
4300                                struct comedi_insn *insn,
4301                                unsigned int *data)
4302 {
4303         data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4304
4305         return 1;
4306 }
4307
4308 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4309                                         struct comedi_subdevice *s,
4310                                         struct comedi_insn *insn,
4311                                         unsigned int *data)
4312 {
4313         struct ni_private *devpriv = dev->private;
4314
4315         data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4316
4317         return 1;
4318 }
4319
4320 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev,
4321                                        unsigned chan)
4322 {
4323         /*  pre-m-series boards have fixed signals on pfi pins */
4324         switch (chan) {
4325         case 0:
4326                 return NI_PFI_OUTPUT_AI_START1;
4327         case 1:
4328                 return NI_PFI_OUTPUT_AI_START2;
4329         case 2:
4330                 return NI_PFI_OUTPUT_AI_CONVERT;
4331         case 3:
4332                 return NI_PFI_OUTPUT_G_SRC1;
4333         case 4:
4334                 return NI_PFI_OUTPUT_G_GATE1;
4335         case 5:
4336                 return NI_PFI_OUTPUT_AO_UPDATE_N;
4337         case 6:
4338                 return NI_PFI_OUTPUT_AO_START1;
4339         case 7:
4340                 return NI_PFI_OUTPUT_AI_START_PULSE;
4341         case 8:
4342                 return NI_PFI_OUTPUT_G_SRC0;
4343         case 9:
4344                 return NI_PFI_OUTPUT_G_GATE0;
4345         default:
4346                 dev_err(dev->class_dev, "bug, unhandled case in switch.\n");
4347                 break;
4348         }
4349         return 0;
4350 }
4351
4352 static int ni_old_set_pfi_routing(struct comedi_device *dev,
4353                                   unsigned chan, unsigned source)
4354 {
4355         /*  pre-m-series boards have fixed signals on pfi pins */
4356         if (source != ni_old_get_pfi_routing(dev, chan))
4357                 return -EINVAL;
4358         return 2;
4359 }
4360
4361 static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev,
4362                                             unsigned chan)
4363 {
4364         struct ni_private *devpriv = dev->private;
4365         const unsigned array_offset = chan / 3;
4366
4367         return NI_M_PFI_OUT_SEL_TO_SRC(chan,
4368                                 devpriv->pfi_output_select_reg[array_offset]);
4369 }
4370
4371 static int ni_m_series_set_pfi_routing(struct comedi_device *dev,
4372                                        unsigned chan, unsigned source)
4373 {
4374         struct ni_private *devpriv = dev->private;
4375         unsigned index = chan / 3;
4376         unsigned short val = devpriv->pfi_output_select_reg[index];
4377
4378         if ((source & 0x1f) != source)
4379                 return -EINVAL;
4380
4381         val &= ~NI_M_PFI_OUT_SEL_MASK(chan);
4382         val |= NI_M_PFI_OUT_SEL(chan, source);
4383         ni_writew(dev, val, NI_M_PFI_OUT_SEL_REG(index));
4384         devpriv->pfi_output_select_reg[index] = val;
4385
4386         return 2;
4387 }
4388
4389 static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan)
4390 {
4391         struct ni_private *devpriv = dev->private;
4392
4393         return (devpriv->is_m_series)
4394                         ? ni_m_series_get_pfi_routing(dev, chan)
4395                         : ni_old_get_pfi_routing(dev, chan);
4396 }
4397
4398 static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan,
4399                               unsigned source)
4400 {
4401         struct ni_private *devpriv = dev->private;
4402
4403         return (devpriv->is_m_series)
4404                         ? ni_m_series_set_pfi_routing(dev, chan, source)
4405                         : ni_old_set_pfi_routing(dev, chan, source);
4406 }
4407
4408 static int ni_config_filter(struct comedi_device *dev,
4409                             unsigned pfi_channel,
4410                             enum ni_pfi_filter_select filter)
4411 {
4412         struct ni_private *devpriv = dev->private;
4413         unsigned bits;
4414
4415         if (!devpriv->is_m_series)
4416                 return -ENOTSUPP;
4417
4418         bits = ni_readl(dev, NI_M_PFI_FILTER_REG);
4419         bits &= ~NI_M_PFI_FILTER_SEL_MASK(pfi_channel);
4420         bits |= NI_M_PFI_FILTER_SEL(pfi_channel, filter);
4421         ni_writel(dev, bits, NI_M_PFI_FILTER_REG);
4422         return 0;
4423 }
4424
4425 static int ni_pfi_insn_config(struct comedi_device *dev,
4426                               struct comedi_subdevice *s,
4427                               struct comedi_insn *insn,
4428                               unsigned int *data)
4429 {
4430         struct ni_private *devpriv = dev->private;
4431         unsigned int chan;
4432
4433         if (insn->n < 1)
4434                 return -EINVAL;
4435
4436         chan = CR_CHAN(insn->chanspec);
4437
4438         switch (data[0]) {
4439         case COMEDI_OUTPUT:
4440                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 1);
4441                 break;
4442         case COMEDI_INPUT:
4443                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 0);
4444                 break;
4445         case INSN_CONFIG_DIO_QUERY:
4446                 data[1] =
4447                     (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
4448                     COMEDI_OUTPUT : COMEDI_INPUT;
4449                 return 0;
4450         case INSN_CONFIG_SET_ROUTING:
4451                 return ni_set_pfi_routing(dev, chan, data[1]);
4452         case INSN_CONFIG_GET_ROUTING:
4453                 data[1] = ni_get_pfi_routing(dev, chan);
4454                 break;
4455         case INSN_CONFIG_FILTER:
4456                 return ni_config_filter(dev, chan, data[1]);
4457         default:
4458                 return -EINVAL;
4459         }
4460         return 0;
4461 }
4462
4463 static int ni_pfi_insn_bits(struct comedi_device *dev,
4464                             struct comedi_subdevice *s,
4465                             struct comedi_insn *insn,
4466                             unsigned int *data)
4467 {
4468         struct ni_private *devpriv = dev->private;
4469
4470         if (!devpriv->is_m_series)
4471                 return -ENOTSUPP;
4472
4473         if (comedi_dio_update_state(s, data))
4474                 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
4475
4476         data[1] = ni_readw(dev, NI_M_PFI_DI_REG);
4477
4478         return insn->n;
4479 }
4480
4481 static int cs5529_wait_for_idle(struct comedi_device *dev)
4482 {
4483         unsigned short status;
4484         const int timeout = HZ;
4485         int i;
4486
4487         for (i = 0; i < timeout; i++) {
4488                 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
4489                 if ((status & CSS_ADC_BUSY) == 0)
4490                         break;
4491                 set_current_state(TASK_INTERRUPTIBLE);
4492                 if (schedule_timeout(1))
4493                         return -EIO;
4494         }
4495         if (i == timeout) {
4496                 dev_err(dev->class_dev, "timeout\n");
4497                 return -ETIME;
4498         }
4499         return 0;
4500 }
4501
4502 static void cs5529_command(struct comedi_device *dev, unsigned short value)
4503 {
4504         static const int timeout = 100;
4505         int i;
4506
4507         ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
4508         /* give time for command to start being serially clocked into cs5529.
4509          * this insures that the CSS_ADC_BUSY bit will get properly
4510          * set before we exit this function.
4511          */
4512         for (i = 0; i < timeout; i++) {
4513                 if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
4514                         break;
4515                 udelay(1);
4516         }
4517         if (i == timeout)
4518                 dev_err(dev->class_dev,
4519                         "possible problem - never saw adc go busy?\n");
4520 }
4521
4522 static int cs5529_do_conversion(struct comedi_device *dev,
4523                                 unsigned short *data)
4524 {
4525         int retval;
4526         unsigned short status;
4527
4528         cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
4529         retval = cs5529_wait_for_idle(dev);
4530         if (retval) {
4531                 dev_err(dev->class_dev,
4532                         "timeout or signal in cs5529_do_conversion()\n");
4533                 return -ETIME;
4534         }
4535         status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
4536         if (status & CSS_OSC_DETECT) {
4537                 dev_err(dev->class_dev,
4538                         "cs5529 conversion error, status CSS_OSC_DETECT\n");
4539                 return -EIO;
4540         }
4541         if (status & CSS_OVERRANGE) {
4542                 dev_err(dev->class_dev,
4543                         "cs5529 conversion error, overrange (ignoring)\n");
4544         }
4545         if (data) {
4546                 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
4547                 /* cs5529 returns 16 bit signed data in bipolar mode */
4548                 *data ^= (1 << 15);
4549         }
4550         return 0;
4551 }
4552
4553 static int cs5529_ai_insn_read(struct comedi_device *dev,
4554                                struct comedi_subdevice *s,
4555                                struct comedi_insn *insn,
4556                                unsigned int *data)
4557 {
4558         int n, retval;
4559         unsigned short sample;
4560         unsigned int channel_select;
4561         const unsigned int INTERNAL_REF = 0x1000;
4562
4563         /* Set calibration adc source.  Docs lie, reference select bits 8 to 11
4564          * do nothing. bit 12 seems to chooses internal reference voltage, bit
4565          * 13 causes the adc input to go overrange (maybe reads external reference?) */
4566         if (insn->chanspec & CR_ALT_SOURCE)
4567                 channel_select = INTERNAL_REF;
4568         else
4569                 channel_select = CR_CHAN(insn->chanspec);
4570         ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
4571
4572         for (n = 0; n < insn->n; n++) {
4573                 retval = cs5529_do_conversion(dev, &sample);
4574                 if (retval < 0)
4575                         return retval;
4576                 data[n] = sample;
4577         }
4578         return insn->n;
4579 }
4580
4581 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
4582                                 unsigned int reg_select_bits)
4583 {
4584         ni_ao_win_outw(dev, ((value >> 16) & 0xff),
4585                        CAL_ADC_Config_Data_High_Word_67xx);
4586         ni_ao_win_outw(dev, (value & 0xffff),
4587                        CAL_ADC_Config_Data_Low_Word_67xx);
4588         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
4589         cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
4590         if (cs5529_wait_for_idle(dev))
4591                 dev_err(dev->class_dev,
4592                         "timeout or signal in %s\n", __func__);
4593 }
4594
4595 static int init_cs5529(struct comedi_device *dev)
4596 {
4597         unsigned int config_bits =
4598             CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
4599
4600 #if 1
4601         /* do self-calibration */
4602         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN,
4603                             CSCMD_CONFIG_REGISTER);
4604         /* need to force a conversion for calibration to run */
4605         cs5529_do_conversion(dev, NULL);
4606 #else
4607         /* force gain calibration to 1 */
4608         cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
4609         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET,
4610                             CSCMD_CONFIG_REGISTER);
4611         if (cs5529_wait_for_idle(dev))
4612                 dev_err(dev->class_dev,
4613                         "timeout or signal in %s\n", __func__);
4614 #endif
4615         return 0;
4616 }
4617
4618 /*
4619  * Find best multiplier/divider to try and get the PLL running at 80 MHz
4620  * given an arbitrary frequency input clock.
4621  */
4622 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
4623                                          unsigned *freq_divider,
4624                                          unsigned *freq_multiplier,
4625                                          unsigned *actual_period_ns)
4626 {
4627         unsigned div;
4628         unsigned best_div = 1;
4629         unsigned mult;
4630         unsigned best_mult = 1;
4631         static const unsigned pico_per_nano = 1000;
4632
4633         const unsigned reference_picosec = reference_period_ns * pico_per_nano;
4634         /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
4635          * 20 MHz for most timing clocks */
4636         static const unsigned target_picosec = 12500;
4637         static const unsigned fudge_factor_80_to_20Mhz = 4;
4638         int best_period_picosec = 0;
4639
4640         for (div = 1; div <= NI_M_PLL_MAX_DIVISOR; ++div) {
4641                 for (mult = 1; mult <= NI_M_PLL_MAX_MULTIPLIER; ++mult) {
4642                         unsigned new_period_ps =
4643                             (reference_picosec * div) / mult;
4644                         if (abs(new_period_ps - target_picosec) <
4645                             abs(best_period_picosec - target_picosec)) {
4646                                 best_period_picosec = new_period_ps;
4647                                 best_div = div;
4648                                 best_mult = mult;
4649                         }
4650                 }
4651         }
4652         if (best_period_picosec == 0)
4653                 return -EIO;
4654
4655         *freq_divider = best_div;
4656         *freq_multiplier = best_mult;
4657         *actual_period_ns =
4658             (best_period_picosec * fudge_factor_80_to_20Mhz +
4659              (pico_per_nano / 2)) / pico_per_nano;
4660         return 0;
4661 }
4662
4663 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
4664                                            unsigned source, unsigned period_ns)
4665 {
4666         struct ni_private *devpriv = dev->private;
4667         static const unsigned min_period_ns = 50;
4668         static const unsigned max_period_ns = 1000;
4669         static const unsigned timeout = 1000;
4670         unsigned pll_control_bits;
4671         unsigned freq_divider;
4672         unsigned freq_multiplier;
4673         unsigned rtsi;
4674         unsigned i;
4675         int retval;
4676
4677         if (source == NI_MIO_PLL_PXI10_CLOCK)
4678                 period_ns = 100;
4679         /*  these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
4680         if (period_ns < min_period_ns || period_ns > max_period_ns) {
4681                 dev_err(dev->class_dev,
4682                         "%s: you must specify an input clock frequency between %i and %i nanosec for the phased-lock loop\n",
4683                         __func__, min_period_ns, max_period_ns);
4684                 return -EINVAL;
4685         }
4686         devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
4687         ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4688                       RTSI_Trig_Direction_Register);
4689         pll_control_bits = NI_M_PLL_CTRL_ENA | NI_M_PLL_CTRL_VCO_MODE_75_150MHZ;
4690         devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4691                                     NI_M_CLK_FOUT2_TIMEBASE3_PLL;
4692         devpriv->clock_and_fout2 &= ~NI_M_CLK_FOUT2_PLL_SRC_MASK;
4693         switch (source) {
4694         case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
4695                 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_STAR;
4696                 break;
4697         case NI_MIO_PLL_PXI10_CLOCK:
4698                 /* pxi clock is 10MHz */
4699                 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_PXI10;
4700                 break;
4701         default:
4702                 for (rtsi = 0; rtsi <= NI_M_MAX_RTSI_CHAN; ++rtsi) {
4703                         if (source == NI_MIO_PLL_RTSI_CLOCK(rtsi)) {
4704                                 devpriv->clock_and_fout2 |=
4705                                         NI_M_CLK_FOUT2_PLL_SRC_RTSI(rtsi);
4706                                 break;
4707                         }
4708                 }
4709                 if (rtsi > NI_M_MAX_RTSI_CHAN)
4710                         return -EINVAL;
4711                 break;
4712         }
4713         retval = ni_mseries_get_pll_parameters(period_ns,
4714                                                &freq_divider,
4715                                                &freq_multiplier,
4716                                                &devpriv->clock_ns);
4717         if (retval < 0) {
4718                 dev_err(dev->class_dev,
4719                         "bug, failed to find pll parameters\n");
4720                 return retval;
4721         }
4722
4723         ni_writew(dev, devpriv->clock_and_fout2, NI_M_CLK_FOUT2_REG);
4724         pll_control_bits |= NI_M_PLL_CTRL_DIVISOR(freq_divider) |
4725                             NI_M_PLL_CTRL_MULTIPLIER(freq_multiplier);
4726
4727         ni_writew(dev, pll_control_bits, NI_M_PLL_CTRL_REG);
4728         devpriv->clock_source = source;
4729         /* it seems to typically take a few hundred microseconds for PLL to lock */
4730         for (i = 0; i < timeout; ++i) {
4731                 if (ni_readw(dev, NI_M_PLL_STATUS_REG) & NI_M_PLL_STATUS_LOCKED)
4732                         break;
4733                 udelay(1);
4734         }
4735         if (i == timeout) {
4736                 dev_err(dev->class_dev,
4737                         "%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns\n",
4738                         __func__, source, period_ns);
4739                 return -ETIMEDOUT;
4740         }
4741         return 3;
4742 }
4743
4744 static int ni_set_master_clock(struct comedi_device *dev,
4745                                unsigned source, unsigned period_ns)
4746 {
4747         struct ni_private *devpriv = dev->private;
4748
4749         if (source == NI_MIO_INTERNAL_CLOCK) {
4750                 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
4751                 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4752                               RTSI_Trig_Direction_Register);
4753                 devpriv->clock_ns = TIMEBASE_1_NS;
4754                 if (devpriv->is_m_series) {
4755                         devpriv->clock_and_fout2 &=
4756                             ~(NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4757                               NI_M_CLK_FOUT2_TIMEBASE3_PLL);
4758                         ni_writew(dev, devpriv->clock_and_fout2,
4759                                   NI_M_CLK_FOUT2_REG);
4760                         ni_writew(dev, 0, NI_M_PLL_CTRL_REG);
4761                 }
4762                 devpriv->clock_source = source;
4763         } else {
4764                 if (devpriv->is_m_series) {
4765                         return ni_mseries_set_pll_master_clock(dev, source,
4766                                                                period_ns);
4767                 } else {
4768                         if (source == NI_MIO_RTSI_CLOCK) {
4769                                 devpriv->rtsi_trig_direction_reg |=
4770                                     Use_RTSI_Clock_Bit;
4771                                 ni_stc_writew(dev,
4772                                               devpriv->rtsi_trig_direction_reg,
4773                                               RTSI_Trig_Direction_Register);
4774                                 if (period_ns == 0) {
4775                                         dev_err(dev->class_dev,
4776                                                 "we don't handle an unspecified clock period correctly yet, returning error\n");
4777                                         return -EINVAL;
4778                                 }
4779                                 devpriv->clock_ns = period_ns;
4780                                 devpriv->clock_source = source;
4781                         } else {
4782                                 return -EINVAL;
4783                         }
4784                 }
4785         }
4786         return 3;
4787 }
4788
4789 static unsigned num_configurable_rtsi_channels(struct comedi_device *dev)
4790 {
4791         struct ni_private *devpriv = dev->private;
4792
4793         return (devpriv->is_m_series) ? 8 : 7;
4794 }
4795
4796 static int ni_valid_rtsi_output_source(struct comedi_device *dev,
4797                                        unsigned chan, unsigned source)
4798 {
4799         struct ni_private *devpriv = dev->private;
4800
4801         if (chan >= num_configurable_rtsi_channels(dev)) {
4802                 if (chan == old_RTSI_clock_channel) {
4803                         if (source == NI_RTSI_OUTPUT_RTSI_OSC)
4804                                 return 1;
4805
4806                         dev_err(dev->class_dev,
4807                                 "%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards\n",
4808                                 __func__, chan, old_RTSI_clock_channel);
4809                         return 0;
4810                 }
4811                 return 0;
4812         }
4813         switch (source) {
4814         case NI_RTSI_OUTPUT_ADR_START1:
4815         case NI_RTSI_OUTPUT_ADR_START2:
4816         case NI_RTSI_OUTPUT_SCLKG:
4817         case NI_RTSI_OUTPUT_DACUPDN:
4818         case NI_RTSI_OUTPUT_DA_START1:
4819         case NI_RTSI_OUTPUT_G_SRC0:
4820         case NI_RTSI_OUTPUT_G_GATE0:
4821         case NI_RTSI_OUTPUT_RGOUT0:
4822         case NI_RTSI_OUTPUT_RTSI_BRD_0:
4823                 return 1;
4824         case NI_RTSI_OUTPUT_RTSI_OSC:
4825                 return (devpriv->is_m_series) ? 1 : 0;
4826         default:
4827                 return 0;
4828         }
4829 }
4830
4831 static int ni_set_rtsi_routing(struct comedi_device *dev,
4832                                unsigned chan, unsigned source)
4833 {
4834         struct ni_private *devpriv = dev->private;
4835
4836         if (ni_valid_rtsi_output_source(dev, chan, source) == 0)
4837                 return -EINVAL;
4838         if (chan < 4) {
4839                 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan);
4840                 devpriv->rtsi_trig_a_output_reg |=
4841                     RTSI_Trig_Output_Bits(chan, source);
4842                 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
4843                               RTSI_Trig_A_Output_Register);
4844         } else if (chan < 8) {
4845                 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan);
4846                 devpriv->rtsi_trig_b_output_reg |=
4847                     RTSI_Trig_Output_Bits(chan, source);
4848                 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
4849                               RTSI_Trig_B_Output_Register);
4850         }
4851         return 2;
4852 }
4853
4854 static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan)
4855 {
4856         struct ni_private *devpriv = dev->private;
4857
4858         if (chan < 4) {
4859                 return RTSI_Trig_Output_Source(chan,
4860                                                devpriv->rtsi_trig_a_output_reg);
4861         } else if (chan < num_configurable_rtsi_channels(dev)) {
4862                 return RTSI_Trig_Output_Source(chan,
4863                                                devpriv->rtsi_trig_b_output_reg);
4864         } else {
4865                 if (chan == old_RTSI_clock_channel)
4866                         return NI_RTSI_OUTPUT_RTSI_OSC;
4867                 dev_err(dev->class_dev, "bug! should never get here?\n");
4868                 return 0;
4869         }
4870 }
4871
4872 static int ni_rtsi_insn_config(struct comedi_device *dev,
4873                                struct comedi_subdevice *s,
4874                                struct comedi_insn *insn,
4875                                unsigned int *data)
4876 {
4877         struct ni_private *devpriv = dev->private;
4878         unsigned int chan = CR_CHAN(insn->chanspec);
4879
4880         switch (data[0]) {
4881         case INSN_CONFIG_DIO_OUTPUT:
4882                 if (chan < num_configurable_rtsi_channels(dev)) {
4883                         devpriv->rtsi_trig_direction_reg |=
4884                             RTSI_Output_Bit(chan, devpriv->is_m_series);
4885                 } else if (chan == old_RTSI_clock_channel) {
4886                         devpriv->rtsi_trig_direction_reg |=
4887                             Drive_RTSI_Clock_Bit;
4888                 }
4889                 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4890                               RTSI_Trig_Direction_Register);
4891                 break;
4892         case INSN_CONFIG_DIO_INPUT:
4893                 if (chan < num_configurable_rtsi_channels(dev)) {
4894                         devpriv->rtsi_trig_direction_reg &=
4895                             ~RTSI_Output_Bit(chan, devpriv->is_m_series);
4896                 } else if (chan == old_RTSI_clock_channel) {
4897                         devpriv->rtsi_trig_direction_reg &=
4898                             ~Drive_RTSI_Clock_Bit;
4899                 }
4900                 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4901                               RTSI_Trig_Direction_Register);
4902                 break;
4903         case INSN_CONFIG_DIO_QUERY:
4904                 if (chan < num_configurable_rtsi_channels(dev)) {
4905                         data[1] =
4906                             (devpriv->rtsi_trig_direction_reg &
4907                              RTSI_Output_Bit(chan, devpriv->is_m_series))
4908                                 ? INSN_CONFIG_DIO_OUTPUT
4909                                 : INSN_CONFIG_DIO_INPUT;
4910                 } else if (chan == old_RTSI_clock_channel) {
4911                         data[1] =
4912                             (devpriv->rtsi_trig_direction_reg &
4913                              Drive_RTSI_Clock_Bit)
4914                             ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
4915                 }
4916                 return 2;
4917         case INSN_CONFIG_SET_CLOCK_SRC:
4918                 return ni_set_master_clock(dev, data[1], data[2]);
4919         case INSN_CONFIG_GET_CLOCK_SRC:
4920                 data[1] = devpriv->clock_source;
4921                 data[2] = devpriv->clock_ns;
4922                 return 3;
4923         case INSN_CONFIG_SET_ROUTING:
4924                 return ni_set_rtsi_routing(dev, chan, data[1]);
4925         case INSN_CONFIG_GET_ROUTING:
4926                 data[1] = ni_get_rtsi_routing(dev, chan);
4927                 return 2;
4928         default:
4929                 return -EINVAL;
4930         }
4931         return 1;
4932 }
4933
4934 static int ni_rtsi_insn_bits(struct comedi_device *dev,
4935                              struct comedi_subdevice *s,
4936                              struct comedi_insn *insn,
4937                              unsigned int *data)
4938 {
4939         data[1] = 0;
4940
4941         return insn->n;
4942 }
4943
4944 static void ni_rtsi_init(struct comedi_device *dev)
4945 {
4946         struct ni_private *devpriv = dev->private;
4947
4948         /*  Initialises the RTSI bus signal switch to a default state */
4949
4950         /*
4951          * Use 10MHz instead of 20MHz for RTSI clock frequency. Appears
4952          * to have no effect, at least on pxi-6281, which always uses
4953          * 20MHz rtsi clock frequency
4954          */
4955         devpriv->clock_and_fout2 = NI_M_CLK_FOUT2_RTSI_10MHZ;
4956         /*  Set clock mode to internal */
4957         if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0)
4958                 dev_err(dev->class_dev, "ni_set_master_clock failed, bug?\n");
4959         /*  default internal lines routing to RTSI bus lines */
4960         devpriv->rtsi_trig_a_output_reg =
4961             RTSI_Trig_Output_Bits(0,
4962                                   NI_RTSI_OUTPUT_ADR_START1) |
4963             RTSI_Trig_Output_Bits(1,
4964                                   NI_RTSI_OUTPUT_ADR_START2) |
4965             RTSI_Trig_Output_Bits(2,
4966                                   NI_RTSI_OUTPUT_SCLKG) |
4967             RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN);
4968         ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
4969                       RTSI_Trig_A_Output_Register);
4970         devpriv->rtsi_trig_b_output_reg =
4971             RTSI_Trig_Output_Bits(4,
4972                                   NI_RTSI_OUTPUT_DA_START1) |
4973             RTSI_Trig_Output_Bits(5,
4974                                   NI_RTSI_OUTPUT_G_SRC0) |
4975             RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0);
4976         if (devpriv->is_m_series)
4977                 devpriv->rtsi_trig_b_output_reg |=
4978                     RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
4979         ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
4980                       RTSI_Trig_B_Output_Register);
4981
4982 /*
4983 * Sets the source and direction of the 4 on board lines
4984 * ni_stc_writew(dev, 0x0000, RTSI_Board_Register);
4985 */
4986 }
4987
4988 #ifdef PCIDMA
4989 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
4990 {
4991         struct ni_gpct *counter = s->private;
4992         int retval;
4993
4994         retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
4995                                               COMEDI_INPUT);
4996         if (retval) {
4997                 dev_err(dev->class_dev,
4998                         "no dma channel available for use by counter\n");
4999                 return retval;
5000         }
5001         ni_tio_acknowledge(counter);
5002         ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5003
5004         return ni_tio_cmd(dev, s);
5005 }
5006
5007 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
5008 {
5009         struct ni_gpct *counter = s->private;
5010         int retval;
5011
5012         retval = ni_tio_cancel(counter);
5013         ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5014         ni_release_gpct_mite_channel(dev, counter->counter_index);
5015         return retval;
5016 }
5017 #endif
5018
5019 static irqreturn_t ni_E_interrupt(int irq, void *d)
5020 {
5021         struct comedi_device *dev = d;
5022         unsigned short a_status;
5023         unsigned short b_status;
5024         unsigned int ai_mite_status = 0;
5025         unsigned int ao_mite_status = 0;
5026         unsigned long flags;
5027 #ifdef PCIDMA
5028         struct ni_private *devpriv = dev->private;
5029         struct mite_struct *mite = devpriv->mite;
5030 #endif
5031
5032         if (!dev->attached)
5033                 return IRQ_NONE;
5034         smp_mb();               /*  make sure dev->attached is checked before handler does anything else. */
5035
5036         /*  lock to avoid race with comedi_poll */
5037         spin_lock_irqsave(&dev->spinlock, flags);
5038         a_status = ni_stc_readw(dev, AI_Status_1_Register);
5039         b_status = ni_stc_readw(dev, AO_Status_1_Register);
5040 #ifdef PCIDMA
5041         if (mite) {
5042                 struct ni_private *devpriv = dev->private;
5043                 unsigned long flags_too;
5044
5045                 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
5046                 if (devpriv->ai_mite_chan) {
5047                         ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
5048                         if (ai_mite_status & CHSR_LINKC)
5049                                 writel(CHOR_CLRLC,
5050                                        devpriv->mite->mite_io_addr +
5051                                        MITE_CHOR(devpriv->
5052                                                  ai_mite_chan->channel));
5053                 }
5054                 if (devpriv->ao_mite_chan) {
5055                         ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
5056                         if (ao_mite_status & CHSR_LINKC)
5057                                 writel(CHOR_CLRLC,
5058                                        mite->mite_io_addr +
5059                                        MITE_CHOR(devpriv->
5060                                                  ao_mite_chan->channel));
5061                 }
5062                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
5063         }
5064 #endif
5065         ack_a_interrupt(dev, a_status);
5066         ack_b_interrupt(dev, b_status);
5067         if ((a_status & Interrupt_A_St) || (ai_mite_status & CHSR_INT))
5068                 handle_a_interrupt(dev, a_status, ai_mite_status);
5069         if ((b_status & Interrupt_B_St) || (ao_mite_status & CHSR_INT))
5070                 handle_b_interrupt(dev, b_status, ao_mite_status);
5071         handle_gpct_interrupt(dev, 0);
5072         handle_gpct_interrupt(dev, 1);
5073         handle_cdio_interrupt(dev);
5074
5075         spin_unlock_irqrestore(&dev->spinlock, flags);
5076         return IRQ_HANDLED;
5077 }
5078
5079 static int ni_alloc_private(struct comedi_device *dev)
5080 {
5081         struct ni_private *devpriv;
5082
5083         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
5084         if (!devpriv)
5085                 return -ENOMEM;
5086
5087         spin_lock_init(&devpriv->window_lock);
5088         spin_lock_init(&devpriv->soft_reg_copy_lock);
5089         spin_lock_init(&devpriv->mite_channel_lock);
5090
5091         return 0;
5092 }
5093
5094 static int ni_E_init(struct comedi_device *dev,
5095                      unsigned interrupt_pin, unsigned irq_polarity)
5096 {
5097         const struct ni_board_struct *board = dev->board_ptr;
5098         struct ni_private *devpriv = dev->private;
5099         struct comedi_subdevice *s;
5100         int ret;
5101         int i;
5102
5103         if (board->n_aochan > MAX_N_AO_CHAN) {
5104                 dev_err(dev->class_dev, "bug! n_aochan > MAX_N_AO_CHAN\n");
5105                 return -EINVAL;
5106         }
5107
5108         /* initialize clock dividers */
5109         devpriv->clock_and_fout = Slow_Internal_Time_Divide_By_2 |
5110                                   Slow_Internal_Timebase |
5111                                   Clock_To_Board_Divide_By_2 |
5112                                   Clock_To_Board;
5113         if (!devpriv->is_6xxx) {
5114                 /* BEAM is this needed for PCI-6143 ?? */
5115                 devpriv->clock_and_fout |= (AI_Output_Divide_By_2 |
5116                                             AO_Output_Divide_By_2);
5117         }
5118         ni_stc_writew(dev, devpriv->clock_and_fout, Clock_and_FOUT_Register);
5119
5120         ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
5121         if (ret)
5122                 return ret;
5123
5124         /* Analog Input subdevice */
5125         s = &dev->subdevices[NI_AI_SUBDEV];
5126         if (board->n_adchan) {
5127                 s->type         = COMEDI_SUBD_AI;
5128                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_DITHER;
5129                 if (!devpriv->is_611x)
5130                         s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
5131                 if (board->ai_maxdata > 0xffff)
5132                         s->subdev_flags |= SDF_LSAMPL;
5133                 if (devpriv->is_m_series)
5134                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
5135                 s->n_chan       = board->n_adchan;
5136                 s->maxdata      = board->ai_maxdata;
5137                 s->range_table  = ni_range_lkup[board->gainlkup];
5138                 s->insn_read    = ni_ai_insn_read;
5139                 s->insn_config  = ni_ai_insn_config;
5140                 if (dev->irq) {
5141                         dev->read_subdev = s;
5142                         s->subdev_flags |= SDF_CMD_READ;
5143                         s->len_chanlist = 512;
5144                         s->do_cmdtest   = ni_ai_cmdtest;
5145                         s->do_cmd       = ni_ai_cmd;
5146                         s->cancel       = ni_ai_reset;
5147                         s->poll         = ni_ai_poll;
5148                         s->munge        = ni_ai_munge;
5149
5150                         if (devpriv->mite)
5151                                 s->async_dma_dir = DMA_FROM_DEVICE;
5152                 }
5153
5154                 /* reset the analog input configuration */
5155                 ni_ai_reset(dev, s);
5156         } else {
5157                 s->type         = COMEDI_SUBD_UNUSED;
5158         }
5159
5160         /* Analog Output subdevice */
5161         s = &dev->subdevices[NI_AO_SUBDEV];
5162         if (board->n_aochan) {
5163                 s->type         = COMEDI_SUBD_AO;
5164                 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
5165                 if (devpriv->is_m_series)
5166                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
5167                 s->n_chan       = board->n_aochan;
5168                 s->maxdata      = board->ao_maxdata;
5169                 s->range_table  = board->ao_range_table;
5170                 s->insn_config  = ni_ao_insn_config;
5171                 s->insn_write   = ni_ao_insn_write;
5172
5173                 ret = comedi_alloc_subdev_readback(s);
5174                 if (ret)
5175                         return ret;
5176
5177                 /*
5178                  * Along with the IRQ we need either a FIFO or DMA for
5179                  * async command support.
5180                  */
5181                 if (dev->irq && (board->ao_fifo_depth || devpriv->mite)) {
5182                         dev->write_subdev = s;
5183                         s->subdev_flags |= SDF_CMD_WRITE;
5184                         s->len_chanlist = s->n_chan;
5185                         s->do_cmdtest   = ni_ao_cmdtest;
5186                         s->do_cmd       = ni_ao_cmd;
5187                         s->cancel       = ni_ao_reset;
5188                         if (!devpriv->is_m_series)
5189                                 s->munge        = ni_ao_munge;
5190
5191                         if (devpriv->mite)
5192                                 s->async_dma_dir = DMA_TO_DEVICE;
5193                 }
5194
5195                 if (devpriv->is_67xx)
5196                         init_ao_67xx(dev, s);
5197
5198                 /* reset the analog output configuration */
5199                 ni_ao_reset(dev, s);
5200         } else {
5201                 s->type         = COMEDI_SUBD_UNUSED;
5202         }
5203
5204         /* Digital I/O subdevice */
5205         s = &dev->subdevices[NI_DIO_SUBDEV];
5206         s->type         = COMEDI_SUBD_DIO;
5207         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
5208         s->n_chan       = board->has_32dio_chan ? 32 : 8;
5209         s->maxdata      = 1;
5210         s->range_table  = &range_digital;
5211         if (devpriv->is_m_series) {
5212                 s->subdev_flags |= SDF_LSAMPL;
5213                 s->insn_bits    = ni_m_series_dio_insn_bits;
5214                 s->insn_config  = ni_m_series_dio_insn_config;
5215                 if (dev->irq) {
5216                         s->subdev_flags |= SDF_CMD_WRITE /* | SDF_CMD_READ */;
5217                         s->len_chanlist = s->n_chan;
5218                         s->do_cmdtest   = ni_cdio_cmdtest;
5219                         s->do_cmd       = ni_cdio_cmd;
5220                         s->cancel       = ni_cdio_cancel;
5221
5222                         /* M-series boards use DMA */
5223                         s->async_dma_dir = DMA_BIDIRECTIONAL;
5224                 }
5225
5226                 /* reset DIO and set all channels to inputs */
5227                 ni_writel(dev, NI_M_CDO_CMD_RESET |
5228                                NI_M_CDI_CMD_RESET,
5229                           NI_M_CDIO_CMD_REG);
5230                 ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
5231         } else {
5232                 s->insn_bits    = ni_dio_insn_bits;
5233                 s->insn_config  = ni_dio_insn_config;
5234
5235                 /* set all channels to inputs */
5236                 devpriv->dio_control = NISTC_DIO_CTRL_DIR(s->io_bits);
5237                 ni_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
5238         }
5239
5240         /* 8255 device */
5241         s = &dev->subdevices[NI_8255_DIO_SUBDEV];
5242         if (board->has_8255) {
5243                 ret = subdev_8255_init(dev, s, ni_8255_callback, Port_A);
5244                 if (ret)
5245                         return ret;
5246         } else {
5247                 s->type = COMEDI_SUBD_UNUSED;
5248         }
5249
5250         /* formerly general purpose counter/timer device, but no longer used */
5251         s = &dev->subdevices[NI_UNUSED_SUBDEV];
5252         s->type = COMEDI_SUBD_UNUSED;
5253
5254         /* Calibration subdevice */
5255         s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
5256         s->type         = COMEDI_SUBD_CALIB;
5257         s->subdev_flags = SDF_INTERNAL;
5258         s->n_chan       = 1;
5259         s->maxdata      = 0;
5260         if (devpriv->is_m_series) {
5261                 /* internal PWM output used for AI nonlinearity calibration */
5262                 s->insn_config  = ni_m_series_pwm_config;
5263
5264                 ni_writel(dev, 0x0, NI_M_CAL_PWM_REG);
5265         } else if (devpriv->is_6143) {
5266                 /* internal PWM output used for AI nonlinearity calibration */
5267                 s->insn_config  = ni_6143_pwm_config;
5268         } else {
5269                 s->subdev_flags |= SDF_WRITABLE;
5270                 s->insn_read    = ni_calib_insn_read;
5271                 s->insn_write   = ni_calib_insn_write;
5272
5273                 /* setup the caldacs and find the real n_chan and maxdata */
5274                 caldac_setup(dev, s);
5275         }
5276
5277         /* EEPROM subdevice */
5278         s = &dev->subdevices[NI_EEPROM_SUBDEV];
5279         s->type         = COMEDI_SUBD_MEMORY;
5280         s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
5281         s->maxdata      = 0xff;
5282         if (devpriv->is_m_series) {
5283                 s->n_chan       = M_SERIES_EEPROM_SIZE;
5284                 s->insn_read    = ni_m_series_eeprom_insn_read;
5285         } else {
5286                 s->n_chan       = 512;
5287                 s->insn_read    = ni_eeprom_insn_read;
5288         }
5289
5290         /* Digital I/O (PFI) subdevice */
5291         s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
5292         s->type         = COMEDI_SUBD_DIO;
5293         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5294         s->maxdata      = 1;
5295         if (devpriv->is_m_series) {
5296                 s->n_chan       = 16;
5297                 s->insn_bits    = ni_pfi_insn_bits;
5298
5299                 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
5300                 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
5301                         ni_writew(dev, devpriv->pfi_output_select_reg[i],
5302                                   NI_M_PFI_OUT_SEL_REG(i));
5303                 }
5304         } else {
5305                 s->n_chan       = 10;
5306         }
5307         s->insn_config  = ni_pfi_insn_config;
5308
5309         ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
5310
5311         /* cs5529 calibration adc */
5312         s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
5313         if (devpriv->is_67xx) {
5314                 s->type = COMEDI_SUBD_AI;
5315                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
5316                 /*  one channel for each analog output channel */
5317                 s->n_chan = board->n_aochan;
5318                 s->maxdata = (1 << 16) - 1;
5319                 s->range_table = &range_unknown;        /* XXX */
5320                 s->insn_read = cs5529_ai_insn_read;
5321                 s->insn_config = NULL;
5322                 init_cs5529(dev);
5323         } else {
5324                 s->type = COMEDI_SUBD_UNUSED;
5325         }
5326
5327         /* Serial */
5328         s = &dev->subdevices[NI_SERIAL_SUBDEV];
5329         s->type = COMEDI_SUBD_SERIAL;
5330         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5331         s->n_chan = 1;
5332         s->maxdata = 0xff;
5333         s->insn_config = ni_serial_insn_config;
5334         devpriv->serial_interval_ns = 0;
5335         devpriv->serial_hw_mode = 0;
5336
5337         /* RTSI */
5338         s = &dev->subdevices[NI_RTSI_SUBDEV];
5339         s->type = COMEDI_SUBD_DIO;
5340         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5341         s->n_chan = 8;
5342         s->maxdata = 1;
5343         s->insn_bits = ni_rtsi_insn_bits;
5344         s->insn_config = ni_rtsi_insn_config;
5345         ni_rtsi_init(dev);
5346
5347         /* allocate and initialize the gpct counter device */
5348         devpriv->counter_dev = ni_gpct_device_construct(dev,
5349                                         ni_gpct_write_register,
5350                                         ni_gpct_read_register,
5351                                         (devpriv->is_m_series)
5352                                                 ? ni_gpct_variant_m_series
5353                                                 : ni_gpct_variant_e_series,
5354                                         NUM_GPCT);
5355         if (!devpriv->counter_dev)
5356                 return -ENOMEM;
5357
5358         /* Counter (gpct) subdevices */
5359         for (i = 0; i < NUM_GPCT; ++i) {
5360                 struct ni_gpct *gpct = &devpriv->counter_dev->counters[i];
5361
5362                 /* setup and initialize the counter */
5363                 gpct->chip_index = 0;
5364                 gpct->counter_index = i;
5365                 ni_tio_init_counter(gpct);
5366
5367                 s = &dev->subdevices[NI_GPCT_SUBDEV(i)];
5368                 s->type         = COMEDI_SUBD_COUNTER;
5369                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL;
5370                 s->n_chan       = 3;
5371                 s->maxdata      = (devpriv->is_m_series) ? 0xffffffff
5372                                                          : 0x00ffffff;
5373                 s->insn_read    = ni_tio_insn_read;
5374                 s->insn_write   = ni_tio_insn_read;
5375                 s->insn_config  = ni_tio_insn_config;
5376 #ifdef PCIDMA
5377                 if (dev->irq && devpriv->mite) {
5378                         s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */;
5379                         s->len_chanlist = 1;
5380                         s->do_cmdtest   = ni_tio_cmdtest;
5381                         s->do_cmd       = ni_gpct_cmd;
5382                         s->cancel       = ni_gpct_cancel;
5383
5384                         s->async_dma_dir = DMA_BIDIRECTIONAL;
5385                 }
5386 #endif
5387                 s->private      = gpct;
5388         }
5389
5390         /* Frequency output subdevice */
5391         s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
5392         s->type         = COMEDI_SUBD_COUNTER;
5393         s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
5394         s->n_chan       = 1;
5395         s->maxdata      = 0xf;
5396         s->insn_read    = ni_freq_out_insn_read;
5397         s->insn_write   = ni_freq_out_insn_write;
5398         s->insn_config  = ni_freq_out_insn_config;
5399
5400         if (dev->irq) {
5401                 ni_stc_writew(dev,
5402                               (irq_polarity ? Interrupt_Output_Polarity : 0) |
5403                               (Interrupt_Output_On_3_Pins & 0) |
5404                               Interrupt_A_Enable | Interrupt_B_Enable |
5405                               Interrupt_A_Output_Select(interrupt_pin) |
5406                               Interrupt_B_Output_Select(interrupt_pin),
5407                               Interrupt_Control_Register);
5408         }
5409
5410         /* DMA setup */
5411         ni_writeb(dev, devpriv->ai_ao_select_reg, AI_AO_Select);
5412         ni_writeb(dev, devpriv->g0_g1_select_reg, G0_G1_Select);
5413
5414         if (devpriv->is_6xxx) {
5415                 ni_writeb(dev, 0, Magic_611x);
5416         } else if (devpriv->is_m_series) {
5417                 int channel;
5418
5419                 for (channel = 0; channel < board->n_aochan; ++channel) {
5420                         ni_writeb(dev, 0xf,
5421                                   NI_M_AO_WAVEFORM_ORDER_REG(channel));
5422                         ni_writeb(dev, 0x0,
5423                                   NI_M_AO_REF_ATTENUATION_REG(channel));
5424                 }
5425                 ni_writeb(dev, 0x0, NI_M_AO_CALIB_REG);
5426         }
5427
5428         return 0;
5429 }
5430
5431 static void mio_common_detach(struct comedi_device *dev)
5432 {
5433         struct ni_private *devpriv = dev->private;
5434
5435         if (devpriv) {
5436                 if (devpriv->counter_dev)
5437                         ni_gpct_device_destroy(devpriv->counter_dev);
5438         }
5439 }