drivers/staging/comedi/drivers/ni_mio_common.c

   1 /*
   2     comedi/drivers/ni_mio_common.c
   3     Hardware driver for DAQ-STC based boards
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
   7     Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18 */
  19
  20 /*
  21         This file is meant to be included by another file, e.g.,
  22         ni_atmio.c or ni_pcimio.c.
  23
  24         Interrupt support originally added by Truxton Fulton
  25         <trux@truxton.com>
  26
  27         References (from ftp://ftp.natinst.com/support/manuals):
  28
  29            340747b.pdf  AT-MIO E series Register Level Programmer Manual
  30            341079b.pdf  PCI E Series RLPM
  31            340934b.pdf  DAQ-STC reference manual
  32         67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/)
  33         release_ni611x.pdf
  34         release_ni67xx.pdf
  35         Other possibly relevant info:
  36
  37            320517c.pdf  User manual (obsolete)
  38            320517f.pdf  User manual (new)
  39            320889a.pdf  delete
  40            320906c.pdf  maximum signal ratings
  41            321066a.pdf  about 16x
  42            321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  43            321808a.pdf  about at-mio-16e-10 rev P
  44            321837a.pdf  discontinuation of at-mio-16de-10 rev d
  45            321838a.pdf  about at-mio-16de-10 rev N
  46
  47         ISSUES:
  48
  49          - the interrupt routine needs to be cleaned up
  50
  51         2006-02-07: S-Series PCI-6143: Support has been added but is not
  52                 fully tested as yet. Terry Barnaby, BEAM Ltd.
  53 */
  54
  55 #include <linux/interrupt.h>
  56 #include <linux/sched.h>
  57 #include <linux/delay.h>
  58 #include "8255.h"
  59 #include "mite.h"
  60
  61 /* A timeout count */
  62 #define NI_TIMEOUT 1000
  63
  64 /* Note: this table must match the ai_gain_* definitions */
  65 static const short ni_gainlkup[][16] = {
  66         [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
  67                         0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  68         [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
  69         [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
  70                         0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  71         [ai_gain_4] = {0, 1, 4, 7},
  72         [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
  73                           0x003, 0x004, 0x005, 0x006},
  74         [ai_gain_622x] = {0, 1, 4, 5},
  75         [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
  76         [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
  77 };
  78
  79 static const struct comedi_lrange range_ni_E_ai = {
  80         16, {
  81                 BIP_RANGE(10),
  82                 BIP_RANGE(5),
  83                 BIP_RANGE(2.5),
  84                 BIP_RANGE(1),
  85                 BIP_RANGE(0.5),
  86                 BIP_RANGE(0.25),
  87                 BIP_RANGE(0.1),
  88                 BIP_RANGE(0.05),
  89                 UNI_RANGE(20),
  90                 UNI_RANGE(10),
  91                 UNI_RANGE(5),
  92                 UNI_RANGE(2),
  93                 UNI_RANGE(1),
  94                 UNI_RANGE(0.5),
  95                 UNI_RANGE(0.2),
  96                 UNI_RANGE(0.1)
  97         }
  98 };
  99
 100 static const struct comedi_lrange range_ni_E_ai_limited = {
 101         8, {
 102                 BIP_RANGE(10),
 103                 BIP_RANGE(5),
 104                 BIP_RANGE(1),
 105                 BIP_RANGE(0.1),
 106                 UNI_RANGE(10),
 107                 UNI_RANGE(5),
 108                 UNI_RANGE(1),
 109                 UNI_RANGE(0.1)
 110         }
 111 };
 112
 113 static const struct comedi_lrange range_ni_E_ai_limited14 = {
 114         14, {
 115                 BIP_RANGE(10),
 116                 BIP_RANGE(5),
 117                 BIP_RANGE(2),
 118                 BIP_RANGE(1),
 119                 BIP_RANGE(0.5),
 120                 BIP_RANGE(0.2),
 121                 BIP_RANGE(0.1),
 122                 UNI_RANGE(10),
 123                 UNI_RANGE(5),
 124                 UNI_RANGE(2),
 125                 UNI_RANGE(1),
 126                 UNI_RANGE(0.5),
 127                 UNI_RANGE(0.2),
 128                 UNI_RANGE(0.1)
 129         }
 130 };
 131
 132 static const struct comedi_lrange range_ni_E_ai_bipolar4 = {
 133         4, {
 134                 BIP_RANGE(10),
 135                 BIP_RANGE(5),
 136                 BIP_RANGE(0.5),
 137                 BIP_RANGE(0.05)
 138         }
 139 };
 140
 141 static const struct comedi_lrange range_ni_E_ai_611x = {
 142         8, {
 143                 BIP_RANGE(50),
 144                 BIP_RANGE(20),
 145                 BIP_RANGE(10),
 146                 BIP_RANGE(5),
 147                 BIP_RANGE(2),
 148                 BIP_RANGE(1),
 149                 BIP_RANGE(0.5),
 150                 BIP_RANGE(0.2)
 151         }
 152 };
 153
 154 static const struct comedi_lrange range_ni_M_ai_622x = {
 155         4, {
 156                 BIP_RANGE(10),
 157                 BIP_RANGE(5),
 158                 BIP_RANGE(1),
 159                 BIP_RANGE(0.2)
 160         }
 161 };
 162
 163 static const struct comedi_lrange range_ni_M_ai_628x = {
 164         7, {
 165                 BIP_RANGE(10),
 166                 BIP_RANGE(5),
 167                 BIP_RANGE(2),
 168                 BIP_RANGE(1),
 169                 BIP_RANGE(0.5),
 170                 BIP_RANGE(0.2),
 171                 BIP_RANGE(0.1)
 172         }
 173 };
 174
 175 static const struct comedi_lrange range_ni_E_ao_ext = {
 176         4, {
 177                 BIP_RANGE(10),
 178                 UNI_RANGE(10),
 179                 RANGE_ext(-1, 1),
 180                 RANGE_ext(0, 1)
 181         }
 182 };
 183
 184 static const struct comedi_lrange *const ni_range_lkup[] = {
 185         [ai_gain_16] = &range_ni_E_ai,
 186         [ai_gain_8] = &range_ni_E_ai_limited,
 187         [ai_gain_14] = &range_ni_E_ai_limited14,
 188         [ai_gain_4] = &range_ni_E_ai_bipolar4,
 189         [ai_gain_611x] = &range_ni_E_ai_611x,
 190         [ai_gain_622x] = &range_ni_M_ai_622x,
 191         [ai_gain_628x] = &range_ni_M_ai_628x,
 192         [ai_gain_6143] = &range_bipolar5
 193 };
 194
 195 enum aimodes {
 196         AIMODE_NONE = 0,
 197         AIMODE_HALF_FULL = 1,
 198         AIMODE_SCAN = 2,
 199         AIMODE_SAMPLE = 3,
 200 };
 201
 202 enum ni_common_subdevices {
 203         NI_AI_SUBDEV,
 204         NI_AO_SUBDEV,
 205         NI_DIO_SUBDEV,
 206         NI_8255_DIO_SUBDEV,
 207         NI_UNUSED_SUBDEV,
 208         NI_CALIBRATION_SUBDEV,
 209         NI_EEPROM_SUBDEV,
 210         NI_PFI_DIO_SUBDEV,
 211         NI_CS5529_CALIBRATION_SUBDEV,
 212         NI_SERIAL_SUBDEV,
 213         NI_RTSI_SUBDEV,
 214         NI_GPCT0_SUBDEV,
 215         NI_GPCT1_SUBDEV,
 216         NI_FREQ_OUT_SUBDEV,
 217         NI_NUM_SUBDEVICES
 218 };
 219 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
 220 {
 221         switch (counter_index) {
 222         case 0:
 223                 return NI_GPCT0_SUBDEV;
 224         case 1:
 225                 return NI_GPCT1_SUBDEV;
 226         default:
 227                 break;
 228         }
 229         BUG();
 230         return NI_GPCT0_SUBDEV;
 231 }
 232
 233 enum timebase_nanoseconds {
 234         TIMEBASE_1_NS = 50,
 235         TIMEBASE_2_NS = 10000
 236 };
 237
 238 #define SERIAL_DISABLED         0
 239 #define SERIAL_600NS            600
 240 #define SERIAL_1_2US            1200
 241 #define SERIAL_10US                     10000
 242
 243 static const int num_adc_stages_611x = 3;
 244
 245 static void ni_writel(struct comedi_device *dev, uint32_t data, int reg)
 246 {
 247         if (dev->mmio)
 248                 writel(data, dev->mmio + reg);
 249
 250         outl(data, dev->iobase + reg);
 251 }
 252
 253 static void ni_writew(struct comedi_device *dev, uint16_t data, int reg)
 254 {
 255         if (dev->mmio)
 256                 writew(data, dev->mmio + reg);
 257
 258         outw(data, dev->iobase + reg);
 259 }
 260
 261 static void ni_writeb(struct comedi_device *dev, uint8_t data, int reg)
 262 {
 263         if (dev->mmio)
 264                 writeb(data, dev->mmio + reg);
 265
 266         outb(data, dev->iobase + reg);
 267 }
 268
 269 static uint32_t ni_readl(struct comedi_device *dev, int reg)
 270 {
 271         if (dev->mmio)
 272                 return readl(dev->mmio + reg);
 273
 274         return inl(dev->iobase + reg);
 275 }
 276
 277 static uint16_t ni_readw(struct comedi_device *dev, int reg)
 278 {
 279         if (dev->mmio)
 280                 return readw(dev->mmio + reg);
 281
 282         return inw(dev->iobase + reg);
 283 }
 284
 285 static uint8_t ni_readb(struct comedi_device *dev, int reg)
 286 {
 287         if (dev->mmio)
 288                 return readb(dev->mmio + reg);
 289
 290         return inb(dev->iobase + reg);
 291 }
 292
 293 /*
 294  * We automatically take advantage of STC registers that can be
 295  * read/written directly in the I/O space of the board.
 296  *
 297  * The AT-MIO and DAQCard devices map the low 8 STC registers to
 298  * iobase+reg*2.
 299  *
 300  * Most PCIMIO devices also map the low 8 STC registers but the
 301  * 611x devices map the read registers to iobase+(addr-1)*2.
 302  * For now non-windowed STC access is disabled if a PCIMIO device
 303  * is detected (devpriv->mite has been initialized).
 304  *
 305  * The M series devices do not used windowed registers for the
 306  * STC registers. The functions below handle the mapping of the
 307  * windowed STC registers to the m series register offsets.
 308  */
 309
 310 struct mio_regmap {
 311         unsigned int mio_reg;
 312         int size;
 313 };
 314
 315 static const struct mio_regmap m_series_stc_write_regmap[] = {
 316         [NISTC_INTA_ACK_REG]            = { 0x104, 2 },
 317         [NISTC_INTB_ACK_REG]            = { 0x106, 2 },
 318         [NISTC_AI_CMD2_REG]             = { 0x108, 2 },
 319         [NISTC_AO_CMD2_REG]             = { 0x10a, 2 },
 320         [NISTC_G0_CMD_REG]              = { 0x10c, 2 },
 321         [NISTC_G1_CMD_REG]              = { 0x10e, 2 },
 322         [NISTC_AI_CMD1_REG]             = { 0x110, 2 },
 323         [NISTC_AO_CMD1_REG]             = { 0x112, 2 },
 324         /*
 325          * NISTC_DIO_OUT_REG maps to:
 326          * { NI_M_DIO_REG, 4 } and { NI_M_SCXI_SER_DO_REG, 1 }
 327          */
 328         [NISTC_DIO_OUT_REG]             = { 0, 0 }, /* DOES NOT MAP CLEANLY */
 329         [NISTC_DIO_CTRL_REG]            = { 0, 0 }, /* DOES NOT MAP CLEANLY */
 330         [NISTC_AI_MODE1_REG]            = { 0x118, 2 },
 331         [NISTC_AI_MODE2_REG]            = { 0x11a, 2 },
 332         [NISTC_AI_SI_LOADA_REG]         = { 0x11c, 4 },
 333         [NISTC_AI_SI_LOADB_REG]         = { 0x120, 4 },
 334         [NISTC_AI_SC_LOADA_REG]         = { 0x124, 4 },
 335         [NISTC_AI_SC_LOADB_REG]         = { 0x128, 4 },
 336         [NISTC_AI_SI2_LOADA_REG]        = { 0x12c, 4 },
 337         [NISTC_AI_SI2_LOADB_REG]        = { 0x130, 4 },
 338         [NISTC_G0_MODE_REG]             = { 0x134, 2 },
 339         [NISTC_G1_MODE_REG]             = { 0x136, 2 },
 340         [NISTC_G0_LOADA_REG]            = { 0x138, 4 },
 341         [NISTC_G0_LOADB_REG]            = { 0x13c, 4 },
 342         [NISTC_G1_LOADA_REG]            = { 0x140, 4 },
 343         [NISTC_G1_LOADB_REG]            = { 0x144, 4 },
 344         [NISTC_G0_INPUT_SEL_REG]        = { 0x148, 2 },
 345         [NISTC_G1_INPUT_SEL_REG]        = { 0x14a, 2 },
 346         [NISTC_AO_MODE1_REG]            = { 0x14c, 2 },
 347         [NISTC_AO_MODE2_REG]            = { 0x14e, 2 },
 348         [NISTC_AO_UI_LOADA_REG]         = { 0x150, 4 },
 349         [NISTC_AO_UI_LOADB_REG]         = { 0x154, 4 },
 350         [NISTC_AO_BC_LOADA_REG]         = { 0x158, 4 },
 351         [NISTC_AO_BC_LOADB_REG]         = { 0x15c, 4 },
 352         [NISTC_AO_UC_LOADA_REG]         = { 0x160, 4 },
 353         [NISTC_AO_UC_LOADB_REG]         = { 0x164, 4 },
 354         [NISTC_CLK_FOUT_REG]            = { 0x170, 2 },
 355         [NISTC_IO_BIDIR_PIN_REG]        = { 0x172, 2 },
 356         [NISTC_RTSI_TRIG_DIR_REG]       = { 0x174, 2 },
 357         [NISTC_INT_CTRL_REG]            = { 0x176, 2 },
 358         [NISTC_AI_OUT_CTRL_REG]         = { 0x178, 2 },
 359         [NISTC_ATRIG_ETC_REG]           = { 0x17a, 2 },
 360         [NISTC_AI_START_STOP_REG]       = { 0x17c, 2 },
 361         [NISTC_AI_TRIG_SEL_REG]         = { 0x17e, 2 },
 362         [AI_DIV_Load_A_Register]        = { 0x180, 4 },
 363         [AO_Start_Select_Register]      = { 0x184, 2 },
 364         [AO_Trigger_Select_Register]    = { 0x186, 2 },
 365         [G_Autoincrement_Register(0)]   = { 0x188, 2 },
 366         [G_Autoincrement_Register(1)]   = { 0x18a, 2 },
 367         [AO_Mode_3_Register]            = { 0x18c, 2 },
 368         [Joint_Reset_Register]          = { 0x190, 2 },
 369         [Interrupt_A_Enable_Register]   = { 0x192, 2 },
 370         [Second_IRQ_A_Enable_Register]  = { 0, 0 }, /* E-Series only */
 371         [Interrupt_B_Enable_Register]   = { 0x196, 2 },
 372         [Second_IRQ_B_Enable_Register]  = { 0, 0 }, /* E-Series only */
 373         [AI_Personal_Register]          = { 0x19a, 2 },
 374         [AO_Personal_Register]          = { 0x19c, 2 },
 375         [RTSI_Trig_A_Output_Register]   = { 0x19e, 2 },
 376         [RTSI_Trig_B_Output_Register]   = { 0x1a0, 2 },
 377         [RTSI_Board_Register]           = { 0, 0 }, /* Unknown */
 378         [Configuration_Memory_Clear]    = { 0x1a4, 2 },
 379         [ADC_FIFO_Clear]                = { 0x1a6, 2 },
 380         [DAC_FIFO_Clear]                = { 0x1a8, 2 },
 381         [AO_Output_Control_Register]    = { 0x1ac, 2 },
 382         [AI_Mode_3_Register]            = { 0x1ae, 2 },
 383 };
 384
 385 static void m_series_stc_write(struct comedi_device *dev,
 386                                unsigned int data, unsigned int reg)
 387 {
 388         const struct mio_regmap *regmap;
 389
 390         if (reg < ARRAY_SIZE(m_series_stc_write_regmap)) {
 391                 regmap = &m_series_stc_write_regmap[reg];
 392         } else {
 393                 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
 394                          __func__, reg);
 395                 return;
 396         }
 397
 398         switch (regmap->size) {
 399         case 4:
 400                 ni_writel(dev, data, regmap->mio_reg);
 401                 break;
 402         case 2:
 403                 ni_writew(dev, data, regmap->mio_reg);
 404                 break;
 405         default:
 406                 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
 407                          __func__, reg);
 408                 break;
 409         }
 410 }
 411
 412 static const struct mio_regmap m_series_stc_read_regmap[] = {
 413         [AI_Status_1_Register]          = { 0x104, 2 },
 414         [AO_Status_1_Register]          = { 0x106, 2 },
 415         [G_Status_Register]             = { 0x108, 2 },
 416         [AI_Status_2_Register]          = { 0, 0 }, /* Unknown */
 417         [AO_Status_2_Register]          = { 0x10c, 2 },
 418         [DIO_Parallel_Input_Register]   = { 0, 0 }, /* Unknown */
 419         [G_HW_Save_Register(0)]         = { 0x110, 4 },
 420         [G_HW_Save_Register(1)]         = { 0x114, 4 },
 421         [G_Save_Register(0)]            = { 0x118, 4 },
 422         [G_Save_Register(1)]            = { 0x11c, 4 },
 423         [AO_UI_Save_Registers]          = { 0x120, 4 },
 424         [AO_BC_Save_Registers]          = { 0x124, 4 },
 425         [AO_UC_Save_Registers]          = { 0x128, 4 },
 426         [Joint_Status_1_Register]       = { 0x136, 2 },
 427         [DIO_Serial_Input_Register]     = { 0x009, 1 },
 428         [Joint_Status_2_Register]       = { 0x13a, 2 },
 429         [AI_SI_Save_Registers]          = { 0x180, 4 },
 430         [AI_SC_Save_Registers]          = { 0x184, 4 },
 431 };
 432
 433 static unsigned int m_series_stc_read(struct comedi_device *dev,
 434                                       unsigned int reg)
 435 {
 436         const struct mio_regmap *regmap;
 437
 438         if (reg < ARRAY_SIZE(m_series_stc_read_regmap)) {
 439                 regmap = &m_series_stc_read_regmap[reg];
 440         } else {
 441                 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
 442                          __func__, reg);
 443                 return 0;
 444         }
 445
 446         switch (regmap->size) {
 447         case 4:
 448                 return ni_readl(dev, regmap->mio_reg);
 449         case 2:
 450                 return ni_readw(dev, regmap->mio_reg);
 451         case 1:
 452                 return ni_readb(dev, regmap->mio_reg);
 453         default:
 454                 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
 455                          __func__, reg);
 456                 return 0;
 457         }
 458 }
 459
 460 static void ni_stc_writew(struct comedi_device *dev, uint16_t data, int reg)
 461 {
 462         struct ni_private *devpriv = dev->private;
 463         unsigned long flags;
 464
 465         if (devpriv->is_m_series) {
 466                 m_series_stc_write(dev, data, reg);
 467         } else {
 468                 spin_lock_irqsave(&devpriv->window_lock, flags);
 469                 if (!devpriv->mite && reg < 8) {
 470                         ni_writew(dev, data, reg * 2);
 471                 } else {
 472                         ni_writew(dev, reg, Window_Address);
 473                         ni_writew(dev, data, Window_Data);
 474                 }
 475                 spin_unlock_irqrestore(&devpriv->window_lock, flags);
 476         }
 477 }
 478
 479 static void ni_stc_writel(struct comedi_device *dev, uint32_t data, int reg)
 480 {
 481         struct ni_private *devpriv = dev->private;
 482
 483         if (devpriv->is_m_series) {
 484                 m_series_stc_write(dev, data, reg);
 485         } else {
 486                 ni_stc_writew(dev, data >> 16, reg);
 487                 ni_stc_writew(dev, data & 0xffff, reg + 1);
 488         }
 489 }
 490
 491 static uint16_t ni_stc_readw(struct comedi_device *dev, int reg)
 492 {
 493         struct ni_private *devpriv = dev->private;
 494         unsigned long flags;
 495         uint16_t val;
 496
 497         if (devpriv->is_m_series) {
 498                 val = m_series_stc_read(dev, reg);
 499         } else {
 500                 spin_lock_irqsave(&devpriv->window_lock, flags);
 501                 if (!devpriv->mite && reg < 8) {
 502                         val = ni_readw(dev, reg * 2);
 503                 } else {
 504                         ni_writew(dev, reg, Window_Address);
 505                         val = ni_readw(dev, Window_Data);
 506                 }
 507                 spin_unlock_irqrestore(&devpriv->window_lock, flags);
 508         }
 509         return val;
 510 }
 511
 512 static uint32_t ni_stc_readl(struct comedi_device *dev, int reg)
 513 {
 514         struct ni_private *devpriv = dev->private;
 515         uint32_t val;
 516
 517         if (devpriv->is_m_series) {
 518                 val = m_series_stc_read(dev, reg);
 519         } else {
 520                 val = ni_stc_readw(dev, reg) << 16;
 521                 val |= ni_stc_readw(dev, reg + 1);
 522         }
 523         return val;
 524 }
 525
 526 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
 527                                    unsigned bit_mask, unsigned bit_values)
 528 {
 529         struct ni_private *devpriv = dev->private;
 530         unsigned long flags;
 531
 532         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 533         switch (reg) {
 534         case Interrupt_A_Enable_Register:
 535                 devpriv->int_a_enable_reg &= ~bit_mask;
 536                 devpriv->int_a_enable_reg |= bit_values & bit_mask;
 537                 ni_stc_writew(dev, devpriv->int_a_enable_reg, reg);
 538                 break;
 539         case Interrupt_B_Enable_Register:
 540                 devpriv->int_b_enable_reg &= ~bit_mask;
 541                 devpriv->int_b_enable_reg |= bit_values & bit_mask;
 542                 ni_stc_writew(dev, devpriv->int_b_enable_reg, reg);
 543                 break;
 544         case NISTC_IO_BIDIR_PIN_REG:
 545                 devpriv->io_bidirection_pin_reg &= ~bit_mask;
 546                 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
 547                 ni_stc_writew(dev, devpriv->io_bidirection_pin_reg, reg);
 548                 break;
 549         case AI_AO_Select:
 550                 devpriv->ai_ao_select_reg &= ~bit_mask;
 551                 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
 552                 ni_writeb(dev, devpriv->ai_ao_select_reg, reg);
 553                 break;
 554         case G0_G1_Select:
 555                 devpriv->g0_g1_select_reg &= ~bit_mask;
 556                 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
 557                 ni_writeb(dev, devpriv->g0_g1_select_reg, reg);
 558                 break;
 559         default:
 560                 dev_err(dev->class_dev, "called with invalid register %d\n",
 561                         reg);
 562                 break;
 563         }
 564         mmiowb();
 565         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 566 }
 567
 568 #ifdef PCIDMA
 569 /* DMA channel setup */
 570
 571 /* negative channel means no channel */
 572 static inline void ni_set_ai_dma_channel(struct comedi_device *dev, int channel)
 573 {
 574         unsigned bitfield;
 575
 576         if (channel >= 0)
 577                 bitfield =
 578                     (ni_stc_dma_channel_select_bitfield(channel) <<
 579                      AI_DMA_Select_Shift) & AI_DMA_Select_Mask;
 580         else
 581                 bitfield = 0;
 582         ni_set_bitfield(dev, AI_AO_Select, AI_DMA_Select_Mask, bitfield);
 583 }
 584
 585 /* negative channel means no channel */
 586 static inline void ni_set_ao_dma_channel(struct comedi_device *dev, int channel)
 587 {
 588         unsigned bitfield;
 589
 590         if (channel >= 0)
 591                 bitfield =
 592                     (ni_stc_dma_channel_select_bitfield(channel) <<
 593                      AO_DMA_Select_Shift) & AO_DMA_Select_Mask;
 594         else
 595                 bitfield = 0;
 596         ni_set_bitfield(dev, AI_AO_Select, AO_DMA_Select_Mask, bitfield);
 597 }
 598
 599 /* negative mite_channel means no channel */
 600 static inline void ni_set_gpct_dma_channel(struct comedi_device *dev,
 601                                            unsigned gpct_index,
 602                                            int mite_channel)
 603 {
 604         unsigned bitfield;
 605
 606         if (mite_channel >= 0)
 607                 bitfield = GPCT_DMA_Select_Bits(gpct_index, mite_channel);
 608         else
 609                 bitfield = 0;
 610         ni_set_bitfield(dev, G0_G1_Select, GPCT_DMA_Select_Mask(gpct_index),
 611                         bitfield);
 612 }
 613
 614 /* negative mite_channel means no channel */
 615 static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
 616                                           int mite_channel)
 617 {
 618         struct ni_private *devpriv = dev->private;
 619         unsigned long flags;
 620         unsigned bits;
 621
 622         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 623         devpriv->cdio_dma_select_reg &= ~NI_M_CDIO_DMA_SEL_CDO_MASK;
 624         if (mite_channel >= 0) {
 625                 /*
 626                  * XXX just guessing ni_stc_dma_channel_select_bitfield()
 627                  * returns the right bits, under the assumption the cdio dma
 628                  * selection works just like ai/ao/gpct.
 629                  * Definitely works for dma channels 0 and 1.
 630                  */
 631                 bits = ni_stc_dma_channel_select_bitfield(mite_channel);
 632                 devpriv->cdio_dma_select_reg |= NI_M_CDIO_DMA_SEL_CDO(bits);
 633         }
 634         ni_writeb(dev, devpriv->cdio_dma_select_reg, NI_M_CDIO_DMA_SEL_REG);
 635         mmiowb();
 636         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 637 }
 638
 639 static int ni_request_ai_mite_channel(struct comedi_device *dev)
 640 {
 641         struct ni_private *devpriv = dev->private;
 642         unsigned long flags;
 643
 644         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 645         BUG_ON(devpriv->ai_mite_chan);
 646         devpriv->ai_mite_chan =
 647             mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
 648         if (!devpriv->ai_mite_chan) {
 649                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 650                 dev_err(dev->class_dev,
 651                         "failed to reserve mite dma channel for analog input\n");
 652                 return -EBUSY;
 653         }
 654         devpriv->ai_mite_chan->dir = COMEDI_INPUT;
 655         ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
 656         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 657         return 0;
 658 }
 659
 660 static int ni_request_ao_mite_channel(struct comedi_device *dev)
 661 {
 662         struct ni_private *devpriv = dev->private;
 663         unsigned long flags;
 664
 665         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 666         BUG_ON(devpriv->ao_mite_chan);
 667         devpriv->ao_mite_chan =
 668             mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
 669         if (!devpriv->ao_mite_chan) {
 670                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 671                 dev_err(dev->class_dev,
 672                         "failed to reserve mite dma channel for analog outut\n");
 673                 return -EBUSY;
 674         }
 675         devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
 676         ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
 677         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 678         return 0;
 679 }
 680
 681 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
 682                                         unsigned gpct_index,
 683                                         enum comedi_io_direction direction)
 684 {
 685         struct ni_private *devpriv = dev->private;
 686         unsigned long flags;
 687         struct mite_channel *mite_chan;
 688
 689         BUG_ON(gpct_index >= NUM_GPCT);
 690         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 691         BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
 692         mite_chan =
 693             mite_request_channel(devpriv->mite,
 694                                  devpriv->gpct_mite_ring[gpct_index]);
 695         if (!mite_chan) {
 696                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 697                 dev_err(dev->class_dev,
 698                         "failed to reserve mite dma channel for counter\n");
 699                 return -EBUSY;
 700         }
 701         mite_chan->dir = direction;
 702         ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
 703                                 mite_chan);
 704         ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
 705         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 706         return 0;
 707 }
 708
 709 #endif /*  PCIDMA */
 710
 711 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
 712 {
 713 #ifdef PCIDMA
 714         struct ni_private *devpriv = dev->private;
 715         unsigned long flags;
 716
 717         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 718         BUG_ON(devpriv->cdo_mite_chan);
 719         devpriv->cdo_mite_chan =
 720             mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
 721         if (!devpriv->cdo_mite_chan) {
 722                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 723                 dev_err(dev->class_dev,
 724                         "failed to reserve mite dma channel for correlated digital output\n");
 725                 return -EBUSY;
 726         }
 727         devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
 728         ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
 729         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 730 #endif /*  PCIDMA */
 731         return 0;
 732 }
 733
 734 static void ni_release_ai_mite_channel(struct comedi_device *dev)
 735 {
 736 #ifdef PCIDMA
 737         struct ni_private *devpriv = dev->private;
 738         unsigned long flags;
 739
 740         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 741         if (devpriv->ai_mite_chan) {
 742                 ni_set_ai_dma_channel(dev, -1);
 743                 mite_release_channel(devpriv->ai_mite_chan);
 744                 devpriv->ai_mite_chan = NULL;
 745         }
 746         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 747 #endif /*  PCIDMA */
 748 }
 749
 750 static void ni_release_ao_mite_channel(struct comedi_device *dev)
 751 {
 752 #ifdef PCIDMA
 753         struct ni_private *devpriv = dev->private;
 754         unsigned long flags;
 755
 756         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 757         if (devpriv->ao_mite_chan) {
 758                 ni_set_ao_dma_channel(dev, -1);
 759                 mite_release_channel(devpriv->ao_mite_chan);
 760                 devpriv->ao_mite_chan = NULL;
 761         }
 762         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 763 #endif /*  PCIDMA */
 764 }
 765
 766 #ifdef PCIDMA
 767 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
 768                                          unsigned gpct_index)
 769 {
 770         struct ni_private *devpriv = dev->private;
 771         unsigned long flags;
 772
 773         BUG_ON(gpct_index >= NUM_GPCT);
 774         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 775         if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
 776                 struct mite_channel *mite_chan =
 777                     devpriv->counter_dev->counters[gpct_index].mite_chan;
 778
 779                 ni_set_gpct_dma_channel(dev, gpct_index, -1);
 780                 ni_tio_set_mite_channel(&devpriv->
 781                                         counter_dev->counters[gpct_index],
 782                                         NULL);
 783                 mite_release_channel(mite_chan);
 784         }
 785         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 786 }
 787 #endif /*  PCIDMA */
 788
 789 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
 790 {
 791 #ifdef PCIDMA
 792         struct ni_private *devpriv = dev->private;
 793         unsigned long flags;
 794
 795         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 796         if (devpriv->cdo_mite_chan) {
 797                 ni_set_cdo_dma_channel(dev, -1);
 798                 mite_release_channel(devpriv->cdo_mite_chan);
 799                 devpriv->cdo_mite_chan = NULL;
 800         }
 801         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 802 #endif /*  PCIDMA */
 803 }
 804
 805 #ifdef PCIDMA
 806 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
 807                                           unsigned gpct_index, short enable)
 808 {
 809         struct ni_private *devpriv = dev->private;
 810         uint16_t val = 0;
 811         int reg;
 812
 813         if (devpriv->is_m_series || gpct_index > 1)
 814                 return;
 815
 816         /*
 817          * e-series boards use the second irq signals to generate
 818          * dma requests for their counters
 819          */
 820         if (gpct_index == 0) {
 821                 reg = Second_IRQ_A_Enable_Register;
 822                 if (enable)
 823                         val = G0_Gate_Second_Irq_Enable;
 824         } else {
 825                 reg = Second_IRQ_B_Enable_Register;
 826                 if (enable)
 827                         val = G1_Gate_Second_Irq_Enable;
 828         }
 829         ni_stc_writew(dev, val, reg);
 830 }
 831 #endif /*  PCIDMA */
 832
 833 static void ni_clear_ai_fifo(struct comedi_device *dev)
 834 {
 835         struct ni_private *devpriv = dev->private;
 836         static const int timeout = 10000;
 837         int i;
 838
 839         if (devpriv->is_6143) {
 840                 /*  Flush the 6143 data FIFO */
 841                 ni_writel(dev, 0x10, AIFIFO_Control_6143);
 842                 ni_writel(dev, 0x00, AIFIFO_Control_6143);
 843                 /*  Wait for complete */
 844                 for (i = 0; i < timeout; i++) {
 845                         if (!(ni_readl(dev, AIFIFO_Status_6143) & 0x10))
 846                                 break;
 847                         udelay(1);
 848                 }
 849                 if (i == timeout)
 850                         dev_err(dev->class_dev, "FIFO flush timeout\n");
 851         } else {
 852                 ni_stc_writew(dev, 1, ADC_FIFO_Clear);
 853                 if (devpriv->is_625x) {
 854                         ni_writeb(dev, 0, NI_M_STATIC_AI_CTRL_REG(0));
 855                         ni_writeb(dev, 1, NI_M_STATIC_AI_CTRL_REG(0));
 856 #if 0
 857                         /* the NI example code does 3 convert pulses for 625x boards,
 858                            but that appears to be wrong in practice. */
 859                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
 860                                       NISTC_AI_CMD1_REG);
 861                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
 862                                       NISTC_AI_CMD1_REG);
 863                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
 864                                       NISTC_AI_CMD1_REG);
 865 #endif
 866                 }
 867         }
 868 }
 869
 870 static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data,
 871                                   int addr)
 872 {
 873         struct ni_private *devpriv = dev->private;
 874         unsigned long flags;
 875
 876         spin_lock_irqsave(&devpriv->window_lock, flags);
 877         ni_writew(dev, addr, AO_Window_Address_611x);
 878         ni_writew(dev, data, AO_Window_Data_611x);
 879         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 880 }
 881
 882 static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data,
 883                                   int addr)
 884 {
 885         struct ni_private *devpriv = dev->private;
 886         unsigned long flags;
 887
 888         spin_lock_irqsave(&devpriv->window_lock, flags);
 889         ni_writew(dev, addr, AO_Window_Address_611x);
 890         ni_writel(dev, data, AO_Window_Data_611x);
 891         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 892 }
 893
 894 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
 895 {
 896         struct ni_private *devpriv = dev->private;
 897         unsigned long flags;
 898         unsigned short data;
 899
 900         spin_lock_irqsave(&devpriv->window_lock, flags);
 901         ni_writew(dev, addr, AO_Window_Address_611x);
 902         data = ni_readw(dev, AO_Window_Data_611x);
 903         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 904         return data;
 905 }
 906
 907 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
 908 * share registers (such as Interrupt_A_Register) without interfering with
 909 * each other.
 910 *
 911 * NOTE: the switch/case statements are optimized out for a constant argument
 912 * so this is actually quite fast---  If you must wrap another function around this
 913 * make it inline to avoid a large speed penalty.
 914 *
 915 * value should only be 1 or 0.
 916 */
 917 static inline void ni_set_bits(struct comedi_device *dev, int reg,
 918                                unsigned bits, unsigned value)
 919 {
 920         unsigned bit_values;
 921
 922         if (value)
 923                 bit_values = bits;
 924         else
 925                 bit_values = 0;
 926         ni_set_bitfield(dev, reg, bits, bit_values);
 927 }
 928
 929 #ifdef PCIDMA
 930 static void ni_sync_ai_dma(struct comedi_device *dev)
 931 {
 932         struct ni_private *devpriv = dev->private;
 933         struct comedi_subdevice *s = dev->read_subdev;
 934         unsigned long flags;
 935
 936         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 937         if (devpriv->ai_mite_chan)
 938                 mite_sync_input_dma(devpriv->ai_mite_chan, s);
 939         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 940 }
 941
 942 static int ni_ai_drain_dma(struct comedi_device *dev)
 943 {
 944         struct ni_private *devpriv = dev->private;
 945         int i;
 946         static const int timeout = 10000;
 947         unsigned long flags;
 948         int retval = 0;
 949
 950         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 951         if (devpriv->ai_mite_chan) {
 952                 for (i = 0; i < timeout; i++) {
 953                         if ((ni_stc_readw(dev, AI_Status_1_Register) &
 954                              AI_FIFO_Empty_St)
 955                             && mite_bytes_in_transit(devpriv->ai_mite_chan) ==
 956                             0)
 957                                 break;
 958                         udelay(5);
 959                 }
 960                 if (i == timeout) {
 961                         dev_err(dev->class_dev, "timed out\n");
 962                         dev_err(dev->class_dev,
 963                                 "mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
 964                                 mite_bytes_in_transit(devpriv->ai_mite_chan),
 965                                 ni_stc_readw(dev, AI_Status_1_Register));
 966                         retval = -1;
 967                 }
 968         }
 969         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 970
 971         ni_sync_ai_dma(dev);
 972
 973         return retval;
 974 }
 975
 976 static void mite_handle_b_linkc(struct mite_struct *mite,
 977                                 struct comedi_device *dev)
 978 {
 979         struct ni_private *devpriv = dev->private;
 980         struct comedi_subdevice *s = dev->write_subdev;
 981         unsigned long flags;
 982
 983         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 984         if (devpriv->ao_mite_chan)
 985                 mite_sync_output_dma(devpriv->ao_mite_chan, s);
 986         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 987 }
 988
 989 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
 990 {
 991         static const int timeout = 10000;
 992         int i;
 993
 994         for (i = 0; i < timeout; i++) {
 995                 unsigned short b_status;
 996
 997                 b_status = ni_stc_readw(dev, AO_Status_1_Register);
 998                 if (b_status & AO_FIFO_Half_Full_St)
 999                         break;
1000                 /* if we poll too often, the pci bus activity seems
1001                    to slow the dma transfer down */
1002                 udelay(10);
1003         }
1004         if (i == timeout) {
1005                 dev_err(dev->class_dev, "timed out waiting for dma load\n");
1006                 return -EPIPE;
1007         }
1008         return 0;
1009 }
1010 #endif /* PCIDMA */
1011
1012 #ifndef PCIDMA
1013
1014 static void ni_ao_fifo_load(struct comedi_device *dev,
1015                             struct comedi_subdevice *s, int n)
1016 {
1017         struct ni_private *devpriv = dev->private;
1018         int i;
1019         unsigned short d;
1020         u32 packed_data;
1021
1022         for (i = 0; i < n; i++) {
1023                 comedi_buf_read_samples(s, &d, 1);
1024
1025                 if (devpriv->is_6xxx) {
1026                         packed_data = d & 0xffff;
1027                         /* 6711 only has 16 bit wide ao fifo */
1028                         if (!devpriv->is_6711) {
1029                                 comedi_buf_read_samples(s, &d, 1);
1030                                 i++;
1031                                 packed_data |= (d << 16) & 0xffff0000;
1032                         }
1033                         ni_writel(dev, packed_data, DAC_FIFO_Data_611x);
1034                 } else {
1035                         ni_writew(dev, d, DAC_FIFO_Data);
1036                 }
1037         }
1038 }
1039
1040 /*
1041  *  There's a small problem if the FIFO gets really low and we
1042  *  don't have the data to fill it.  Basically, if after we fill
1043  *  the FIFO with all the data available, the FIFO is _still_
1044  *  less than half full, we never clear the interrupt.  If the
1045  *  IRQ is in edge mode, we never get another interrupt, because
1046  *  this one wasn't cleared.  If in level mode, we get flooded
1047  *  with interrupts that we can't fulfill, because nothing ever
1048  *  gets put into the buffer.
1049  *
1050  *  This kind of situation is recoverable, but it is easier to
1051  *  just pretend we had a FIFO underrun, since there is a good
1052  *  chance it will happen anyway.  This is _not_ the case for
1053  *  RT code, as RT code might purposely be running close to the
1054  *  metal.  Needs to be fixed eventually.
1055  */
1056 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1057                                  struct comedi_subdevice *s)
1058 {
1059         const struct ni_board_struct *board = dev->board_ptr;
1060         unsigned int nbytes;
1061         unsigned int nsamples;
1062
1063         nbytes = comedi_buf_read_n_available(s);
1064         if (nbytes == 0) {
1065                 s->async->events |= COMEDI_CB_OVERFLOW;
1066                 return 0;
1067         }
1068
1069         nsamples = comedi_bytes_to_samples(s, nbytes);
1070         if (nsamples > board->ao_fifo_depth / 2)
1071                 nsamples = board->ao_fifo_depth / 2;
1072
1073         ni_ao_fifo_load(dev, s, nsamples);
1074
1075         return 1;
1076 }
1077
1078 static int ni_ao_prep_fifo(struct comedi_device *dev,
1079                            struct comedi_subdevice *s)
1080 {
1081         const struct ni_board_struct *board = dev->board_ptr;
1082         struct ni_private *devpriv = dev->private;
1083         unsigned int nbytes;
1084         unsigned int nsamples;
1085
1086         /* reset fifo */
1087         ni_stc_writew(dev, 1, DAC_FIFO_Clear);
1088         if (devpriv->is_6xxx)
1089                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
1090
1091         /* load some data */
1092         nbytes = comedi_buf_read_n_available(s);
1093         if (nbytes == 0)
1094                 return 0;
1095
1096         nsamples = comedi_bytes_to_samples(s, nbytes);
1097         if (nsamples > board->ao_fifo_depth)
1098                 nsamples = board->ao_fifo_depth;
1099
1100         ni_ao_fifo_load(dev, s, nsamples);
1101
1102         return nsamples;
1103 }
1104
1105 static void ni_ai_fifo_read(struct comedi_device *dev,
1106                             struct comedi_subdevice *s, int n)
1107 {
1108         struct ni_private *devpriv = dev->private;
1109         struct comedi_async *async = s->async;
1110         u32 dl;
1111         unsigned short data;
1112         int i;
1113
1114         if (devpriv->is_611x) {
1115                 for (i = 0; i < n / 2; i++) {
1116                         dl = ni_readl(dev, ADC_FIFO_Data_611x);
1117                         /* This may get the hi/lo data in the wrong order */
1118                         data = (dl >> 16) & 0xffff;
1119                         comedi_buf_write_samples(s, &data, 1);
1120                         data = dl & 0xffff;
1121                         comedi_buf_write_samples(s, &data, 1);
1122                 }
1123                 /* Check if there's a single sample stuck in the FIFO */
1124                 if (n % 2) {
1125                         dl = ni_readl(dev, ADC_FIFO_Data_611x);
1126                         data = dl & 0xffff;
1127                         comedi_buf_write_samples(s, &data, 1);
1128                 }
1129         } else if (devpriv->is_6143) {
1130                 /*  This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
1131                 for (i = 0; i < n / 2; i++) {
1132                         dl = ni_readl(dev, AIFIFO_Data_6143);
1133
1134                         data = (dl >> 16) & 0xffff;
1135                         comedi_buf_write_samples(s, &data, 1);
1136                         data = dl & 0xffff;
1137                         comedi_buf_write_samples(s, &data, 1);
1138                 }
1139                 if (n % 2) {
1140                         /* Assume there is a single sample stuck in the FIFO */
1141                         /* Get stranded sample into FIFO */
1142                         ni_writel(dev, 0x01, AIFIFO_Control_6143);
1143                         dl = ni_readl(dev, AIFIFO_Data_6143);
1144                         data = (dl >> 16) & 0xffff;
1145                         comedi_buf_write_samples(s, &data, 1);
1146                 }
1147         } else {
1148                 if (n > sizeof(devpriv->ai_fifo_buffer) /
1149                     sizeof(devpriv->ai_fifo_buffer[0])) {
1150                         dev_err(dev->class_dev,
1151                                 "bug! ai_fifo_buffer too small\n");
1152                         async->events |= COMEDI_CB_ERROR;
1153                         return;
1154                 }
1155                 for (i = 0; i < n; i++) {
1156                         devpriv->ai_fifo_buffer[i] =
1157                             ni_readw(dev, ADC_FIFO_Data_Register);
1158                 }
1159                 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, n);
1160         }
1161 }
1162
1163 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1164 {
1165         const struct ni_board_struct *board = dev->board_ptr;
1166         struct comedi_subdevice *s = dev->read_subdev;
1167         int n;
1168
1169         n = board->ai_fifo_depth / 2;
1170
1171         ni_ai_fifo_read(dev, s, n);
1172 }
1173 #endif
1174
1175 /*
1176    Empties the AI fifo
1177 */
1178 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1179 {
1180         struct ni_private *devpriv = dev->private;
1181         struct comedi_subdevice *s = dev->read_subdev;
1182         u32 dl;
1183         unsigned short data;
1184         unsigned short fifo_empty;
1185         int i;
1186
1187         if (devpriv->is_611x) {
1188                 while ((ni_stc_readw(dev, AI_Status_1_Register) &
1189                         AI_FIFO_Empty_St) == 0) {
1190                         dl = ni_readl(dev, ADC_FIFO_Data_611x);
1191
1192                         /* This may get the hi/lo data in the wrong order */
1193                         data = dl >> 16;
1194                         comedi_buf_write_samples(s, &data, 1);
1195                         data = dl & 0xffff;
1196                         comedi_buf_write_samples(s, &data, 1);
1197                 }
1198         } else if (devpriv->is_6143) {
1199                 i = 0;
1200                 while (ni_readl(dev, AIFIFO_Status_6143) & 0x04) {
1201                         dl = ni_readl(dev, AIFIFO_Data_6143);
1202
1203                         /* This may get the hi/lo data in the wrong order */
1204                         data = dl >> 16;
1205                         comedi_buf_write_samples(s, &data, 1);
1206                         data = dl & 0xffff;
1207                         comedi_buf_write_samples(s, &data, 1);
1208                         i += 2;
1209                 }
1210                 /*  Check if stranded sample is present */
1211                 if (ni_readl(dev, AIFIFO_Status_6143) & 0x01) {
1212                         /* Get stranded sample into FIFO */
1213                         ni_writel(dev, 0x01, AIFIFO_Control_6143);
1214                         dl = ni_readl(dev, AIFIFO_Data_6143);
1215                         data = (dl >> 16) & 0xffff;
1216                         comedi_buf_write_samples(s, &data, 1);
1217                 }
1218
1219         } else {
1220                 fifo_empty = ni_stc_readw(dev, AI_Status_1_Register) &
1221                              AI_FIFO_Empty_St;
1222                 while (fifo_empty == 0) {
1223                         for (i = 0;
1224                              i <
1225                              sizeof(devpriv->ai_fifo_buffer) /
1226                              sizeof(devpriv->ai_fifo_buffer[0]); i++) {
1227                                 fifo_empty = ni_stc_readw(dev,
1228                                                           AI_Status_1_Register) &
1229                                                 AI_FIFO_Empty_St;
1230                                 if (fifo_empty)
1231                                         break;
1232                                 devpriv->ai_fifo_buffer[i] =
1233                                     ni_readw(dev, ADC_FIFO_Data_Register);
1234                         }
1235                         comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, i);
1236                 }
1237         }
1238 }
1239
1240 static void get_last_sample_611x(struct comedi_device *dev)
1241 {
1242         struct ni_private *devpriv = dev->private;
1243         struct comedi_subdevice *s = dev->read_subdev;
1244         unsigned short data;
1245         u32 dl;
1246
1247         if (!devpriv->is_611x)
1248                 return;
1249
1250         /* Check if there's a single sample stuck in the FIFO */
1251         if (ni_readb(dev, XXX_Status) & 0x80) {
1252                 dl = ni_readl(dev, ADC_FIFO_Data_611x);
1253                 data = dl & 0xffff;
1254                 comedi_buf_write_samples(s, &data, 1);
1255         }
1256 }
1257
1258 static void get_last_sample_6143(struct comedi_device *dev)
1259 {
1260         struct ni_private *devpriv = dev->private;
1261         struct comedi_subdevice *s = dev->read_subdev;
1262         unsigned short data;
1263         u32 dl;
1264
1265         if (!devpriv->is_6143)
1266                 return;
1267
1268         /* Check if there's a single sample stuck in the FIFO */
1269         if (ni_readl(dev, AIFIFO_Status_6143) & 0x01) {
1270                 /* Get stranded sample into FIFO */
1271                 ni_writel(dev, 0x01, AIFIFO_Control_6143);
1272                 dl = ni_readl(dev, AIFIFO_Data_6143);
1273
1274                 /* This may get the hi/lo data in the wrong order */
1275                 data = (dl >> 16) & 0xffff;
1276                 comedi_buf_write_samples(s, &data, 1);
1277         }
1278 }
1279
1280 static void shutdown_ai_command(struct comedi_device *dev)
1281 {
1282         struct comedi_subdevice *s = dev->read_subdev;
1283
1284 #ifdef PCIDMA
1285         ni_ai_drain_dma(dev);
1286 #endif
1287         ni_handle_fifo_dregs(dev);
1288         get_last_sample_611x(dev);
1289         get_last_sample_6143(dev);
1290
1291         s->async->events |= COMEDI_CB_EOA;
1292 }
1293
1294 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
1295 {
1296         struct ni_private *devpriv = dev->private;
1297
1298         if (devpriv->aimode == AIMODE_SCAN) {
1299 #ifdef PCIDMA
1300                 static const int timeout = 10;
1301                 int i;
1302
1303                 for (i = 0; i < timeout; i++) {
1304                         ni_sync_ai_dma(dev);
1305                         if ((s->async->events & COMEDI_CB_EOS))
1306                                 break;
1307                         udelay(1);
1308                 }
1309 #else
1310                 ni_handle_fifo_dregs(dev);
1311                 s->async->events |= COMEDI_CB_EOS;
1312 #endif
1313         }
1314         /* handle special case of single scan */
1315         if (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)
1316                 shutdown_ai_command(dev);
1317 }
1318
1319 static void handle_gpct_interrupt(struct comedi_device *dev,
1320                                   unsigned short counter_index)
1321 {
1322 #ifdef PCIDMA
1323         struct ni_private *devpriv = dev->private;
1324         struct comedi_subdevice *s;
1325
1326         s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
1327
1328         ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
1329                                 s);
1330         comedi_handle_events(dev, s);
1331 #endif
1332 }
1333
1334 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
1335 {
1336         unsigned short ack = 0;
1337
1338         if (a_status & AI_SC_TC_St)
1339                 ack |= NISTC_INTA_ACK_AI_SC_TC;
1340         if (a_status & AI_START1_St)
1341                 ack |= NISTC_INTA_ACK_AI_START1;
1342         if (a_status & AI_START_St)
1343                 ack |= NISTC_INTA_ACK_AI_START;
1344         if (a_status & AI_STOP_St)
1345                 ack |= NISTC_INTA_ACK_AI_STOP;
1346         if (ack)
1347                 ni_stc_writew(dev, ack, NISTC_INTA_ACK_REG);
1348 }
1349
1350 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
1351                                unsigned ai_mite_status)
1352 {
1353         struct comedi_subdevice *s = dev->read_subdev;
1354         struct comedi_cmd *cmd = &s->async->cmd;
1355
1356         /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */
1357         if (s->type == COMEDI_SUBD_UNUSED)
1358                 return;
1359
1360 #ifdef PCIDMA
1361         if (ai_mite_status & CHSR_LINKC)
1362                 ni_sync_ai_dma(dev);
1363
1364         if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1365                                CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1366                                CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1367                 dev_err(dev->class_dev,
1368                         "unknown mite interrupt (ai_mite_status=%08x)\n",
1369                         ai_mite_status);
1370                 s->async->events |= COMEDI_CB_ERROR;
1371                 /* disable_irq(dev->irq); */
1372         }
1373 #endif
1374
1375         /* test for all uncommon interrupt events at the same time */
1376         if (status & (AI_Overrun_St | AI_Overflow_St | AI_SC_TC_Error_St |
1377                       AI_SC_TC_St | AI_START1_St)) {
1378                 if (status == 0xffff) {
1379                         dev_err(dev->class_dev, "Card removed?\n");
1380                         /* we probably aren't even running a command now,
1381                          * so it's a good idea to be careful. */
1382                         if (comedi_is_subdevice_running(s)) {
1383                                 s->async->events |= COMEDI_CB_ERROR;
1384                                 comedi_handle_events(dev, s);
1385                         }
1386                         return;
1387                 }
1388                 if (status & (AI_Overrun_St | AI_Overflow_St |
1389                               AI_SC_TC_Error_St)) {
1390                         dev_err(dev->class_dev, "ai error a_status=%04x\n",
1391                                 status);
1392
1393                         shutdown_ai_command(dev);
1394
1395                         s->async->events |= COMEDI_CB_ERROR;
1396                         if (status & (AI_Overrun_St | AI_Overflow_St))
1397                                 s->async->events |= COMEDI_CB_OVERFLOW;
1398
1399                         comedi_handle_events(dev, s);
1400                         return;
1401                 }
1402                 if (status & AI_SC_TC_St) {
1403                         if (cmd->stop_src == TRIG_COUNT)
1404                                 shutdown_ai_command(dev);
1405                 }
1406         }
1407 #ifndef PCIDMA
1408         if (status & AI_FIFO_Half_Full_St) {
1409                 int i;
1410                 static const int timeout = 10;
1411                 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1412                  *fail to get the fifo less than half full, so loop to be sure.*/
1413                 for (i = 0; i < timeout; ++i) {
1414                         ni_handle_fifo_half_full(dev);
1415                         if ((ni_stc_readw(dev, AI_Status_1_Register) &
1416                              AI_FIFO_Half_Full_St) == 0)
1417                                 break;
1418                 }
1419         }
1420 #endif /*  !PCIDMA */
1421
1422         if ((status & AI_STOP_St))
1423                 ni_handle_eos(dev, s);
1424
1425         comedi_handle_events(dev, s);
1426 }
1427
1428 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1429 {
1430         unsigned short ack = 0;
1431
1432         if (b_status & AO_BC_TC_St)
1433                 ack |= NISTC_INTB_ACK_AO_BC_TC;
1434         if (b_status & AO_Overrun_St)
1435                 ack |= NISTC_INTB_ACK_AO_ERR;
1436         if (b_status & AO_START_St)
1437                 ack |= NISTC_INTB_ACK_AO_START;
1438         if (b_status & AO_START1_St)
1439                 ack |= NISTC_INTB_ACK_AO_START1;
1440         if (b_status & AO_UC_TC_St)
1441                 ack |= NISTC_INTB_ACK_AO_UC_TC;
1442         if (b_status & AO_UI2_TC_St)
1443                 ack |= NISTC_INTB_ACK_AO_UI2_TC;
1444         if (b_status & AO_UPDATE_St)
1445                 ack |= NISTC_INTB_ACK_AO_UPDATE;
1446         if (ack)
1447                 ni_stc_writew(dev, ack, NISTC_INTB_ACK_REG);
1448 }
1449
1450 static void handle_b_interrupt(struct comedi_device *dev,
1451                                unsigned short b_status, unsigned ao_mite_status)
1452 {
1453         struct comedi_subdevice *s = dev->write_subdev;
1454         /* unsigned short ack=0; */
1455
1456 #ifdef PCIDMA
1457         /* Currently, mite.c requires us to handle LINKC */
1458         if (ao_mite_status & CHSR_LINKC) {
1459                 struct ni_private *devpriv = dev->private;
1460
1461                 mite_handle_b_linkc(devpriv->mite, dev);
1462         }
1463
1464         if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1465                                CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1466                                CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1467                 dev_err(dev->class_dev,
1468                         "unknown mite interrupt (ao_mite_status=%08x)\n",
1469                         ao_mite_status);
1470                 s->async->events |= COMEDI_CB_ERROR;
1471         }
1472 #endif
1473
1474         if (b_status == 0xffff)
1475                 return;
1476         if (b_status & AO_Overrun_St) {
1477                 dev_err(dev->class_dev,
1478                         "AO FIFO underrun status=0x%04x status2=0x%04x\n",
1479                         b_status, ni_stc_readw(dev, AO_Status_2_Register));
1480                 s->async->events |= COMEDI_CB_OVERFLOW;
1481         }
1482
1483         if (b_status & AO_BC_TC_St)
1484                 s->async->events |= COMEDI_CB_EOA;
1485
1486 #ifndef PCIDMA
1487         if (b_status & AO_FIFO_Request_St) {
1488                 int ret;
1489
1490                 ret = ni_ao_fifo_half_empty(dev, s);
1491                 if (!ret) {
1492                         dev_err(dev->class_dev, "AO buffer underrun\n");
1493                         ni_set_bits(dev, Interrupt_B_Enable_Register,
1494                                     AO_FIFO_Interrupt_Enable |
1495                                     AO_Error_Interrupt_Enable, 0);
1496                         s->async->events |= COMEDI_CB_OVERFLOW;
1497                 }
1498         }
1499 #endif
1500
1501         comedi_handle_events(dev, s);
1502 }
1503
1504 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1505                         void *data, unsigned int num_bytes,
1506                         unsigned int chan_index)
1507 {
1508         struct ni_private *devpriv = dev->private;
1509         struct comedi_async *async = s->async;
1510         struct comedi_cmd *cmd = &async->cmd;
1511         unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
1512         unsigned short *array = data;
1513         unsigned int *larray = data;
1514         unsigned int i;
1515
1516         for (i = 0; i < nsamples; i++) {
1517 #ifdef PCIDMA
1518                 if (s->subdev_flags & SDF_LSAMPL)
1519                         larray[i] = le32_to_cpu(larray[i]);
1520                 else
1521                         array[i] = le16_to_cpu(array[i]);
1522 #endif
1523                 if (s->subdev_flags & SDF_LSAMPL)
1524                         larray[i] += devpriv->ai_offset[chan_index];
1525                 else
1526                         array[i] += devpriv->ai_offset[chan_index];
1527                 chan_index++;
1528                 chan_index %= cmd->chanlist_len;
1529         }
1530 }
1531
1532 #ifdef PCIDMA
1533
1534 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1535 {
1536         struct ni_private *devpriv = dev->private;
1537         struct comedi_subdevice *s = dev->read_subdev;
1538         int retval;
1539         unsigned long flags;
1540
1541         retval = ni_request_ai_mite_channel(dev);
1542         if (retval)
1543                 return retval;
1544
1545         /* write alloc the entire buffer */
1546         comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
1547
1548         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1549         if (!devpriv->ai_mite_chan) {
1550                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1551                 return -EIO;
1552         }
1553
1554         if (devpriv->is_611x || devpriv->is_6143)
1555                 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1556         else if (devpriv->is_628x)
1557                 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1558         else
1559                 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1560
1561         /*start the MITE */
1562         mite_dma_arm(devpriv->ai_mite_chan);
1563         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1564
1565         return 0;
1566 }
1567
1568 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1569 {
1570         struct ni_private *devpriv = dev->private;
1571         struct comedi_subdevice *s = dev->write_subdev;
1572         int retval;
1573         unsigned long flags;
1574
1575         retval = ni_request_ao_mite_channel(dev);
1576         if (retval)
1577                 return retval;
1578
1579         /* read alloc the entire buffer */
1580         comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
1581
1582         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1583         if (devpriv->ao_mite_chan) {
1584                 if (devpriv->is_611x || devpriv->is_6713) {
1585                         mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1586                 } else {
1587                         /* doing 32 instead of 16 bit wide transfers from memory
1588                            makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1589                         mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1590                 }
1591                 mite_dma_arm(devpriv->ao_mite_chan);
1592         } else {
1593                 retval = -EIO;
1594         }
1595         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1596
1597         return retval;
1598 }
1599
1600 #endif /*  PCIDMA */
1601
1602 /*
1603    used for both cancel ioctl and board initialization
1604
1605    this is pretty harsh for a cancel, but it works...
1606  */
1607
1608 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1609 {
1610         struct ni_private *devpriv = dev->private;
1611         unsigned ai_out_ctrl;
1612
1613         ni_release_ai_mite_channel(dev);
1614         /* ai configuration */
1615         ni_stc_writew(dev, AI_Configuration_Start | AI_Reset,
1616                       Joint_Reset_Register);
1617
1618         ni_set_bits(dev, Interrupt_A_Enable_Register,
1619                     AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable |
1620                     AI_START2_Interrupt_Enable | AI_START_Interrupt_Enable |
1621                     AI_STOP_Interrupt_Enable | AI_Error_Interrupt_Enable |
1622                     AI_FIFO_Interrupt_Enable, 0);
1623
1624         ni_clear_ai_fifo(dev);
1625
1626         if (!devpriv->is_6143)
1627                 ni_writeb(dev, 0, Misc_Command);
1628
1629         ni_stc_writew(dev, NISTC_AI_CMD1_DISARM, NISTC_AI_CMD1_REG);
1630         ni_stc_writew(dev, NISTC_AI_MODE1_START_STOP |
1631                            NISTC_AI_MODE1_RSVD
1632                             /*| NISTC_AI_MODE1_TRIGGER_ONCE */,
1633                       NISTC_AI_MODE1_REG);
1634         ni_stc_writew(dev, 0, NISTC_AI_MODE2_REG);
1635         /* generate FIFO interrupts on non-empty */
1636         ni_stc_writew(dev, (0 << 6) | 0x0000, AI_Mode_3_Register);
1637
1638         ai_out_ctrl = NISTC_AI_OUT_CTRL_SCAN_IN_PROG_SEL(3) |
1639                       NISTC_AI_OUT_CTRL_EXTMUX_CLK_SEL(0) |
1640                       NISTC_AI_OUT_CTRL_LOCALMUX_CLK_SEL(2) |
1641                       NISTC_AI_OUT_CTRL_SC_TC_SEL(3);
1642         if (devpriv->is_611x) {
1643                 ni_stc_writew(dev,
1644                               AI_SHIFTIN_Pulse_Width |
1645                               AI_SOC_Polarity |
1646                               AI_LOCALMUX_CLK_Pulse_Width,
1647                               AI_Personal_Register);
1648                 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1649         } else if (devpriv->is_6143) {
1650                 ni_stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1651                                    AI_SOC_Polarity |
1652                                    AI_LOCALMUX_CLK_Pulse_Width,
1653                               AI_Personal_Register);
1654                 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1655         } else {
1656                 ni_stc_writew(dev,
1657                               AI_SHIFTIN_Pulse_Width |
1658                               AI_SOC_Polarity |
1659                               AI_CONVERT_Pulse_Width |
1660                               AI_LOCALMUX_CLK_Pulse_Width,
1661                               AI_Personal_Register);
1662                 if (devpriv->is_622x)
1663                         ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1664                 else
1665                         ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1666         }
1667         ni_stc_writew(dev, ai_out_ctrl, NISTC_AI_OUT_CTRL_REG);
1668
1669         /* the following registers should not be changed, because there
1670          * are no backup registers in devpriv.  If you want to change
1671          * any of these, add a backup register and other appropriate code:
1672          *      NISTC_AI_MODE1_REG
1673          *      AI_Mode_3_Register
1674          *      AI_Personal_Register
1675          *      NISTC_AI_OUT_CTRL_REG
1676          */
1677
1678         /* clear interrupts */
1679         ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
1680
1681         ni_stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
1682
1683         return 0;
1684 }
1685
1686 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1687 {
1688         unsigned long flags;
1689         int count;
1690
1691         /*  lock to avoid race with interrupt handler */
1692         spin_lock_irqsave(&dev->spinlock, flags);
1693 #ifndef PCIDMA
1694         ni_handle_fifo_dregs(dev);
1695 #else
1696         ni_sync_ai_dma(dev);
1697 #endif
1698         count = comedi_buf_n_bytes_ready(s);
1699         spin_unlock_irqrestore(&dev->spinlock, flags);
1700
1701         return count;
1702 }
1703
1704 static void ni_prime_channelgain_list(struct comedi_device *dev)
1705 {
1706         int i;
1707
1708         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, NISTC_AI_CMD1_REG);
1709         for (i = 0; i < NI_TIMEOUT; ++i) {
1710                 if (!(ni_stc_readw(dev, AI_Status_1_Register) &
1711                       AI_FIFO_Empty_St)) {
1712                         ni_stc_writew(dev, 1, ADC_FIFO_Clear);
1713                         return;
1714                 }
1715                 udelay(1);
1716         }
1717         dev_err(dev->class_dev, "timeout loading channel/gain list\n");
1718 }
1719
1720 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1721                                               unsigned int n_chan,
1722                                               unsigned int *list)
1723 {
1724         const struct ni_board_struct *board = dev->board_ptr;
1725         struct ni_private *devpriv = dev->private;
1726         unsigned int chan, range, aref;
1727         unsigned int i;
1728         unsigned int dither;
1729         unsigned range_code;
1730
1731         ni_stc_writew(dev, 1, Configuration_Memory_Clear);
1732
1733         if ((list[0] & CR_ALT_SOURCE)) {
1734                 unsigned bypass_bits;
1735
1736                 chan = CR_CHAN(list[0]);
1737                 range = CR_RANGE(list[0]);
1738                 range_code = ni_gainlkup[board->gainlkup][range];
1739                 dither = (list[0] & CR_ALT_FILTER) != 0;
1740                 bypass_bits = NI_M_CFG_BYPASS_FIFO |
1741                               NI_M_CFG_BYPASS_AI_CHAN(chan) |
1742                               NI_M_CFG_BYPASS_AI_GAIN(range_code) |
1743                               devpriv->ai_calib_source;
1744                 if (dither)
1745                         bypass_bits |= NI_M_CFG_BYPASS_AI_DITHER;
1746                 /*  don't use 2's complement encoding */
1747                 bypass_bits |= NI_M_CFG_BYPASS_AI_POLARITY;
1748                 ni_writel(dev, bypass_bits, NI_M_CFG_BYPASS_FIFO_REG);
1749         } else {
1750                 ni_writel(dev, 0, NI_M_CFG_BYPASS_FIFO_REG);
1751         }
1752         for (i = 0; i < n_chan; i++) {
1753                 unsigned config_bits = 0;
1754
1755                 chan = CR_CHAN(list[i]);
1756                 aref = CR_AREF(list[i]);
1757                 range = CR_RANGE(list[i]);
1758                 dither = (list[i] & CR_ALT_FILTER) != 0;
1759
1760                 range_code = ni_gainlkup[board->gainlkup][range];
1761                 devpriv->ai_offset[i] = 0;
1762                 switch (aref) {
1763                 case AREF_DIFF:
1764                         config_bits |= NI_M_AI_CFG_CHAN_TYPE_DIFF;
1765                         break;
1766                 case AREF_COMMON:
1767                         config_bits |= NI_M_AI_CFG_CHAN_TYPE_COMMON;
1768                         break;
1769                 case AREF_GROUND:
1770                         config_bits |= NI_M_AI_CFG_CHAN_TYPE_GROUND;
1771                         break;
1772                 case AREF_OTHER:
1773                         break;
1774                 }
1775                 config_bits |= NI_M_AI_CFG_CHAN_SEL(chan);
1776                 config_bits |= NI_M_AI_CFG_BANK_SEL(chan);
1777                 config_bits |= NI_M_AI_CFG_GAIN(range_code);
1778                 if (i == n_chan - 1)
1779                         config_bits |= NI_M_AI_CFG_LAST_CHAN;
1780                 if (dither)
1781                         config_bits |= NI_M_AI_CFG_DITHER;
1782                 /*  don't use 2's complement encoding */
1783                 config_bits |= NI_M_AI_CFG_POLARITY;
1784                 ni_writew(dev, config_bits, NI_M_AI_CFG_FIFO_DATA_REG);
1785         }
1786         ni_prime_channelgain_list(dev);
1787 }
1788
1789 /*
1790  * Notes on the 6110 and 6111:
1791  * These boards a slightly different than the rest of the series, since
1792  * they have multiple A/D converters.
1793  * From the driver side, the configuration memory is a
1794  * little different.
1795  * Configuration Memory Low:
1796  *   bits 15-9: same
1797  *   bit 8: unipolar/bipolar (should be 0 for bipolar)
1798  *   bits 0-3: gain.  This is 4 bits instead of 3 for the other boards
1799  *       1001 gain=0.1 (+/- 50)
1800  *       1010 0.2
1801  *       1011 0.1
1802  *       0001 1
1803  *       0010 2
1804  *       0011 5
1805  *       0100 10
1806  *       0101 20
1807  *       0110 50
1808  * Configuration Memory High:
1809  *   bits 12-14: Channel Type
1810  *       001 for differential
1811  *       000 for calibration
1812  *   bit 11: coupling  (this is not currently handled)
1813  *       1 AC coupling
1814  *       0 DC coupling
1815  *   bits 0-2: channel
1816  *       valid channels are 0-3
1817  */
1818 static void ni_load_channelgain_list(struct comedi_device *dev,
1819                                      struct comedi_subdevice *s,
1820                                      unsigned int n_chan, unsigned int *list)
1821 {
1822         const struct ni_board_struct *board = dev->board_ptr;
1823         struct ni_private *devpriv = dev->private;
1824         unsigned int offset = (s->maxdata + 1) >> 1;
1825         unsigned int chan, range, aref;
1826         unsigned int i;
1827         unsigned int hi, lo;
1828         unsigned int dither;
1829
1830         if (devpriv->is_m_series) {
1831                 ni_m_series_load_channelgain_list(dev, n_chan, list);
1832                 return;
1833         }
1834         if (n_chan == 1 && !devpriv->is_611x && !devpriv->is_6143) {
1835                 if (devpriv->changain_state
1836                     && devpriv->changain_spec == list[0]) {
1837                         /*  ready to go. */
1838                         return;
1839                 }
1840                 devpriv->changain_state = 1;
1841                 devpriv->changain_spec = list[0];
1842         } else {
1843                 devpriv->changain_state = 0;
1844         }
1845
1846         ni_stc_writew(dev, 1, Configuration_Memory_Clear);
1847
1848         /*  Set up Calibration mode if required */
1849         if (devpriv->is_6143) {
1850                 if ((list[0] & CR_ALT_SOURCE)
1851                     && !devpriv->ai_calib_source_enabled) {
1852                         /*  Strobe Relay enable bit */
1853                         ni_writew(dev, devpriv->ai_calib_source |
1854                                        Calibration_Channel_6143_RelayOn,
1855                                   Calibration_Channel_6143);
1856                         ni_writew(dev, devpriv->ai_calib_source,
1857                                   Calibration_Channel_6143);
1858                         devpriv->ai_calib_source_enabled = 1;
1859                         msleep_interruptible(100);      /*  Allow relays to change */
1860                 } else if (!(list[0] & CR_ALT_SOURCE)
1861                            && devpriv->ai_calib_source_enabled) {
1862                         /*  Strobe Relay disable bit */
1863                         ni_writew(dev, devpriv->ai_calib_source |
1864                                        Calibration_Channel_6143_RelayOff,
1865                                   Calibration_Channel_6143);
1866                         ni_writew(dev, devpriv->ai_calib_source,
1867                                   Calibration_Channel_6143);
1868                         devpriv->ai_calib_source_enabled = 0;
1869                         msleep_interruptible(100);      /*  Allow relays to change */
1870                 }
1871         }
1872
1873         for (i = 0; i < n_chan; i++) {
1874                 if (!devpriv->is_6143 && (list[i] & CR_ALT_SOURCE))
1875                         chan = devpriv->ai_calib_source;
1876                 else
1877                         chan = CR_CHAN(list[i]);
1878                 aref = CR_AREF(list[i]);
1879                 range = CR_RANGE(list[i]);
1880                 dither = (list[i] & CR_ALT_FILTER) != 0;
1881
1882                 /* fix the external/internal range differences */
1883                 range = ni_gainlkup[board->gainlkup][range];
1884                 if (devpriv->is_611x)
1885                         devpriv->ai_offset[i] = offset;
1886                 else
1887                         devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
1888
1889                 hi = 0;
1890                 if ((list[i] & CR_ALT_SOURCE)) {
1891                         if (devpriv->is_611x)
1892                                 ni_writew(dev, CR_CHAN(list[i]) & 0x0003,
1893                                           Calibration_Channel_Select_611x);
1894                 } else {
1895                         if (devpriv->is_611x)
1896                                 aref = AREF_DIFF;
1897                         else if (devpriv->is_6143)
1898                                 aref = AREF_OTHER;
1899                         switch (aref) {
1900                         case AREF_DIFF:
1901                                 hi |= AI_DIFFERENTIAL;
1902                                 break;
1903                         case AREF_COMMON:
1904                                 hi |= AI_COMMON;
1905                                 break;
1906                         case AREF_GROUND:
1907                                 hi |= AI_GROUND;
1908                                 break;
1909                         case AREF_OTHER:
1910                                 break;
1911                         }
1912                 }
1913                 hi |= AI_CONFIG_CHANNEL(chan);
1914
1915                 ni_writew(dev, hi, Configuration_Memory_High);
1916
1917                 if (!devpriv->is_6143) {
1918                         lo = range;
1919                         if (i == n_chan - 1)
1920                                 lo |= AI_LAST_CHANNEL;
1921                         if (dither)
1922                                 lo |= AI_DITHER;
1923
1924                         ni_writew(dev, lo, Configuration_Memory_Low);
1925                 }
1926         }
1927
1928         /* prime the channel/gain list */
1929         if (!devpriv->is_611x && !devpriv->is_6143)
1930                 ni_prime_channelgain_list(dev);
1931 }
1932
1933 static int ni_ai_insn_read(struct comedi_device *dev,
1934                            struct comedi_subdevice *s,
1935                            struct comedi_insn *insn,
1936                            unsigned int *data)
1937 {
1938         struct ni_private *devpriv = dev->private;
1939         unsigned int mask = (s->maxdata + 1) >> 1;
1940         int i, n;
1941         unsigned signbits;
1942         unsigned int d;
1943         unsigned long dl;
1944
1945         ni_load_channelgain_list(dev, s, 1, &insn->chanspec);
1946
1947         ni_clear_ai_fifo(dev);
1948
1949         signbits = devpriv->ai_offset[0];
1950         if (devpriv->is_611x) {
1951                 for (n = 0; n < num_adc_stages_611x; n++) {
1952                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1953                                       NISTC_AI_CMD1_REG);
1954                         udelay(1);
1955                 }
1956                 for (n = 0; n < insn->n; n++) {
1957                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1958                                       NISTC_AI_CMD1_REG);
1959                         /* The 611x has screwy 32-bit FIFOs. */
1960                         d = 0;
1961                         for (i = 0; i < NI_TIMEOUT; i++) {
1962                                 if (ni_readb(dev, XXX_Status) & 0x80) {
1963                                         d = ni_readl(dev, ADC_FIFO_Data_611x);
1964                                         d >>= 16;
1965                                         d &= 0xffff;
1966                                         break;
1967                                 }
1968                                 if (!(ni_stc_readw(dev, AI_Status_1_Register) &
1969                                       AI_FIFO_Empty_St)) {
1970                                         d = ni_readl(dev, ADC_FIFO_Data_611x);
1971                                         d &= 0xffff;
1972                                         break;
1973                                 }
1974                         }
1975                         if (i == NI_TIMEOUT) {
1976                                 dev_err(dev->class_dev, "timeout\n");
1977                                 return -ETIME;
1978                         }
1979                         d += signbits;
1980                         data[n] = d;
1981                 }
1982         } else if (devpriv->is_6143) {
1983                 for (n = 0; n < insn->n; n++) {
1984                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1985                                       NISTC_AI_CMD1_REG);
1986
1987                         /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1988                         dl = 0;
1989                         for (i = 0; i < NI_TIMEOUT; i++) {
1990                                 if (ni_readl(dev, AIFIFO_Status_6143) & 0x01) {
1991                                         /* Get stranded sample into FIFO */
1992                                         ni_writel(dev, 0x01,
1993                                                   AIFIFO_Control_6143);
1994                                         dl = ni_readl(dev, AIFIFO_Data_6143);
1995                                         break;
1996                                 }
1997                         }
1998                         if (i == NI_TIMEOUT) {
1999                                 dev_err(dev->class_dev, "timeout\n");
2000                                 return -ETIME;
2001                         }
2002                         data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
2003                 }
2004         } else {
2005                 for (n = 0; n < insn->n; n++) {
2006                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
2007                                       NISTC_AI_CMD1_REG);
2008                         for (i = 0; i < NI_TIMEOUT; i++) {
2009                                 if (!(ni_stc_readw(dev, AI_Status_1_Register) &
2010                                       AI_FIFO_Empty_St))
2011                                         break;
2012                         }
2013                         if (i == NI_TIMEOUT) {
2014                                 dev_err(dev->class_dev, "timeout\n");
2015                                 return -ETIME;
2016                         }
2017                         if (devpriv->is_m_series) {
2018                                 dl = ni_readl(dev, NI_M_AI_FIFO_DATA_REG);
2019                                 dl &= mask;
2020                                 data[n] = dl;
2021                         } else {
2022                                 d = ni_readw(dev, ADC_FIFO_Data_Register);
2023                                 d += signbits;  /* subtle: needs to be short addition */
2024                                 data[n] = d;
2025                         }
2026                 }
2027         }
2028         return insn->n;
2029 }
2030
2031 static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec,
2032                           unsigned int flags)
2033 {
2034         struct ni_private *devpriv = dev->private;
2035         int divider;
2036
2037         switch (flags & CMDF_ROUND_MASK) {
2038         case CMDF_ROUND_NEAREST:
2039         default:
2040                 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
2041                 break;
2042         case CMDF_ROUND_DOWN:
2043                 divider = (nanosec) / devpriv->clock_ns;
2044                 break;
2045         case CMDF_ROUND_UP:
2046                 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
2047                 break;
2048         }
2049         return divider - 1;
2050 }
2051
2052 static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer)
2053 {
2054         struct ni_private *devpriv = dev->private;
2055
2056         return devpriv->clock_ns * (timer + 1);
2057 }
2058
2059 static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev,
2060                                          unsigned num_channels)
2061 {
2062         const struct ni_board_struct *board = dev->board_ptr;
2063         struct ni_private *devpriv = dev->private;
2064
2065         /* simultaneously-sampled inputs */
2066         if (devpriv->is_611x || devpriv->is_6143)
2067                 return board->ai_speed;
2068
2069         /* multiplexed inputs */
2070         return board->ai_speed * num_channels;
2071 }
2072
2073 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2074                          struct comedi_cmd *cmd)
2075 {
2076         const struct ni_board_struct *board = dev->board_ptr;
2077         struct ni_private *devpriv = dev->private;
2078         int err = 0;
2079         unsigned int tmp;
2080         unsigned int sources;
2081
2082         /* Step 1 : check if triggers are trivially valid */
2083
2084         err |= comedi_check_trigger_src(&cmd->start_src,
2085                                         TRIG_NOW | TRIG_INT | TRIG_EXT);
2086         err |= comedi_check_trigger_src(&cmd->scan_begin_src,
2087                                         TRIG_TIMER | TRIG_EXT);
2088
2089         sources = TRIG_TIMER | TRIG_EXT;
2090         if (devpriv->is_611x || devpriv->is_6143)
2091                 sources |= TRIG_NOW;
2092         err |= comedi_check_trigger_src(&cmd->convert_src, sources);
2093
2094         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2095         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2096
2097         if (err)
2098                 return 1;
2099
2100         /* Step 2a : make sure trigger sources are unique */
2101
2102         err |= comedi_check_trigger_is_unique(cmd->start_src);
2103         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
2104         err |= comedi_check_trigger_is_unique(cmd->convert_src);
2105         err |= comedi_check_trigger_is_unique(cmd->stop_src);
2106
2107         /* Step 2b : and mutually compatible */
2108
2109         if (err)
2110                 return 2;
2111
2112         /* Step 3: check if arguments are trivially valid */
2113
2114         switch (cmd->start_src) {
2115         case TRIG_NOW:
2116         case TRIG_INT:
2117                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
2118                 break;
2119         case TRIG_EXT:
2120                 tmp = CR_CHAN(cmd->start_arg);
2121
2122                 if (tmp > 16)
2123                         tmp = 16;
2124                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2125                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
2126                 break;
2127         }
2128
2129         if (cmd->scan_begin_src == TRIG_TIMER) {
2130                 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
2131                         ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2132                 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
2133                                                     devpriv->clock_ns *
2134                                                     0xffffff);
2135         } else if (cmd->scan_begin_src == TRIG_EXT) {
2136                 /* external trigger */
2137                 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2138
2139                 if (tmp > 16)
2140                         tmp = 16;
2141                 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2142                 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, tmp);
2143         } else {                /* TRIG_OTHER */
2144                 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2145         }
2146
2147         if (cmd->convert_src == TRIG_TIMER) {
2148                 if (devpriv->is_611x || devpriv->is_6143) {
2149                         err |= comedi_check_trigger_arg_is(&cmd->convert_arg,
2150                                                            0);
2151                 } else {
2152                         err |= comedi_check_trigger_arg_min(&cmd->convert_arg,
2153                                                             board->ai_speed);
2154                         err |= comedi_check_trigger_arg_max(&cmd->convert_arg,
2155                                                             devpriv->clock_ns *
2156                                                             0xffff);
2157                 }
2158         } else if (cmd->convert_src == TRIG_EXT) {
2159                 /* external trigger */
2160                 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2161
2162                 if (tmp > 16)
2163                         tmp = 16;
2164                 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2165                 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, tmp);
2166         } else if (cmd->convert_src == TRIG_NOW) {
2167                 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
2168         }
2169
2170         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
2171                                            cmd->chanlist_len);
2172
2173         if (cmd->stop_src == TRIG_COUNT) {
2174                 unsigned int max_count = 0x01000000;
2175
2176                 if (devpriv->is_611x)
2177                         max_count -= num_adc_stages_611x;
2178                 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, max_count);
2179                 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
2180         } else {
2181                 /* TRIG_NONE */
2182                 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
2183         }
2184
2185         if (err)
2186                 return 3;
2187
2188         /* step 4: fix up any arguments */
2189
2190         if (cmd->scan_begin_src == TRIG_TIMER) {
2191                 tmp = cmd->scan_begin_arg;
2192                 cmd->scan_begin_arg =
2193                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2194                                                        cmd->scan_begin_arg,
2195                                                        cmd->flags));
2196                 if (tmp != cmd->scan_begin_arg)
2197                         err++;
2198         }
2199         if (cmd->convert_src == TRIG_TIMER) {
2200                 if (!devpriv->is_611x && !devpriv->is_6143) {
2201                         tmp = cmd->convert_arg;
2202                         cmd->convert_arg =
2203                             ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2204                                                                cmd->convert_arg,
2205                                                                cmd->flags));
2206                         if (tmp != cmd->convert_arg)
2207                                 err++;
2208                         if (cmd->scan_begin_src == TRIG_TIMER &&
2209                             cmd->scan_begin_arg <
2210                             cmd->convert_arg * cmd->scan_end_arg) {
2211                                 cmd->scan_begin_arg =
2212                                     cmd->convert_arg * cmd->scan_end_arg;
2213                                 err++;
2214                         }
2215                 }
2216         }
2217
2218         if (err)
2219                 return 4;
2220
2221         return 0;
2222 }
2223
2224 static int ni_ai_inttrig(struct comedi_device *dev,
2225                          struct comedi_subdevice *s,
2226                          unsigned int trig_num)
2227 {
2228         struct ni_private *devpriv = dev->private;
2229         struct comedi_cmd *cmd = &s->async->cmd;
2230
2231         if (trig_num != cmd->start_arg)
2232                 return -EINVAL;
2233
2234         ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE | devpriv->ai_cmd2,
2235                       NISTC_AI_CMD2_REG);
2236         s->async->inttrig = NULL;
2237
2238         return 1;
2239 }
2240
2241 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2242 {
2243         struct ni_private *devpriv = dev->private;
2244         const struct comedi_cmd *cmd = &s->async->cmd;
2245         int timer;
2246         int mode1 = 0;          /* mode1 is needed for both stop and convert */
2247         int mode2 = 0;
2248         int start_stop_select = 0;
2249         unsigned int stop_count;
2250         int interrupt_a_enable = 0;
2251         unsigned ai_trig;
2252
2253         if (dev->irq == 0) {
2254                 dev_err(dev->class_dev, "cannot run command without an irq\n");
2255                 return -EIO;
2256         }
2257         ni_clear_ai_fifo(dev);
2258
2259         ni_load_channelgain_list(dev, s, cmd->chanlist_len, cmd->chanlist);
2260
2261         /* start configuration */
2262         ni_stc_writew(dev, AI_Configuration_Start, Joint_Reset_Register);
2263
2264         /* disable analog triggering for now, since it
2265          * interferes with the use of pfi0 */
2266         devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_ENA;
2267         ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG);
2268
2269         ai_trig = NISTC_AI_TRIG_START2_SEL(0) | NISTC_AI_TRIG_START1_SYNC;
2270         switch (cmd->start_src) {
2271         case TRIG_INT:
2272         case TRIG_NOW:
2273                 ai_trig |= NISTC_AI_TRIG_START1_EDGE |
2274                            NISTC_AI_TRIG_START1_SEL(0),
2275                            NISTC_AI_TRIG_SEL_REG;
2276                 break;
2277         case TRIG_EXT:
2278                 ai_trig |= NISTC_AI_TRIG_START1_SEL(CR_CHAN(cmd->start_arg) +
2279                                                     1);
2280
2281                 if (cmd->start_arg & CR_INVERT)
2282                         ai_trig |= NISTC_AI_TRIG_START1_POLARITY;
2283                 if (cmd->start_arg & CR_EDGE)
2284                         ai_trig |= NISTC_AI_TRIG_START1_EDGE;
2285                 break;
2286         }
2287         ni_stc_writew(dev, ai_trig, NISTC_AI_TRIG_SEL_REG);
2288
2289         mode2 &= ~NISTC_AI_MODE2_PRE_TRIGGER;
2290         mode2 &= ~NISTC_AI_MODE2_SC_INIT_LOAD_SRC;
2291         mode2 &= ~NISTC_AI_MODE2_SC_RELOAD_MODE;
2292         ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2293
2294         if (cmd->chanlist_len == 1 || devpriv->is_611x || devpriv->is_6143) {
2295                 /* logic low */
2296                 start_stop_select |= NISTC_AI_STOP_POLARITY |
2297                                      NISTC_AI_STOP_SEL(31) |
2298                                      NISTC_AI_STOP_SYNC;
2299         } else {
2300                 /*  ai configuration memory */
2301                 start_stop_select |= NISTC_AI_STOP_SEL(19);
2302         }
2303         ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2304
2305         devpriv->ai_cmd2 = 0;
2306         switch (cmd->stop_src) {
2307         case TRIG_COUNT:
2308                 stop_count = cmd->stop_arg - 1;
2309
2310                 if (devpriv->is_611x) {
2311                         /*  have to take 3 stage adc pipeline into account */
2312                         stop_count += num_adc_stages_611x;
2313                 }
2314                 /* stage number of scans */
2315                 ni_stc_writel(dev, stop_count, NISTC_AI_SC_LOADA_REG);
2316
2317                 mode1 |= NISTC_AI_MODE1_START_STOP |
2318                          NISTC_AI_MODE1_RSVD |
2319                          NISTC_AI_MODE1_TRIGGER_ONCE;
2320                 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2321                 /* load SC (Scan Count) */
2322                 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2323
2324                 if (stop_count == 0) {
2325                         devpriv->ai_cmd2 |= NISTC_AI_CMD2_END_ON_EOS;
2326                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2327                         /*  this is required to get the last sample for chanlist_len > 1, not sure why */
2328                         if (cmd->chanlist_len > 1)
2329                                 start_stop_select |= NISTC_AI_STOP_POLARITY |
2330                                                      NISTC_AI_STOP_EDGE;
2331                 }
2332                 break;
2333         case TRIG_NONE:
2334                 /* stage number of scans */
2335                 ni_stc_writel(dev, 0, NISTC_AI_SC_LOADA_REG);
2336
2337                 mode1 |= NISTC_AI_MODE1_START_STOP |
2338                          NISTC_AI_MODE1_RSVD |
2339                          NISTC_AI_MODE1_CONTINUOUS;
2340                 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2341
2342                 /* load SC (Scan Count) */
2343                 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2344                 break;
2345         }
2346
2347         switch (cmd->scan_begin_src) {
2348         case TRIG_TIMER:
2349                 /*
2350                  * stop bits for non 611x boards
2351                  * AI_SI_Special_Trigger_Delay=0
2352                  * NISTC_AI_MODE2_PRE_TRIGGER=0
2353                  * NISTC_AI_START_STOP_REG:
2354                  * NISTC_AI_START_POLARITY=0    (?) rising edge
2355                  * NISTC_AI_START_EDGE=1        edge triggered
2356                  * NISTC_AI_START_SYNC=1        (?)
2357                  * NISTC_AI_START_SEL=0         SI_TC
2358                  * NISTC_AI_STOP_POLARITY=0     rising edge
2359                  * NISTC_AI_STOP_EDGE=0         level
2360                  * NISTC_AI_STOP_SYNC=1
2361                  * NISTC_AI_STOP_SEL=19         external pin (configuration mem)
2362                  */
2363                 start_stop_select |= NISTC_AI_START_EDGE | NISTC_AI_START_SYNC;
2364                 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2365
2366                 mode2 &= ~NISTC_AI_MODE2_SI_INIT_LOAD_SRC;      /* A */
2367                 mode2 |= NISTC_AI_MODE2_SI_RELOAD_MODE(0);
2368                 /* mode2 |= NISTC_AI_MODE2_SC_RELOAD_MODE; */
2369                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2370
2371                 /* load SI */
2372                 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2373                                        CMDF_ROUND_NEAREST);
2374                 ni_stc_writel(dev, timer, NISTC_AI_SI_LOADA_REG);
2375                 ni_stc_writew(dev, NISTC_AI_CMD1_SI_LOAD, NISTC_AI_CMD1_REG);
2376                 break;
2377         case TRIG_EXT:
2378                 if (cmd->scan_begin_arg & CR_EDGE)
2379                         start_stop_select |= NISTC_AI_START_EDGE;
2380                 if (cmd->scan_begin_arg & CR_INVERT)    /* falling edge */
2381                         start_stop_select |= NISTC_AI_START_POLARITY;
2382                 if (cmd->scan_begin_src != cmd->convert_src ||
2383                     (cmd->scan_begin_arg & ~CR_EDGE) !=
2384                     (cmd->convert_arg & ~CR_EDGE))
2385                         start_stop_select |= NISTC_AI_START_SYNC;
2386                 start_stop_select |=
2387                     NISTC_AI_START_SEL(1 + CR_CHAN(cmd->scan_begin_arg));
2388                 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2389                 break;
2390         }
2391
2392         switch (cmd->convert_src) {
2393         case TRIG_TIMER:
2394         case TRIG_NOW:
2395                 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2396                         timer = 1;
2397                 else
2398                         timer = ni_ns_to_timer(dev, cmd->convert_arg,
2399                                                CMDF_ROUND_NEAREST);
2400                 /* 0,0 does not work */
2401                 ni_stc_writew(dev, 1, NISTC_AI_SI2_LOADA_REG);
2402                 ni_stc_writew(dev, timer, NISTC_AI_SI2_LOADB_REG);
2403
2404                 mode2 &= ~NISTC_AI_MODE2_SI2_INIT_LOAD_SRC;     /* A */
2405                 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE;        /* alternate */
2406                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2407
2408                 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_LOAD, NISTC_AI_CMD1_REG);
2409
2410                 mode2 |= NISTC_AI_MODE2_SI2_INIT_LOAD_SRC;      /* B */
2411                 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE;        /* alternate */
2412                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2413                 break;
2414         case TRIG_EXT:
2415                 mode1 |= NISTC_AI_MODE1_CONVERT_SRC(1 + cmd->convert_arg);
2416                 if ((cmd->convert_arg & CR_INVERT) == 0)
2417                         mode1 |= NISTC_AI_MODE1_CONVERT_POLARITY;
2418                 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2419
2420                 mode2 |= NISTC_AI_MODE2_SC_GATE_ENA |
2421                          NISTC_AI_MODE2_START_STOP_GATE_ENA;
2422                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2423
2424                 break;
2425         }
2426
2427         if (dev->irq) {
2428                 /* interrupt on FIFO, errors, SC_TC */
2429                 interrupt_a_enable |= AI_Error_Interrupt_Enable |
2430                     AI_SC_TC_Interrupt_Enable;
2431
2432 #ifndef PCIDMA
2433                 interrupt_a_enable |= AI_FIFO_Interrupt_Enable;
2434 #endif
2435
2436                 if ((cmd->flags & CMDF_WAKE_EOS) ||
2437                     (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)) {
2438                         /* wake on end-of-scan */
2439                         devpriv->aimode = AIMODE_SCAN;
2440                 } else {
2441                         devpriv->aimode = AIMODE_HALF_FULL;
2442                 }
2443
2444                 switch (devpriv->aimode) {
2445                 case AIMODE_HALF_FULL:
2446                         /*generate FIFO interrupts and DMA requests on half-full */
2447 #ifdef PCIDMA
2448                         ni_stc_writew(dev, AI_FIFO_Mode_HF_to_E,
2449                                       AI_Mode_3_Register);
2450 #else
2451                         ni_stc_writew(dev, AI_FIFO_Mode_HF,
2452                                       AI_Mode_3_Register);
2453 #endif
2454                         break;
2455                 case AIMODE_SAMPLE:
2456                         /*generate FIFO interrupts on non-empty */
2457                         ni_stc_writew(dev, AI_FIFO_Mode_NE,
2458                                       AI_Mode_3_Register);
2459                         break;
2460                 case AIMODE_SCAN:
2461 #ifdef PCIDMA
2462                         ni_stc_writew(dev, AI_FIFO_Mode_NE,
2463                                       AI_Mode_3_Register);
2464 #else
2465                         ni_stc_writew(dev, AI_FIFO_Mode_HF,
2466                                       AI_Mode_3_Register);
2467 #endif
2468                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2469                         break;
2470                 default:
2471                         break;
2472                 }
2473
2474                 /* clear interrupts */
2475                 ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
2476
2477                 ni_set_bits(dev, Interrupt_A_Enable_Register,
2478                             interrupt_a_enable, 1);
2479         } else {
2480                 /* interrupt on nothing */
2481                 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
2482
2483                 /* XXX start polling if necessary */
2484         }
2485
2486         /* end configuration */
2487         ni_stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
2488
2489         switch (cmd->scan_begin_src) {
2490         case TRIG_TIMER:
2491                 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2492                                    NISTC_AI_CMD1_SI_ARM |
2493                                    NISTC_AI_CMD1_DIV_ARM |
2494                                    NISTC_AI_CMD1_SC_ARM,
2495                               NISTC_AI_CMD1_REG);
2496                 break;
2497         case TRIG_EXT:
2498                 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2499                                    NISTC_AI_CMD1_SI_ARM |       /* XXX ? */
2500                                    NISTC_AI_CMD1_DIV_ARM |
2501                                    NISTC_AI_CMD1_SC_ARM,
2502                               NISTC_AI_CMD1_REG);
2503                 break;
2504         }
2505
2506 #ifdef PCIDMA
2507         {
2508                 int retval = ni_ai_setup_MITE_dma(dev);
2509
2510                 if (retval)
2511                         return retval;
2512         }
2513 #endif
2514
2515         if (cmd->start_src == TRIG_NOW) {
2516                 ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE |
2517                                    devpriv->ai_cmd2,
2518                               NISTC_AI_CMD2_REG);
2519                 s->async->inttrig = NULL;
2520         } else if (cmd->start_src == TRIG_EXT) {
2521                 s->async->inttrig = NULL;
2522         } else {        /* TRIG_INT */
2523                 s->async->inttrig = ni_ai_inttrig;
2524         }
2525
2526         return 0;
2527 }
2528
2529 static int ni_ai_insn_config(struct comedi_device *dev,
2530                              struct comedi_subdevice *s,
2531                              struct comedi_insn *insn, unsigned int *data)
2532 {
2533         struct ni_private *devpriv = dev->private;
2534
2535         if (insn->n < 1)
2536                 return -EINVAL;
2537
2538         switch (data[0]) {
2539         case INSN_CONFIG_ALT_SOURCE:
2540                 if (devpriv->is_m_series) {
2541                         if (data[1] & ~NI_M_CFG_BYPASS_AI_CAL_MASK)
2542                                 return -EINVAL;
2543                         devpriv->ai_calib_source = data[1];
2544                 } else if (devpriv->is_6143) {
2545                         unsigned int calib_source;
2546
2547                         calib_source = data[1] & 0xf;
2548
2549                         devpriv->ai_calib_source = calib_source;
2550                         ni_writew(dev, calib_source, Calibration_Channel_6143);
2551                 } else {
2552                         unsigned int calib_source;
2553                         unsigned int calib_source_adjust;
2554
2555                         calib_source = data[1] & 0xf;
2556                         calib_source_adjust = (data[1] >> 4) & 0xff;
2557
2558                         if (calib_source >= 8)
2559                                 return -EINVAL;
2560                         devpriv->ai_calib_source = calib_source;
2561                         if (devpriv->is_611x) {
2562                                 ni_writeb(dev, calib_source_adjust,
2563                                           Cal_Gain_Select_611x);
2564                         }
2565                 }
2566                 return 2;
2567         default:
2568                 break;
2569         }
2570
2571         return -EINVAL;
2572 }
2573
2574 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2575                         void *data, unsigned int num_bytes,
2576                         unsigned int chan_index)
2577 {
2578         struct comedi_cmd *cmd = &s->async->cmd;
2579         unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
2580         unsigned short *array = data;
2581         unsigned int i;
2582
2583         for (i = 0; i < nsamples; i++) {
2584                 unsigned int range = CR_RANGE(cmd->chanlist[chan_index]);
2585                 unsigned short val = array[i];
2586
2587                 /*
2588                  * Munge data from unsigned to two's complement for
2589                  * bipolar ranges.
2590                  */
2591                 if (comedi_range_is_bipolar(s, range))
2592                         val = comedi_offset_munge(s, val);
2593 #ifdef PCIDMA
2594                 val = cpu_to_le16(val);
2595 #endif
2596                 array[i] = val;
2597
2598                 chan_index++;
2599                 chan_index %= cmd->chanlist_len;
2600         }
2601 }
2602
2603 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2604                                           struct comedi_subdevice *s,
2605                                           unsigned int chanspec[],
2606                                           unsigned int n_chans, int timed)
2607 {
2608         struct ni_private *devpriv = dev->private;
2609         unsigned int range;
2610         unsigned int chan;
2611         unsigned int conf;
2612         int i;
2613         int invert = 0;
2614
2615         if (timed) {
2616                 for (i = 0; i < s->n_chan; ++i) {
2617                         devpriv->ao_conf[i] &= ~NI_M_AO_CFG_BANK_UPDATE_TIMED;
2618                         ni_writeb(dev, devpriv->ao_conf[i],
2619                                   NI_M_AO_CFG_BANK_REG(i));
2620                         ni_writeb(dev, 0xf, NI_M_AO_WAVEFORM_ORDER_REG(i));
2621                 }
2622         }
2623         for (i = 0; i < n_chans; i++) {
2624                 const struct comedi_krange *krange;
2625
2626                 chan = CR_CHAN(chanspec[i]);
2627                 range = CR_RANGE(chanspec[i]);
2628                 krange = s->range_table->range + range;
2629                 invert = 0;
2630                 conf = 0;
2631                 switch (krange->max - krange->min) {
2632                 case 20000000:
2633                         conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2634                         ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2635                         break;
2636                 case 10000000:
2637                         conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2638                         ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2639                         break;
2640                 case 4000000:
2641                         conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2642                         ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2643                                   NI_M_AO_REF_ATTENUATION_REG(chan));
2644                         break;
2645                 case 2000000:
2646                         conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2647                         ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2648                                   NI_M_AO_REF_ATTENUATION_REG(chan));
2649                         break;
2650                 default:
2651                         dev_err(dev->class_dev,
2652                                 "bug! unhandled ao reference voltage\n");
2653                         break;
2654                 }
2655                 switch (krange->max + krange->min) {
2656                 case 0:
2657                         conf |= NI_M_AO_CFG_BANK_OFFSET_0V;
2658                         break;
2659                 case 10000000:
2660                         conf |= NI_M_AO_CFG_BANK_OFFSET_5V;
2661                         break;
2662                 default:
2663                         dev_err(dev->class_dev,
2664                                 "bug! unhandled ao offset voltage\n");
2665                         break;
2666                 }
2667                 if (timed)
2668                         conf |= NI_M_AO_CFG_BANK_UPDATE_TIMED;
2669                 ni_writeb(dev, conf, NI_M_AO_CFG_BANK_REG(chan));
2670                 devpriv->ao_conf[chan] = conf;
2671                 ni_writeb(dev, i, NI_M_AO_WAVEFORM_ORDER_REG(chan));
2672         }
2673         return invert;
2674 }
2675
2676 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2677                                      struct comedi_subdevice *s,
2678                                      unsigned int chanspec[],
2679                                      unsigned int n_chans)
2680 {
2681         struct ni_private *devpriv = dev->private;
2682         unsigned int range;
2683         unsigned int chan;
2684         unsigned int conf;
2685         int i;
2686         int invert = 0;
2687
2688         for (i = 0; i < n_chans; i++) {
2689                 chan = CR_CHAN(chanspec[i]);
2690                 range = CR_RANGE(chanspec[i]);
2691                 conf = AO_Channel(chan);
2692
2693                 if (comedi_range_is_bipolar(s, range)) {
2694                         conf |= AO_Bipolar;
2695                         invert = (s->maxdata + 1) >> 1;
2696                 } else {
2697                         invert = 0;
2698                 }
2699                 if (comedi_range_is_external(s, range))
2700                         conf |= AO_Ext_Ref;
2701
2702                 /* not all boards can deglitch, but this shouldn't hurt */
2703                 if (chanspec[i] & CR_DEGLITCH)
2704                         conf |= AO_Deglitch;
2705
2706                 /* analog reference */
2707                 /* AREF_OTHER connects AO ground to AI ground, i think */
2708                 conf |= (CR_AREF(chanspec[i]) ==
2709                          AREF_OTHER) ? AO_Ground_Ref : 0;
2710
2711                 ni_writew(dev, conf, AO_Configuration);
2712                 devpriv->ao_conf[chan] = conf;
2713         }
2714         return invert;
2715 }
2716
2717 static int ni_ao_config_chanlist(struct comedi_device *dev,
2718                                  struct comedi_subdevice *s,
2719                                  unsigned int chanspec[], unsigned int n_chans,
2720                                  int timed)
2721 {
2722         struct ni_private *devpriv = dev->private;
2723
2724         if (devpriv->is_m_series)
2725                 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
2726                                                       timed);
2727         else
2728                 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2729 }
2730
2731 static int ni_ao_insn_write(struct comedi_device *dev,
2732                             struct comedi_subdevice *s,
2733                             struct comedi_insn *insn,
2734                             unsigned int *data)
2735 {
2736         struct ni_private *devpriv = dev->private;
2737         unsigned int chan = CR_CHAN(insn->chanspec);
2738         unsigned int range = CR_RANGE(insn->chanspec);
2739         int reg;
2740         int i;
2741
2742         if (devpriv->is_6xxx) {
2743                 ni_ao_win_outw(dev, 1 << chan, AO_Immediate_671x);
2744
2745                 reg = DACx_Direct_Data_671x(chan);
2746         } else if (devpriv->is_m_series) {
2747                 reg = NI_M_DAC_DIRECT_DATA_REG(chan);
2748         } else {
2749                 reg = (chan) ? DAC1_Direct_Data : DAC0_Direct_Data;
2750         }
2751
2752         ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2753
2754         for (i = 0; i < insn->n; i++) {
2755                 unsigned int val = data[i];
2756
2757                 s->readback[chan] = val;
2758
2759                 if (devpriv->is_6xxx) {
2760                         /*
2761                          * 6xxx boards have bipolar outputs, munge the
2762                          * unsigned comedi values to 2's complement
2763                          */
2764                         val = comedi_offset_munge(s, val);
2765
2766                         ni_ao_win_outw(dev, val, reg);
2767                 } else if (devpriv->is_m_series) {
2768                         /*
2769                          * M-series boards use offset binary values for
2770                          * bipolar and uinpolar outputs
2771                          */
2772                         ni_writew(dev, val, reg);
2773                 } else {
2774                         /*
2775                          * Non-M series boards need two's complement values
2776                          * for bipolar ranges.
2777                          */
2778                         if (comedi_range_is_bipolar(s, range))
2779                                 val = comedi_offset_munge(s, val);
2780
2781                         ni_writew(dev, val, reg);
2782                 }
2783         }
2784
2785         return insn->n;
2786 }
2787
2788 static int ni_ao_insn_config(struct comedi_device *dev,
2789                              struct comedi_subdevice *s,
2790                              struct comedi_insn *insn, unsigned int *data)
2791 {
2792         const struct ni_board_struct *board = dev->board_ptr;
2793         struct ni_private *devpriv = dev->private;
2794         unsigned int nbytes;
2795
2796         switch (data[0]) {
2797         case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
2798                 switch (data[1]) {
2799                 case COMEDI_OUTPUT:
2800                         nbytes = comedi_samples_to_bytes(s,
2801                                                          board->ao_fifo_depth);
2802                         data[2] = 1 + nbytes;
2803                         if (devpriv->mite)
2804                                 data[2] += devpriv->mite->fifo_size;
2805                         break;
2806                 case COMEDI_INPUT:
2807                         data[2] = 0;
2808                         break;
2809                 default:
2810                         return -EINVAL;
2811                 }
2812                 return 0;
2813         default:
2814                 break;
2815         }
2816
2817         return -EINVAL;
2818 }
2819
2820 static int ni_ao_inttrig(struct comedi_device *dev,
2821                          struct comedi_subdevice *s,
2822                          unsigned int trig_num)
2823 {
2824         struct ni_private *devpriv = dev->private;
2825         struct comedi_cmd *cmd = &s->async->cmd;
2826         int ret;
2827         int interrupt_b_bits;
2828         int i;
2829         static const int timeout = 1000;
2830
2831         if (trig_num != cmd->start_arg)
2832                 return -EINVAL;
2833
2834         /* Null trig at beginning prevent ao start trigger from executing more than
2835            once per command (and doing things like trying to allocate the ao dma channel
2836            multiple times) */
2837         s->async->inttrig = NULL;
2838
2839         ni_set_bits(dev, Interrupt_B_Enable_Register,
2840                     AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
2841         interrupt_b_bits = AO_Error_Interrupt_Enable;
2842 #ifdef PCIDMA
2843         ni_stc_writew(dev, 1, DAC_FIFO_Clear);
2844         if (devpriv->is_6xxx)
2845                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
2846         ret = ni_ao_setup_MITE_dma(dev);
2847         if (ret)
2848                 return ret;
2849         ret = ni_ao_wait_for_dma_load(dev);
2850         if (ret < 0)
2851                 return ret;
2852 #else
2853         ret = ni_ao_prep_fifo(dev, s);
2854         if (ret == 0)
2855                 return -EPIPE;
2856
2857         interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
2858 #endif
2859
2860         ni_stc_writew(dev, devpriv->ao_mode3 | AO_Not_An_UPDATE,
2861                       AO_Mode_3_Register);
2862         ni_stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
2863         /* wait for DACs to be loaded */
2864         for (i = 0; i < timeout; i++) {
2865                 udelay(1);
2866                 if ((ni_stc_readw(dev, Joint_Status_2_Register) &
2867                      AO_TMRDACWRs_In_Progress_St) == 0)
2868                         break;
2869         }
2870         if (i == timeout) {
2871                 dev_err(dev->class_dev,
2872                         "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear\n");
2873                 return -EIO;
2874         }
2875         /*
2876          * stc manual says we are need to clear error interrupt after
2877          * AO_TMRDACWRs_In_Progress_St clears
2878          */
2879         ni_stc_writew(dev, NISTC_INTB_ACK_AO_ERR, NISTC_INTB_ACK_REG);
2880
2881         ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
2882
2883         ni_stc_writew(dev, NISTC_AO_CMD1_UI_ARM |
2884                            NISTC_AO_CMD1_UC_ARM |
2885                            NISTC_AO_CMD1_BC_ARM |
2886                            NISTC_AO_CMD1_DAC1_UPDATE_MODE |
2887                            NISTC_AO_CMD1_DAC0_UPDATE_MODE |
2888                            devpriv->ao_cmd1,
2889                       NISTC_AO_CMD1_REG);
2890
2891         ni_stc_writew(dev, NISTC_AO_CMD2_START1_PULSE | devpriv->ao_cmd2,
2892                       NISTC_AO_CMD2_REG);
2893
2894         return 0;
2895 }
2896
2897 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2898 {
2899         const struct ni_board_struct *board = dev->board_ptr;
2900         struct ni_private *devpriv = dev->private;
2901         const struct comedi_cmd *cmd = &s->async->cmd;
2902         int bits;
2903         int i;
2904         unsigned trigvar;
2905
2906         if (dev->irq == 0) {
2907                 dev_err(dev->class_dev, "cannot run command without an irq\n");
2908                 return -EIO;
2909         }
2910
2911         ni_stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
2912
2913         ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);
2914
2915         if (devpriv->is_6xxx) {
2916                 ni_ao_win_outw(dev, CLEAR_WG, AO_Misc_611x);
2917
2918                 bits = 0;
2919                 for (i = 0; i < cmd->chanlist_len; i++) {
2920                         int chan;
2921
2922                         chan = CR_CHAN(cmd->chanlist[i]);
2923                         bits |= 1 << chan;
2924                         ni_ao_win_outw(dev, chan, AO_Waveform_Generation_611x);
2925                 }
2926                 ni_ao_win_outw(dev, bits, AO_Timed_611x);
2927         }
2928
2929         ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
2930
2931         if (cmd->stop_src == TRIG_NONE) {
2932                 devpriv->ao_mode1 |= NISTC_AO_MODE1_CONTINUOUS;
2933                 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_TRIGGER_ONCE;
2934         } else {
2935                 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_CONTINUOUS;
2936                 devpriv->ao_mode1 |= NISTC_AO_MODE1_TRIGGER_ONCE;
2937         }
2938         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
2939         switch (cmd->start_src) {
2940         case TRIG_INT:
2941         case TRIG_NOW:
2942                 devpriv->ao_trigger_select &=
2943                     ~(AO_START1_Polarity | AO_START1_Select(-1));
2944                 devpriv->ao_trigger_select |= AO_START1_Edge | AO_START1_Sync;
2945                 ni_stc_writew(dev, devpriv->ao_trigger_select,
2946                               AO_Trigger_Select_Register);
2947                 break;
2948         case TRIG_EXT:
2949                 devpriv->ao_trigger_select =
2950                     AO_START1_Select(CR_CHAN(cmd->start_arg) + 1);
2951                 if (cmd->start_arg & CR_INVERT)
2952                         devpriv->ao_trigger_select |= AO_START1_Polarity;       /*  0=active high, 1=active low. see daq-stc 3-24 (p186) */
2953                 if (cmd->start_arg & CR_EDGE)
2954                         devpriv->ao_trigger_select |= AO_START1_Edge;   /*  0=edge detection disabled, 1=enabled */
2955                 ni_stc_writew(dev, devpriv->ao_trigger_select,
2956                               AO_Trigger_Select_Register);
2957                 break;
2958         default:
2959                 BUG();
2960                 break;
2961         }
2962         devpriv->ao_mode3 &= ~AO_Trigger_Length;
2963         ni_stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
2964
2965         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
2966         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_BC_INIT_LOAD_SRC;
2967         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
2968         if (cmd->stop_src == TRIG_NONE)
2969                 ni_stc_writel(dev, 0xffffff, NISTC_AO_BC_LOADA_REG);
2970         else
2971                 ni_stc_writel(dev, 0, NISTC_AO_BC_LOADA_REG);
2972         ni_stc_writew(dev, NISTC_AO_CMD1_BC_LOAD, NISTC_AO_CMD1_REG);
2973         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_UC_INIT_LOAD_SRC;
2974         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
2975         switch (cmd->stop_src) {
2976         case TRIG_COUNT:
2977                 if (devpriv->is_m_series) {
2978                         /*  this is how the NI example code does it for m-series boards, verified correct with 6259 */
2979                         ni_stc_writel(dev, cmd->stop_arg - 1,
2980                                       NISTC_AO_UC_LOADA_REG);
2981                         ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
2982                                       NISTC_AO_CMD1_REG);
2983                 } else {
2984                         ni_stc_writel(dev, cmd->stop_arg,
2985                                       NISTC_AO_UC_LOADA_REG);
2986                         ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
2987                                       NISTC_AO_CMD1_REG);
2988                         ni_stc_writel(dev, cmd->stop_arg - 1,
2989                                       NISTC_AO_UC_LOADA_REG);
2990                 }
2991                 break;
2992         case TRIG_NONE:
2993                 ni_stc_writel(dev, 0xffffff, NISTC_AO_UC_LOADA_REG);
2994                 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD, NISTC_AO_CMD1_REG);
2995                 ni_stc_writel(dev, 0xffffff, NISTC_AO_UC_LOADA_REG);
2996                 break;
2997         default:
2998                 ni_stc_writel(dev, 0, NISTC_AO_UC_LOADA_REG);
2999                 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD, NISTC_AO_CMD1_REG);
3000                 ni_stc_writel(dev, cmd->stop_arg, NISTC_AO_UC_LOADA_REG);
3001         }
3002
3003         devpriv->ao_mode1 &= ~(NISTC_AO_MODE1_UPDATE_SRC_MASK |
3004                                NISTC_AO_MODE1_UI_SRC_MASK |
3005                                NISTC_AO_MODE1_UPDATE_SRC_POLARITY |
3006                                NISTC_AO_MODE1_UI_SRC_POLARITY);
3007         switch (cmd->scan_begin_src) {
3008         case TRIG_TIMER:
3009                 devpriv->ao_cmd2 &= ~NISTC_AO_CMD2_BC_GATE_ENA;
3010                 trigvar =
3011                     ni_ns_to_timer(dev, cmd->scan_begin_arg,
3012                                    CMDF_ROUND_NEAREST);
3013                 ni_stc_writel(dev, 1, NISTC_AO_UI_LOADA_REG);
3014                 ni_stc_writew(dev, NISTC_AO_CMD1_UI_LOAD, NISTC_AO_CMD1_REG);
3015                 ni_stc_writel(dev, trigvar, NISTC_AO_UI_LOADA_REG);
3016                 break;
3017         case TRIG_EXT:
3018                 devpriv->ao_mode1 |=
3019                     NISTC_AO_MODE1_UPDATE_SRC(cmd->scan_begin_arg);
3020                 if (cmd->scan_begin_arg & CR_INVERT)
3021                         devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC_POLARITY;
3022                 devpriv->ao_cmd2 |= NISTC_AO_CMD2_BC_GATE_ENA;
3023                 break;
3024         default:
3025                 BUG();
3026                 break;
3027         }
3028         ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG);
3029         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3030         devpriv->ao_mode2 &= ~(NISTC_AO_MODE2_UI_RELOAD_MODE(3) |
3031                                NISTC_AO_MODE2_UI_INIT_LOAD_SRC);
3032         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3033
3034         if (cmd->scan_end_arg > 1) {
3035                 devpriv->ao_mode1 |= NISTC_AO_MODE1_MULTI_CHAN;
3036                 ni_stc_writew(dev,
3037                               AO_Number_Of_Channels(cmd->scan_end_arg - 1) |
3038                               AO_UPDATE_Output_Select(AO_Update_Output_High_Z),
3039                               AO_Output_Control_Register);
3040         } else {
3041                 unsigned bits;
3042
3043                 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_MULTI_CHAN;
3044                 bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z);
3045                 if (devpriv->is_m_series || devpriv->is_6xxx) {
3046                         bits |= AO_Number_Of_Channels(0);
3047                 } else {
3048                         bits |=
3049                             AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0]));
3050                 }
3051                 ni_stc_writew(dev, bits, AO_Output_Control_Register);
3052         }
3053         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3054
3055         ni_stc_writew(dev, NISTC_AO_CMD1_DAC1_UPDATE_MODE |
3056                            NISTC_AO_CMD1_DAC0_UPDATE_MODE,
3057                       NISTC_AO_CMD1_REG);
3058
3059         devpriv->ao_mode3 |= AO_Stop_On_Overrun_Error;
3060         ni_stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3061
3062         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_MODE_MASK;
3063 #ifdef PCIDMA
3064         devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF_F;
3065 #else
3066         devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF;
3067 #endif
3068         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_REXMIT_ENA;
3069         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3070
3071         bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3072             AO_TMRDACWR_Pulse_Width;
3073         if (board->ao_fifo_depth)
3074                 bits |= AO_FIFO_Enable;
3075         else
3076                 bits |= AO_DMA_PIO_Control;
3077 #if 0
3078         /* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281,
3079            verified with bus analyzer. */
3080         if (devpriv->is_m_series)
3081                 bits |= AO_Number_Of_DAC_Packages;
3082 #endif
3083         ni_stc_writew(dev, bits, AO_Personal_Register);
3084         /*  enable sending of ao dma requests */
3085         ni_stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
3086
3087         ni_stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3088
3089         if (cmd->stop_src == TRIG_COUNT) {
3090                 ni_stc_writew(dev, NISTC_INTB_ACK_AO_BC_TC,
3091                               NISTC_INTB_ACK_REG);
3092                 ni_set_bits(dev, Interrupt_B_Enable_Register,
3093                             AO_BC_TC_Interrupt_Enable, 1);
3094         }
3095
3096         s->async->inttrig = ni_ao_inttrig;
3097
3098         return 0;
3099 }
3100
3101 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3102                          struct comedi_cmd *cmd)
3103 {
3104         const struct ni_board_struct *board = dev->board_ptr;
3105         struct ni_private *devpriv = dev->private;
3106         int err = 0;
3107         unsigned int tmp;
3108
3109         /* Step 1 : check if triggers are trivially valid */
3110
3111         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3112         err |= comedi_check_trigger_src(&cmd->scan_begin_src,
3113                                         TRIG_TIMER | TRIG_EXT);
3114         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3115         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3116         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3117
3118         if (err)
3119                 return 1;
3120
3121         /* Step 2a : make sure trigger sources are unique */
3122
3123         err |= comedi_check_trigger_is_unique(cmd->start_src);
3124         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
3125         err |= comedi_check_trigger_is_unique(cmd->stop_src);
3126
3127         /* Step 2b : and mutually compatible */
3128
3129         if (err)
3130                 return 2;
3131
3132         /* Step 3: check if arguments are trivially valid */
3133
3134         switch (cmd->start_src) {
3135         case TRIG_INT:
3136                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3137                 break;
3138         case TRIG_EXT:
3139                 tmp = CR_CHAN(cmd->start_arg);
3140
3141                 if (tmp > 18)
3142                         tmp = 18;
3143                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3144                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
3145                 break;
3146         }
3147
3148         if (cmd->scan_begin_src == TRIG_TIMER) {
3149                 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
3150                                                     board->ao_speed);
3151                 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
3152                                                     devpriv->clock_ns *
3153                                                     0xffffff);
3154         }
3155
3156         err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3157         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3158                                            cmd->chanlist_len);
3159
3160         if (cmd->stop_src == TRIG_COUNT)
3161                 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3162         else    /* TRIG_NONE */
3163                 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
3164
3165         if (err)
3166                 return 3;
3167
3168         /* step 4: fix up any arguments */
3169         if (cmd->scan_begin_src == TRIG_TIMER) {
3170                 tmp = cmd->scan_begin_arg;
3171                 cmd->scan_begin_arg =
3172                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3173                                                        cmd->scan_begin_arg,
3174                                                        cmd->flags));
3175                 if (tmp != cmd->scan_begin_arg)
3176                         err++;
3177         }
3178         if (err)
3179                 return 4;
3180
3181         return 0;
3182 }
3183
3184 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3185 {
3186         struct ni_private *devpriv = dev->private;
3187
3188         ni_release_ao_mite_channel(dev);
3189
3190         ni_stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3191         ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);
3192         ni_set_bits(dev, Interrupt_B_Enable_Register, ~0, 0);
3193         ni_stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
3194         ni_stc_writew(dev, NISTC_INTB_ACK_AO_ALL, NISTC_INTB_ACK_REG);
3195         ni_stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3196                       AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
3197         ni_stc_writew(dev, 0, AO_Output_Control_Register);
3198         ni_stc_writew(dev, 0, AO_Start_Select_Register);
3199         devpriv->ao_cmd1 = 0;
3200         ni_stc_writew(dev, devpriv->ao_cmd1, NISTC_AO_CMD1_REG);
3201         devpriv->ao_cmd2 = 0;
3202         ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG);
3203         devpriv->ao_mode1 = 0;
3204         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3205         devpriv->ao_mode2 = 0;
3206         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3207         if (devpriv->is_m_series)
3208                 devpriv->ao_mode3 = AO_Last_Gate_Disable;
3209         else
3210                 devpriv->ao_mode3 = 0;
3211         ni_stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3212         devpriv->ao_trigger_select = 0;
3213         ni_stc_writew(dev, devpriv->ao_trigger_select,
3214                       AO_Trigger_Select_Register);
3215         if (devpriv->is_6xxx) {
3216                 unsigned immediate_bits = 0;
3217                 unsigned i;
3218
3219                 for (i = 0; i < s->n_chan; ++i)
3220                         immediate_bits |= 1 << i;
3221                 ni_ao_win_outw(dev, immediate_bits, AO_Immediate_671x);
3222                 ni_ao_win_outw(dev, CLEAR_WG, AO_Misc_611x);
3223         }
3224         ni_stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3225
3226         return 0;
3227 }
3228
3229 /* digital io */
3230
3231 static int ni_dio_insn_config(struct comedi_device *dev,
3232                               struct comedi_subdevice *s,
3233                               struct comedi_insn *insn,
3234                               unsigned int *data)
3235 {
3236         struct ni_private *devpriv = dev->private;
3237         int ret;
3238
3239         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3240         if (ret)
3241                 return ret;
3242
3243         devpriv->dio_control &= ~NISTC_DIO_CTRL_DIR_MASK;
3244         devpriv->dio_control |= NISTC_DIO_CTRL_DIR(s->io_bits);
3245         ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3246
3247         return insn->n;
3248 }
3249
3250 static int ni_dio_insn_bits(struct comedi_device *dev,
3251                             struct comedi_subdevice *s,
3252                             struct comedi_insn *insn,
3253                             unsigned int *data)
3254 {
3255         struct ni_private *devpriv = dev->private;
3256
3257         /* Make sure we're not using the serial part of the dio */
3258         if ((data[0] & (NISTC_DIO_SDIN | NISTC_DIO_SDOUT)) &&
3259             devpriv->serial_interval_ns)
3260                 return -EBUSY;
3261
3262         if (comedi_dio_update_state(s, data)) {
3263                 devpriv->dio_output &= ~NISTC_DIO_OUT_PARALLEL_MASK;
3264                 devpriv->dio_output |= NISTC_DIO_OUT_PARALLEL(s->state);
3265                 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3266         }
3267
3268         data[1] = ni_stc_readw(dev, DIO_Parallel_Input_Register);
3269
3270         return insn->n;
3271 }
3272
3273 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3274                                        struct comedi_subdevice *s,
3275                                        struct comedi_insn *insn,
3276                                        unsigned int *data)
3277 {
3278         int ret;
3279
3280         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3281         if (ret)
3282                 return ret;
3283
3284         ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
3285
3286         return insn->n;
3287 }
3288
3289 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3290                                      struct comedi_subdevice *s,
3291                                      struct comedi_insn *insn,
3292                                      unsigned int *data)
3293 {
3294         if (comedi_dio_update_state(s, data))
3295                 ni_writel(dev, s->state, NI_M_DIO_REG);
3296
3297         data[1] = ni_readl(dev, NI_M_DIO_REG);
3298
3299         return insn->n;
3300 }
3301
3302 static int ni_cdio_check_chanlist(struct comedi_device *dev,
3303                                   struct comedi_subdevice *s,
3304                                   struct comedi_cmd *cmd)
3305 {
3306         int i;
3307
3308         for (i = 0; i < cmd->chanlist_len; ++i) {
3309                 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3310
3311                 if (chan != i)
3312                         return -EINVAL;
3313         }
3314
3315         return 0;
3316 }
3317
3318 static int ni_cdio_cmdtest(struct comedi_device *dev,
3319                            struct comedi_subdevice *s, struct comedi_cmd *cmd)
3320 {
3321         int err = 0;
3322         int tmp;
3323
3324         /* Step 1 : check if triggers are trivially valid */
3325
3326         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT);
3327         err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3328         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3329         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3330         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3331
3332         if (err)
3333                 return 1;
3334
3335         /* Step 2a : make sure trigger sources are unique */
3336         /* Step 2b : and mutually compatible */
3337
3338         /* Step 3: check if arguments are trivially valid */
3339
3340         err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3341
3342         tmp = cmd->scan_begin_arg;
3343         tmp &= CR_PACK_FLAGS(NI_M_CDO_MODE_SAMPLE_SRC_MASK, 0, 0, CR_INVERT);
3344         if (tmp != cmd->scan_begin_arg)
3345                 err |= -EINVAL;
3346
3347         err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3348         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3349                                            cmd->chanlist_len);
3350         err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
3351
3352         if (err)
3353                 return 3;
3354
3355         /* Step 4: fix up any arguments */
3356
3357         /* Step 5: check channel list if it exists */
3358
3359         if (cmd->chanlist && cmd->chanlist_len > 0)
3360                 err |= ni_cdio_check_chanlist(dev, s, cmd);
3361
3362         if (err)
3363                 return 5;
3364
3365         return 0;
3366 }
3367
3368 static int ni_cdo_inttrig(struct comedi_device *dev,
3369                           struct comedi_subdevice *s,
3370                           unsigned int trig_num)
3371 {
3372         struct comedi_cmd *cmd = &s->async->cmd;
3373         const unsigned timeout = 1000;
3374         int retval = 0;
3375         unsigned i;
3376 #ifdef PCIDMA
3377         struct ni_private *devpriv = dev->private;
3378         unsigned long flags;
3379 #endif
3380
3381         if (trig_num != cmd->start_arg)
3382                 return -EINVAL;
3383
3384         s->async->inttrig = NULL;
3385
3386         /* read alloc the entire buffer */
3387         comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
3388
3389 #ifdef PCIDMA
3390         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3391         if (devpriv->cdo_mite_chan) {
3392                 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3393                 mite_dma_arm(devpriv->cdo_mite_chan);
3394         } else {
3395                 dev_err(dev->class_dev, "BUG: no cdo mite channel?\n");
3396                 retval = -EIO;
3397         }
3398         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3399         if (retval < 0)
3400                 return retval;
3401 #endif
3402         /*
3403          * XXX not sure what interrupt C group does
3404          * wait for dma to fill output fifo
3405          * ni_writeb(dev, NI_M_INTC_ENA, NI_M_INTC_ENA_REG);
3406          */
3407         for (i = 0; i < timeout; ++i) {
3408                 if (ni_readl(dev, NI_M_CDIO_STATUS_REG) &
3409                     NI_M_CDIO_STATUS_CDO_FIFO_FULL)
3410                         break;
3411                 udelay(10);
3412         }
3413         if (i == timeout) {
3414                 dev_err(dev->class_dev, "dma failed to fill cdo fifo!\n");
3415                 s->cancel(dev, s);
3416                 return -EIO;
3417         }
3418         ni_writel(dev, NI_M_CDO_CMD_ARM |
3419                        NI_M_CDO_CMD_ERR_INT_ENA_SET |
3420                        NI_M_CDO_CMD_F_E_INT_ENA_SET,
3421                   NI_M_CDIO_CMD_REG);
3422         return retval;
3423 }
3424
3425 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3426 {
3427         const struct comedi_cmd *cmd = &s->async->cmd;
3428         unsigned cdo_mode_bits;
3429         int retval;
3430
3431         ni_writel(dev, NI_M_CDO_CMD_RESET, NI_M_CDIO_CMD_REG);
3432         cdo_mode_bits = NI_M_CDO_MODE_FIFO_MODE |
3433                         NI_M_CDO_MODE_HALT_ON_ERROR |
3434                         NI_M_CDO_MODE_SAMPLE_SRC(CR_CHAN(cmd->scan_begin_arg));
3435         if (cmd->scan_begin_arg & CR_INVERT)
3436                 cdo_mode_bits |= NI_M_CDO_MODE_POLARITY;
3437         ni_writel(dev, cdo_mode_bits, NI_M_CDO_MODE_REG);
3438         if (s->io_bits) {
3439                 ni_writel(dev, s->state, NI_M_CDO_FIFO_DATA_REG);
3440                 ni_writel(dev, NI_M_CDO_CMD_SW_UPDATE, NI_M_CDIO_CMD_REG);
3441                 ni_writel(dev, s->io_bits, NI_M_CDO_MASK_ENA_REG);
3442         } else {
3443                 dev_err(dev->class_dev,
3444                         "attempted to run digital output command with no lines configured as outputs\n");
3445                 return -EIO;
3446         }
3447         retval = ni_request_cdo_mite_channel(dev);
3448         if (retval < 0)
3449                 return retval;
3450
3451         s->async->inttrig = ni_cdo_inttrig;
3452
3453         return 0;
3454 }
3455
3456 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3457 {
3458         ni_writel(dev, NI_M_CDO_CMD_DISARM |
3459                        NI_M_CDO_CMD_ERR_INT_ENA_CLR |
3460                        NI_M_CDO_CMD_F_E_INT_ENA_CLR |
3461                        NI_M_CDO_CMD_F_REQ_INT_ENA_CLR,
3462                   NI_M_CDIO_CMD_REG);
3463         /*
3464          * XXX not sure what interrupt C group does
3465          * ni_writeb(dev, 0, NI_M_INTC_ENA_REG);
3466          */
3467         ni_writel(dev, 0, NI_M_CDO_MASK_ENA_REG);
3468         ni_release_cdo_mite_channel(dev);
3469         return 0;
3470 }
3471
3472 static void handle_cdio_interrupt(struct comedi_device *dev)
3473 {
3474         struct ni_private *devpriv = dev->private;
3475         unsigned cdio_status;
3476         struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3477 #ifdef PCIDMA
3478         unsigned long flags;
3479 #endif
3480
3481         if (!devpriv->is_m_series)
3482                 return;
3483 #ifdef PCIDMA
3484         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3485         if (devpriv->cdo_mite_chan) {
3486                 unsigned cdo_mite_status =
3487                     mite_get_status(devpriv->cdo_mite_chan);
3488                 if (cdo_mite_status & CHSR_LINKC) {
3489                         writel(CHOR_CLRLC,
3490                                devpriv->mite->mite_io_addr +
3491                                MITE_CHOR(devpriv->cdo_mite_chan->channel));
3492                 }
3493                 mite_sync_output_dma(devpriv->cdo_mite_chan, s);
3494         }
3495         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3496 #endif
3497
3498         cdio_status = ni_readl(dev, NI_M_CDIO_STATUS_REG);
3499         if (cdio_status & NI_M_CDIO_STATUS_CDO_ERROR) {
3500                 /* XXX just guessing this is needed and does something useful */
3501                 ni_writel(dev, NI_M_CDO_CMD_ERR_INT_CONFIRM,
3502                           NI_M_CDIO_CMD_REG);
3503                 s->async->events |= COMEDI_CB_OVERFLOW;
3504         }
3505         if (cdio_status & NI_M_CDIO_STATUS_CDO_FIFO_EMPTY) {
3506                 ni_writel(dev, NI_M_CDO_CMD_F_E_INT_ENA_CLR,
3507                           NI_M_CDIO_CMD_REG);
3508                 /* s->async->events |= COMEDI_CB_EOA; */
3509         }
3510         comedi_handle_events(dev, s);
3511 }
3512
3513 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3514                                    struct comedi_subdevice *s,
3515                                    unsigned char data_out,
3516                                    unsigned char *data_in)
3517 {
3518         struct ni_private *devpriv = dev->private;
3519         unsigned int status1;
3520         int err = 0, count = 20;
3521
3522         devpriv->dio_output &= ~NISTC_DIO_OUT_SERIAL_MASK;
3523         devpriv->dio_output |= NISTC_DIO_OUT_SERIAL(data_out);
3524         ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3525
3526         status1 = ni_stc_readw(dev, Joint_Status_1_Register);
3527         if (status1 & DIO_Serial_IO_In_Progress_St) {
3528                 err = -EBUSY;
3529                 goto Error;
3530         }
3531
3532         devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_START;
3533         ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3534         devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_START;
3535
3536         /* Wait until STC says we're done, but don't loop infinitely. */
3537         while ((status1 = ni_stc_readw(dev, Joint_Status_1_Register)) &
3538                DIO_Serial_IO_In_Progress_St) {
3539                 /* Delay one bit per loop */
3540                 udelay((devpriv->serial_interval_ns + 999) / 1000);
3541                 if (--count < 0) {
3542                         dev_err(dev->class_dev,
3543                                 "SPI serial I/O didn't finish in time!\n");
3544                         err = -ETIME;
3545                         goto Error;
3546                 }
3547         }
3548
3549         /* Delay for last bit. This delay is absolutely necessary, because
3550            DIO_Serial_IO_In_Progress_St goes high one bit too early. */
3551         udelay((devpriv->serial_interval_ns + 999) / 1000);
3552
3553         if (data_in)
3554                 *data_in = ni_stc_readw(dev, DIO_Serial_Input_Register);
3555
3556 Error:
3557         ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3558
3559         return err;
3560 }
3561
3562 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
3563                                    struct comedi_subdevice *s,
3564                                    unsigned char data_out,
3565                                    unsigned char *data_in)
3566 {
3567         struct ni_private *devpriv = dev->private;
3568         unsigned char mask, input = 0;
3569
3570         /* Wait for one bit before transfer */
3571         udelay((devpriv->serial_interval_ns + 999) / 1000);
3572
3573         for (mask = 0x80; mask; mask >>= 1) {
3574                 /* Output current bit; note that we cannot touch s->state
3575                    because it is a per-subdevice field, and serial is
3576                    a separate subdevice from DIO. */
3577                 devpriv->dio_output &= ~NISTC_DIO_SDOUT;
3578                 if (data_out & mask)
3579                         devpriv->dio_output |= NISTC_DIO_SDOUT;
3580                 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3581
3582                 /* Assert SDCLK (active low, inverted), wait for half of
3583                    the delay, deassert SDCLK, and wait for the other half. */
3584                 devpriv->dio_control |= NISTC_DIO_SDCLK;
3585                 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3586
3587                 udelay((devpriv->serial_interval_ns + 999) / 2000);
3588
3589                 devpriv->dio_control &= ~NISTC_DIO_SDCLK;
3590                 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3591
3592                 udelay((devpriv->serial_interval_ns + 999) / 2000);
3593
3594                 /* Input current bit */
3595                 if (ni_stc_readw(dev, DIO_Parallel_Input_Register) &
3596                     NISTC_DIO_SDIN)
3597                         input |= mask;
3598         }
3599
3600         if (data_in)
3601                 *data_in = input;
3602
3603         return 0;
3604 }
3605
3606 static int ni_serial_insn_config(struct comedi_device *dev,
3607                                  struct comedi_subdevice *s,
3608                                  struct comedi_insn *insn,
3609                                  unsigned int *data)
3610 {
3611         struct ni_private *devpriv = dev->private;
3612         unsigned clk_fout = devpriv->clock_and_fout;
3613         int err = insn->n;
3614         unsigned char byte_out, byte_in = 0;
3615
3616         if (insn->n != 2)
3617                 return -EINVAL;
3618
3619         switch (data[0]) {
3620         case INSN_CONFIG_SERIAL_CLOCK:
3621                 devpriv->serial_hw_mode = 1;
3622                 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_ENA;
3623
3624                 if (data[1] == SERIAL_DISABLED) {
3625                         devpriv->serial_hw_mode = 0;
3626                         devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3627                                                   NISTC_DIO_SDCLK);
3628                         data[1] = SERIAL_DISABLED;
3629                         devpriv->serial_interval_ns = data[1];
3630                 } else if (data[1] <= SERIAL_600NS) {
3631                         /* Warning: this clock speed is too fast to reliably
3632                            control SCXI. */
3633                         devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3634                         clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE;
3635                         clk_fout &= ~NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3636                         data[1] = SERIAL_600NS;
3637                         devpriv->serial_interval_ns = data[1];
3638                 } else if (data[1] <= SERIAL_1_2US) {
3639                         devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3640                         clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3641                                     NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3642                         data[1] = SERIAL_1_2US;
3643                         devpriv->serial_interval_ns = data[1];
3644                 } else if (data[1] <= SERIAL_10US) {
3645                         devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3646                         clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3647                                     NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3648                         /* Note: NISTC_CLK_FOUT_DIO_SER_OUT_DIV2 only affects
3649                            600ns/1.2us. If you turn divide_by_2 off with the
3650                            slow clock, you will still get 10us, except then
3651                            all your delays are wrong. */
3652                         data[1] = SERIAL_10US;
3653                         devpriv->serial_interval_ns = data[1];
3654                 } else {
3655                         devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3656                                                   NISTC_DIO_SDCLK);
3657                         devpriv->serial_hw_mode = 0;
3658                         data[1] = (data[1] / 1000) * 1000;
3659                         devpriv->serial_interval_ns = data[1];
3660                 }
3661                 devpriv->clock_and_fout = clk_fout;
3662
3663                 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3664                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3665                 return 1;
3666
3667         case INSN_CONFIG_BIDIRECTIONAL_DATA:
3668
3669                 if (devpriv->serial_interval_ns == 0)
3670                         return -EINVAL;
3671
3672                 byte_out = data[1] & 0xFF;
3673
3674                 if (devpriv->serial_hw_mode) {
3675                         err = ni_serial_hw_readwrite8(dev, s, byte_out,
3676                                                       &byte_in);
3677                 } else if (devpriv->serial_interval_ns > 0) {
3678                         err = ni_serial_sw_readwrite8(dev, s, byte_out,
3679                                                       &byte_in);
3680                 } else {
3681                         dev_err(dev->class_dev, "serial disabled!\n");
3682                         return -EINVAL;
3683                 }
3684                 if (err < 0)
3685                         return err;
3686                 data[1] = byte_in & 0xFF;
3687                 return insn->n;
3688
3689                 break;
3690         default:
3691                 return -EINVAL;
3692         }
3693 }
3694
3695 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
3696 {
3697         int i;
3698
3699         for (i = 0; i < s->n_chan; i++) {
3700                 ni_ao_win_outw(dev, AO_Channel(i) | 0x0,
3701                                AO_Configuration_2_67xx);
3702         }
3703         ni_ao_win_outw(dev, 0x0, AO_Later_Single_Point_Updates);
3704 }
3705
3706 static const struct mio_regmap ni_gpct_to_stc_regmap[] = {
3707         [NITIO_G0_AUTO_INC]     = { G_Autoincrement_Register(0), 2 },
3708         [NITIO_G1_AUTO_INC]     = { G_Autoincrement_Register(1), 2 },
3709         [NITIO_G0_CMD]          = { NISTC_G0_CMD_REG, 2 },
3710         [NITIO_G1_CMD]          = { NISTC_G1_CMD_REG, 2 },
3711         [NITIO_G0_HW_SAVE]      = { G_HW_Save_Register(0), 4 },
3712         [NITIO_G1_HW_SAVE]      = { G_HW_Save_Register(1), 4 },
3713         [NITIO_G0_SW_SAVE]      = { G_Save_Register(0), 4 },
3714         [NITIO_G1_SW_SAVE]      = { G_Save_Register(1), 4 },
3715         [NITIO_G0_MODE]         = { NISTC_G0_MODE_REG, 2 },
3716         [NITIO_G1_MODE]         = { NISTC_G1_MODE_REG, 2 },
3717         [NITIO_G0_LOADA]        = { NISTC_G0_LOADA_REG, 4 },
3718         [NITIO_G1_LOADA]        = { NISTC_G1_LOADA_REG, 4 },
3719         [NITIO_G0_LOADB]        = { NISTC_G0_LOADB_REG, 4 },
3720         [NITIO_G1_LOADB]        = { NISTC_G1_LOADB_REG, 4 },
3721         [NITIO_G0_INPUT_SEL]    = { NISTC_G0_INPUT_SEL_REG, 2 },
3722         [NITIO_G1_INPUT_SEL]    = { NISTC_G1_INPUT_SEL_REG, 2 },
3723         [NITIO_G0_CNT_MODE]     = { 0x1b0, 2 }, /* M-Series only */
3724         [NITIO_G1_CNT_MODE]     = { 0x1b2, 2 }, /* M-Series only */
3725         [NITIO_G0_GATE2]        = { 0x1b4, 2 }, /* M-Series only */
3726         [NITIO_G1_GATE2]        = { 0x1b6, 2 }, /* M-Series only */
3727         [NITIO_G01_STATUS]      = { G_Status_Register, 2 },
3728         [NITIO_G01_RESET]       = { Joint_Reset_Register, 2 },
3729         [NITIO_G01_STATUS1]     = { Joint_Status_1_Register, 2 },
3730         [NITIO_G01_STATUS2]     = { Joint_Status_2_Register, 2 },
3731         [NITIO_G0_DMA_CFG]      = { 0x1b8, 2 }, /* M-Series only */
3732         [NITIO_G1_DMA_CFG]      = { 0x1ba, 2 }, /* M-Series only */
3733         [NITIO_G0_DMA_STATUS]   = { 0x1b8, 2 }, /* M-Series only */
3734         [NITIO_G1_DMA_STATUS]   = { 0x1ba, 2 }, /* M-Series only */
3735         [NITIO_G0_ABZ]          = { 0x1c0, 2 }, /* M-Series only */
3736         [NITIO_G1_ABZ]          = { 0x1c2, 2 }, /* M-Series only */
3737         [NITIO_G0_INT_ACK]      = { NISTC_INTA_ACK_REG, 2 },
3738         [NITIO_G1_INT_ACK]      = { NISTC_INTB_ACK_REG, 2 },
3739         [NITIO_G0_STATUS]       = { AI_Status_1_Register, 2 },
3740         [NITIO_G1_STATUS]       = { AO_Status_1_Register, 2 },
3741         [NITIO_G0_INT_ENA]      = { Interrupt_A_Enable_Register, 2 },
3742         [NITIO_G1_INT_ENA]      = { Interrupt_B_Enable_Register, 2 },
3743 };
3744
3745 static unsigned int ni_gpct_to_stc_register(struct comedi_device *dev,
3746                                             enum ni_gpct_register reg)
3747 {
3748         const struct mio_regmap *regmap;
3749
3750         if (reg < ARRAY_SIZE(ni_gpct_to_stc_regmap)) {
3751                 regmap = &ni_gpct_to_stc_regmap[reg];
3752         } else {
3753                 dev_warn(dev->class_dev,"%s: unhandled register 0x%x\n",
3754                          __func__, reg);
3755                 return 0;
3756         }
3757
3758         return regmap->mio_reg;
3759 }
3760
3761 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
3762                                    enum ni_gpct_register reg)
3763 {
3764         struct comedi_device *dev = counter->counter_dev->dev;
3765         unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
3766         /* bits in the join reset register which are relevant to counters */
3767         static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset;
3768         static const unsigned gpct_interrupt_a_enable_mask =
3769             G0_Gate_Interrupt_Enable | G0_TC_Interrupt_Enable;
3770         static const unsigned gpct_interrupt_b_enable_mask =
3771             G1_Gate_Interrupt_Enable | G1_TC_Interrupt_Enable;
3772
3773         if (stc_register == 0)
3774                 return;
3775
3776         switch (reg) {
3777                 /* m-series only registers */
3778         case NITIO_G0_CNT_MODE:
3779         case NITIO_G1_CNT_MODE:
3780         case NITIO_G0_GATE2:
3781         case NITIO_G1_GATE2:
3782         case NITIO_G0_DMA_CFG:
3783         case NITIO_G1_DMA_CFG:
3784         case NITIO_G0_ABZ:
3785         case NITIO_G1_ABZ:
3786                 ni_writew(dev, bits, stc_register);
3787                 break;
3788
3789                 /* 32 bit registers */
3790         case NITIO_G0_LOADA:
3791         case NITIO_G1_LOADA:
3792         case NITIO_G0_LOADB:
3793         case NITIO_G1_LOADB:
3794                 ni_stc_writel(dev, bits, stc_register);
3795                 break;
3796
3797                 /* 16 bit registers */
3798         case NITIO_G0_INT_ENA:
3799                 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
3800                 ni_set_bitfield(dev, stc_register,
3801                                 gpct_interrupt_a_enable_mask, bits);
3802                 break;
3803         case NITIO_G1_INT_ENA:
3804                 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
3805                 ni_set_bitfield(dev, stc_register,
3806                                 gpct_interrupt_b_enable_mask, bits);
3807                 break;
3808         case NITIO_G01_RESET:
3809                 BUG_ON(bits & ~gpct_joint_reset_mask);
3810                 /* fall-through */
3811         default:
3812                 ni_stc_writew(dev, bits, stc_register);
3813         }
3814 }
3815
3816 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
3817                                       enum ni_gpct_register reg)
3818 {
3819         struct comedi_device *dev = counter->counter_dev->dev;
3820         unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
3821
3822         if (stc_register == 0)
3823                 return 0;
3824
3825         switch (reg) {
3826                 /* m-series only registers */
3827         case NITIO_G0_DMA_STATUS:
3828         case NITIO_G1_DMA_STATUS:
3829                 return ni_readw(dev, stc_register);
3830
3831                 /* 32 bit registers */
3832         case NITIO_G0_HW_SAVE:
3833         case NITIO_G1_HW_SAVE:
3834         case NITIO_G0_SW_SAVE:
3835         case NITIO_G1_SW_SAVE:
3836                 return ni_stc_readl(dev, stc_register);
3837
3838                 /* 16 bit registers */
3839         default:
3840                 return ni_stc_readw(dev, stc_register);
3841         }
3842 }
3843
3844 static int ni_freq_out_insn_read(struct comedi_device *dev,
3845                                  struct comedi_subdevice *s,
3846                                  struct comedi_insn *insn,
3847                                  unsigned int *data)
3848 {
3849         struct ni_private *devpriv = dev->private;
3850         unsigned int val = NISTC_CLK_FOUT_TO_DIVIDER(devpriv->clock_and_fout);
3851         int i;
3852
3853         for (i = 0; i < insn->n; i++)
3854                 data[i] = val;
3855
3856         return insn->n;
3857 }
3858
3859 static int ni_freq_out_insn_write(struct comedi_device *dev,
3860                                   struct comedi_subdevice *s,
3861                                   struct comedi_insn *insn,
3862                                   unsigned int *data)
3863 {
3864         struct ni_private *devpriv = dev->private;
3865
3866         if (insn->n) {
3867                 unsigned int val = data[insn->n - 1];
3868
3869                 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_ENA;
3870                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3871                 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_DIVIDER_MASK;
3872
3873                 /* use the last data value to set the fout divider */
3874                 devpriv->clock_and_fout |= NISTC_CLK_FOUT_DIVIDER(val);
3875
3876                 devpriv->clock_and_fout |= NISTC_CLK_FOUT_ENA;
3877                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3878         }
3879         return insn->n;
3880 }
3881
3882 static int ni_freq_out_insn_config(struct comedi_device *dev,
3883                                    struct comedi_subdevice *s,
3884                                    struct comedi_insn *insn,
3885                                    unsigned int *data)
3886 {
3887         struct ni_private *devpriv = dev->private;
3888
3889         switch (data[0]) {
3890         case INSN_CONFIG_SET_CLOCK_SRC:
3891                 switch (data[1]) {
3892                 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
3893                         devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_TIMEBASE_SEL;
3894                         break;
3895                 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
3896                         devpriv->clock_and_fout |= NISTC_CLK_FOUT_TIMEBASE_SEL;
3897                         break;
3898                 default:
3899                         return -EINVAL;
3900                 }
3901                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3902                 break;
3903         case INSN_CONFIG_GET_CLOCK_SRC:
3904                 if (devpriv->clock_and_fout & NISTC_CLK_FOUT_TIMEBASE_SEL) {
3905                         data[1] = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
3906                         data[2] = TIMEBASE_2_NS;
3907                 } else {
3908                         data[1] = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
3909                         data[2] = TIMEBASE_1_NS * 2;
3910                 }
3911                 break;
3912         default:
3913                 return -EINVAL;
3914         }
3915         return insn->n;
3916 }
3917
3918 static int ni_8255_callback(struct comedi_device *dev,
3919                             int dir, int port, int data, unsigned long iobase)
3920 {
3921         if (dir) {
3922                 ni_writeb(dev, data, iobase + 2 * port);
3923                 return 0;
3924         }
3925
3926         return ni_readb(dev, iobase + 2 * port);
3927 }
3928
3929 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
3930 {
3931         struct ni_private *devpriv = dev->private;
3932
3933         data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
3934         data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
3935         return 3;
3936 }
3937
3938 static int ni_m_series_pwm_config(struct comedi_device *dev,
3939                                   struct comedi_subdevice *s,
3940                                   struct comedi_insn *insn,
3941                                   unsigned int *data)
3942 {
3943         struct ni_private *devpriv = dev->private;
3944         unsigned up_count, down_count;
3945
3946         switch (data[0]) {
3947         case INSN_CONFIG_PWM_OUTPUT:
3948                 switch (data[1]) {
3949                 case CMDF_ROUND_NEAREST:
3950                         up_count =
3951                             (data[2] +
3952                              devpriv->clock_ns / 2) / devpriv->clock_ns;
3953                         break;
3954                 case CMDF_ROUND_DOWN:
3955                         up_count = data[2] / devpriv->clock_ns;
3956                         break;
3957                 case CMDF_ROUND_UP:
3958                         up_count =
3959                             (data[2] + devpriv->clock_ns -
3960                              1) / devpriv->clock_ns;
3961                         break;
3962                 default:
3963                         return -EINVAL;
3964                 }
3965                 switch (data[3]) {
3966                 case CMDF_ROUND_NEAREST:
3967                         down_count =
3968                             (data[4] +
3969                              devpriv->clock_ns / 2) / devpriv->clock_ns;
3970                         break;
3971                 case CMDF_ROUND_DOWN:
3972                         down_count = data[4] / devpriv->clock_ns;
3973                         break;
3974                 case CMDF_ROUND_UP:
3975                         down_count =
3976                             (data[4] + devpriv->clock_ns -
3977                              1) / devpriv->clock_ns;
3978                         break;
3979                 default:
3980                         return -EINVAL;
3981                 }
3982                 if (up_count * devpriv->clock_ns != data[2] ||
3983                     down_count * devpriv->clock_ns != data[4]) {
3984                         data[2] = up_count * devpriv->clock_ns;
3985                         data[4] = down_count * devpriv->clock_ns;
3986                         return -EAGAIN;
3987                 }
3988                 ni_writel(dev, NI_M_CAL_PWM_HIGH_TIME(up_count) |
3989                                NI_M_CAL_PWM_LOW_TIME(down_count),
3990                           NI_M_CAL_PWM_REG);
3991                 devpriv->pwm_up_count = up_count;
3992                 devpriv->pwm_down_count = down_count;
3993                 return 5;
3994         case INSN_CONFIG_GET_PWM_OUTPUT:
3995                 return ni_get_pwm_config(dev, data);
3996         default:
3997                 return -EINVAL;
3998         }
3999         return 0;
4000 }
4001
4002 static int ni_6143_pwm_config(struct comedi_device *dev,
4003                               struct comedi_subdevice *s,
4004                               struct comedi_insn *insn,
4005                               unsigned int *data)
4006 {
4007         struct ni_private *devpriv = dev->private;
4008         unsigned up_count, down_count;
4009
4010         switch (data[0]) {
4011         case INSN_CONFIG_PWM_OUTPUT:
4012                 switch (data[1]) {
4013                 case CMDF_ROUND_NEAREST:
4014                         up_count =
4015                             (data[2] +
4016                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4017                         break;
4018                 case CMDF_ROUND_DOWN:
4019                         up_count = data[2] / devpriv->clock_ns;
4020                         break;
4021                 case CMDF_ROUND_UP:
4022                         up_count =
4023                             (data[2] + devpriv->clock_ns -
4024                              1) / devpriv->clock_ns;
4025                         break;
4026                 default:
4027                         return -EINVAL;
4028                 }
4029                 switch (data[3]) {
4030                 case CMDF_ROUND_NEAREST:
4031                         down_count =
4032                             (data[4] +
4033                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4034                         break;
4035                 case CMDF_ROUND_DOWN:
4036                         down_count = data[4] / devpriv->clock_ns;
4037                         break;
4038                 case CMDF_ROUND_UP:
4039                         down_count =
4040                             (data[4] + devpriv->clock_ns -
4041                              1) / devpriv->clock_ns;
4042                         break;
4043                 default:
4044                         return -EINVAL;
4045                 }
4046                 if (up_count * devpriv->clock_ns != data[2] ||
4047                     down_count * devpriv->clock_ns != data[4]) {
4048                         data[2] = up_count * devpriv->clock_ns;
4049                         data[4] = down_count * devpriv->clock_ns;
4050                         return -EAGAIN;
4051                 }
4052                 ni_writel(dev, up_count, Calibration_HighTime_6143);
4053                 devpriv->pwm_up_count = up_count;
4054                 ni_writel(dev, down_count, Calibration_LowTime_6143);
4055                 devpriv->pwm_down_count = down_count;
4056                 return 5;
4057         case INSN_CONFIG_GET_PWM_OUTPUT:
4058                 return ni_get_pwm_config(dev, data);
4059         default:
4060                 return -EINVAL;
4061         }
4062         return 0;
4063 }
4064
4065 static int pack_mb88341(int addr, int val, int *bitstring)
4066 {
4067         /*
4068            Fujitsu MB 88341
4069            Note that address bits are reversed.  Thanks to
4070            Ingo Keen for noticing this.
4071
4072            Note also that the 88341 expects address values from
4073            1-12, whereas we use channel numbers 0-11.  The NI
4074            docs use 1-12, also, so be careful here.
4075          */
4076         addr++;
4077         *bitstring = ((addr & 0x1) << 11) |
4078             ((addr & 0x2) << 9) |
4079             ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
4080         return 12;
4081 }
4082
4083 static int pack_dac8800(int addr, int val, int *bitstring)
4084 {
4085         *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
4086         return 11;
4087 }
4088
4089 static int pack_dac8043(int addr, int val, int *bitstring)
4090 {
4091         *bitstring = val & 0xfff;
4092         return 12;
4093 }
4094
4095 static int pack_ad8522(int addr, int val, int *bitstring)
4096 {
4097         *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
4098         return 16;
4099 }
4100
4101 static int pack_ad8804(int addr, int val, int *bitstring)
4102 {
4103         *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
4104         return 12;
4105 }
4106
4107 static int pack_ad8842(int addr, int val, int *bitstring)
4108 {
4109         *bitstring = ((addr + 1) << 8) | (val & 0xff);
4110         return 12;
4111 }
4112
4113 struct caldac_struct {
4114         int n_chans;
4115         int n_bits;
4116         int (*packbits)(int, int, int *);
4117 };
4118
4119 static struct caldac_struct caldacs[] = {
4120         [mb88341] = {12, 8, pack_mb88341},
4121         [dac8800] = {8, 8, pack_dac8800},
4122         [dac8043] = {1, 12, pack_dac8043},
4123         [ad8522] = {2, 12, pack_ad8522},
4124         [ad8804] = {12, 8, pack_ad8804},
4125         [ad8842] = {8, 8, pack_ad8842},
4126         [ad8804_debug] = {16, 8, pack_ad8804},
4127 };
4128
4129 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
4130 {
4131         const struct ni_board_struct *board = dev->board_ptr;
4132         struct ni_private *devpriv = dev->private;
4133         unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
4134         int i;
4135         int type;
4136
4137         if (devpriv->caldacs[addr] == val)
4138                 return;
4139         devpriv->caldacs[addr] = val;
4140
4141         for (i = 0; i < 3; i++) {
4142                 type = board->caldac[i];
4143                 if (type == caldac_none)
4144                         break;
4145                 if (addr < caldacs[type].n_chans) {
4146                         bits = caldacs[type].packbits(addr, val, &bitstring);
4147                         loadbit = SerDacLd(i);
4148                         break;
4149                 }
4150                 addr -= caldacs[type].n_chans;
4151         }
4152
4153         /* bits will be 0 if there is no caldac for the given addr */
4154         if (bits == 0)
4155                 return;
4156
4157         for (bit = 1 << (bits - 1); bit; bit >>= 1) {
4158                 ni_writeb(dev, ((bit & bitstring) ? 0x02 : 0), Serial_Command);
4159                 udelay(1);
4160                 ni_writeb(dev, 1 | ((bit & bitstring) ? 0x02 : 0),
4161                           Serial_Command);
4162                 udelay(1);
4163         }
4164         ni_writeb(dev, loadbit, Serial_Command);
4165         udelay(1);
4166         ni_writeb(dev, 0, Serial_Command);
4167 }
4168
4169 static int ni_calib_insn_write(struct comedi_device *dev,
4170                                struct comedi_subdevice *s,
4171                                struct comedi_insn *insn,
4172                                unsigned int *data)
4173 {
4174         ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4175
4176         return 1;
4177 }
4178
4179 static int ni_calib_insn_read(struct comedi_device *dev,
4180                               struct comedi_subdevice *s,
4181                               struct comedi_insn *insn,
4182                               unsigned int *data)
4183 {
4184         struct ni_private *devpriv = dev->private;
4185
4186         data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4187
4188         return 1;
4189 }
4190
4191 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4192 {
4193         const struct ni_board_struct *board = dev->board_ptr;
4194         struct ni_private *devpriv = dev->private;
4195         int i, j;
4196         int n_dacs;
4197         int n_chans = 0;
4198         int n_bits;
4199         int diffbits = 0;
4200         int type;
4201         int chan;
4202
4203         type = board->caldac[0];
4204         if (type == caldac_none)
4205                 return;
4206         n_bits = caldacs[type].n_bits;
4207         for (i = 0; i < 3; i++) {
4208                 type = board->caldac[i];
4209                 if (type == caldac_none)
4210                         break;
4211                 if (caldacs[type].n_bits != n_bits)
4212                         diffbits = 1;
4213                 n_chans += caldacs[type].n_chans;
4214         }
4215         n_dacs = i;
4216         s->n_chan = n_chans;
4217
4218         if (diffbits) {
4219                 unsigned int *maxdata_list;
4220
4221                 if (n_chans > MAX_N_CALDACS)
4222                         dev_err(dev->class_dev,
4223                                 "BUG! MAX_N_CALDACS too small\n");
4224                 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
4225                 chan = 0;
4226                 for (i = 0; i < n_dacs; i++) {
4227                         type = board->caldac[i];
4228                         for (j = 0; j < caldacs[type].n_chans; j++) {
4229                                 maxdata_list[chan] =
4230                                     (1 << caldacs[type].n_bits) - 1;
4231                                 chan++;
4232                         }
4233                 }
4234
4235                 for (chan = 0; chan < s->n_chan; chan++)
4236                         ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
4237         } else {
4238                 type = board->caldac[0];
4239                 s->maxdata = (1 << caldacs[type].n_bits) - 1;
4240
4241                 for (chan = 0; chan < s->n_chan; chan++)
4242                         ni_write_caldac(dev, i, s->maxdata / 2);
4243         }
4244 }
4245
4246 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4247 {
4248         int bit;
4249         int bitstring;
4250
4251         bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4252         ni_writeb(dev, 0x04, Serial_Command);
4253         for (bit = 0x8000; bit; bit >>= 1) {
4254                 ni_writeb(dev, 0x04 | ((bit & bitstring) ? 0x02 : 0),
4255                           Serial_Command);
4256                 ni_writeb(dev, 0x05 | ((bit & bitstring) ? 0x02 : 0),
4257                           Serial_Command);
4258         }
4259         bitstring = 0;
4260         for (bit = 0x80; bit; bit >>= 1) {
4261                 ni_writeb(dev, 0x04, Serial_Command);
4262                 ni_writeb(dev, 0x05, Serial_Command);
4263                 bitstring |= ((ni_readb(dev, XXX_Status) & PROMOUT) ? bit : 0);
4264         }
4265         ni_writeb(dev, 0x00, Serial_Command);
4266
4267         return bitstring;
4268 }
4269
4270 static int ni_eeprom_insn_read(struct comedi_device *dev,
4271                                struct comedi_subdevice *s,
4272                                struct comedi_insn *insn,
4273                                unsigned int *data)
4274 {
4275         data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4276
4277         return 1;
4278 }
4279
4280 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4281                                         struct comedi_subdevice *s,
4282                                         struct comedi_insn *insn,
4283                                         unsigned int *data)
4284 {
4285         struct ni_private *devpriv = dev->private;
4286
4287         data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4288
4289         return 1;
4290 }
4291
4292 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev,
4293                                        unsigned chan)
4294 {
4295         /*  pre-m-series boards have fixed signals on pfi pins */
4296         switch (chan) {
4297         case 0:
4298                 return NI_PFI_OUTPUT_AI_START1;
4299         case 1:
4300                 return NI_PFI_OUTPUT_AI_START2;
4301         case 2:
4302                 return NI_PFI_OUTPUT_AI_CONVERT;
4303         case 3:
4304                 return NI_PFI_OUTPUT_G_SRC1;
4305         case 4:
4306                 return NI_PFI_OUTPUT_G_GATE1;
4307         case 5:
4308                 return NI_PFI_OUTPUT_AO_UPDATE_N;
4309         case 6:
4310                 return NI_PFI_OUTPUT_AO_START1;
4311         case 7:
4312                 return NI_PFI_OUTPUT_AI_START_PULSE;
4313         case 8:
4314                 return NI_PFI_OUTPUT_G_SRC0;
4315         case 9:
4316                 return NI_PFI_OUTPUT_G_GATE0;
4317         default:
4318                 dev_err(dev->class_dev, "bug, unhandled case in switch.\n");
4319                 break;
4320         }
4321         return 0;
4322 }
4323
4324 static int ni_old_set_pfi_routing(struct comedi_device *dev,
4325                                   unsigned chan, unsigned source)
4326 {
4327         /*  pre-m-series boards have fixed signals on pfi pins */
4328         if (source != ni_old_get_pfi_routing(dev, chan))
4329                 return -EINVAL;
4330         return 2;
4331 }
4332
4333 static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev,
4334                                             unsigned chan)
4335 {
4336         struct ni_private *devpriv = dev->private;
4337         const unsigned array_offset = chan / 3;
4338
4339         return NI_M_PFI_OUT_SEL_TO_SRC(chan,
4340                                 devpriv->pfi_output_select_reg[array_offset]);
4341 }
4342
4343 static int ni_m_series_set_pfi_routing(struct comedi_device *dev,
4344                                        unsigned chan, unsigned source)
4345 {
4346         struct ni_private *devpriv = dev->private;
4347         unsigned index = chan / 3;
4348         unsigned short val = devpriv->pfi_output_select_reg[index];
4349
4350         if ((source & 0x1f) != source)
4351                 return -EINVAL;
4352
4353         val &= ~NI_M_PFI_OUT_SEL_MASK(chan);
4354         val |= NI_M_PFI_OUT_SEL(chan, source);
4355         ni_writew(dev, val, NI_M_PFI_OUT_SEL_REG(index));
4356         devpriv->pfi_output_select_reg[index] = val;
4357
4358         return 2;
4359 }
4360
4361 static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan)
4362 {
4363         struct ni_private *devpriv = dev->private;
4364
4365         return (devpriv->is_m_series)
4366                         ? ni_m_series_get_pfi_routing(dev, chan)
4367                         : ni_old_get_pfi_routing(dev, chan);
4368 }
4369
4370 static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan,
4371                               unsigned source)
4372 {
4373         struct ni_private *devpriv = dev->private;
4374
4375         return (devpriv->is_m_series)
4376                         ? ni_m_series_set_pfi_routing(dev, chan, source)
4377                         : ni_old_set_pfi_routing(dev, chan, source);
4378 }
4379
4380 static int ni_config_filter(struct comedi_device *dev,
4381                             unsigned pfi_channel,
4382                             enum ni_pfi_filter_select filter)
4383 {
4384         struct ni_private *devpriv = dev->private;
4385         unsigned bits;
4386
4387         if (!devpriv->is_m_series)
4388                 return -ENOTSUPP;
4389
4390         bits = ni_readl(dev, NI_M_PFI_FILTER_REG);
4391         bits &= ~NI_M_PFI_FILTER_SEL_MASK(pfi_channel);
4392         bits |= NI_M_PFI_FILTER_SEL(pfi_channel, filter);
4393         ni_writel(dev, bits, NI_M_PFI_FILTER_REG);
4394         return 0;
4395 }
4396
4397 static int ni_pfi_insn_config(struct comedi_device *dev,
4398                               struct comedi_subdevice *s,
4399                               struct comedi_insn *insn,
4400                               unsigned int *data)
4401 {
4402         struct ni_private *devpriv = dev->private;
4403         unsigned int chan;
4404
4405         if (insn->n < 1)
4406                 return -EINVAL;
4407
4408         chan = CR_CHAN(insn->chanspec);
4409
4410         switch (data[0]) {
4411         case COMEDI_OUTPUT:
4412                 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, 1);
4413                 break;
4414         case COMEDI_INPUT:
4415                 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, 0);
4416                 break;
4417         case INSN_CONFIG_DIO_QUERY:
4418                 data[1] =
4419                     (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
4420                     COMEDI_OUTPUT : COMEDI_INPUT;
4421                 return 0;
4422         case INSN_CONFIG_SET_ROUTING:
4423                 return ni_set_pfi_routing(dev, chan, data[1]);
4424         case INSN_CONFIG_GET_ROUTING:
4425                 data[1] = ni_get_pfi_routing(dev, chan);
4426                 break;
4427         case INSN_CONFIG_FILTER:
4428                 return ni_config_filter(dev, chan, data[1]);
4429         default:
4430                 return -EINVAL;
4431         }
4432         return 0;
4433 }
4434
4435 static int ni_pfi_insn_bits(struct comedi_device *dev,
4436                             struct comedi_subdevice *s,
4437                             struct comedi_insn *insn,
4438                             unsigned int *data)
4439 {
4440         struct ni_private *devpriv = dev->private;
4441
4442         if (!devpriv->is_m_series)
4443                 return -ENOTSUPP;
4444
4445         if (comedi_dio_update_state(s, data))
4446                 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
4447
4448         data[1] = ni_readw(dev, NI_M_PFI_DI_REG);
4449
4450         return insn->n;
4451 }
4452
4453 static int cs5529_wait_for_idle(struct comedi_device *dev)
4454 {
4455         unsigned short status;
4456         const int timeout = HZ;
4457         int i;
4458
4459         for (i = 0; i < timeout; i++) {
4460                 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
4461                 if ((status & CSS_ADC_BUSY) == 0)
4462                         break;
4463                 set_current_state(TASK_INTERRUPTIBLE);
4464                 if (schedule_timeout(1))
4465                         return -EIO;
4466         }
4467         if (i == timeout) {
4468                 dev_err(dev->class_dev, "timeout\n");
4469                 return -ETIME;
4470         }
4471         return 0;
4472 }
4473
4474 static void cs5529_command(struct comedi_device *dev, unsigned short value)
4475 {
4476         static const int timeout = 100;
4477         int i;
4478
4479         ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
4480         /* give time for command to start being serially clocked into cs5529.
4481          * this insures that the CSS_ADC_BUSY bit will get properly
4482          * set before we exit this function.
4483          */
4484         for (i = 0; i < timeout; i++) {
4485                 if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
4486                         break;
4487                 udelay(1);
4488         }
4489         if (i == timeout)
4490                 dev_err(dev->class_dev,
4491                         "possible problem - never saw adc go busy?\n");
4492 }
4493
4494 static int cs5529_do_conversion(struct comedi_device *dev,
4495                                 unsigned short *data)
4496 {
4497         int retval;
4498         unsigned short status;
4499
4500         cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
4501         retval = cs5529_wait_for_idle(dev);
4502         if (retval) {
4503                 dev_err(dev->class_dev,
4504                         "timeout or signal in cs5529_do_conversion()\n");
4505                 return -ETIME;
4506         }
4507         status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
4508         if (status & CSS_OSC_DETECT) {
4509                 dev_err(dev->class_dev,
4510                         "cs5529 conversion error, status CSS_OSC_DETECT\n");
4511                 return -EIO;
4512         }
4513         if (status & CSS_OVERRANGE) {
4514                 dev_err(dev->class_dev,
4515                         "cs5529 conversion error, overrange (ignoring)\n");
4516         }
4517         if (data) {
4518                 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
4519                 /* cs5529 returns 16 bit signed data in bipolar mode */
4520                 *data ^= (1 << 15);
4521         }
4522         return 0;
4523 }
4524
4525 static int cs5529_ai_insn_read(struct comedi_device *dev,
4526                                struct comedi_subdevice *s,
4527                                struct comedi_insn *insn,
4528                                unsigned int *data)
4529 {
4530         int n, retval;
4531         unsigned short sample;
4532         unsigned int channel_select;
4533         const unsigned int INTERNAL_REF = 0x1000;
4534
4535         /* Set calibration adc source.  Docs lie, reference select bits 8 to 11
4536          * do nothing. bit 12 seems to chooses internal reference voltage, bit
4537          * 13 causes the adc input to go overrange (maybe reads external reference?) */
4538         if (insn->chanspec & CR_ALT_SOURCE)
4539                 channel_select = INTERNAL_REF;
4540         else
4541                 channel_select = CR_CHAN(insn->chanspec);
4542         ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
4543
4544         for (n = 0; n < insn->n; n++) {
4545                 retval = cs5529_do_conversion(dev, &sample);
4546                 if (retval < 0)
4547                         return retval;
4548                 data[n] = sample;
4549         }
4550         return insn->n;
4551 }
4552
4553 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
4554                                 unsigned int reg_select_bits)
4555 {
4556         ni_ao_win_outw(dev, ((value >> 16) & 0xff),
4557                        CAL_ADC_Config_Data_High_Word_67xx);
4558         ni_ao_win_outw(dev, (value & 0xffff),
4559                        CAL_ADC_Config_Data_Low_Word_67xx);
4560         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
4561         cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
4562         if (cs5529_wait_for_idle(dev))
4563                 dev_err(dev->class_dev,
4564                         "timeout or signal in %s\n", __func__);
4565 }
4566
4567 static int init_cs5529(struct comedi_device *dev)
4568 {
4569         unsigned int config_bits =
4570             CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
4571
4572 #if 1
4573         /* do self-calibration */
4574         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN,
4575                             CSCMD_CONFIG_REGISTER);
4576         /* need to force a conversion for calibration to run */
4577         cs5529_do_conversion(dev, NULL);
4578 #else
4579         /* force gain calibration to 1 */
4580         cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
4581         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET,
4582                             CSCMD_CONFIG_REGISTER);
4583         if (cs5529_wait_for_idle(dev))
4584                 dev_err(dev->class_dev,
4585                         "timeout or signal in %s\n", __func__);
4586 #endif
4587         return 0;
4588 }
4589
4590 /*
4591  * Find best multiplier/divider to try and get the PLL running at 80 MHz
4592  * given an arbitrary frequency input clock.
4593  */
4594 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
4595                                          unsigned *freq_divider,
4596                                          unsigned *freq_multiplier,
4597                                          unsigned *actual_period_ns)
4598 {
4599         unsigned div;
4600         unsigned best_div = 1;
4601         unsigned mult;
4602         unsigned best_mult = 1;
4603         static const unsigned pico_per_nano = 1000;
4604
4605         const unsigned reference_picosec = reference_period_ns * pico_per_nano;
4606         /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
4607          * 20 MHz for most timing clocks */
4608         static const unsigned target_picosec = 12500;
4609         static const unsigned fudge_factor_80_to_20Mhz = 4;
4610         int best_period_picosec = 0;
4611
4612         for (div = 1; div <= NI_M_PLL_MAX_DIVISOR; ++div) {
4613                 for (mult = 1; mult <= NI_M_PLL_MAX_MULTIPLIER; ++mult) {
4614                         unsigned new_period_ps =
4615                             (reference_picosec * div) / mult;
4616                         if (abs(new_period_ps - target_picosec) <
4617                             abs(best_period_picosec - target_picosec)) {
4618                                 best_period_picosec = new_period_ps;
4619                                 best_div = div;
4620                                 best_mult = mult;
4621                         }
4622                 }
4623         }
4624         if (best_period_picosec == 0)
4625                 return -EIO;
4626
4627         *freq_divider = best_div;
4628         *freq_multiplier = best_mult;
4629         *actual_period_ns =
4630             (best_period_picosec * fudge_factor_80_to_20Mhz +
4631              (pico_per_nano / 2)) / pico_per_nano;
4632         return 0;
4633 }
4634
4635 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
4636                                            unsigned source, unsigned period_ns)
4637 {
4638         struct ni_private *devpriv = dev->private;
4639         static const unsigned min_period_ns = 50;
4640         static const unsigned max_period_ns = 1000;
4641         static const unsigned timeout = 1000;
4642         unsigned pll_control_bits;
4643         unsigned freq_divider;
4644         unsigned freq_multiplier;
4645         unsigned rtsi;
4646         unsigned i;
4647         int retval;
4648
4649         if (source == NI_MIO_PLL_PXI10_CLOCK)
4650                 period_ns = 100;
4651         /*  these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
4652         if (period_ns < min_period_ns || period_ns > max_period_ns) {
4653                 dev_err(dev->class_dev,
4654                         "%s: you must specify an input clock frequency between %i and %i nanosec for the phased-lock loop\n",
4655                         __func__, min_period_ns, max_period_ns);
4656                 return -EINVAL;
4657         }
4658         devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
4659         ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4660                       NISTC_RTSI_TRIG_DIR_REG);
4661         pll_control_bits = NI_M_PLL_CTRL_ENA | NI_M_PLL_CTRL_VCO_MODE_75_150MHZ;
4662         devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4663                                     NI_M_CLK_FOUT2_TIMEBASE3_PLL;
4664         devpriv->clock_and_fout2 &= ~NI_M_CLK_FOUT2_PLL_SRC_MASK;
4665         switch (source) {
4666         case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
4667                 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_STAR;
4668                 break;
4669         case NI_MIO_PLL_PXI10_CLOCK:
4670                 /* pxi clock is 10MHz */
4671                 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_PXI10;
4672                 break;
4673         default:
4674                 for (rtsi = 0; rtsi <= NI_M_MAX_RTSI_CHAN; ++rtsi) {
4675                         if (source == NI_MIO_PLL_RTSI_CLOCK(rtsi)) {
4676                                 devpriv->clock_and_fout2 |=
4677                                         NI_M_CLK_FOUT2_PLL_SRC_RTSI(rtsi);
4678                                 break;
4679                         }
4680                 }
4681                 if (rtsi > NI_M_MAX_RTSI_CHAN)
4682                         return -EINVAL;
4683                 break;
4684         }
4685         retval = ni_mseries_get_pll_parameters(period_ns,
4686                                                &freq_divider,
4687                                                &freq_multiplier,
4688                                                &devpriv->clock_ns);
4689         if (retval < 0) {
4690                 dev_err(dev->class_dev,
4691                         "bug, failed to find pll parameters\n");
4692                 return retval;
4693         }
4694
4695         ni_writew(dev, devpriv->clock_and_fout2, NI_M_CLK_FOUT2_REG);
4696         pll_control_bits |= NI_M_PLL_CTRL_DIVISOR(freq_divider) |
4697                             NI_M_PLL_CTRL_MULTIPLIER(freq_multiplier);
4698
4699         ni_writew(dev, pll_control_bits, NI_M_PLL_CTRL_REG);
4700         devpriv->clock_source = source;
4701         /* it seems to typically take a few hundred microseconds for PLL to lock */
4702         for (i = 0; i < timeout; ++i) {
4703                 if (ni_readw(dev, NI_M_PLL_STATUS_REG) & NI_M_PLL_STATUS_LOCKED)
4704                         break;
4705                 udelay(1);
4706         }
4707         if (i == timeout) {
4708                 dev_err(dev->class_dev,
4709                         "%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns\n",
4710                         __func__, source, period_ns);
4711                 return -ETIMEDOUT;
4712         }
4713         return 3;
4714 }
4715
4716 static int ni_set_master_clock(struct comedi_device *dev,
4717                                unsigned source, unsigned period_ns)
4718 {
4719         struct ni_private *devpriv = dev->private;
4720
4721         if (source == NI_MIO_INTERNAL_CLOCK) {
4722                 devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
4723                 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4724                               NISTC_RTSI_TRIG_DIR_REG);
4725                 devpriv->clock_ns = TIMEBASE_1_NS;
4726                 if (devpriv->is_m_series) {
4727                         devpriv->clock_and_fout2 &=
4728                             ~(NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4729                               NI_M_CLK_FOUT2_TIMEBASE3_PLL);
4730                         ni_writew(dev, devpriv->clock_and_fout2,
4731                                   NI_M_CLK_FOUT2_REG);
4732                         ni_writew(dev, 0, NI_M_PLL_CTRL_REG);
4733                 }
4734                 devpriv->clock_source = source;
4735         } else {
4736                 if (devpriv->is_m_series) {
4737                         return ni_mseries_set_pll_master_clock(dev, source,
4738                                                                period_ns);
4739                 } else {
4740                         if (source == NI_MIO_RTSI_CLOCK) {
4741                                 devpriv->rtsi_trig_direction_reg |=
4742                                     NISTC_RTSI_TRIG_USE_CLK;
4743                                 ni_stc_writew(dev,
4744                                               devpriv->rtsi_trig_direction_reg,
4745                                               NISTC_RTSI_TRIG_DIR_REG);
4746                                 if (period_ns == 0) {
4747                                         dev_err(dev->class_dev,
4748                                                 "we don't handle an unspecified clock period correctly yet, returning error\n");
4749                                         return -EINVAL;
4750                                 }
4751                                 devpriv->clock_ns = period_ns;
4752                                 devpriv->clock_source = source;
4753                         } else {
4754                                 return -EINVAL;
4755                         }
4756                 }
4757         }
4758         return 3;
4759 }
4760
4761 static int ni_valid_rtsi_output_source(struct comedi_device *dev,
4762                                        unsigned chan, unsigned source)
4763 {
4764         struct ni_private *devpriv = dev->private;
4765
4766         if (chan >= NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
4767                 if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4768                         if (source == NI_RTSI_OUTPUT_RTSI_OSC)
4769                                 return 1;
4770
4771                         dev_err(dev->class_dev,
4772                                 "%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards\n",
4773                                 __func__, chan, NISTC_RTSI_TRIG_OLD_CLK_CHAN);
4774                         return 0;
4775                 }
4776                 return 0;
4777         }
4778         switch (source) {
4779         case NI_RTSI_OUTPUT_ADR_START1:
4780         case NI_RTSI_OUTPUT_ADR_START2:
4781         case NI_RTSI_OUTPUT_SCLKG:
4782         case NI_RTSI_OUTPUT_DACUPDN:
4783         case NI_RTSI_OUTPUT_DA_START1:
4784         case NI_RTSI_OUTPUT_G_SRC0:
4785         case NI_RTSI_OUTPUT_G_GATE0:
4786         case NI_RTSI_OUTPUT_RGOUT0:
4787         case NI_RTSI_OUTPUT_RTSI_BRD_0:
4788                 return 1;
4789         case NI_RTSI_OUTPUT_RTSI_OSC:
4790                 return (devpriv->is_m_series) ? 1 : 0;
4791         default:
4792                 return 0;
4793         }
4794 }
4795
4796 static int ni_set_rtsi_routing(struct comedi_device *dev,
4797                                unsigned chan, unsigned source)
4798 {
4799         struct ni_private *devpriv = dev->private;
4800
4801         if (ni_valid_rtsi_output_source(dev, chan, source) == 0)
4802                 return -EINVAL;
4803         if (chan < 4) {
4804                 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan);
4805                 devpriv->rtsi_trig_a_output_reg |=
4806                     RTSI_Trig_Output_Bits(chan, source);
4807                 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
4808                               RTSI_Trig_A_Output_Register);
4809         } else if (chan < 8) {
4810                 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan);
4811                 devpriv->rtsi_trig_b_output_reg |=
4812                     RTSI_Trig_Output_Bits(chan, source);
4813                 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
4814                               RTSI_Trig_B_Output_Register);
4815         }
4816         return 2;
4817 }
4818
4819 static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan)
4820 {
4821         struct ni_private *devpriv = dev->private;
4822
4823         if (chan < 4) {
4824                 return RTSI_Trig_Output_Source(chan,
4825                                                devpriv->rtsi_trig_a_output_reg);
4826         } else if (chan < NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
4827                 return RTSI_Trig_Output_Source(chan,
4828                                                devpriv->rtsi_trig_b_output_reg);
4829         } else {
4830                 if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN)
4831                         return NI_RTSI_OUTPUT_RTSI_OSC;
4832                 dev_err(dev->class_dev, "bug! should never get here?\n");
4833                 return 0;
4834         }
4835 }
4836
4837 static int ni_rtsi_insn_config(struct comedi_device *dev,
4838                                struct comedi_subdevice *s,
4839                                struct comedi_insn *insn,
4840                                unsigned int *data)
4841 {
4842         struct ni_private *devpriv = dev->private;
4843         unsigned int chan = CR_CHAN(insn->chanspec);
4844         unsigned int max_chan = NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series);
4845
4846         switch (data[0]) {
4847         case INSN_CONFIG_DIO_OUTPUT:
4848                 if (chan < max_chan) {
4849                         devpriv->rtsi_trig_direction_reg |=
4850                             NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
4851                 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4852                         devpriv->rtsi_trig_direction_reg |=
4853                             NISTC_RTSI_TRIG_DRV_CLK;
4854                 }
4855                 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4856                               NISTC_RTSI_TRIG_DIR_REG);
4857                 break;
4858         case INSN_CONFIG_DIO_INPUT:
4859                 if (chan < max_chan) {
4860                         devpriv->rtsi_trig_direction_reg &=
4861                             ~NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
4862                 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4863                         devpriv->rtsi_trig_direction_reg &=
4864                             ~NISTC_RTSI_TRIG_DRV_CLK;
4865                 }
4866                 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4867                               NISTC_RTSI_TRIG_DIR_REG);
4868                 break;
4869         case INSN_CONFIG_DIO_QUERY:
4870                 if (chan < max_chan) {
4871                         data[1] =
4872                             (devpriv->rtsi_trig_direction_reg &
4873                              NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series))
4874                                 ? INSN_CONFIG_DIO_OUTPUT
4875                                 : INSN_CONFIG_DIO_INPUT;
4876                 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4877                         data[1] = (devpriv->rtsi_trig_direction_reg &
4878                                    NISTC_RTSI_TRIG_DRV_CLK)
4879                                   ? INSN_CONFIG_DIO_OUTPUT
4880                                   : INSN_CONFIG_DIO_INPUT;
4881                 }
4882                 return 2;
4883         case INSN_CONFIG_SET_CLOCK_SRC:
4884                 return ni_set_master_clock(dev, data[1], data[2]);
4885         case INSN_CONFIG_GET_CLOCK_SRC:
4886                 data[1] = devpriv->clock_source;
4887                 data[2] = devpriv->clock_ns;
4888                 return 3;
4889         case INSN_CONFIG_SET_ROUTING:
4890                 return ni_set_rtsi_routing(dev, chan, data[1]);
4891         case INSN_CONFIG_GET_ROUTING:
4892                 data[1] = ni_get_rtsi_routing(dev, chan);
4893                 return 2;
4894         default:
4895                 return -EINVAL;
4896         }
4897         return 1;
4898 }
4899
4900 static int ni_rtsi_insn_bits(struct comedi_device *dev,
4901                              struct comedi_subdevice *s,
4902                              struct comedi_insn *insn,
4903                              unsigned int *data)
4904 {
4905         data[1] = 0;
4906
4907         return insn->n;
4908 }
4909
4910 static void ni_rtsi_init(struct comedi_device *dev)
4911 {
4912         struct ni_private *devpriv = dev->private;
4913
4914         /*  Initialises the RTSI bus signal switch to a default state */
4915
4916         /*
4917          * Use 10MHz instead of 20MHz for RTSI clock frequency. Appears
4918          * to have no effect, at least on pxi-6281, which always uses
4919          * 20MHz rtsi clock frequency
4920          */
4921         devpriv->clock_and_fout2 = NI_M_CLK_FOUT2_RTSI_10MHZ;
4922         /*  Set clock mode to internal */
4923         if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0)
4924                 dev_err(dev->class_dev, "ni_set_master_clock failed, bug?\n");
4925         /*  default internal lines routing to RTSI bus lines */
4926         devpriv->rtsi_trig_a_output_reg =
4927             RTSI_Trig_Output_Bits(0,
4928                                   NI_RTSI_OUTPUT_ADR_START1) |
4929             RTSI_Trig_Output_Bits(1,
4930                                   NI_RTSI_OUTPUT_ADR_START2) |
4931             RTSI_Trig_Output_Bits(2,
4932                                   NI_RTSI_OUTPUT_SCLKG) |
4933             RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN);
4934         ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
4935                       RTSI_Trig_A_Output_Register);
4936         devpriv->rtsi_trig_b_output_reg =
4937             RTSI_Trig_Output_Bits(4,
4938                                   NI_RTSI_OUTPUT_DA_START1) |
4939             RTSI_Trig_Output_Bits(5,
4940                                   NI_RTSI_OUTPUT_G_SRC0) |
4941             RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0);
4942         if (devpriv->is_m_series)
4943                 devpriv->rtsi_trig_b_output_reg |=
4944                     RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
4945         ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
4946                       RTSI_Trig_B_Output_Register);
4947
4948 /*
4949 * Sets the source and direction of the 4 on board lines
4950 * ni_stc_writew(dev, 0x0000, RTSI_Board_Register);
4951 */
4952 }
4953
4954 #ifdef PCIDMA
4955 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
4956 {
4957         struct ni_gpct *counter = s->private;
4958         int retval;
4959
4960         retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
4961                                               COMEDI_INPUT);
4962         if (retval) {
4963                 dev_err(dev->class_dev,
4964                         "no dma channel available for use by counter\n");
4965                 return retval;
4966         }
4967         ni_tio_acknowledge(counter);
4968         ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
4969
4970         return ni_tio_cmd(dev, s);
4971 }
4972
4973 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
4974 {
4975         struct ni_gpct *counter = s->private;
4976         int retval;
4977
4978         retval = ni_tio_cancel(counter);
4979         ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
4980         ni_release_gpct_mite_channel(dev, counter->counter_index);
4981         return retval;
4982 }
4983 #endif
4984
4985 static irqreturn_t ni_E_interrupt(int irq, void *d)
4986 {
4987         struct comedi_device *dev = d;
4988         unsigned short a_status;
4989         unsigned short b_status;
4990         unsigned int ai_mite_status = 0;
4991         unsigned int ao_mite_status = 0;
4992         unsigned long flags;
4993 #ifdef PCIDMA
4994         struct ni_private *devpriv = dev->private;
4995         struct mite_struct *mite = devpriv->mite;
4996 #endif
4997
4998         if (!dev->attached)
4999                 return IRQ_NONE;
5000         smp_mb();               /*  make sure dev->attached is checked before handler does anything else. */
5001
5002         /*  lock to avoid race with comedi_poll */
5003         spin_lock_irqsave(&dev->spinlock, flags);
5004         a_status = ni_stc_readw(dev, AI_Status_1_Register);
5005         b_status = ni_stc_readw(dev, AO_Status_1_Register);
5006 #ifdef PCIDMA
5007         if (mite) {
5008                 struct ni_private *devpriv = dev->private;
5009                 unsigned long flags_too;
5010
5011                 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
5012                 if (devpriv->ai_mite_chan) {
5013                         ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
5014                         if (ai_mite_status & CHSR_LINKC)
5015                                 writel(CHOR_CLRLC,
5016                                        devpriv->mite->mite_io_addr +
5017                                        MITE_CHOR(devpriv->
5018                                                  ai_mite_chan->channel));
5019                 }
5020                 if (devpriv->ao_mite_chan) {
5021                         ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
5022                         if (ao_mite_status & CHSR_LINKC)
5023                                 writel(CHOR_CLRLC,
5024                                        mite->mite_io_addr +
5025                                        MITE_CHOR(devpriv->
5026                                                  ao_mite_chan->channel));
5027                 }
5028                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
5029         }
5030 #endif
5031         ack_a_interrupt(dev, a_status);
5032         ack_b_interrupt(dev, b_status);
5033         if ((a_status & Interrupt_A_St) || (ai_mite_status & CHSR_INT))
5034                 handle_a_interrupt(dev, a_status, ai_mite_status);
5035         if ((b_status & Interrupt_B_St) || (ao_mite_status & CHSR_INT))
5036                 handle_b_interrupt(dev, b_status, ao_mite_status);
5037         handle_gpct_interrupt(dev, 0);
5038         handle_gpct_interrupt(dev, 1);
5039         handle_cdio_interrupt(dev);
5040
5041         spin_unlock_irqrestore(&dev->spinlock, flags);
5042         return IRQ_HANDLED;
5043 }
5044
5045 static int ni_alloc_private(struct comedi_device *dev)
5046 {
5047         struct ni_private *devpriv;
5048
5049         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
5050         if (!devpriv)
5051                 return -ENOMEM;
5052
5053         spin_lock_init(&devpriv->window_lock);
5054         spin_lock_init(&devpriv->soft_reg_copy_lock);
5055         spin_lock_init(&devpriv->mite_channel_lock);
5056
5057         return 0;
5058 }
5059
5060 static int ni_E_init(struct comedi_device *dev,
5061                      unsigned interrupt_pin, unsigned irq_polarity)
5062 {
5063         const struct ni_board_struct *board = dev->board_ptr;
5064         struct ni_private *devpriv = dev->private;
5065         struct comedi_subdevice *s;
5066         int ret;
5067         int i;
5068
5069         if (board->n_aochan > MAX_N_AO_CHAN) {
5070                 dev_err(dev->class_dev, "bug! n_aochan > MAX_N_AO_CHAN\n");
5071                 return -EINVAL;
5072         }
5073
5074         /* initialize clock dividers */
5075         devpriv->clock_and_fout = NISTC_CLK_FOUT_SLOW_DIV2 |
5076                                   NISTC_CLK_FOUT_SLOW_TIMEBASE |
5077                                   NISTC_CLK_FOUT_TO_BOARD_DIV2 |
5078                                   NISTC_CLK_FOUT_TO_BOARD;
5079         if (!devpriv->is_6xxx) {
5080                 /* BEAM is this needed for PCI-6143 ?? */
5081                 devpriv->clock_and_fout |= (NISTC_CLK_FOUT_AI_OUT_DIV2 |
5082                                             NISTC_CLK_FOUT_AO_OUT_DIV2);
5083         }
5084         ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
5085
5086         ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
5087         if (ret)
5088                 return ret;
5089
5090         /* Analog Input subdevice */
5091         s = &dev->subdevices[NI_AI_SUBDEV];
5092         if (board->n_adchan) {
5093                 s->type         = COMEDI_SUBD_AI;
5094                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_DITHER;
5095                 if (!devpriv->is_611x)
5096                         s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
5097                 if (board->ai_maxdata > 0xffff)
5098                         s->subdev_flags |= SDF_LSAMPL;
5099                 if (devpriv->is_m_series)
5100                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
5101                 s->n_chan       = board->n_adchan;
5102                 s->maxdata      = board->ai_maxdata;
5103                 s->range_table  = ni_range_lkup[board->gainlkup];
5104                 s->insn_read    = ni_ai_insn_read;
5105                 s->insn_config  = ni_ai_insn_config;
5106                 if (dev->irq) {
5107                         dev->read_subdev = s;
5108                         s->subdev_flags |= SDF_CMD_READ;
5109                         s->len_chanlist = 512;
5110                         s->do_cmdtest   = ni_ai_cmdtest;
5111                         s->do_cmd       = ni_ai_cmd;
5112                         s->cancel       = ni_ai_reset;
5113                         s->poll         = ni_ai_poll;
5114                         s->munge        = ni_ai_munge;
5115
5116                         if (devpriv->mite)
5117                                 s->async_dma_dir = DMA_FROM_DEVICE;
5118                 }
5119
5120                 /* reset the analog input configuration */
5121                 ni_ai_reset(dev, s);
5122         } else {
5123                 s->type         = COMEDI_SUBD_UNUSED;
5124         }
5125
5126         /* Analog Output subdevice */
5127         s = &dev->subdevices[NI_AO_SUBDEV];
5128         if (board->n_aochan) {
5129                 s->type         = COMEDI_SUBD_AO;
5130                 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
5131                 if (devpriv->is_m_series)
5132                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
5133                 s->n_chan       = board->n_aochan;
5134                 s->maxdata      = board->ao_maxdata;
5135                 s->range_table  = board->ao_range_table;
5136                 s->insn_config  = ni_ao_insn_config;
5137                 s->insn_write   = ni_ao_insn_write;
5138
5139                 ret = comedi_alloc_subdev_readback(s);
5140                 if (ret)
5141                         return ret;
5142
5143                 /*
5144                  * Along with the IRQ we need either a FIFO or DMA for
5145                  * async command support.
5146                  */
5147                 if (dev->irq && (board->ao_fifo_depth || devpriv->mite)) {
5148                         dev->write_subdev = s;
5149                         s->subdev_flags |= SDF_CMD_WRITE;
5150                         s->len_chanlist = s->n_chan;
5151                         s->do_cmdtest   = ni_ao_cmdtest;
5152                         s->do_cmd       = ni_ao_cmd;
5153                         s->cancel       = ni_ao_reset;
5154                         if (!devpriv->is_m_series)
5155                                 s->munge        = ni_ao_munge;
5156
5157                         if (devpriv->mite)
5158                                 s->async_dma_dir = DMA_TO_DEVICE;
5159                 }
5160
5161                 if (devpriv->is_67xx)
5162                         init_ao_67xx(dev, s);
5163
5164                 /* reset the analog output configuration */
5165                 ni_ao_reset(dev, s);
5166         } else {
5167                 s->type         = COMEDI_SUBD_UNUSED;
5168         }
5169
5170         /* Digital I/O subdevice */
5171         s = &dev->subdevices[NI_DIO_SUBDEV];
5172         s->type         = COMEDI_SUBD_DIO;
5173         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
5174         s->n_chan       = board->has_32dio_chan ? 32 : 8;
5175         s->maxdata      = 1;
5176         s->range_table  = &range_digital;
5177         if (devpriv->is_m_series) {
5178                 s->subdev_flags |= SDF_LSAMPL;
5179                 s->insn_bits    = ni_m_series_dio_insn_bits;
5180                 s->insn_config  = ni_m_series_dio_insn_config;
5181                 if (dev->irq) {
5182                         s->subdev_flags |= SDF_CMD_WRITE /* | SDF_CMD_READ */;
5183                         s->len_chanlist = s->n_chan;
5184                         s->do_cmdtest   = ni_cdio_cmdtest;
5185                         s->do_cmd       = ni_cdio_cmd;
5186                         s->cancel       = ni_cdio_cancel;
5187
5188                         /* M-series boards use DMA */
5189                         s->async_dma_dir = DMA_BIDIRECTIONAL;
5190                 }
5191
5192                 /* reset DIO and set all channels to inputs */
5193                 ni_writel(dev, NI_M_CDO_CMD_RESET |
5194                                NI_M_CDI_CMD_RESET,
5195                           NI_M_CDIO_CMD_REG);
5196                 ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
5197         } else {
5198                 s->insn_bits    = ni_dio_insn_bits;
5199                 s->insn_config  = ni_dio_insn_config;
5200
5201                 /* set all channels to inputs */
5202                 devpriv->dio_control = NISTC_DIO_CTRL_DIR(s->io_bits);
5203                 ni_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
5204         }
5205
5206         /* 8255 device */
5207         s = &dev->subdevices[NI_8255_DIO_SUBDEV];
5208         if (board->has_8255) {
5209                 ret = subdev_8255_init(dev, s, ni_8255_callback, Port_A);
5210                 if (ret)
5211                         return ret;
5212         } else {
5213                 s->type = COMEDI_SUBD_UNUSED;
5214         }
5215
5216         /* formerly general purpose counter/timer device, but no longer used */
5217         s = &dev->subdevices[NI_UNUSED_SUBDEV];
5218         s->type = COMEDI_SUBD_UNUSED;
5219
5220         /* Calibration subdevice */
5221         s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
5222         s->type         = COMEDI_SUBD_CALIB;
5223         s->subdev_flags = SDF_INTERNAL;
5224         s->n_chan       = 1;
5225         s->maxdata      = 0;
5226         if (devpriv->is_m_series) {
5227                 /* internal PWM output used for AI nonlinearity calibration */
5228                 s->insn_config  = ni_m_series_pwm_config;
5229
5230                 ni_writel(dev, 0x0, NI_M_CAL_PWM_REG);
5231         } else if (devpriv->is_6143) {
5232                 /* internal PWM output used for AI nonlinearity calibration */
5233                 s->insn_config  = ni_6143_pwm_config;
5234         } else {
5235                 s->subdev_flags |= SDF_WRITABLE;
5236                 s->insn_read    = ni_calib_insn_read;
5237                 s->insn_write   = ni_calib_insn_write;
5238
5239                 /* setup the caldacs and find the real n_chan and maxdata */
5240                 caldac_setup(dev, s);
5241         }
5242
5243         /* EEPROM subdevice */
5244         s = &dev->subdevices[NI_EEPROM_SUBDEV];
5245         s->type         = COMEDI_SUBD_MEMORY;
5246         s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
5247         s->maxdata      = 0xff;
5248         if (devpriv->is_m_series) {
5249                 s->n_chan       = M_SERIES_EEPROM_SIZE;
5250                 s->insn_read    = ni_m_series_eeprom_insn_read;
5251         } else {
5252                 s->n_chan       = 512;
5253                 s->insn_read    = ni_eeprom_insn_read;
5254         }
5255
5256         /* Digital I/O (PFI) subdevice */
5257         s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
5258         s->type         = COMEDI_SUBD_DIO;
5259         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5260         s->maxdata      = 1;
5261         if (devpriv->is_m_series) {
5262                 s->n_chan       = 16;
5263                 s->insn_bits    = ni_pfi_insn_bits;
5264
5265                 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
5266                 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
5267                         ni_writew(dev, devpriv->pfi_output_select_reg[i],
5268                                   NI_M_PFI_OUT_SEL_REG(i));
5269                 }
5270         } else {
5271                 s->n_chan       = 10;
5272         }
5273         s->insn_config  = ni_pfi_insn_config;
5274
5275         ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, ~0, 0);
5276
5277         /* cs5529 calibration adc */
5278         s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
5279         if (devpriv->is_67xx) {
5280                 s->type = COMEDI_SUBD_AI;
5281                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
5282                 /*  one channel for each analog output channel */
5283                 s->n_chan = board->n_aochan;
5284                 s->maxdata = (1 << 16) - 1;
5285                 s->range_table = &range_unknown;        /* XXX */
5286                 s->insn_read = cs5529_ai_insn_read;
5287                 s->insn_config = NULL;
5288                 init_cs5529(dev);
5289         } else {
5290                 s->type = COMEDI_SUBD_UNUSED;
5291         }
5292
5293         /* Serial */
5294         s = &dev->subdevices[NI_SERIAL_SUBDEV];
5295         s->type = COMEDI_SUBD_SERIAL;
5296         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5297         s->n_chan = 1;
5298         s->maxdata = 0xff;
5299         s->insn_config = ni_serial_insn_config;
5300         devpriv->serial_interval_ns = 0;
5301         devpriv->serial_hw_mode = 0;
5302
5303         /* RTSI */
5304         s = &dev->subdevices[NI_RTSI_SUBDEV];
5305         s->type = COMEDI_SUBD_DIO;
5306         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5307         s->n_chan = 8;
5308         s->maxdata = 1;
5309         s->insn_bits = ni_rtsi_insn_bits;
5310         s->insn_config = ni_rtsi_insn_config;
5311         ni_rtsi_init(dev);
5312
5313         /* allocate and initialize the gpct counter device */
5314         devpriv->counter_dev = ni_gpct_device_construct(dev,
5315                                         ni_gpct_write_register,
5316                                         ni_gpct_read_register,
5317                                         (devpriv->is_m_series)
5318                                                 ? ni_gpct_variant_m_series
5319                                                 : ni_gpct_variant_e_series,
5320                                         NUM_GPCT);
5321         if (!devpriv->counter_dev)
5322                 return -ENOMEM;
5323
5324         /* Counter (gpct) subdevices */
5325         for (i = 0; i < NUM_GPCT; ++i) {
5326                 struct ni_gpct *gpct = &devpriv->counter_dev->counters[i];
5327
5328                 /* setup and initialize the counter */
5329                 gpct->chip_index = 0;
5330                 gpct->counter_index = i;
5331                 ni_tio_init_counter(gpct);
5332
5333                 s = &dev->subdevices[NI_GPCT_SUBDEV(i)];
5334                 s->type         = COMEDI_SUBD_COUNTER;
5335                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL;
5336                 s->n_chan       = 3;
5337                 s->maxdata      = (devpriv->is_m_series) ? 0xffffffff
5338                                                          : 0x00ffffff;
5339                 s->insn_read    = ni_tio_insn_read;
5340                 s->insn_write   = ni_tio_insn_read;
5341                 s->insn_config  = ni_tio_insn_config;
5342 #ifdef PCIDMA
5343                 if (dev->irq && devpriv->mite) {
5344                         s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */;
5345                         s->len_chanlist = 1;
5346                         s->do_cmdtest   = ni_tio_cmdtest;
5347                         s->do_cmd       = ni_gpct_cmd;
5348                         s->cancel       = ni_gpct_cancel;
5349
5350                         s->async_dma_dir = DMA_BIDIRECTIONAL;
5351                 }
5352 #endif
5353                 s->private      = gpct;
5354         }
5355
5356         /* Frequency output subdevice */
5357         s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
5358         s->type         = COMEDI_SUBD_COUNTER;
5359         s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
5360         s->n_chan       = 1;
5361         s->maxdata      = 0xf;
5362         s->insn_read    = ni_freq_out_insn_read;
5363         s->insn_write   = ni_freq_out_insn_write;
5364         s->insn_config  = ni_freq_out_insn_config;
5365
5366         if (dev->irq) {
5367                 ni_stc_writew(dev,
5368                               (irq_polarity ? NISTC_INT_CTRL_INT_POL : 0) |
5369                               (NISTC_INT_CTRL_3PIN_INT & 0) |
5370                               NISTC_INT_CTRL_INTA_ENA |
5371                               NISTC_INT_CTRL_INTB_ENA |
5372                               NISTC_INT_CTRL_INTA_SEL(interrupt_pin) |
5373                               NISTC_INT_CTRL_INTB_SEL(interrupt_pin),
5374                               NISTC_INT_CTRL_REG);
5375         }
5376
5377         /* DMA setup */
5378         ni_writeb(dev, devpriv->ai_ao_select_reg, AI_AO_Select);
5379         ni_writeb(dev, devpriv->g0_g1_select_reg, G0_G1_Select);
5380
5381         if (devpriv->is_6xxx) {
5382                 ni_writeb(dev, 0, Magic_611x);
5383         } else if (devpriv->is_m_series) {
5384                 int channel;
5385
5386                 for (channel = 0; channel < board->n_aochan; ++channel) {
5387                         ni_writeb(dev, 0xf,
5388                                   NI_M_AO_WAVEFORM_ORDER_REG(channel));
5389                         ni_writeb(dev, 0x0,
5390                                   NI_M_AO_REF_ATTENUATION_REG(channel));
5391                 }
5392                 ni_writeb(dev, 0x0, NI_M_AO_CALIB_REG);
5393         }
5394
5395         return 0;
5396 }
5397
5398 static void mio_common_detach(struct comedi_device *dev)
5399 {
5400         struct ni_private *devpriv = dev->private;
5401
5402         if (devpriv) {
5403                 if (devpriv->counter_dev)
5404                         ni_gpct_device_destroy(devpriv->counter_dev);
5405         }
5406 }