drivers/staging/comedi/drivers/ni_pcidio.c

   1 /*
   2     comedi/drivers/ni_pcidio.c
   3     driver for National Instruments PCI-DIO-32HS
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1999,2002 David A. Schleef <ds@schleef.org>
   7
   8     This program is free software; you can redistribute it and/or modify
   9     it under the terms of the GNU General Public License as published by
  10     the Free Software Foundation; either version 2 of the License, or
  11     (at your option) any later version.
  12
  13     This program is distributed in the hope that it will be useful,
  14     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16     GNU General Public License for more details.
  17 */
  18 /*
  19 Driver: ni_pcidio
  20 Description: National Instruments PCI-DIO32HS, PCI-6533
  21 Author: ds
  22 Status: works
  23 Devices: [National Instruments] PCI-DIO-32HS (ni_pcidio)
  24          [National Instruments] PXI-6533, PCI-6533 (pxi-6533)
  25          [National Instruments] PCI-6534 (pci-6534)
  26 Updated: Mon, 09 Jan 2012 14:27:23 +0000
  27
  28 The DIO32HS board appears as one subdevice, with 32 channels.
  29 Each channel is individually I/O configurable.  The channel order
  30 is 0=A0, 1=A1, 2=A2, ... 8=B0, 16=C0, 24=D0.  The driver only
  31 supports simple digital I/O; no handshaking is supported.
  32
  33 DMA mostly works for the PCI-DIO32HS, but only in timed input mode.
  34
  35 The PCI-DIO-32HS/PCI-6533 has a configurable external trigger. Setting
  36 scan_begin_arg to 0 or CR_EDGE triggers on the leading edge. Setting
  37 scan_begin_arg to CR_INVERT or (CR_EDGE | CR_INVERT) triggers on the
  38 trailing edge.
  39
  40 This driver could be easily modified to support AT-MIO32HS and
  41 AT-MIO96.
  42
  43 The PCI-6534 requires a firmware upload after power-up to work, the
  44 firmware data and instructions for loading it with comedi_config
  45 it are contained in the
  46 comedi_nonfree_firmware tarball available from http://www.comedi.org
  47 */
  48
  49 #define USE_DMA
  50 /* #define DEBUG_FLAGS */
  51
  52 #include <linux/module.h>
  53 #include <linux/delay.h>
  54 #include <linux/interrupt.h>
  55 #include <linux/sched.h>
  56
  57 #include "../comedidev.h"
  58
  59 #include "comedi_fc.h"
  60 #include "mite.h"
  61
  62 #define PCI_DIO_SIZE 4096
  63 #define PCI_MITE_SIZE 4096
  64
  65 /* defines for the PCI-DIO-32HS */
  66
  67 #define Window_Address                  4       /* W */
  68 #define Interrupt_And_Window_Status     4       /* R */
  69 #define IntStatus1                              (1<<0)
  70 #define IntStatus2                              (1<<1)
  71 #define WindowAddressStatus_mask                0x7c
  72
  73 #define Master_DMA_And_Interrupt_Control 5      /* W */
  74 #define InterruptLine(x)                        ((x)&3)
  75 #define OpenInt                         (1<<2)
  76 #define Group_Status                    5       /* R */
  77 #define DataLeft                                (1<<0)
  78 #define Req                                     (1<<2)
  79 #define StopTrig                                (1<<3)
  80
  81 #define Group_1_Flags                   6       /* R */
  82 #define Group_2_Flags                   7       /* R */
  83 #define TransferReady                           (1<<0)
  84 #define CountExpired                            (1<<1)
  85 #define Waited                          (1<<5)
  86 #define PrimaryTC                               (1<<6)
  87 #define SecondaryTC                             (1<<7)
  88   /* #define SerialRose */
  89   /* #define ReqRose */
  90   /* #define Paused */
  91
  92 #define Group_1_First_Clear             6       /* W */
  93 #define Group_2_First_Clear             7       /* W */
  94 #define ClearWaited                             (1<<3)
  95 #define ClearPrimaryTC                  (1<<4)
  96 #define ClearSecondaryTC                        (1<<5)
  97 #define DMAReset                                (1<<6)
  98 #define FIFOReset                               (1<<7)
  99 #define ClearAll                                0xf8
 100
 101 #define Group_1_FIFO                    8       /* W */
 102 #define Group_2_FIFO                    12      /* W */
 103
 104 #define Transfer_Count                  20
 105 #define Chip_ID_D                       24
 106 #define Chip_ID_I                       25
 107 #define Chip_ID_O                       26
 108 #define Chip_Version                    27
 109 #define Port_IO(x)                      (28+(x))
 110 #define Port_Pin_Directions(x)          (32+(x))
 111 #define Port_Pin_Mask(x)                (36+(x))
 112 #define Port_Pin_Polarities(x)          (40+(x))
 113
 114 #define Master_Clock_Routing            45
 115 #define RTSIClocking(x)                 (((x)&3)<<4)
 116
 117 #define Group_1_Second_Clear            46      /* W */
 118 #define Group_2_Second_Clear            47      /* W */
 119 #define ClearExpired                            (1<<0)
 120
 121 #define Port_Pattern(x)                 (48+(x))
 122
 123 #define Data_Path                       64
 124 #define FIFOEnableA             (1<<0)
 125 #define FIFOEnableB             (1<<1)
 126 #define FIFOEnableC             (1<<2)
 127 #define FIFOEnableD             (1<<3)
 128 #define Funneling(x)            (((x)&3)<<4)
 129 #define GroupDirection  (1<<7)
 130
 131 #define Protocol_Register_1             65
 132 #define OpMode                          Protocol_Register_1
 133 #define RunMode(x)              ((x)&7)
 134 #define Numbered                (1<<3)
 135
 136 #define Protocol_Register_2             66
 137 #define ClockReg                        Protocol_Register_2
 138 #define ClockLine(x)            (((x)&3)<<5)
 139 #define InvertStopTrig  (1<<7)
 140 #define DataLatching(x)       (((x)&3)<<5)
 141
 142 #define Protocol_Register_3             67
 143 #define Sequence                        Protocol_Register_3
 144
 145 #define Protocol_Register_14            68      /* 16 bit */
 146 #define ClockSpeed                      Protocol_Register_14
 147
 148 #define Protocol_Register_4             70
 149 #define ReqReg                          Protocol_Register_4
 150 #define ReqConditioning(x)      (((x)&7)<<3)
 151
 152 #define Protocol_Register_5             71
 153 #define BlockMode                       Protocol_Register_5
 154
 155 #define FIFO_Control                    72
 156 #define ReadyLevel(x)           ((x)&7)
 157
 158 #define Protocol_Register_6             73
 159 #define LinePolarities                  Protocol_Register_6
 160 #define InvertAck               (1<<0)
 161 #define InvertReq               (1<<1)
 162 #define InvertClock             (1<<2)
 163 #define InvertSerial            (1<<3)
 164 #define OpenAck         (1<<4)
 165 #define OpenClock               (1<<5)
 166
 167 #define Protocol_Register_7             74
 168 #define AckSer                          Protocol_Register_7
 169 #define AckLine(x)              (((x)&3)<<2)
 170 #define ExchangePins            (1<<7)
 171
 172 #define Interrupt_Control               75
 173   /* bits same as flags */
 174
 175 #define DMA_Line_Control_Group1         76
 176 #define DMA_Line_Control_Group2         108
 177 /* channel zero is none */
 178 static inline unsigned primary_DMAChannel_bits(unsigned channel)
 179 {
 180         return channel & 0x3;
 181 }
 182
 183 static inline unsigned secondary_DMAChannel_bits(unsigned channel)
 184 {
 185         return (channel << 2) & 0xc;
 186 }
 187
 188 #define Transfer_Size_Control           77
 189 #define TransferWidth(x)        ((x)&3)
 190 #define TransferLength(x)       (((x)&3)<<3)
 191 #define RequireRLevel           (1<<5)
 192
 193 #define Protocol_Register_15            79
 194 #define DAQOptions                      Protocol_Register_15
 195 #define StartSource(x)                  ((x)&0x3)
 196 #define InvertStart                             (1<<2)
 197 #define StopSource(x)                           (((x)&0x3)<<3)
 198 #define ReqStart                                (1<<6)
 199 #define PreStart                                (1<<7)
 200
 201 #define Pattern_Detection               81
 202 #define DetectionMethod                 (1<<0)
 203 #define InvertMatch                             (1<<1)
 204 #define IE_Pattern_Detection                    (1<<2)
 205
 206 #define Protocol_Register_9             82
 207 #define ReqDelay                        Protocol_Register_9
 208
 209 #define Protocol_Register_10            83
 210 #define ReqNotDelay                     Protocol_Register_10
 211
 212 #define Protocol_Register_11            84
 213 #define AckDelay                        Protocol_Register_11
 214
 215 #define Protocol_Register_12            85
 216 #define AckNotDelay                     Protocol_Register_12
 217
 218 #define Protocol_Register_13            86
 219 #define Data1Delay                      Protocol_Register_13
 220
 221 #define Protocol_Register_8             88      /* 32 bit */
 222 #define StartDelay                      Protocol_Register_8
 223
 224 /* Firmware files for PCI-6524 */
 225 #define FW_PCI_6534_MAIN                "ni6534a.bin"
 226 #define FW_PCI_6534_SCARAB_DI           "niscrb01.bin"
 227 #define FW_PCI_6534_SCARAB_DO           "niscrb02.bin"
 228 MODULE_FIRMWARE(FW_PCI_6534_MAIN);
 229 MODULE_FIRMWARE(FW_PCI_6534_SCARAB_DI);
 230 MODULE_FIRMWARE(FW_PCI_6534_SCARAB_DO);
 231
 232 enum pci_6534_firmware_registers {      /* 16 bit */
 233         Firmware_Control_Register = 0x100,
 234         Firmware_Status_Register = 0x104,
 235         Firmware_Data_Register = 0x108,
 236         Firmware_Mask_Register = 0x10c,
 237         Firmware_Debug_Register = 0x110,
 238 };
 239 /* main fpga registers (32 bit)*/
 240 enum pci_6534_fpga_registers {
 241         FPGA_Control1_Register = 0x200,
 242         FPGA_Control2_Register = 0x204,
 243         FPGA_Irq_Mask_Register = 0x208,
 244         FPGA_Status_Register = 0x20c,
 245         FPGA_Signature_Register = 0x210,
 246         FPGA_SCALS_Counter_Register = 0x280,    /*write-clear */
 247         FPGA_SCAMS_Counter_Register = 0x284,    /*write-clear */
 248         FPGA_SCBLS_Counter_Register = 0x288,    /*write-clear */
 249         FPGA_SCBMS_Counter_Register = 0x28c,    /*write-clear */
 250         FPGA_Temp_Control_Register = 0x2a0,
 251         FPGA_DAR_Register = 0x2a8,
 252         FPGA_ELC_Read_Register = 0x2b8,
 253         FPGA_ELC_Write_Register = 0x2bc,
 254 };
 255 enum FPGA_Control_Bits {
 256         FPGA_Enable_Bit = 0x8000,
 257 };
 258
 259 #define TIMER_BASE 50           /* nanoseconds */
 260
 261 #ifdef USE_DMA
 262 #define IntEn (CountExpired|Waited|PrimaryTC|SecondaryTC)
 263 #else
 264 #define IntEn (TransferReady|CountExpired|Waited|PrimaryTC|SecondaryTC)
 265 #endif
 266
 267 static int ni_pcidio_cancel(struct comedi_device *dev,
 268                             struct comedi_subdevice *s);
 269
 270 enum nidio_boardid {
 271         BOARD_PCIDIO_32HS,
 272         BOARD_PXI6533,
 273         BOARD_PCI6534,
 274 };
 275
 276 struct nidio_board {
 277         const char *name;
 278         unsigned int uses_firmware:1;
 279 };
 280
 281 static const struct nidio_board nidio_boards[] = {
 282         [BOARD_PCIDIO_32HS] = {
 283                 .name           = "pci-dio-32hs",
 284         },
 285         [BOARD_PXI6533] = {
 286                 .name           = "pxi-6533",
 287         },
 288         [BOARD_PCI6534] = {
 289                 .name           = "pci-6534",
 290                 .uses_firmware  = 1,
 291         },
 292 };
 293
 294 struct nidio96_private {
 295         struct mite_struct *mite;
 296         int boardtype;
 297         int dio;
 298         unsigned short OpModeBits;
 299         struct mite_channel *di_mite_chan;
 300         struct mite_dma_descriptor_ring *di_mite_ring;
 301         spinlock_t mite_channel_lock;
 302 };
 303
 304 static int ni_pcidio_cmdtest(struct comedi_device *dev,
 305                              struct comedi_subdevice *s,
 306                              struct comedi_cmd *cmd);
 307 static int ni_pcidio_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
 308 static int ni_pcidio_inttrig(struct comedi_device *dev,
 309                              struct comedi_subdevice *s, unsigned int trignum);
 310 static int ni_pcidio_ns_to_timer(int *nanosec, int round_mode);
 311 static int setup_mite_dma(struct comedi_device *dev,
 312                           struct comedi_subdevice *s);
 313
 314 #ifdef DEBUG_FLAGS
 315 static void ni_pcidio_print_flags(unsigned int flags);
 316 static void ni_pcidio_print_status(unsigned int status);
 317 #else
 318 #define ni_pcidio_print_flags(x)
 319 #define ni_pcidio_print_status(x)
 320 #endif
 321
 322 static int ni_pcidio_request_di_mite_channel(struct comedi_device *dev)
 323 {
 324         struct nidio96_private *devpriv = dev->private;
 325         unsigned long flags;
 326
 327         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 328         BUG_ON(devpriv->di_mite_chan);
 329         devpriv->di_mite_chan =
 330             mite_request_channel_in_range(devpriv->mite,
 331                                           devpriv->di_mite_ring, 1, 2);
 332         if (devpriv->di_mite_chan == NULL) {
 333                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 334                 comedi_error(dev, "failed to reserve mite dma channel.");
 335                 return -EBUSY;
 336         }
 337         devpriv->di_mite_chan->dir = COMEDI_INPUT;
 338         writeb(primary_DMAChannel_bits(devpriv->di_mite_chan->channel) |
 339                secondary_DMAChannel_bits(devpriv->di_mite_chan->channel),
 340                devpriv->mite->daq_io_addr + DMA_Line_Control_Group1);
 341         mmiowb();
 342         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 343         return 0;
 344 }
 345
 346 static void ni_pcidio_release_di_mite_channel(struct comedi_device *dev)
 347 {
 348         struct nidio96_private *devpriv = dev->private;
 349         unsigned long flags;
 350
 351         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 352         if (devpriv->di_mite_chan) {
 353                 mite_dma_disarm(devpriv->di_mite_chan);
 354                 mite_dma_reset(devpriv->di_mite_chan);
 355                 mite_release_channel(devpriv->di_mite_chan);
 356                 devpriv->di_mite_chan = NULL;
 357                 writeb(primary_DMAChannel_bits(0) |
 358                        secondary_DMAChannel_bits(0),
 359                        devpriv->mite->daq_io_addr + DMA_Line_Control_Group1);
 360                 mmiowb();
 361         }
 362         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 363 }
 364
 365 static void ni_pcidio_event(struct comedi_device *dev,
 366                             struct comedi_subdevice *s)
 367 {
 368         if (s->
 369             async->events & (COMEDI_CB_EOA | COMEDI_CB_ERROR |
 370                              COMEDI_CB_OVERFLOW)) {
 371                 ni_pcidio_cancel(dev, s);
 372         }
 373         comedi_event(dev, s);
 374 }
 375
 376 static int ni_pcidio_poll(struct comedi_device *dev, struct comedi_subdevice *s)
 377 {
 378         struct nidio96_private *devpriv = dev->private;
 379         unsigned long irq_flags;
 380         int count;
 381
 382         spin_lock_irqsave(&dev->spinlock, irq_flags);
 383         spin_lock(&devpriv->mite_channel_lock);
 384         if (devpriv->di_mite_chan)
 385                 mite_sync_input_dma(devpriv->di_mite_chan, s->async);
 386         spin_unlock(&devpriv->mite_channel_lock);
 387         count = s->async->buf_write_count - s->async->buf_read_count;
 388         spin_unlock_irqrestore(&dev->spinlock, irq_flags);
 389         return count;
 390 }
 391
 392 static irqreturn_t nidio_interrupt(int irq, void *d)
 393 {
 394         struct comedi_device *dev = d;
 395         struct nidio96_private *devpriv = dev->private;
 396         struct comedi_subdevice *s = &dev->subdevices[0];
 397         struct comedi_async *async = s->async;
 398         struct mite_struct *mite = devpriv->mite;
 399
 400         /* int i, j; */
 401         unsigned int auxdata = 0;
 402         unsigned short data1 = 0;
 403         unsigned short data2 = 0;
 404         int flags;
 405         int status;
 406         int work = 0;
 407         unsigned int m_status = 0;
 408
 409         /* interrupcions parasites */
 410         if (!dev->attached) {
 411                 /* assume it's from another card */
 412                 return IRQ_NONE;
 413         }
 414
 415         /* Lock to avoid race with comedi_poll */
 416         spin_lock(&dev->spinlock);
 417
 418         status = readb(devpriv->mite->daq_io_addr +
 419                        Interrupt_And_Window_Status);
 420         flags = readb(devpriv->mite->daq_io_addr + Group_1_Flags);
 421
 422         DPRINTK("ni_pcidio_interrupt: status=0x%02x,flags=0x%02x\n",
 423                 status, flags);
 424         ni_pcidio_print_flags(flags);
 425         ni_pcidio_print_status(status);
 426
 427         spin_lock(&devpriv->mite_channel_lock);
 428         if (devpriv->di_mite_chan)
 429                 m_status = mite_get_status(devpriv->di_mite_chan);
 430 #ifdef MITE_DEBUG
 431         mite_print_chsr(m_status);
 432 #endif
 433
 434         /* mite_dump_regs(mite); */
 435         if (m_status & CHSR_INT) {
 436                 if (m_status & CHSR_LINKC) {
 437                         writel(CHOR_CLRLC,
 438                                mite->mite_io_addr +
 439                                MITE_CHOR(devpriv->di_mite_chan->channel));
 440                         mite_sync_input_dma(devpriv->di_mite_chan, s->async);
 441                         /* XXX need to byteswap */
 442                 }
 443                 if (m_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_DRDY |
 444                                  CHSR_DRQ1 | CHSR_MRDY)) {
 445                         DPRINTK("unknown mite interrupt, disabling IRQ\n");
 446                         async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
 447                         disable_irq(dev->irq);
 448                 }
 449         }
 450         spin_unlock(&devpriv->mite_channel_lock);
 451
 452         while (status & DataLeft) {
 453                 work++;
 454                 if (work > 20) {
 455                         DPRINTK("too much work in interrupt\n");
 456                         writeb(0x00,
 457                                devpriv->mite->daq_io_addr +
 458                                Master_DMA_And_Interrupt_Control);
 459                         break;
 460                 }
 461
 462                 flags &= IntEn;
 463
 464                 if (flags & TransferReady) {
 465                         /* DPRINTK("TransferReady\n"); */
 466                         while (flags & TransferReady) {
 467                                 work++;
 468                                 if (work > 100) {
 469                                         DPRINTK("too much work in interrupt\n");
 470                                         writeb(0x00,
 471                                                devpriv->mite->daq_io_addr +
 472                                                Master_DMA_And_Interrupt_Control
 473                                               );
 474                                         goto out;
 475                                 }
 476                                 auxdata =
 477                                     readl(devpriv->mite->daq_io_addr +
 478                                           Group_1_FIFO);
 479                                 data1 = auxdata & 0xffff;
 480                                 data2 = (auxdata & 0xffff0000) >> 16;
 481                                 comedi_buf_put(async, data1);
 482                                 comedi_buf_put(async, data2);
 483                                 /* DPRINTK("read:%d, %d\n",data1,data2); */
 484                                 flags = readb(devpriv->mite->daq_io_addr +
 485                                               Group_1_Flags);
 486                         }
 487                         /* DPRINTK("buf_int_count: %d\n",
 488                                 async->buf_int_count); */
 489                         /* DPRINTK("1) IntEn=%d,flags=%d,status=%d\n",
 490                                 IntEn,flags,status); */
 491                         /* ni_pcidio_print_flags(flags); */
 492                         /* ni_pcidio_print_status(status); */
 493                         async->events |= COMEDI_CB_BLOCK;
 494                 }
 495
 496                 if (flags & CountExpired) {
 497                         DPRINTK("CountExpired\n");
 498                         writeb(ClearExpired,
 499                                devpriv->mite->daq_io_addr +
 500                                Group_1_Second_Clear);
 501                         async->events |= COMEDI_CB_EOA;
 502
 503                         writeb(0x00, devpriv->mite->daq_io_addr + OpMode);
 504                         break;
 505                 } else if (flags & Waited) {
 506                         DPRINTK("Waited\n");
 507                         writeb(ClearWaited,
 508                                devpriv->mite->daq_io_addr +
 509                                Group_1_First_Clear);
 510                         async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
 511                         break;
 512                 } else if (flags & PrimaryTC) {
 513                         DPRINTK("PrimaryTC\n");
 514                         writeb(ClearPrimaryTC,
 515                                devpriv->mite->daq_io_addr +
 516                                Group_1_First_Clear);
 517                         async->events |= COMEDI_CB_EOA;
 518                 } else if (flags & SecondaryTC) {
 519                         DPRINTK("SecondaryTC\n");
 520                         writeb(ClearSecondaryTC,
 521                                devpriv->mite->daq_io_addr +
 522                                Group_1_First_Clear);
 523                         async->events |= COMEDI_CB_EOA;
 524                 }
 525 #if 0
 526                 else {
 527                         DPRINTK("ni_pcidio: unknown interrupt\n");
 528                         async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
 529                         writeb(0x00,
 530                                devpriv->mite->daq_io_addr +
 531                                Master_DMA_And_Interrupt_Control);
 532                 }
 533 #endif
 534                 flags = readb(devpriv->mite->daq_io_addr + Group_1_Flags);
 535                 status = readb(devpriv->mite->daq_io_addr +
 536                                Interrupt_And_Window_Status);
 537                 /* DPRINTK("loop end: IntEn=0x%02x,flags=0x%02x,"
 538                         "status=0x%02x\n", IntEn, flags, status); */
 539                 /* ni_pcidio_print_flags(flags); */
 540                 /* ni_pcidio_print_status(status); */
 541         }
 542
 543 out:
 544         ni_pcidio_event(dev, s);
 545 #if 0
 546         if (!tag) {
 547                 writeb(0x03,
 548                        devpriv->mite->daq_io_addr +
 549                        Master_DMA_And_Interrupt_Control);
 550         }
 551 #endif
 552
 553         spin_unlock(&dev->spinlock);
 554         return IRQ_HANDLED;
 555 }
 556
 557 #ifdef DEBUG_FLAGS
 558 static const char *bit_set_string(unsigned int bits, unsigned int bit,
 559                                   const char *const strings[])
 560 {
 561         return (bits & (1U << bit)) ? strings[bit] : "";
 562 }
 563
 564 static const char *const flags_strings[] = {
 565         " TransferReady", " CountExpired", " 2", " 3",
 566         " 4", " Waited", " PrimaryTC", " SecondaryTC",
 567 };
 568
 569
 570 static void ni_pcidio_print_flags(unsigned int flags)
 571 {
 572         pr_debug("group_1_flags:%s%s%s%s%s%s%s%s\n",
 573                  bit_set_string(flags, 7, flags_strings),
 574                  bit_set_string(flags, 6, flags_strings),
 575                  bit_set_string(flags, 5, flags_strings),
 576                  bit_set_string(flags, 4, flags_strings),
 577                  bit_set_string(flags, 3, flags_strings),
 578                  bit_set_string(flags, 2, flags_strings),
 579                  bit_set_string(flags, 1, flags_strings),
 580                  bit_set_string(flags, 0, flags_strings));
 581 }
 582
 583 static const char *const status_strings[] = {
 584         " DataLeft1", " Reserved1", " Req1", " StopTrig1",
 585         " DataLeft2", " Reserved2", " Req2", " StopTrig2",
 586 };
 587
 588 static void ni_pcidio_print_status(unsigned int flags)
 589 {
 590         pr_debug("group_status:%s%s%s%s%s%s%s%s\n",
 591                  bit_set_string(flags, 7, status_strings),
 592                  bit_set_string(flags, 6, status_strings),
 593                  bit_set_string(flags, 5, status_strings),
 594                  bit_set_string(flags, 4, status_strings),
 595                  bit_set_string(flags, 3, status_strings),
 596                  bit_set_string(flags, 2, status_strings),
 597                  bit_set_string(flags, 1, status_strings),
 598                  bit_set_string(flags, 0, status_strings));
 599 }
 600 #endif
 601
 602 #ifdef unused
 603 static void debug_int(struct comedi_device *dev)
 604 {
 605         struct nidio96_private *devpriv = dev->private;
 606         int a, b;
 607         static int n_int;
 608         struct timeval tv;
 609
 610         do_gettimeofday(&tv);
 611         a = readb(devpriv->mite->daq_io_addr + Group_Status);
 612         b = readb(devpriv->mite->daq_io_addr + Group_1_Flags);
 613
 614         if (n_int < 10) {
 615                 DPRINTK("status 0x%02x flags 0x%02x time %06d\n", a, b,
 616                         (int)tv.tv_usec);
 617         }
 618
 619         while (b & 1) {
 620                 writew(0xff, devpriv->mite->daq_io_addr + Group_1_FIFO);
 621                 b = readb(devpriv->mite->daq_io_addr + Group_1_Flags);
 622         }
 623
 624         b = readb(devpriv->mite->daq_io_addr + Group_1_Flags);
 625
 626         if (n_int < 10) {
 627                 DPRINTK("new status 0x%02x\n", b);
 628                 n_int++;
 629         }
 630 }
 631 #endif
 632
 633 static int ni_pcidio_insn_config(struct comedi_device *dev,
 634                                  struct comedi_subdevice *s,
 635                                  struct comedi_insn *insn,
 636                                  unsigned int *data)
 637 {
 638         struct nidio96_private *devpriv = dev->private;
 639         int ret;
 640
 641         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
 642         if (ret)
 643                 return ret;
 644
 645         writel(s->io_bits, devpriv->mite->daq_io_addr + Port_Pin_Directions(0));
 646
 647         return insn->n;
 648 }
 649
 650 static int ni_pcidio_insn_bits(struct comedi_device *dev,
 651                                struct comedi_subdevice *s,
 652                                struct comedi_insn *insn,
 653                                unsigned int *data)
 654 {
 655         struct nidio96_private *devpriv = dev->private;
 656
 657         if (comedi_dio_update_state(s, data))
 658                 writel(s->state, devpriv->mite->daq_io_addr + Port_IO(0));
 659
 660         data[1] = readl(devpriv->mite->daq_io_addr + Port_IO(0));
 661
 662         return insn->n;
 663 }
 664
 665 static int ni_pcidio_cmdtest(struct comedi_device *dev,
 666                              struct comedi_subdevice *s, struct comedi_cmd *cmd)
 667 {
 668         int err = 0;
 669         int tmp;
 670
 671         /* Step 1 : check if triggers are trivially valid */
 672
 673         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_INT);
 674         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
 675                                         TRIG_TIMER | TRIG_EXT);
 676         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
 677         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
 678         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
 679
 680         if (err)
 681                 return 1;
 682
 683         /* Step 2a : make sure trigger sources are unique */
 684
 685         err |= cfc_check_trigger_is_unique(cmd->start_src);
 686         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
 687         err |= cfc_check_trigger_is_unique(cmd->stop_src);
 688
 689         /* Step 2b : and mutually compatible */
 690
 691         if (err)
 692                 return 2;
 693
 694         /* Step 3: check if arguments are trivially valid */
 695
 696         err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
 697
 698 #define MAX_SPEED       (TIMER_BASE)    /* in nanoseconds */
 699
 700         if (cmd->scan_begin_src == TRIG_TIMER) {
 701                 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
 702                                                  MAX_SPEED);
 703                 /* no minimum speed */
 704         } else {
 705                 /* TRIG_EXT */
 706                 /* should be level/edge, hi/lo specification here */
 707                 if ((cmd->scan_begin_arg & ~(CR_EDGE | CR_INVERT)) != 0) {
 708                         cmd->scan_begin_arg &= (CR_EDGE | CR_INVERT);
 709                         err |= -EINVAL;
 710                 }
 711         }
 712
 713         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
 714         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
 715
 716         if (cmd->stop_src == TRIG_COUNT) {
 717                 /* no limit */
 718         } else {        /* TRIG_NONE */
 719                 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
 720         }
 721
 722         if (err)
 723                 return 3;
 724
 725         /* step 4: fix up any arguments */
 726
 727         if (cmd->scan_begin_src == TRIG_TIMER) {
 728                 tmp = cmd->scan_begin_arg;
 729                 ni_pcidio_ns_to_timer(&cmd->scan_begin_arg,
 730                                       cmd->flags & TRIG_ROUND_MASK);
 731                 if (tmp != cmd->scan_begin_arg)
 732                         err++;
 733         }
 734
 735         if (err)
 736                 return 4;
 737
 738         return 0;
 739 }
 740
 741 static int ni_pcidio_ns_to_timer(int *nanosec, int round_mode)
 742 {
 743         int divider, base;
 744
 745         base = TIMER_BASE;
 746
 747         switch (round_mode) {
 748         case TRIG_ROUND_NEAREST:
 749         default:
 750                 divider = (*nanosec + base / 2) / base;
 751                 break;
 752         case TRIG_ROUND_DOWN:
 753                 divider = (*nanosec) / base;
 754                 break;
 755         case TRIG_ROUND_UP:
 756                 divider = (*nanosec + base - 1) / base;
 757                 break;
 758         }
 759
 760         *nanosec = base * divider;
 761         return divider;
 762 }
 763
 764 static int ni_pcidio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
 765 {
 766         struct nidio96_private *devpriv = dev->private;
 767         struct comedi_cmd *cmd = &s->async->cmd;
 768
 769         /* XXX configure ports for input */
 770         writel(0x0000, devpriv->mite->daq_io_addr + Port_Pin_Directions(0));
 771
 772         if (1) {
 773                 /* enable fifos A B C D */
 774                 writeb(0x0f, devpriv->mite->daq_io_addr + Data_Path);
 775
 776                 /* set transfer width a 32 bits */
 777                 writeb(TransferWidth(0) | TransferLength(0),
 778                        devpriv->mite->daq_io_addr + Transfer_Size_Control);
 779         } else {
 780                 writeb(0x03, devpriv->mite->daq_io_addr + Data_Path);
 781                 writeb(TransferWidth(3) | TransferLength(0),
 782                        devpriv->mite->daq_io_addr + Transfer_Size_Control);
 783         }
 784
 785         /* protocol configuration */
 786         if (cmd->scan_begin_src == TRIG_TIMER) {
 787                 /* page 4-5, "input with internal REQs" */
 788                 writeb(0, devpriv->mite->daq_io_addr + OpMode);
 789                 writeb(0x00, devpriv->mite->daq_io_addr + ClockReg);
 790                 writeb(1, devpriv->mite->daq_io_addr + Sequence);
 791                 writeb(0x04, devpriv->mite->daq_io_addr + ReqReg);
 792                 writeb(4, devpriv->mite->daq_io_addr + BlockMode);
 793                 writeb(3, devpriv->mite->daq_io_addr + LinePolarities);
 794                 writeb(0xc0, devpriv->mite->daq_io_addr + AckSer);
 795                 writel(ni_pcidio_ns_to_timer(&cmd->scan_begin_arg,
 796                                              TRIG_ROUND_NEAREST),
 797                        devpriv->mite->daq_io_addr + StartDelay);
 798                 writeb(1, devpriv->mite->daq_io_addr + ReqDelay);
 799                 writeb(1, devpriv->mite->daq_io_addr + ReqNotDelay);
 800                 writeb(1, devpriv->mite->daq_io_addr + AckDelay);
 801                 writeb(0x0b, devpriv->mite->daq_io_addr + AckNotDelay);
 802                 writeb(0x01, devpriv->mite->daq_io_addr + Data1Delay);
 803                 /* manual, page 4-5: ClockSpeed comment is incorrectly listed
 804                  * on DAQOptions */
 805                 writew(0, devpriv->mite->daq_io_addr + ClockSpeed);
 806                 writeb(0, devpriv->mite->daq_io_addr + DAQOptions);
 807         } else {
 808                 /* TRIG_EXT */
 809                 /* page 4-5, "input with external REQs" */
 810                 writeb(0, devpriv->mite->daq_io_addr + OpMode);
 811                 writeb(0x00, devpriv->mite->daq_io_addr + ClockReg);
 812                 writeb(0, devpriv->mite->daq_io_addr + Sequence);
 813                 writeb(0x00, devpriv->mite->daq_io_addr + ReqReg);
 814                 writeb(4, devpriv->mite->daq_io_addr + BlockMode);
 815                 if (!(cmd->scan_begin_arg & CR_INVERT)) {
 816                         /* Leading Edge pulse mode */
 817                         writeb(0, devpriv->mite->daq_io_addr + LinePolarities);
 818                 } else {
 819                         /* Trailing Edge pulse mode */
 820                         writeb(2, devpriv->mite->daq_io_addr + LinePolarities);
 821                 }
 822                 writeb(0x00, devpriv->mite->daq_io_addr + AckSer);
 823                 writel(1, devpriv->mite->daq_io_addr + StartDelay);
 824                 writeb(1, devpriv->mite->daq_io_addr + ReqDelay);
 825                 writeb(1, devpriv->mite->daq_io_addr + ReqNotDelay);
 826                 writeb(1, devpriv->mite->daq_io_addr + AckDelay);
 827                 writeb(0x0C, devpriv->mite->daq_io_addr + AckNotDelay);
 828                 writeb(0x10, devpriv->mite->daq_io_addr + Data1Delay);
 829                 writew(0, devpriv->mite->daq_io_addr + ClockSpeed);
 830                 writeb(0x60, devpriv->mite->daq_io_addr + DAQOptions);
 831         }
 832
 833         if (cmd->stop_src == TRIG_COUNT) {
 834                 writel(cmd->stop_arg,
 835                        devpriv->mite->daq_io_addr + Transfer_Count);
 836         } else {
 837                 /* XXX */
 838         }
 839
 840 #ifdef USE_DMA
 841         writeb(ClearPrimaryTC | ClearSecondaryTC,
 842                devpriv->mite->daq_io_addr + Group_1_First_Clear);
 843
 844         {
 845                 int retval = setup_mite_dma(dev, s);
 846                 if (retval)
 847                         return retval;
 848         }
 849 #else
 850         writeb(0x00, devpriv->mite->daq_io_addr + DMA_Line_Control_Group1);
 851 #endif
 852         writeb(0x00, devpriv->mite->daq_io_addr + DMA_Line_Control_Group2);
 853
 854         /* clear and enable interrupts */
 855         writeb(0xff, devpriv->mite->daq_io_addr + Group_1_First_Clear);
 856         /* writeb(ClearExpired,
 857                devpriv->mite->daq_io_addr+Group_1_Second_Clear); */
 858
 859         writeb(IntEn, devpriv->mite->daq_io_addr + Interrupt_Control);
 860         writeb(0x03,
 861                devpriv->mite->daq_io_addr + Master_DMA_And_Interrupt_Control);
 862
 863         if (cmd->stop_src == TRIG_NONE) {
 864                 devpriv->OpModeBits = DataLatching(0) | RunMode(7);
 865         } else {                /* TRIG_TIMER */
 866                 devpriv->OpModeBits = Numbered | RunMode(7);
 867         }
 868         if (cmd->start_src == TRIG_NOW) {
 869                 /* start */
 870                 writeb(devpriv->OpModeBits,
 871                        devpriv->mite->daq_io_addr + OpMode);
 872                 s->async->inttrig = NULL;
 873         } else {
 874                 /* TRIG_INT */
 875                 s->async->inttrig = ni_pcidio_inttrig;
 876         }
 877
 878         DPRINTK("ni_pcidio: command started\n");
 879         return 0;
 880 }
 881
 882 static int setup_mite_dma(struct comedi_device *dev, struct comedi_subdevice *s)
 883 {
 884         struct nidio96_private *devpriv = dev->private;
 885         int retval;
 886         unsigned long flags;
 887
 888         retval = ni_pcidio_request_di_mite_channel(dev);
 889         if (retval)
 890                 return retval;
 891
 892         /* write alloc the entire buffer */
 893         comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
 894
 895         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 896         if (devpriv->di_mite_chan) {
 897                 mite_prep_dma(devpriv->di_mite_chan, 32, 32);
 898                 mite_dma_arm(devpriv->di_mite_chan);
 899         } else
 900                 retval = -EIO;
 901         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 902
 903         return retval;
 904 }
 905
 906 static int ni_pcidio_inttrig(struct comedi_device *dev,
 907                              struct comedi_subdevice *s, unsigned int trignum)
 908 {
 909         struct nidio96_private *devpriv = dev->private;
 910
 911         if (trignum != 0)
 912                 return -EINVAL;
 913
 914         writeb(devpriv->OpModeBits, devpriv->mite->daq_io_addr + OpMode);
 915         s->async->inttrig = NULL;
 916
 917         return 1;
 918 }
 919
 920 static int ni_pcidio_cancel(struct comedi_device *dev,
 921                             struct comedi_subdevice *s)
 922 {
 923         struct nidio96_private *devpriv = dev->private;
 924
 925         writeb(0x00,
 926                devpriv->mite->daq_io_addr + Master_DMA_And_Interrupt_Control);
 927         ni_pcidio_release_di_mite_channel(dev);
 928
 929         return 0;
 930 }
 931
 932 static int ni_pcidio_change(struct comedi_device *dev,
 933                             struct comedi_subdevice *s, unsigned long new_size)
 934 {
 935         struct nidio96_private *devpriv = dev->private;
 936         int ret;
 937
 938         ret = mite_buf_change(devpriv->di_mite_ring, s->async);
 939         if (ret < 0)
 940                 return ret;
 941
 942         memset(s->async->prealloc_buf, 0xaa, s->async->prealloc_bufsz);
 943
 944         return 0;
 945 }
 946
 947 static int pci_6534_load_fpga(struct comedi_device *dev,
 948                               const u8 *data, size_t data_len,
 949                               unsigned long context)
 950 {
 951         struct nidio96_private *devpriv = dev->private;
 952         static const int timeout = 1000;
 953         int fpga_index = context;
 954         int i;
 955         size_t j;
 956
 957         writew(0x80 | fpga_index,
 958                devpriv->mite->daq_io_addr + Firmware_Control_Register);
 959         writew(0xc0 | fpga_index,
 960                devpriv->mite->daq_io_addr + Firmware_Control_Register);
 961         for (i = 0;
 962              (readw(devpriv->mite->daq_io_addr +
 963                     Firmware_Status_Register) & 0x2) == 0 && i < timeout; ++i) {
 964                 udelay(1);
 965         }
 966         if (i == timeout) {
 967                 dev_warn(dev->class_dev,
 968                          "ni_pcidio: failed to load fpga %i, waiting for status 0x2\n",
 969                          fpga_index);
 970                 return -EIO;
 971         }
 972         writew(0x80 | fpga_index,
 973                devpriv->mite->daq_io_addr + Firmware_Control_Register);
 974         for (i = 0;
 975              readw(devpriv->mite->daq_io_addr + Firmware_Status_Register) !=
 976              0x3 && i < timeout; ++i) {
 977                 udelay(1);
 978         }
 979         if (i == timeout) {
 980                 dev_warn(dev->class_dev,
 981                          "ni_pcidio: failed to load fpga %i, waiting for status 0x3\n",
 982                          fpga_index);
 983                 return -EIO;
 984         }
 985         for (j = 0; j + 1 < data_len;) {
 986                 unsigned int value = data[j++];
 987                 value |= data[j++] << 8;
 988                 writew(value,
 989                        devpriv->mite->daq_io_addr + Firmware_Data_Register);
 990                 for (i = 0;
 991                      (readw(devpriv->mite->daq_io_addr +
 992                             Firmware_Status_Register) & 0x2) == 0
 993                      && i < timeout; ++i) {
 994                         udelay(1);
 995                 }
 996                 if (i == timeout) {
 997                         dev_warn(dev->class_dev,
 998                                  "ni_pcidio: failed to load word into fpga %i\n",
 999                                  fpga_index);
1000                         return -EIO;
1001                 }
1002                 if (need_resched())
1003                         schedule();
1004         }
1005         writew(0x0, devpriv->mite->daq_io_addr + Firmware_Control_Register);
1006         return 0;
1007 }
1008
1009 static int pci_6534_reset_fpga(struct comedi_device *dev, int fpga_index)
1010 {
1011         return pci_6534_load_fpga(dev, NULL, 0, fpga_index);
1012 }
1013
1014 static int pci_6534_reset_fpgas(struct comedi_device *dev)
1015 {
1016         struct nidio96_private *devpriv = dev->private;
1017         int ret;
1018         int i;
1019
1020         writew(0x0, devpriv->mite->daq_io_addr + Firmware_Control_Register);
1021         for (i = 0; i < 3; ++i) {
1022                 ret = pci_6534_reset_fpga(dev, i);
1023                 if (ret < 0)
1024                         break;
1025         }
1026         writew(0x0, devpriv->mite->daq_io_addr + Firmware_Mask_Register);
1027         return ret;
1028 }
1029
1030 static void pci_6534_init_main_fpga(struct comedi_device *dev)
1031 {
1032         struct nidio96_private *devpriv = dev->private;
1033
1034         writel(0, devpriv->mite->daq_io_addr + FPGA_Control1_Register);
1035         writel(0, devpriv->mite->daq_io_addr + FPGA_Control2_Register);
1036         writel(0, devpriv->mite->daq_io_addr + FPGA_SCALS_Counter_Register);
1037         writel(0, devpriv->mite->daq_io_addr + FPGA_SCAMS_Counter_Register);
1038         writel(0, devpriv->mite->daq_io_addr + FPGA_SCBLS_Counter_Register);
1039         writel(0, devpriv->mite->daq_io_addr + FPGA_SCBMS_Counter_Register);
1040 }
1041
1042 static int pci_6534_upload_firmware(struct comedi_device *dev)
1043 {
1044         struct nidio96_private *devpriv = dev->private;
1045         static const char *const fw_file[3] = {
1046                 FW_PCI_6534_SCARAB_DI,  /* loaded into scarab A for DI */
1047                 FW_PCI_6534_SCARAB_DO,  /* loaded into scarab B for DO */
1048                 FW_PCI_6534_MAIN,       /* loaded into main FPGA */
1049         };
1050         int ret;
1051         int n;
1052
1053         ret = pci_6534_reset_fpgas(dev);
1054         if (ret < 0)
1055                 return ret;
1056         /* load main FPGA first, then the two scarabs */
1057         for (n = 2; n >= 0; n--) {
1058                 ret = comedi_load_firmware(dev, &devpriv->mite->pcidev->dev,
1059                                            fw_file[n],
1060                                            pci_6534_load_fpga, n);
1061                 if (ret == 0 && n == 2)
1062                         pci_6534_init_main_fpga(dev);
1063                 if (ret < 0)
1064                         break;
1065         }
1066         return ret;
1067 }
1068
1069 static int nidio_auto_attach(struct comedi_device *dev,
1070                              unsigned long context)
1071 {
1072         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1073         const struct nidio_board *board = NULL;
1074         struct nidio96_private *devpriv;
1075         struct comedi_subdevice *s;
1076         int ret;
1077         unsigned int irq;
1078
1079         if (context < ARRAY_SIZE(nidio_boards))
1080                 board = &nidio_boards[context];
1081         if (!board)
1082                 return -ENODEV;
1083         dev->board_ptr = board;
1084         dev->board_name = board->name;
1085
1086         ret = comedi_pci_enable(dev);
1087         if (ret)
1088                 return ret;
1089
1090         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
1091         if (!devpriv)
1092                 return -ENOMEM;
1093
1094         spin_lock_init(&devpriv->mite_channel_lock);
1095
1096         devpriv->mite = mite_alloc(pcidev);
1097         if (!devpriv->mite)
1098                 return -ENOMEM;
1099
1100         ret = mite_setup(devpriv->mite);
1101         if (ret < 0) {
1102                 dev_warn(dev->class_dev, "error setting up mite\n");
1103                 return ret;
1104         }
1105
1106         devpriv->di_mite_ring = mite_alloc_ring(devpriv->mite);
1107         if (devpriv->di_mite_ring == NULL)
1108                 return -ENOMEM;
1109
1110         irq = mite_irq(devpriv->mite);
1111         if (board->uses_firmware) {
1112                 ret = pci_6534_upload_firmware(dev);
1113                 if (ret < 0)
1114                         return ret;
1115         }
1116
1117         ret = comedi_alloc_subdevices(dev, 1);
1118         if (ret)
1119                 return ret;
1120
1121         dev_info(dev->class_dev, "%s rev=%d\n", dev->board_name,
1122                  readb(devpriv->mite->daq_io_addr + Chip_Version));
1123
1124         s = &dev->subdevices[0];
1125
1126         dev->read_subdev = s;
1127         s->type = COMEDI_SUBD_DIO;
1128         s->subdev_flags =
1129                 SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_PACKED |
1130                 SDF_CMD_READ;
1131         s->n_chan = 32;
1132         s->range_table = &range_digital;
1133         s->maxdata = 1;
1134         s->insn_config = &ni_pcidio_insn_config;
1135         s->insn_bits = &ni_pcidio_insn_bits;
1136         s->do_cmd = &ni_pcidio_cmd;
1137         s->do_cmdtest = &ni_pcidio_cmdtest;
1138         s->cancel = &ni_pcidio_cancel;
1139         s->len_chanlist = 32;   /* XXX */
1140         s->buf_change = &ni_pcidio_change;
1141         s->async_dma_dir = DMA_BIDIRECTIONAL;
1142         s->poll = &ni_pcidio_poll;
1143
1144         writel(0, devpriv->mite->daq_io_addr + Port_IO(0));
1145         writel(0, devpriv->mite->daq_io_addr + Port_Pin_Directions(0));
1146         writel(0, devpriv->mite->daq_io_addr + Port_Pin_Mask(0));
1147
1148         /* disable interrupts on board */
1149         writeb(0x00,
1150                 devpriv->mite->daq_io_addr +
1151                 Master_DMA_And_Interrupt_Control);
1152
1153         ret = request_irq(irq, nidio_interrupt, IRQF_SHARED,
1154                                 "ni_pcidio", dev);
1155         if (ret < 0)
1156                 dev_warn(dev->class_dev, "irq not available\n");
1157
1158         dev->irq = irq;
1159
1160         return 0;
1161 }
1162
1163 static void nidio_detach(struct comedi_device *dev)
1164 {
1165         struct nidio96_private *devpriv = dev->private;
1166
1167         if (dev->irq)
1168                 free_irq(dev->irq, dev);
1169         if (devpriv) {
1170                 if (devpriv->di_mite_ring) {
1171                         mite_free_ring(devpriv->di_mite_ring);
1172                         devpriv->di_mite_ring = NULL;
1173                 }
1174                 if (devpriv->mite) {
1175                         mite_unsetup(devpriv->mite);
1176                         mite_free(devpriv->mite);
1177                 }
1178         }
1179         comedi_pci_disable(dev);
1180 }
1181
1182 static struct comedi_driver ni_pcidio_driver = {
1183         .driver_name    = "ni_pcidio",
1184         .module         = THIS_MODULE,
1185         .auto_attach    = nidio_auto_attach,
1186         .detach         = nidio_detach,
1187 };
1188
1189 static int ni_pcidio_pci_probe(struct pci_dev *dev,
1190                                const struct pci_device_id *id)
1191 {
1192         return comedi_pci_auto_config(dev, &ni_pcidio_driver, id->driver_data);
1193 }
1194
1195 static DEFINE_PCI_DEVICE_TABLE(ni_pcidio_pci_table) = {
1196         { PCI_VDEVICE(NI, 0x1150), BOARD_PCIDIO_32HS },
1197         { PCI_VDEVICE(NI, 0x12b0), BOARD_PCI6534 },
1198         { PCI_VDEVICE(NI, 0x1320), BOARD_PXI6533 },
1199         { 0 }
1200 };
1201 MODULE_DEVICE_TABLE(pci, ni_pcidio_pci_table);
1202
1203 static struct pci_driver ni_pcidio_pci_driver = {
1204         .name           = "ni_pcidio",
1205         .id_table       = ni_pcidio_pci_table,
1206         .probe          = ni_pcidio_pci_probe,
1207         .remove         = comedi_pci_auto_unconfig,
1208 };
1209 module_comedi_pci_driver(ni_pcidio_driver, ni_pcidio_pci_driver);
1210
1211 MODULE_AUTHOR("Comedi http://www.comedi.org");
1212 MODULE_DESCRIPTION("Comedi low-level driver");
1213 MODULE_LICENSE("GPL");