drivers/staging/comedi/drivers/ni_pcimio.c

   1 /*
   2     comedi/drivers/ni_pcimio.c
   3     Hardware driver for NI PCI-MIO E series cards
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
   7
   8     This program is free software; you can redistribute it and/or modify
   9     it under the terms of the GNU General Public License as published by
  10     the Free Software Foundation; either version 2 of the License, or
  11     (at your option) any later version.
  12
  13     This program is distributed in the hope that it will be useful,
  14     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16     GNU General Public License for more details.
  17
  18     You should have received a copy of the GNU General Public License
  19     along with this program; if not, write to the Free Software
  20     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21 */
  22 /*
  23 Driver: ni_pcimio
  24 Description: National Instruments PCI-MIO-E series and M series (all boards)
  25 Author: ds, John Hallen, Frank Mori Hess, Rolf Mueller, Herbert Peremans,
  26   Herman Bruyninckx, Terry Barnaby
  27 Status: works
  28 Devices: [National Instruments] PCI-MIO-16XE-50 (ni_pcimio),
  29   PCI-MIO-16XE-10, PXI-6030E, PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-6014, PCI-6040E,
  30   PXI-6040E, PCI-6030E, PCI-6031E, PCI-6032E, PCI-6033E, PCI-6071E, PCI-6023E,
  31   PCI-6024E, PCI-6025E, PXI-6025E, PCI-6034E, PCI-6035E, PCI-6052E,
  32   PCI-6110, PCI-6111, PCI-6220, PCI-6221, PCI-6224, PXI-6224,
  33   PCI-6225, PXI-6225, PCI-6229, PCI-6250, PCI-6251, PCIe-6251, PXIe-6251,
  34   PCI-6254, PCI-6259, PCIe-6259,
  35   PCI-6280, PCI-6281, PXI-6281, PCI-6284, PCI-6289,
  36   PCI-6711, PXI-6711, PCI-6713, PXI-6713,
  37   PXI-6071E, PCI-6070E, PXI-6070E,
  38   PXI-6052E, PCI-6036E, PCI-6731, PCI-6733, PXI-6733,
  39   PCI-6143, PXI-6143
  40 Updated: Mon, 09 Jan 2012 14:52:48 +0000
  41
  42 These boards are almost identical to the AT-MIO E series, except that
  43 they use the PCI bus instead of ISA (i.e., AT).  See the notes for
  44 the ni_atmio.o driver for additional information about these boards.
  45
  46 Autocalibration is supported on many of the devices, using the
  47 comedi_calibrate (or comedi_soft_calibrate for m-series) utility.
  48 M-Series boards do analog input and analog output calibration entirely
  49 in software. The software calibration corrects
  50 the analog input for offset, gain and
  51 nonlinearity.  The analog outputs are corrected for offset and gain.
  52 See the comedilib documentation on comedi_get_softcal_converter() for
  53 more information.
  54
  55 By default, the driver uses DMA to transfer analog input data to
  56 memory.  When DMA is enabled, not all triggering features are
  57 supported.
  58
  59 Digital I/O may not work on 673x.
  60
  61 Note that the PCI-6143 is a simultaineous sampling device with 8 convertors.
  62 With this board all of the convertors perform one simultaineous sample during
  63 a scan interval. The period for a scan is used for the convert time in a
  64 Comedi cmd. The convert trigger source is normally set to TRIG_NOW by default.
  65
  66 The RTSI trigger bus is supported on these cards on
  67 subdevice 10. See the comedilib documentation for details.
  68
  69 Information (number of channels, bits, etc.) for some devices may be
  70 incorrect.  Please check this and submit a bug if there are problems
  71 for your device.
  72
  73 SCXI is probably broken for m-series boards.
  74
  75 Bugs:
  76  - When DMA is enabled, COMEDI_EV_CONVERT does
  77    not work correctly.
  78
  79 */
  80 /*
  81         The PCI-MIO E series driver was originally written by
  82         Tomasz Motylewski <...>, and ported to comedi by ds.
  83
  84         References:
  85
  86            341079b.pdf  PCI E Series Register-Level Programmer Manual
  87            340934b.pdf  DAQ-STC reference manual
  88
  89            322080b.pdf  6711/6713/6715 User Manual
  90
  91            320945c.pdf  PCI E Series User Manual
  92            322138a.pdf  PCI-6052E and DAQPad-6052E User Manual
  93
  94         ISSUES:
  95
  96         need to deal with external reference for DAC, and other DAC
  97         properties in board properties
  98
  99         deal with at-mio-16de-10 revision D to N changes, etc.
 100
 101         need to add other CALDAC type
 102
 103         need to slow down DAC loading.  I don't trust NI's claim that
 104         two writes to the PCI bus slows IO enough.  I would prefer to
 105         use udelay().  Timing specs: (clock)
 106                 AD8522          30ns
 107                 DAC8043         120ns
 108                 DAC8800         60ns
 109                 MB88341         ?
 110
 111 */
 112
 113 #include <linux/delay.h>
 114
 115 #include "../comedidev.h"
 116
 117 #include <asm/byteorder.h>
 118
 119 #include "ni_stc.h"
 120 #include "mite.h"
 121
 122 /* #define PCI_DEBUG */
 123
 124 #define PCIDMA
 125
 126 #define PCIMIO 1
 127 #undef ATMIO
 128
 129 #define MAX_N_CALDACS (16+16+2)
 130
 131 #define DRV_NAME "ni_pcimio"
 132
 133 /* These are not all the possible ao ranges for 628x boards.
 134  They can do OFFSET +- REFERENCE where OFFSET can be
 135  0V, 5V, APFI<0,1>, or AO<0...3> and RANGE can
 136  be 10V, 5V, 2V, 1V, APFI<0,1>, AO<0...3>.  That's
 137  63 different possibilities.  An AO channel
 138  can not act as it's own OFFSET or REFERENCE.
 139 */
 140 static const struct comedi_lrange range_ni_M_628x_ao = { 8, {
 141                                                              RANGE(-10, 10),
 142                                                              RANGE(-5, 5),
 143                                                              RANGE(-2, 2),
 144                                                              RANGE(-1, 1),
 145                                                              RANGE(-5, 15),
 146                                                              RANGE(0, 10),
 147                                                              RANGE(3, 7),
 148                                                              RANGE(4, 6),
 149                                                              RANGE_ext(-1, 1)
 150                                                              }
 151 };
 152
 153 static const struct comedi_lrange range_ni_M_625x_ao = { 3, {
 154                                                              RANGE(-10, 10),
 155                                                              RANGE(-5, 5),
 156                                                              RANGE_ext(-1, 1)
 157                                                              }
 158 };
 159
 160 enum ni_pcimio_boardid {
 161         BOARD_PCIMIO_16XE_50,
 162         BOARD_PCIMIO_16XE_10,
 163         BOARD_PCI6014,
 164         BOARD_PXI6030E,
 165         BOARD_PCIMIO_16E_1,
 166         BOARD_PCIMIO_16E_4,
 167         BOARD_PXI6040E,
 168         BOARD_PCI6031E,
 169         BOARD_PCI6032E,
 170         BOARD_PCI6033E,
 171         BOARD_PCI6071E,
 172         BOARD_PCI6023E,
 173         BOARD_PCI6024E,
 174         BOARD_PCI6025E,
 175         BOARD_PXI6025E,
 176         BOARD_PCI6034E,
 177         BOARD_PCI6035E,
 178         BOARD_PCI6052E,
 179         BOARD_PCI6110,
 180         BOARD_PCI6111,
 181         /* BOARD_PCI6115, */
 182         /* BOARD_PXI6115, */
 183         BOARD_PCI6711,
 184         BOARD_PXI6711,
 185         BOARD_PCI6713,
 186         BOARD_PXI6713,
 187         BOARD_PCI6731,
 188         /* BOARD_PXI6731, */
 189         BOARD_PCI6733,
 190         BOARD_PXI6733,
 191         BOARD_PXI6071E,
 192         BOARD_PXI6070E,
 193         BOARD_PXI6052E,
 194         BOARD_PXI6031E,
 195         BOARD_PCI6036E,
 196         BOARD_PCI6220,
 197         BOARD_PCI6221,
 198         BOARD_PCI6221_37PIN,
 199         BOARD_PCI6224,
 200         BOARD_PXI6224,
 201         BOARD_PCI6225,
 202         BOARD_PXI6225,
 203         BOARD_PCI6229,
 204         BOARD_PCI6250,
 205         BOARD_PCI6251,
 206         BOARD_PCIE6251,
 207         BOARD_PXIE6251,
 208         BOARD_PCI6254,
 209         BOARD_PCI6259,
 210         BOARD_PCIE6259,
 211         BOARD_PCI6280,
 212         BOARD_PCI6281,
 213         BOARD_PXI6281,
 214         BOARD_PCI6284,
 215         BOARD_PCI6289,
 216         BOARD_PCI6143,
 217         BOARD_PXI6143,
 218 };
 219
 220 static const struct ni_board_struct ni_boards[] = {
 221         [BOARD_PCIMIO_16XE_50] = {
 222                 .name           = "pci-mio-16xe-50",
 223                 .n_adchan       = 16,
 224                 .adbits         = 16,
 225                 .ai_fifo_depth  = 2048,
 226                 .alwaysdither   = 1,
 227                 .gainlkup       = ai_gain_8,
 228                 .ai_speed       = 50000,
 229                 .n_aochan       = 2,
 230                 .aobits         = 12,
 231                 .ao_range_table = &range_bipolar10,
 232                 .ao_speed       = 50000,
 233                 .num_p0_dio_channels = 8,
 234                 .caldac         = { dac8800, dac8043 },
 235         },
 236         [BOARD_PCIMIO_16XE_10] = {
 237                 .name           = "pci-mio-16xe-10",    /*  aka pci-6030E */
 238                 .n_adchan       = 16,
 239                 .adbits         = 16,
 240                 .ai_fifo_depth  = 512,
 241                 .alwaysdither   = 1,
 242                 .gainlkup       = ai_gain_14,
 243                 .ai_speed       = 10000,
 244                 .n_aochan       = 2,
 245                 .aobits         = 16,
 246                 .ao_fifo_depth  = 2048,
 247                 .ao_range_table = &range_ni_E_ao_ext,
 248                 .ao_unipolar    = 1,
 249                 .ao_speed       = 10000,
 250                 .num_p0_dio_channels = 8,
 251                 .caldac         = { dac8800, dac8043, ad8522 },
 252         },
 253         [BOARD_PCI6014] = {
 254                 .name           = "pci-6014",
 255                 .n_adchan       = 16,
 256                 .adbits         = 16,
 257                 .ai_fifo_depth  = 512,
 258                 .alwaysdither   = 1,
 259                 .gainlkup       = ai_gain_4,
 260                 .ai_speed       = 5000,
 261                 .n_aochan       = 2,
 262                 .aobits         = 16,
 263                 .ao_range_table = &range_bipolar10,
 264                 .ao_speed       = 100000,
 265                 .num_p0_dio_channels = 8,
 266                 .caldac         = { ad8804_debug },
 267         },
 268         [BOARD_PXI6030E] = {
 269                 .name           = "pxi-6030e",
 270                 .n_adchan       = 16,
 271                 .adbits         = 16,
 272                 .ai_fifo_depth  = 512,
 273                 .alwaysdither   = 1,
 274                 .gainlkup       = ai_gain_14,
 275                 .ai_speed       = 10000,
 276                 .n_aochan       = 2,
 277                 .aobits         = 16,
 278                 .ao_fifo_depth  = 2048,
 279                 .ao_range_table = &range_ni_E_ao_ext,
 280                 .ao_unipolar    = 1,
 281                 .ao_speed       = 10000,
 282                 .num_p0_dio_channels = 8,
 283                 .caldac         = { dac8800, dac8043, ad8522 },
 284         },
 285         [BOARD_PCIMIO_16E_1] = {
 286                 .name           = "pci-mio-16e-1",      /* aka pci-6070e */
 287                 .n_adchan       = 16,
 288                 .adbits         = 12,
 289                 .ai_fifo_depth  = 512,
 290                 .gainlkup       = ai_gain_16,
 291                 .ai_speed       = 800,
 292                 .n_aochan       = 2,
 293                 .aobits         = 12,
 294                 .ao_fifo_depth  = 2048,
 295                 .ao_range_table = &range_ni_E_ao_ext,
 296                 .ao_unipolar    = 1,
 297                 .ao_speed       = 1000,
 298                 .num_p0_dio_channels = 8,
 299                 .caldac         = { mb88341 },
 300         },
 301         [BOARD_PCIMIO_16E_4] = {
 302                 .name           = "pci-mio-16e-4",      /* aka pci-6040e */
 303                 .n_adchan       = 16,
 304                 .adbits         = 12,
 305                 .ai_fifo_depth  = 512,
 306                 .gainlkup       = ai_gain_16,
 307                 /*
 308                  * there have been reported problems with
 309                  * full speed on this board
 310                  */
 311                 .ai_speed       = 2000,
 312                 .n_aochan       = 2,
 313                 .aobits         = 12,
 314                 .ao_fifo_depth  = 512,
 315                 .ao_range_table = &range_ni_E_ao_ext,
 316                 .ao_unipolar    = 1,
 317                 .ao_speed       = 1000,
 318                 .num_p0_dio_channels = 8,
 319                 .caldac         = { ad8804_debug },     /* doc says mb88341 */
 320         },
 321         [BOARD_PXI6040E] = {
 322                 .name           = "pxi-6040e",
 323                 .n_adchan       = 16,
 324                 .adbits         = 12,
 325                 .ai_fifo_depth  = 512,
 326                 .gainlkup       = ai_gain_16,
 327                 .ai_speed       = 2000,
 328                 .n_aochan       = 2,
 329                 .aobits         = 12,
 330                 .ao_fifo_depth  = 512,
 331                 .ao_range_table = &range_ni_E_ao_ext,
 332                 .ao_unipolar    = 1,
 333                 .ao_speed       = 1000,
 334                 .num_p0_dio_channels = 8,
 335                 .caldac         = { mb88341 },
 336         },
 337         [BOARD_PCI6031E] = {
 338                 .name           = "pci-6031e",
 339                 .n_adchan       = 64,
 340                 .adbits         = 16,
 341                 .ai_fifo_depth  = 512,
 342                 .alwaysdither   = 1,
 343                 .gainlkup       = ai_gain_14,
 344                 .ai_speed       = 10000,
 345                 .n_aochan       = 2,
 346                 .aobits         = 16,
 347                 .ao_fifo_depth  = 2048,
 348                 .ao_range_table = &range_ni_E_ao_ext,
 349                 .ao_unipolar    = 1,
 350                 .ao_speed       = 10000,
 351                 .num_p0_dio_channels = 8,
 352                 .caldac         = { dac8800, dac8043, ad8522 },
 353         },
 354         [BOARD_PCI6032E] = {
 355                 .name           = "pci-6032e",
 356                 .n_adchan       = 16,
 357                 .adbits         = 16,
 358                 .ai_fifo_depth  = 512,
 359                 .alwaysdither   = 1,
 360                 .gainlkup       = ai_gain_14,
 361                 .ai_speed       = 10000,
 362                 .num_p0_dio_channels = 8,
 363                 .caldac         = { dac8800, dac8043, ad8522 },
 364         },
 365         [BOARD_PCI6033E] = {
 366                 .name           = "pci-6033e",
 367                 .n_adchan       = 64,
 368                 .adbits         = 16,
 369                 .ai_fifo_depth  = 512,
 370                 .alwaysdither   = 1,
 371                 .gainlkup       = ai_gain_14,
 372                 .ai_speed       = 10000,
 373                 .num_p0_dio_channels = 8,
 374                 .caldac         = { dac8800, dac8043, ad8522 },
 375         },
 376         [BOARD_PCI6071E] = {
 377                 .name           = "pci-6071e",
 378                 .n_adchan       = 64,
 379                 .adbits         = 12,
 380                 .ai_fifo_depth  = 512,
 381                 .alwaysdither   = 1,
 382                 .gainlkup       = ai_gain_16,
 383                 .ai_speed       = 800,
 384                 .n_aochan       = 2,
 385                 .aobits         = 12,
 386                 .ao_fifo_depth  = 2048,
 387                 .ao_range_table = &range_ni_E_ao_ext,
 388                 .ao_unipolar    = 1,
 389                 .ao_speed       = 1000,
 390                 .num_p0_dio_channels = 8,
 391                 .caldac         = { ad8804_debug },
 392         },
 393         [BOARD_PCI6023E] = {
 394                 .name           = "pci-6023e",
 395                 .n_adchan       = 16,
 396                 .adbits         = 12,
 397                 .ai_fifo_depth  = 512,
 398                 .gainlkup       = ai_gain_4,
 399                 .ai_speed       = 5000,
 400                 .num_p0_dio_channels = 8,
 401                 .caldac         = { ad8804_debug },     /* manual is wrong */
 402         },
 403         [BOARD_PCI6024E] = {
 404                 .name           = "pci-6024e",
 405                 .n_adchan       = 16,
 406                 .adbits         = 12,
 407                 .ai_fifo_depth  = 512,
 408                 .gainlkup       = ai_gain_4,
 409                 .ai_speed       = 5000,
 410                 .n_aochan       = 2,
 411                 .aobits         = 12,
 412                 .ao_range_table = &range_bipolar10,
 413                 .ao_speed       = 100000,
 414                 .num_p0_dio_channels = 8,
 415                 .caldac         = { ad8804_debug },     /* manual is wrong */
 416         },
 417         [BOARD_PCI6025E] = {
 418                 .name           = "pci-6025e",
 419                 .n_adchan       = 16,
 420                 .adbits         = 12,
 421                 .ai_fifo_depth  = 512,
 422                 .gainlkup       = ai_gain_4,
 423                 .ai_speed       = 5000,
 424                 .n_aochan       = 2,
 425                 .aobits         = 12,
 426                 .ao_range_table = &range_bipolar10,
 427                 .ao_speed       = 100000,
 428                 .num_p0_dio_channels = 8,
 429                 .caldac         = { ad8804_debug },     /* manual is wrong */
 430                 .has_8255       = 1,
 431         },
 432         [BOARD_PXI6025E] = {
 433                 .name           = "pxi-6025e",
 434                 .n_adchan       = 16,
 435                 .adbits         = 12,
 436                 .ai_fifo_depth  = 512,
 437                 .gainlkup       = ai_gain_4,
 438                 .ai_speed       = 5000,
 439                 .n_aochan       = 2,
 440                 .aobits         = 12,
 441                 .ao_range_table = &range_ni_E_ao_ext,
 442                 .ao_unipolar    = 1,
 443                 .ao_speed       = 100000,
 444                 .num_p0_dio_channels = 8,
 445                 .caldac         = { ad8804_debug },     /* manual is wrong */
 446                 .has_8255       = 1,
 447         },
 448         [BOARD_PCI6034E] = {
 449                 .name           = "pci-6034e",
 450                 .n_adchan       = 16,
 451                 .adbits         = 16,
 452                 .ai_fifo_depth  = 512,
 453                 .alwaysdither   = 1,
 454                 .gainlkup       = ai_gain_4,
 455                 .ai_speed       = 5000,
 456                 .num_p0_dio_channels = 8,
 457                 .caldac         = { ad8804_debug },
 458         },
 459         [BOARD_PCI6035E] = {
 460                 .name           = "pci-6035e",
 461                 .n_adchan       = 16,
 462                 .adbits         = 16,
 463                 .ai_fifo_depth  = 512,
 464                 .alwaysdither   = 1,
 465                 .gainlkup       = ai_gain_4,
 466                 .ai_speed       = 5000,
 467                 .n_aochan       = 2,
 468                 .aobits         = 12,
 469                 .ao_range_table = &range_bipolar10,
 470                 .ao_speed       = 100000,
 471                 .num_p0_dio_channels = 8,
 472                 .caldac         = { ad8804_debug },
 473         },
 474         [BOARD_PCI6052E] = {
 475                 .name           = "pci-6052e",
 476                 .n_adchan       = 16,
 477                 .adbits         = 16,
 478                 .ai_fifo_depth  = 512,
 479                 .alwaysdither   = 1,
 480                 .gainlkup       = ai_gain_16,
 481                 .ai_speed       = 3000,
 482                 .n_aochan       = 2,
 483                 .aobits         = 16,
 484                 .ao_unipolar    = 1,
 485                 .ao_fifo_depth  = 2048,
 486                 .ao_range_table = &range_ni_E_ao_ext,
 487                 .ao_speed       = 3000,
 488                 .num_p0_dio_channels = 8,
 489                 /* manual is wrong */
 490                 .caldac         = { ad8804_debug, ad8804_debug, ad8522 },
 491         },
 492         [BOARD_PCI6110] = {
 493                 .name           = "pci-6110",
 494                 .n_adchan       = 4,
 495                 .adbits         = 12,
 496                 .ai_fifo_depth  = 8192,
 497                 .alwaysdither   = 0,
 498                 .gainlkup       = ai_gain_611x,
 499                 .ai_speed       = 200,
 500                 .n_aochan       = 2,
 501                 .aobits         = 16,
 502                 .reg_type       = ni_reg_611x,
 503                 .ao_range_table = &range_bipolar10,
 504                 .ao_fifo_depth  = 2048,
 505                 .ao_speed       = 250,
 506                 .num_p0_dio_channels = 8,
 507                 .caldac         = { ad8804, ad8804 },
 508         },
 509         [BOARD_PCI6111] = {
 510                 .name           = "pci-6111",
 511                 .n_adchan       = 2,
 512                 .adbits         = 12,
 513                 .ai_fifo_depth  = 8192,
 514                 .gainlkup       = ai_gain_611x,
 515                 .ai_speed       = 200,
 516                 .n_aochan       = 2,
 517                 .aobits         = 16,
 518                 .reg_type       = ni_reg_611x,
 519                 .ao_range_table = &range_bipolar10,
 520                 .ao_fifo_depth  = 2048,
 521                 .ao_speed       = 250,
 522                 .num_p0_dio_channels = 8,
 523                 .caldac         = { ad8804, ad8804 },
 524         },
 525 #if 0
 526         /* The 6115 boards probably need their own driver */
 527         [BOARD_PCI6115] = {     /* .device_id = 0x2ed0, */
 528                 .name           = "pci-6115",
 529                 .n_adchan       = 4,
 530                 .adbits         = 12,
 531                 .ai_fifo_depth  = 8192,
 532                 .gainlkup       = ai_gain_611x,
 533                 .ai_speed       = 100,
 534                 .n_aochan       = 2,
 535                 .aobits         = 16,
 536                 .ao_671x        = 1,
 537                 .ao_fifo_depth  = 2048,
 538                 .ao_speed       = 250,
 539                 .num_p0_dio_channels = 8,
 540                 .reg_611x       = 1,
 541                 /* XXX */
 542                 .caldac         = { ad8804_debug, ad8804_debug, ad8804_debug },
 543         },
 544 #endif
 545 #if 0
 546         [BOARD_PXI6115] = {     /* .device_id = ????, */
 547                 .name           = "pxi-6115",
 548                 .n_adchan       = 4,
 549                 .adbits         = 12,
 550                 .ai_fifo_depth  = 8192,
 551                 .gainlkup       = ai_gain_611x,
 552                 .ai_speed       = 100,
 553                 .n_aochan       = 2,
 554                 .aobits         = 16,
 555                 .ao_671x        = 1,
 556                 .ao_fifo_depth  = 2048,
 557                 .ao_speed       = 250,
 558                 .reg_611x       = 1,
 559                 .num_p0_dio_channels = 8,
 560                 /* XXX */
 561                 .caldac         = { ad8804_debug, ad8804_debug, ad8804_debug },
 562         },
 563 #endif
 564         [BOARD_PCI6711] = {
 565                 .name = "pci-6711",
 566                 .n_aochan       = 4,
 567                 .aobits         = 12,
 568                 /* data sheet says 8192, but fifo really holds 16384 samples */
 569                 .ao_fifo_depth  = 16384,
 570                 .ao_range_table = &range_bipolar10,
 571                 .ao_speed       = 1000,
 572                 .num_p0_dio_channels = 8,
 573                 .reg_type       = ni_reg_6711,
 574                 .caldac         = { ad8804_debug },
 575         },
 576         [BOARD_PXI6711] = {
 577                 .name           = "pxi-6711",
 578                 .n_aochan       = 4,
 579                 .aobits         = 12,
 580                 .ao_fifo_depth  = 16384,
 581                 .ao_range_table = &range_bipolar10,
 582                 .ao_speed       = 1000,
 583                 .num_p0_dio_channels = 8,
 584                 .reg_type       = ni_reg_6711,
 585                 .caldac         = { ad8804_debug },
 586         },
 587         [BOARD_PCI6713] = {
 588                 .name           = "pci-6713",
 589                 .n_aochan       = 8,
 590                 .aobits         = 12,
 591                 .ao_fifo_depth  = 16384,
 592                 .ao_range_table = &range_bipolar10,
 593                 .ao_speed       = 1000,
 594                 .num_p0_dio_channels = 8,
 595                 .reg_type       = ni_reg_6713,
 596                 .caldac         = { ad8804_debug, ad8804_debug },
 597         },
 598         [BOARD_PXI6713] = {
 599                 .name           = "pxi-6713",
 600                 .n_aochan       = 8,
 601                 .aobits         = 12,
 602                 .ao_fifo_depth  = 16384,
 603                 .ao_range_table = &range_bipolar10,
 604                 .ao_speed       = 1000,
 605                 .num_p0_dio_channels = 8,
 606                 .reg_type       = ni_reg_6713,
 607                 .caldac         = { ad8804_debug, ad8804_debug },
 608         },
 609         [BOARD_PCI6731] = {
 610                 .name           = "pci-6731",
 611                 .n_aochan       = 4,
 612                 .aobits         = 16,
 613                 .ao_fifo_depth  = 8192,
 614                 .ao_range_table = &range_bipolar10,
 615                 .ao_speed       = 1000,
 616                 .num_p0_dio_channels = 8,
 617                 .reg_type       = ni_reg_6711,
 618                 .caldac         = { ad8804_debug },
 619         },
 620 #if 0
 621         [BOARD_PXI6731] = {     /* .device_id = ????, */
 622                 .name           = "pxi-6731",
 623                 .n_aochan       = 4,
 624                 .aobits         = 16,
 625                 .ao_fifo_depth  = 8192,
 626                 .ao_range_table = &range_bipolar10,
 627                 .num_p0_dio_channels = 8,
 628                 .reg_type       = ni_reg_6711,
 629                 .caldac         = { ad8804_debug },
 630         },
 631 #endif
 632         [BOARD_PCI6733] = {
 633                 .name           = "pci-6733",
 634                 .n_aochan       = 8,
 635                 .aobits         = 16,
 636                 .ao_fifo_depth  = 16384,
 637                 .ao_range_table = &range_bipolar10,
 638                 .ao_speed       = 1000,
 639                 .num_p0_dio_channels = 8,
 640                 .reg_type       = ni_reg_6713,
 641                 .caldac         = { ad8804_debug, ad8804_debug },
 642         },
 643         [BOARD_PXI6733] = {
 644                 .name           = "pxi-6733",
 645                 .n_aochan       = 8,
 646                 .aobits         = 16,
 647                 .ao_fifo_depth  = 16384,
 648                 .ao_range_table = &range_bipolar10,
 649                 .ao_speed       = 1000,
 650                 .num_p0_dio_channels = 8,
 651                 .reg_type       = ni_reg_6713,
 652                 .caldac         = { ad8804_debug, ad8804_debug },
 653         },
 654         [BOARD_PXI6071E] = {
 655                 .name           = "pxi-6071e",
 656                 .n_adchan       = 64,
 657                 .adbits         = 12,
 658                 .ai_fifo_depth  = 512,
 659                 .alwaysdither   = 1,
 660                 .gainlkup       = ai_gain_16,
 661                 .ai_speed       = 800,
 662                 .n_aochan       = 2,
 663                 .aobits         = 12,
 664                 .ao_fifo_depth  = 2048,
 665                 .ao_range_table = &range_ni_E_ao_ext,
 666                 .ao_unipolar    = 1,
 667                 .ao_speed       = 1000,
 668                 .num_p0_dio_channels = 8,
 669                 .caldac         = { ad8804_debug },
 670         },
 671         [BOARD_PXI6070E] = {
 672                 .name           = "pxi-6070e",
 673                 .n_adchan       = 16,
 674                 .adbits         = 12,
 675                 .ai_fifo_depth  = 512,
 676                 .alwaysdither   = 1,
 677                 .gainlkup       = ai_gain_16,
 678                 .ai_speed       = 800,
 679                 .n_aochan       = 2,
 680                 .aobits         = 12,
 681                 .ao_fifo_depth  = 2048,
 682                 .ao_range_table = &range_ni_E_ao_ext,
 683                 .ao_unipolar    = 1,
 684                 .ao_speed       = 1000,
 685                 .num_p0_dio_channels = 8,
 686                 .caldac         = { ad8804_debug },
 687         },
 688         [BOARD_PXI6052E] = {
 689                 .name           = "pxi-6052e",
 690                 .n_adchan       = 16,
 691                 .adbits         = 16,
 692                 .ai_fifo_depth  = 512,
 693                 .alwaysdither   = 1,
 694                 .gainlkup       = ai_gain_16,
 695                 .ai_speed       = 3000,
 696                 .n_aochan       = 2,
 697                 .aobits         = 16,
 698                 .ao_unipolar    = 1,
 699                 .ao_fifo_depth  = 2048,
 700                 .ao_range_table = &range_ni_E_ao_ext,
 701                 .ao_speed       = 3000,
 702                 .num_p0_dio_channels = 8,
 703                 .caldac         = { mb88341, mb88341, ad8522 },
 704         },
 705         [BOARD_PXI6031E] = {
 706                 .name           = "pxi-6031e",
 707                 .n_adchan       = 64,
 708                 .adbits         = 16,
 709                 .ai_fifo_depth  = 512,
 710                 .alwaysdither   = 1,
 711                 .gainlkup       = ai_gain_14,
 712                 .ai_speed       = 10000,
 713                 .n_aochan       = 2,
 714                 .aobits         = 16,
 715                 .ao_fifo_depth  = 2048,
 716                 .ao_range_table = &range_ni_E_ao_ext,
 717                 .ao_unipolar    = 1,
 718                 .ao_speed       = 10000,
 719                 .num_p0_dio_channels = 8,
 720                 .caldac         = { dac8800, dac8043, ad8522 },
 721         },
 722         [BOARD_PCI6036E] = {
 723                 .name = "pci-6036e",
 724                 .n_adchan       = 16,
 725                 .adbits         = 16,
 726                 .ai_fifo_depth  = 512,
 727                 .alwaysdither   = 1,
 728                 .gainlkup       = ai_gain_4,
 729                 .ai_speed       = 5000,
 730                 .n_aochan       = 2,
 731                 .aobits         = 16,
 732                 .ao_range_table = &range_bipolar10,
 733                 .ao_speed       = 100000,
 734                 .num_p0_dio_channels = 8,
 735                 .caldac         = { ad8804_debug },
 736         },
 737         [BOARD_PCI6220] = {
 738                 .name           = "pci-6220",
 739                 .n_adchan       = 16,
 740                 .adbits         = 16,
 741                 .ai_fifo_depth  = 512,          /* FIXME: guess */
 742                 .gainlkup       = ai_gain_622x,
 743                 .ai_speed       = 4000,
 744                 .num_p0_dio_channels = 8,
 745                 .reg_type       = ni_reg_622x,
 746                 .caldac         = { caldac_none },
 747         },
 748         [BOARD_PCI6221] = {
 749                 .name           = "pci-6221",
 750                 .n_adchan       = 16,
 751                 .adbits         = 16,
 752                 .ai_fifo_depth  = 4095,
 753                 .gainlkup       = ai_gain_622x,
 754                 .ai_speed       = 4000,
 755                 .n_aochan       = 2,
 756                 .aobits         = 16,
 757                 .ao_fifo_depth  = 8191,
 758                 .ao_range_table = &range_bipolar10,
 759                 .reg_type       = ni_reg_622x,
 760                 .ao_speed       = 1200,
 761                 .num_p0_dio_channels = 8,
 762                 .caldac         = { caldac_none },
 763         },
 764         [BOARD_PCI6221_37PIN] = {
 765                 .name           = "pci-6221_37pin",
 766                 .n_adchan       = 16,
 767                 .adbits         = 16,
 768                 .ai_fifo_depth  = 4095,
 769                 .gainlkup       = ai_gain_622x,
 770                 .ai_speed       = 4000,
 771                 .n_aochan       = 2,
 772                 .aobits         = 16,
 773                 .ao_fifo_depth  = 8191,
 774                 .ao_range_table = &range_bipolar10,
 775                 .reg_type       = ni_reg_622x,
 776                 .ao_speed       = 1200,
 777                 .num_p0_dio_channels = 8,
 778                 .caldac         = { caldac_none },
 779         },
 780         [BOARD_PCI6224] = {
 781                 .name           = "pci-6224",
 782                 .n_adchan       = 32,
 783                 .adbits         = 16,
 784                 .ai_fifo_depth  = 4095,
 785                 .gainlkup       = ai_gain_622x,
 786                 .ai_speed       = 4000,
 787                 .reg_type       = ni_reg_622x,
 788                 .num_p0_dio_channels = 32,
 789                 .caldac         = { caldac_none },
 790         },
 791         [BOARD_PXI6224] = {
 792                 .name           = "pxi-6224",
 793                 .n_adchan       = 32,
 794                 .adbits         = 16,
 795                 .ai_fifo_depth  = 4095,
 796                 .gainlkup       = ai_gain_622x,
 797                 .ai_speed       = 4000,
 798                 .reg_type       = ni_reg_622x,
 799                 .num_p0_dio_channels = 32,
 800                 .caldac         = { caldac_none },
 801         },
 802         [BOARD_PCI6225] = {
 803                 .name           = "pci-6225",
 804                 .n_adchan       = 80,
 805                 .adbits         = 16,
 806                 .ai_fifo_depth  = 4095,
 807                 .gainlkup       = ai_gain_622x,
 808                 .ai_speed       = 4000,
 809                 .n_aochan       = 2,
 810                 .aobits         = 16,
 811                 .ao_fifo_depth  = 8191,
 812                 .ao_range_table = &range_bipolar10,
 813                 .reg_type       = ni_reg_622x,
 814                 .ao_speed       = 1200,
 815                 .num_p0_dio_channels = 32,
 816                 .caldac         = { caldac_none },
 817         },
 818         [BOARD_PXI6225] = {
 819                 .name           = "pxi-6225",
 820                 .n_adchan       = 80,
 821                 .adbits         = 16,
 822                 .ai_fifo_depth  = 4095,
 823                 .gainlkup       = ai_gain_622x,
 824                 .ai_speed       = 4000,
 825                 .n_aochan       = 2,
 826                 .aobits         = 16,
 827                 .ao_fifo_depth  = 8191,
 828                 .ao_range_table = &range_bipolar10,
 829                 .reg_type       = ni_reg_622x,
 830                 .ao_speed       = 1200,
 831                 .num_p0_dio_channels = 32,
 832                 .caldac         = { caldac_none },
 833         },
 834         [BOARD_PCI6229] = {
 835                 .name           = "pci-6229",
 836                 .n_adchan       = 32,
 837                 .adbits         = 16,
 838                 .ai_fifo_depth  = 4095,
 839                 .gainlkup       = ai_gain_622x,
 840                 .ai_speed       = 4000,
 841                 .n_aochan       = 4,
 842                 .aobits         = 16,
 843                 .ao_fifo_depth  = 8191,
 844                 .ao_range_table = &range_bipolar10,
 845                 .reg_type       = ni_reg_622x,
 846                 .ao_speed       = 1200,
 847                 .num_p0_dio_channels = 32,
 848                 .caldac         = { caldac_none },
 849         },
 850         [BOARD_PCI6250] = {
 851                 .name           = "pci-6250",
 852                 .n_adchan       = 16,
 853                 .adbits         = 16,
 854                 .ai_fifo_depth  = 4095,
 855                 .gainlkup       = ai_gain_628x,
 856                 .ai_speed       = 800,
 857                 .reg_type       = ni_reg_625x,
 858                 .num_p0_dio_channels = 8,
 859                 .caldac         = { caldac_none },
 860         },
 861         [BOARD_PCI6251] = {
 862                 .name           = "pci-6251",
 863                 .n_adchan       = 16,
 864                 .adbits         = 16,
 865                 .ai_fifo_depth  = 4095,
 866                 .gainlkup       = ai_gain_628x,
 867                 .ai_speed       = 800,
 868                 .n_aochan       = 2,
 869                 .aobits         = 16,
 870                 .ao_fifo_depth  = 8191,
 871                 .ao_range_table = &range_ni_M_625x_ao,
 872                 .reg_type       = ni_reg_625x,
 873                 .ao_speed       = 350,
 874                 .num_p0_dio_channels = 8,
 875                 .caldac         = { caldac_none },
 876         },
 877         [BOARD_PCIE6251] = {
 878                 .name           = "pcie-6251",
 879                 .n_adchan       = 16,
 880                 .adbits         = 16,
 881                 .ai_fifo_depth  = 4095,
 882                 .gainlkup       = ai_gain_628x,
 883                 .ai_speed       = 800,
 884                 .n_aochan       = 2,
 885                 .aobits         = 16,
 886                 .ao_fifo_depth  = 8191,
 887                 .ao_range_table = &range_ni_M_625x_ao,
 888                 .reg_type       = ni_reg_625x,
 889                 .ao_speed       = 350,
 890                 .num_p0_dio_channels = 8,
 891                 .caldac         = { caldac_none },
 892         },
 893         [BOARD_PXIE6251] = {
 894                 .name           = "pxie-6251",
 895                 .n_adchan       = 16,
 896                 .adbits         = 16,
 897                 .ai_fifo_depth  = 4095,
 898                 .gainlkup       = ai_gain_628x,
 899                 .ai_speed       = 800,
 900                 .n_aochan       = 2,
 901                 .aobits         = 16,
 902                 .ao_fifo_depth  = 8191,
 903                 .ao_range_table = &range_ni_M_625x_ao,
 904                 .reg_type       = ni_reg_625x,
 905                 .ao_speed       = 350,
 906                 .num_p0_dio_channels = 8,
 907                 .caldac         = { caldac_none },
 908         },
 909         [BOARD_PCI6254] = {
 910                 .name           = "pci-6254",
 911                 .n_adchan       = 32,
 912                 .adbits         = 16,
 913                 .ai_fifo_depth  = 4095,
 914                 .gainlkup       = ai_gain_628x,
 915                 .ai_speed       = 800,
 916                 .reg_type       = ni_reg_625x,
 917                 .num_p0_dio_channels = 32,
 918                 .caldac         = { caldac_none },
 919         },
 920         [BOARD_PCI6259] = {
 921                 .name           = "pci-6259",
 922                 .n_adchan       = 32,
 923                 .adbits         = 16,
 924                 .ai_fifo_depth  = 4095,
 925                 .gainlkup       = ai_gain_628x,
 926                 .ai_speed       = 800,
 927                 .n_aochan       = 4,
 928                 .aobits         = 16,
 929                 .ao_fifo_depth  = 8191,
 930                 .ao_range_table = &range_ni_M_625x_ao,
 931                 .reg_type       = ni_reg_625x,
 932                 .ao_speed       = 350,
 933                 .num_p0_dio_channels = 32,
 934                 .caldac         = { caldac_none },
 935         },
 936         [BOARD_PCIE6259] = {
 937                 .name           = "pcie-6259",
 938                 .n_adchan       = 32,
 939                 .adbits         = 16,
 940                 .ai_fifo_depth  = 4095,
 941                 .gainlkup       = ai_gain_628x,
 942                 .ai_speed       = 800,
 943                 .n_aochan       = 4,
 944                 .aobits         = 16,
 945                 .ao_fifo_depth  = 8191,
 946                 .ao_range_table = &range_ni_M_625x_ao,
 947                 .reg_type       = ni_reg_625x,
 948                 .ao_speed       = 350,
 949                 .num_p0_dio_channels = 32,
 950                 .caldac         = { caldac_none },
 951         },
 952         [BOARD_PCI6280] = {
 953                 .name           = "pci-6280",
 954                 .n_adchan       = 16,
 955                 .adbits         = 18,
 956                 .ai_fifo_depth  = 2047,
 957                 .gainlkup       = ai_gain_628x,
 958                 .ai_speed       = 1600,
 959                 .ao_fifo_depth  = 8191,
 960                 .reg_type       = ni_reg_628x,
 961                 .num_p0_dio_channels = 8,
 962                 .caldac         = { caldac_none },
 963         },
 964         [BOARD_PCI6281] = {
 965                 .name           = "pci-6281",
 966                 .n_adchan       = 16,
 967                 .adbits         = 18,
 968                 .ai_fifo_depth  = 2047,
 969                 .gainlkup       = ai_gain_628x,
 970                 .ai_speed       = 1600,
 971                 .n_aochan       = 2,
 972                 .aobits         = 16,
 973                 .ao_fifo_depth  = 8191,
 974                 .ao_range_table = &range_ni_M_628x_ao,
 975                 .reg_type       = ni_reg_628x,
 976                 .ao_unipolar    = 1,
 977                 .ao_speed       = 350,
 978                 .num_p0_dio_channels = 8,
 979                 .caldac         = { caldac_none },
 980         },
 981         [BOARD_PXI6281] = {
 982                 .name           = "pxi-6281",
 983                 .n_adchan       = 16,
 984                 .adbits         = 18,
 985                 .ai_fifo_depth  = 2047,
 986                 .gainlkup       = ai_gain_628x,
 987                 .ai_speed       = 1600,
 988                 .n_aochan       = 2,
 989                 .aobits         = 16,
 990                 .ao_fifo_depth  = 8191,
 991                 .ao_range_table = &range_ni_M_628x_ao,
 992                 .reg_type       = ni_reg_628x,
 993                 .ao_unipolar    = 1,
 994                 .ao_speed       = 350,
 995                 .num_p0_dio_channels = 8,
 996                 .caldac         = { caldac_none },
 997         },
 998         [BOARD_PCI6284] = {
 999                 .name           = "pci-6284",
1000                 .n_adchan       = 32,
1001                 .adbits         = 18,
1002                 .ai_fifo_depth  = 2047,
1003                 .gainlkup       = ai_gain_628x,
1004                 .ai_speed       = 1600,
1005                 .reg_type       = ni_reg_628x,
1006                 .num_p0_dio_channels = 32,
1007                 .caldac         = { caldac_none },
1008         },
1009         [BOARD_PCI6289] = {
1010                 .name           = "pci-6289",
1011                 .n_adchan       = 32,
1012                 .adbits         = 18,
1013                 .ai_fifo_depth  = 2047,
1014                 .gainlkup       = ai_gain_628x,
1015                 .ai_speed       = 1600,
1016                 .n_aochan       = 4,
1017                 .aobits         = 16,
1018                 .ao_fifo_depth  = 8191,
1019                 .ao_range_table = &range_ni_M_628x_ao,
1020                 .reg_type       = ni_reg_628x,
1021                 .ao_unipolar    = 1,
1022                 .ao_speed       = 350,
1023                 .num_p0_dio_channels = 32,
1024                 .caldac         = { caldac_none },
1025         },
1026         [BOARD_PCI6143] = {
1027                 .name           = "pci-6143",
1028                 .n_adchan       = 8,
1029                 .adbits         = 16,
1030                 .ai_fifo_depth  = 1024,
1031                 .gainlkup       = ai_gain_6143,
1032                 .ai_speed       = 4000,
1033                 .reg_type       = ni_reg_6143,
1034                 .num_p0_dio_channels = 8,
1035                 .caldac         = { ad8804_debug, ad8804_debug },
1036         },
1037         [BOARD_PXI6143] = {
1038                 .name           = "pxi-6143",
1039                 .n_adchan       = 8,
1040                 .adbits         = 16,
1041                 .ai_fifo_depth  = 1024,
1042                 .gainlkup       = ai_gain_6143,
1043                 .ai_speed       = 4000,
1044                 .reg_type       = ni_reg_6143,
1045                 .num_p0_dio_channels = 8,
1046                 .caldac         = { ad8804_debug, ad8804_debug },
1047         },
1048 };
1049
1050 struct ni_private {
1051 NI_PRIVATE_COMMON};
1052
1053 /* How we access registers */
1054
1055 #define ni_writel(a, b) (writel((a), devpriv->mite->daq_io_addr + (b)))
1056 #define ni_readl(a)     (readl(devpriv->mite->daq_io_addr + (a)))
1057 #define ni_writew(a, b) (writew((a), devpriv->mite->daq_io_addr + (b)))
1058 #define ni_readw(a)     (readw(devpriv->mite->daq_io_addr + (a)))
1059 #define ni_writeb(a, b) (writeb((a), devpriv->mite->daq_io_addr + (b)))
1060 #define ni_readb(a)     (readb(devpriv->mite->daq_io_addr + (a)))
1061
1062 /* How we access STC registers */
1063
1064 /* We automatically take advantage of STC registers that can be
1065  * read/written directly in the I/O space of the board.  Most
1066  * PCIMIO devices map the low 8 STC registers to iobase+addr*2.
1067  * The 611x devices map the write registers to iobase+addr*2, and
1068  * the read registers to iobase+(addr-1)*2. */
1069 /* However, the 611x boards still aren't working, so I'm disabling
1070  * non-windowed STC access temporarily */
1071
1072 static void e_series_win_out(struct comedi_device *dev, uint16_t data, int reg)
1073 {
1074         struct ni_private *devpriv = dev->private;
1075         unsigned long flags;
1076
1077         spin_lock_irqsave(&devpriv->window_lock, flags);
1078         ni_writew(reg, Window_Address);
1079         ni_writew(data, Window_Data);
1080         spin_unlock_irqrestore(&devpriv->window_lock, flags);
1081 }
1082
1083 static uint16_t e_series_win_in(struct comedi_device *dev, int reg)
1084 {
1085         struct ni_private *devpriv = dev->private;
1086         unsigned long flags;
1087         uint16_t ret;
1088
1089         spin_lock_irqsave(&devpriv->window_lock, flags);
1090         ni_writew(reg, Window_Address);
1091         ret = ni_readw(Window_Data);
1092         spin_unlock_irqrestore(&devpriv->window_lock, flags);
1093
1094         return ret;
1095 }
1096
1097 static void m_series_stc_writew(struct comedi_device *dev, uint16_t data,
1098                                 int reg)
1099 {
1100         struct ni_private *devpriv = dev->private;
1101         unsigned offset;
1102
1103         switch (reg) {
1104         case ADC_FIFO_Clear:
1105                 offset = M_Offset_AI_FIFO_Clear;
1106                 break;
1107         case AI_Command_1_Register:
1108                 offset = M_Offset_AI_Command_1;
1109                 break;
1110         case AI_Command_2_Register:
1111                 offset = M_Offset_AI_Command_2;
1112                 break;
1113         case AI_Mode_1_Register:
1114                 offset = M_Offset_AI_Mode_1;
1115                 break;
1116         case AI_Mode_2_Register:
1117                 offset = M_Offset_AI_Mode_2;
1118                 break;
1119         case AI_Mode_3_Register:
1120                 offset = M_Offset_AI_Mode_3;
1121                 break;
1122         case AI_Output_Control_Register:
1123                 offset = M_Offset_AI_Output_Control;
1124                 break;
1125         case AI_Personal_Register:
1126                 offset = M_Offset_AI_Personal;
1127                 break;
1128         case AI_SI2_Load_A_Register:
1129                 /*  this is actually a 32 bit register on m series boards */
1130                 ni_writel(data, M_Offset_AI_SI2_Load_A);
1131                 return;
1132                 break;
1133         case AI_SI2_Load_B_Register:
1134                 /*  this is actually a 32 bit register on m series boards */
1135                 ni_writel(data, M_Offset_AI_SI2_Load_B);
1136                 return;
1137                 break;
1138         case AI_START_STOP_Select_Register:
1139                 offset = M_Offset_AI_START_STOP_Select;
1140                 break;
1141         case AI_Trigger_Select_Register:
1142                 offset = M_Offset_AI_Trigger_Select;
1143                 break;
1144         case Analog_Trigger_Etc_Register:
1145                 offset = M_Offset_Analog_Trigger_Etc;
1146                 break;
1147         case AO_Command_1_Register:
1148                 offset = M_Offset_AO_Command_1;
1149                 break;
1150         case AO_Command_2_Register:
1151                 offset = M_Offset_AO_Command_2;
1152                 break;
1153         case AO_Mode_1_Register:
1154                 offset = M_Offset_AO_Mode_1;
1155                 break;
1156         case AO_Mode_2_Register:
1157                 offset = M_Offset_AO_Mode_2;
1158                 break;
1159         case AO_Mode_3_Register:
1160                 offset = M_Offset_AO_Mode_3;
1161                 break;
1162         case AO_Output_Control_Register:
1163                 offset = M_Offset_AO_Output_Control;
1164                 break;
1165         case AO_Personal_Register:
1166                 offset = M_Offset_AO_Personal;
1167                 break;
1168         case AO_Start_Select_Register:
1169                 offset = M_Offset_AO_Start_Select;
1170                 break;
1171         case AO_Trigger_Select_Register:
1172                 offset = M_Offset_AO_Trigger_Select;
1173                 break;
1174         case Clock_and_FOUT_Register:
1175                 offset = M_Offset_Clock_and_FOUT;
1176                 break;
1177         case Configuration_Memory_Clear:
1178                 offset = M_Offset_Configuration_Memory_Clear;
1179                 break;
1180         case DAC_FIFO_Clear:
1181                 offset = M_Offset_AO_FIFO_Clear;
1182                 break;
1183         case DIO_Control_Register:
1184                 printk
1185                     ("%s: FIXME: register 0x%x does not map cleanly on to m-series boards.\n",
1186                      __func__, reg);
1187                 return;
1188                 break;
1189         case G_Autoincrement_Register(0):
1190                 offset = M_Offset_G0_Autoincrement;
1191                 break;
1192         case G_Autoincrement_Register(1):
1193                 offset = M_Offset_G1_Autoincrement;
1194                 break;
1195         case G_Command_Register(0):
1196                 offset = M_Offset_G0_Command;
1197                 break;
1198         case G_Command_Register(1):
1199                 offset = M_Offset_G1_Command;
1200                 break;
1201         case G_Input_Select_Register(0):
1202                 offset = M_Offset_G0_Input_Select;
1203                 break;
1204         case G_Input_Select_Register(1):
1205                 offset = M_Offset_G1_Input_Select;
1206                 break;
1207         case G_Mode_Register(0):
1208                 offset = M_Offset_G0_Mode;
1209                 break;
1210         case G_Mode_Register(1):
1211                 offset = M_Offset_G1_Mode;
1212                 break;
1213         case Interrupt_A_Ack_Register:
1214                 offset = M_Offset_Interrupt_A_Ack;
1215                 break;
1216         case Interrupt_A_Enable_Register:
1217                 offset = M_Offset_Interrupt_A_Enable;
1218                 break;
1219         case Interrupt_B_Ack_Register:
1220                 offset = M_Offset_Interrupt_B_Ack;
1221                 break;
1222         case Interrupt_B_Enable_Register:
1223                 offset = M_Offset_Interrupt_B_Enable;
1224                 break;
1225         case Interrupt_Control_Register:
1226                 offset = M_Offset_Interrupt_Control;
1227                 break;
1228         case IO_Bidirection_Pin_Register:
1229                 offset = M_Offset_IO_Bidirection_Pin;
1230                 break;
1231         case Joint_Reset_Register:
1232                 offset = M_Offset_Joint_Reset;
1233                 break;
1234         case RTSI_Trig_A_Output_Register:
1235                 offset = M_Offset_RTSI_Trig_A_Output;
1236                 break;
1237         case RTSI_Trig_B_Output_Register:
1238                 offset = M_Offset_RTSI_Trig_B_Output;
1239                 break;
1240         case RTSI_Trig_Direction_Register:
1241                 offset = M_Offset_RTSI_Trig_Direction;
1242                 break;
1243                 /* FIXME: DIO_Output_Register (16 bit reg) is replaced by M_Offset_Static_Digital_Output (32 bit)
1244                    and M_Offset_SCXI_Serial_Data_Out (8 bit) */
1245         default:
1246                 dev_warn(dev->class_dev,
1247                          "%s: bug! unhandled register=0x%x in switch.\n",
1248                          __func__, reg);
1249                 BUG();
1250                 return;
1251                 break;
1252         }
1253         ni_writew(data, offset);
1254 }
1255
1256 static uint16_t m_series_stc_readw(struct comedi_device *dev, int reg)
1257 {
1258         struct ni_private *devpriv = dev->private;
1259         unsigned offset;
1260
1261         switch (reg) {
1262         case AI_Status_1_Register:
1263                 offset = M_Offset_AI_Status_1;
1264                 break;
1265         case AO_Status_1_Register:
1266                 offset = M_Offset_AO_Status_1;
1267                 break;
1268         case AO_Status_2_Register:
1269                 offset = M_Offset_AO_Status_2;
1270                 break;
1271         case DIO_Serial_Input_Register:
1272                 return ni_readb(M_Offset_SCXI_Serial_Data_In);
1273                 break;
1274         case Joint_Status_1_Register:
1275                 offset = M_Offset_Joint_Status_1;
1276                 break;
1277         case Joint_Status_2_Register:
1278                 offset = M_Offset_Joint_Status_2;
1279                 break;
1280         case G_Status_Register:
1281                 offset = M_Offset_G01_Status;
1282                 break;
1283         default:
1284                 dev_warn(dev->class_dev,
1285                          "%s: bug! unhandled register=0x%x in switch.\n",
1286                          __func__, reg);
1287                 BUG();
1288                 return 0;
1289                 break;
1290         }
1291         return ni_readw(offset);
1292 }
1293
1294 static void m_series_stc_writel(struct comedi_device *dev, uint32_t data,
1295                                 int reg)
1296 {
1297         struct ni_private *devpriv = dev->private;
1298         unsigned offset;
1299
1300         switch (reg) {
1301         case AI_SC_Load_A_Registers:
1302                 offset = M_Offset_AI_SC_Load_A;
1303                 break;
1304         case AI_SI_Load_A_Registers:
1305                 offset = M_Offset_AI_SI_Load_A;
1306                 break;
1307         case AO_BC_Load_A_Register:
1308                 offset = M_Offset_AO_BC_Load_A;
1309                 break;
1310         case AO_UC_Load_A_Register:
1311                 offset = M_Offset_AO_UC_Load_A;
1312                 break;
1313         case AO_UI_Load_A_Register:
1314                 offset = M_Offset_AO_UI_Load_A;
1315                 break;
1316         case G_Load_A_Register(0):
1317                 offset = M_Offset_G0_Load_A;
1318                 break;
1319         case G_Load_A_Register(1):
1320                 offset = M_Offset_G1_Load_A;
1321                 break;
1322         case G_Load_B_Register(0):
1323                 offset = M_Offset_G0_Load_B;
1324                 break;
1325         case G_Load_B_Register(1):
1326                 offset = M_Offset_G1_Load_B;
1327                 break;
1328         default:
1329                 dev_warn(dev->class_dev,
1330                          "%s: bug! unhandled register=0x%x in switch.\n",
1331                          __func__, reg);
1332                 BUG();
1333                 return;
1334                 break;
1335         }
1336         ni_writel(data, offset);
1337 }
1338
1339 static uint32_t m_series_stc_readl(struct comedi_device *dev, int reg)
1340 {
1341         struct ni_private *devpriv = dev->private;
1342         unsigned offset;
1343
1344         switch (reg) {
1345         case G_HW_Save_Register(0):
1346                 offset = M_Offset_G0_HW_Save;
1347                 break;
1348         case G_HW_Save_Register(1):
1349                 offset = M_Offset_G1_HW_Save;
1350                 break;
1351         case G_Save_Register(0):
1352                 offset = M_Offset_G0_Save;
1353                 break;
1354         case G_Save_Register(1):
1355                 offset = M_Offset_G1_Save;
1356                 break;
1357         default:
1358                 dev_warn(dev->class_dev,
1359                          "%s: bug! unhandled register=0x%x in switch.\n",
1360                          __func__, reg);
1361                 BUG();
1362                 return 0;
1363                 break;
1364         }
1365         return ni_readl(offset);
1366 }
1367
1368 #define interrupt_pin(a)        0
1369 #define IRQ_POLARITY 1
1370
1371 #define NI_E_IRQ_FLAGS          IRQF_SHARED
1372
1373 #include "ni_mio_common.c"
1374
1375 static int pcimio_ai_change(struct comedi_device *dev,
1376                             struct comedi_subdevice *s, unsigned long new_size);
1377 static int pcimio_ao_change(struct comedi_device *dev,
1378                             struct comedi_subdevice *s, unsigned long new_size);
1379 static int pcimio_gpct0_change(struct comedi_device *dev,
1380                                struct comedi_subdevice *s,
1381                                unsigned long new_size);
1382 static int pcimio_gpct1_change(struct comedi_device *dev,
1383                                struct comedi_subdevice *s,
1384                                unsigned long new_size);
1385 static int pcimio_dio_change(struct comedi_device *dev,
1386                              struct comedi_subdevice *s,
1387                              unsigned long new_size);
1388
1389 static void m_series_init_eeprom_buffer(struct comedi_device *dev)
1390 {
1391         struct ni_private *devpriv = dev->private;
1392         static const int Start_Cal_EEPROM = 0x400;
1393         static const unsigned window_size = 10;
1394         static const int serial_number_eeprom_offset = 0x4;
1395         static const int serial_number_eeprom_length = 0x4;
1396         unsigned old_iodwbsr_bits;
1397         unsigned old_iodwbsr1_bits;
1398         unsigned old_iodwcr1_bits;
1399         int i;
1400
1401         old_iodwbsr_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR);
1402         old_iodwbsr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1403         old_iodwcr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1404         writel(0x0, devpriv->mite->mite_io_addr + MITE_IODWBSR);
1405         writel(((0x80 | window_size) | devpriv->mite->daq_phys_addr),
1406                devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1407         writel(0x1 | old_iodwcr1_bits,
1408                devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1409         writel(0xf, devpriv->mite->mite_io_addr + 0x30);
1410
1411         BUG_ON(serial_number_eeprom_length > sizeof(devpriv->serial_number));
1412         for (i = 0; i < serial_number_eeprom_length; ++i) {
1413                 char *byte_ptr = (char *)&devpriv->serial_number + i;
1414                 *byte_ptr = ni_readb(serial_number_eeprom_offset + i);
1415         }
1416         devpriv->serial_number = be32_to_cpu(devpriv->serial_number);
1417
1418         for (i = 0; i < M_SERIES_EEPROM_SIZE; ++i)
1419                 devpriv->eeprom_buffer[i] = ni_readb(Start_Cal_EEPROM + i);
1420
1421         writel(old_iodwbsr1_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1422         writel(old_iodwbsr_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR);
1423         writel(old_iodwcr1_bits, devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1424         writel(0x0, devpriv->mite->mite_io_addr + 0x30);
1425 }
1426
1427 static void init_6143(struct comedi_device *dev)
1428 {
1429         const struct ni_board_struct *board = comedi_board(dev);
1430         struct ni_private *devpriv = dev->private;
1431
1432         /*  Disable interrupts */
1433         devpriv->stc_writew(dev, 0, Interrupt_Control_Register);
1434
1435         /*  Initialise 6143 AI specific bits */
1436         ni_writeb(0x00, Magic_6143);    /*  Set G0,G1 DMA mode to E series version */
1437         ni_writeb(0x80, PipelineDelay_6143);    /*  Set EOCMode, ADCMode and pipelinedelay */
1438         ni_writeb(0x00, EOC_Set_6143);  /*  Set EOC Delay */
1439
1440         /* Set the FIFO half full level */
1441         ni_writel(board->ai_fifo_depth / 2, AIFIFO_Flag_6143);
1442
1443         /*  Strobe Relay disable bit */
1444         devpriv->ai_calib_source_enabled = 0;
1445         ni_writew(devpriv->ai_calib_source | Calibration_Channel_6143_RelayOff,
1446                   Calibration_Channel_6143);
1447         ni_writew(devpriv->ai_calib_source, Calibration_Channel_6143);
1448 }
1449
1450 static void pcimio_detach(struct comedi_device *dev)
1451 {
1452         struct ni_private *devpriv = dev->private;
1453
1454         mio_common_detach(dev);
1455         if (dev->irq)
1456                 free_irq(dev->irq, dev);
1457         if (devpriv) {
1458                 mite_free_ring(devpriv->ai_mite_ring);
1459                 mite_free_ring(devpriv->ao_mite_ring);
1460                 mite_free_ring(devpriv->cdo_mite_ring);
1461                 mite_free_ring(devpriv->gpct_mite_ring[0]);
1462                 mite_free_ring(devpriv->gpct_mite_ring[1]);
1463                 if (devpriv->mite) {
1464                         mite_unsetup(devpriv->mite);
1465                         mite_free(devpriv->mite);
1466                 }
1467         }
1468         comedi_pci_disable(dev);
1469 }
1470
1471 static int pcimio_auto_attach(struct comedi_device *dev,
1472                               unsigned long context)
1473 {
1474         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1475         const struct ni_board_struct *board = NULL;
1476         struct ni_private *devpriv;
1477         int ret;
1478
1479         if (context < ARRAY_SIZE(ni_boards))
1480                 board = &ni_boards[context];
1481         if (!board)
1482                 return -ENODEV;
1483         dev->board_ptr = board;
1484         dev->board_name = board->name;
1485
1486         ret = comedi_pci_enable(dev);
1487         if (ret)
1488                 return ret;
1489
1490         ret = ni_alloc_private(dev);
1491         if (ret)
1492                 return ret;
1493         devpriv = dev->private;
1494
1495         devpriv->mite = mite_alloc(pcidev);
1496         if (!devpriv->mite)
1497                 return -ENOMEM;
1498
1499         if (board->reg_type & ni_reg_m_series_mask) {
1500                 devpriv->stc_writew = &m_series_stc_writew;
1501                 devpriv->stc_readw = &m_series_stc_readw;
1502                 devpriv->stc_writel = &m_series_stc_writel;
1503                 devpriv->stc_readl = &m_series_stc_readl;
1504         } else {
1505                 devpriv->stc_writew = &e_series_win_out;
1506                 devpriv->stc_readw = &e_series_win_in;
1507                 devpriv->stc_writel = &win_out2;
1508                 devpriv->stc_readl = &win_in2;
1509         }
1510
1511         ret = mite_setup(devpriv->mite);
1512         if (ret < 0) {
1513                 pr_warn("error setting up mite\n");
1514                 return ret;
1515         }
1516
1517         devpriv->ai_mite_ring = mite_alloc_ring(devpriv->mite);
1518         if (devpriv->ai_mite_ring == NULL)
1519                 return -ENOMEM;
1520         devpriv->ao_mite_ring = mite_alloc_ring(devpriv->mite);
1521         if (devpriv->ao_mite_ring == NULL)
1522                 return -ENOMEM;
1523         devpriv->cdo_mite_ring = mite_alloc_ring(devpriv->mite);
1524         if (devpriv->cdo_mite_ring == NULL)
1525                 return -ENOMEM;
1526         devpriv->gpct_mite_ring[0] = mite_alloc_ring(devpriv->mite);
1527         if (devpriv->gpct_mite_ring[0] == NULL)
1528                 return -ENOMEM;
1529         devpriv->gpct_mite_ring[1] = mite_alloc_ring(devpriv->mite);
1530         if (devpriv->gpct_mite_ring[1] == NULL)
1531                 return -ENOMEM;
1532
1533         if (board->reg_type & ni_reg_m_series_mask)
1534                 m_series_init_eeprom_buffer(dev);
1535         if (board->reg_type == ni_reg_6143)
1536                 init_6143(dev);
1537
1538         dev->irq = mite_irq(devpriv->mite);
1539
1540         if (dev->irq == 0) {
1541                 pr_warn("unknown irq (bad)\n");
1542         } else {
1543                 pr_debug("( irq = %u )\n", dev->irq);
1544                 ret = request_irq(dev->irq, ni_E_interrupt, NI_E_IRQ_FLAGS,
1545                                   DRV_NAME, dev);
1546                 if (ret < 0) {
1547                         pr_warn("irq not available\n");
1548                         dev->irq = 0;
1549                 }
1550         }
1551
1552         ret = ni_E_init(dev);
1553         if (ret < 0)
1554                 return ret;
1555
1556         dev->subdevices[NI_AI_SUBDEV].buf_change = &pcimio_ai_change;
1557         dev->subdevices[NI_AO_SUBDEV].buf_change = &pcimio_ao_change;
1558         dev->subdevices[NI_GPCT_SUBDEV(0)].buf_change = &pcimio_gpct0_change;
1559         dev->subdevices[NI_GPCT_SUBDEV(1)].buf_change = &pcimio_gpct1_change;
1560         dev->subdevices[NI_DIO_SUBDEV].buf_change = &pcimio_dio_change;
1561
1562         return ret;
1563 }
1564
1565 static int pcimio_ai_change(struct comedi_device *dev,
1566                             struct comedi_subdevice *s, unsigned long new_size)
1567 {
1568         struct ni_private *devpriv = dev->private;
1569         int ret;
1570
1571         ret = mite_buf_change(devpriv->ai_mite_ring, s->async);
1572         if (ret < 0)
1573                 return ret;
1574
1575         return 0;
1576 }
1577
1578 static int pcimio_ao_change(struct comedi_device *dev,
1579                             struct comedi_subdevice *s, unsigned long new_size)
1580 {
1581         struct ni_private *devpriv = dev->private;
1582         int ret;
1583
1584         ret = mite_buf_change(devpriv->ao_mite_ring, s->async);
1585         if (ret < 0)
1586                 return ret;
1587
1588         return 0;
1589 }
1590
1591 static int pcimio_gpct0_change(struct comedi_device *dev,
1592                                struct comedi_subdevice *s,
1593                                unsigned long new_size)
1594 {
1595         struct ni_private *devpriv = dev->private;
1596         int ret;
1597
1598         ret = mite_buf_change(devpriv->gpct_mite_ring[0], s->async);
1599         if (ret < 0)
1600                 return ret;
1601
1602         return 0;
1603 }
1604
1605 static int pcimio_gpct1_change(struct comedi_device *dev,
1606                                struct comedi_subdevice *s,
1607                                unsigned long new_size)
1608 {
1609         struct ni_private *devpriv = dev->private;
1610         int ret;
1611
1612         ret = mite_buf_change(devpriv->gpct_mite_ring[1], s->async);
1613         if (ret < 0)
1614                 return ret;
1615
1616         return 0;
1617 }
1618
1619 static int pcimio_dio_change(struct comedi_device *dev,
1620                              struct comedi_subdevice *s, unsigned long new_size)
1621 {
1622         struct ni_private *devpriv = dev->private;
1623         int ret;
1624
1625         ret = mite_buf_change(devpriv->cdo_mite_ring, s->async);
1626         if (ret < 0)
1627                 return ret;
1628
1629         return 0;
1630 }
1631
1632 static struct comedi_driver ni_pcimio_driver = {
1633         .driver_name    = "ni_pcimio",
1634         .module         = THIS_MODULE,
1635         .auto_attach    = pcimio_auto_attach,
1636         .detach         = pcimio_detach,
1637 };
1638
1639 static int ni_pcimio_pci_probe(struct pci_dev *dev,
1640                                const struct pci_device_id *id)
1641 {
1642         return comedi_pci_auto_config(dev, &ni_pcimio_driver, id->driver_data);
1643 }
1644
1645 static DEFINE_PCI_DEVICE_TABLE(ni_pcimio_pci_table) = {
1646         { PCI_VDEVICE(NI, 0x0162), BOARD_PCIMIO_16XE_50 },      /* 0x1620? */
1647         { PCI_VDEVICE(NI, 0x1170), BOARD_PCIMIO_16XE_10 },
1648         { PCI_VDEVICE(NI, 0x1180), BOARD_PCIMIO_16E_1 },
1649         { PCI_VDEVICE(NI, 0x1190), BOARD_PCIMIO_16E_4 },
1650         { PCI_VDEVICE(NI, 0x11b0), BOARD_PXI6070E },
1651         { PCI_VDEVICE(NI, 0x11c0), BOARD_PXI6040E },
1652         { PCI_VDEVICE(NI, 0x11d0), BOARD_PXI6030E },
1653         { PCI_VDEVICE(NI, 0x1270), BOARD_PCI6032E },
1654         { PCI_VDEVICE(NI, 0x1330), BOARD_PCI6031E },
1655         { PCI_VDEVICE(NI, 0x1340), BOARD_PCI6033E },
1656         { PCI_VDEVICE(NI, 0x1350), BOARD_PCI6071E },
1657         { PCI_VDEVICE(NI, 0x14e0), BOARD_PCI6110 },
1658         { PCI_VDEVICE(NI, 0x14f0), BOARD_PCI6111 },
1659         { PCI_VDEVICE(NI, 0x1580), BOARD_PXI6031E },
1660         { PCI_VDEVICE(NI, 0x15b0), BOARD_PXI6071E },
1661         { PCI_VDEVICE(NI, 0x1880), BOARD_PCI6711 },
1662         { PCI_VDEVICE(NI, 0x1870), BOARD_PCI6713 },
1663         { PCI_VDEVICE(NI, 0x18b0), BOARD_PCI6052E },
1664         { PCI_VDEVICE(NI, 0x18c0), BOARD_PXI6052E },
1665         { PCI_VDEVICE(NI, 0x2410), BOARD_PCI6733 },
1666         { PCI_VDEVICE(NI, 0x2420), BOARD_PXI6733 },
1667         { PCI_VDEVICE(NI, 0x2430), BOARD_PCI6731 },
1668         { PCI_VDEVICE(NI, 0x2890), BOARD_PCI6036E },
1669         { PCI_VDEVICE(NI, 0x28c0), BOARD_PCI6014 },
1670         { PCI_VDEVICE(NI, 0x2a60), BOARD_PCI6023E },
1671         { PCI_VDEVICE(NI, 0x2a70), BOARD_PCI6024E },
1672         { PCI_VDEVICE(NI, 0x2a80), BOARD_PCI6025E },
1673         { PCI_VDEVICE(NI, 0x2ab0), BOARD_PXI6025E },
1674         { PCI_VDEVICE(NI, 0x2b80), BOARD_PXI6713 },
1675         { PCI_VDEVICE(NI, 0x2b90), BOARD_PXI6711 },
1676         { PCI_VDEVICE(NI, 0x2c80), BOARD_PCI6035E },
1677         { PCI_VDEVICE(NI, 0x2ca0), BOARD_PCI6034E },
1678         { PCI_VDEVICE(NI, 0x70aa), BOARD_PCI6229 },
1679         { PCI_VDEVICE(NI, 0x70ab), BOARD_PCI6259 },
1680         { PCI_VDEVICE(NI, 0x70ac), BOARD_PCI6289 },
1681         { PCI_VDEVICE(NI, 0x70af), BOARD_PCI6221 },
1682         { PCI_VDEVICE(NI, 0x70b0), BOARD_PCI6220 },
1683         { PCI_VDEVICE(NI, 0x70b4), BOARD_PCI6250 },
1684         { PCI_VDEVICE(NI, 0x70b6), BOARD_PCI6280 },
1685         { PCI_VDEVICE(NI, 0x70b7), BOARD_PCI6254 },
1686         { PCI_VDEVICE(NI, 0x70b8), BOARD_PCI6251 },
1687         { PCI_VDEVICE(NI, 0x70bc), BOARD_PCI6284 },
1688         { PCI_VDEVICE(NI, 0x70bd), BOARD_PCI6281 },
1689         { PCI_VDEVICE(NI, 0x70bf), BOARD_PXI6281 },
1690         { PCI_VDEVICE(NI, 0x70c0), BOARD_PCI6143 },
1691         { PCI_VDEVICE(NI, 0x70f2), BOARD_PCI6224 },
1692         { PCI_VDEVICE(NI, 0x70f3), BOARD_PXI6224 },
1693         { PCI_VDEVICE(NI, 0x710d), BOARD_PXI6143 },
1694         { PCI_VDEVICE(NI, 0x716c), BOARD_PCI6225 },
1695         { PCI_VDEVICE(NI, 0x716d), BOARD_PXI6225 },
1696         { PCI_VDEVICE(NI, 0x717f), BOARD_PCIE6259 },
1697         { PCI_VDEVICE(NI, 0x71bc), BOARD_PCI6221_37PIN },
1698         { PCI_VDEVICE(NI, 0x717d), BOARD_PCIE6251 },
1699         { PCI_VDEVICE(NI, 0x72e8), BOARD_PXIE6251 },
1700         { 0 }
1701 };
1702 MODULE_DEVICE_TABLE(pci, ni_pcimio_pci_table);
1703
1704 static struct pci_driver ni_pcimio_pci_driver = {
1705         .name           = "ni_pcimio",
1706         .id_table       = ni_pcimio_pci_table,
1707         .probe          = ni_pcimio_pci_probe,
1708         .remove         = comedi_pci_auto_unconfig,
1709 };
1710 module_comedi_pci_driver(ni_pcimio_driver, ni_pcimio_pci_driver);
1711
1712 MODULE_AUTHOR("Comedi http://www.comedi.org");
1713 MODULE_DESCRIPTION("Comedi low-level driver");
1714 MODULE_LICENSE("GPL");