2 comedi/drivers/ni_pcimio.c
3 Hardware driver for NI PCI-MIO E series cards
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 Description: National Instruments PCI-MIO-E series and M series (all boards)
25 Author: ds, John Hallen, Frank Mori Hess, Rolf Mueller, Herbert Peremans,
26 Herman Bruyninckx, Terry Barnaby
28 Devices: [National Instruments] PCI-MIO-16XE-50 (ni_pcimio),
29 PCI-MIO-16XE-10, PXI-6030E, PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-6014, PCI-6040E,
30 PXI-6040E, PCI-6030E, PCI-6031E, PCI-6032E, PCI-6033E, PCI-6071E, PCI-6023E,
31 PCI-6024E, PCI-6025E, PXI-6025E, PCI-6034E, PCI-6035E, PCI-6052E,
32 PCI-6110, PCI-6111, PCI-6220, PCI-6221, PCI-6224, PXI-6224,
33 PCI-6225, PXI-6225, PCI-6229, PCI-6250, PCI-6251, PCIe-6251, PXIe-6251,
34 PCI-6254, PCI-6259, PCIe-6259,
35 PCI-6280, PCI-6281, PXI-6281, PCI-6284, PCI-6289,
36 PCI-6711, PXI-6711, PCI-6713, PXI-6713,
37 PXI-6071E, PCI-6070E, PXI-6070E,
38 PXI-6052E, PCI-6036E, PCI-6731, PCI-6733, PXI-6733,
40 Updated: Mon, 09 Jan 2012 14:52:48 +0000
42 These boards are almost identical to the AT-MIO E series, except that
43 they use the PCI bus instead of ISA (i.e., AT). See the notes for
44 the ni_atmio.o driver for additional information about these boards.
46 Autocalibration is supported on many of the devices, using the
47 comedi_calibrate (or comedi_soft_calibrate for m-series) utility.
48 M-Series boards do analog input and analog output calibration entirely
49 in software. The software calibration corrects
50 the analog input for offset, gain and
51 nonlinearity. The analog outputs are corrected for offset and gain.
52 See the comedilib documentation on comedi_get_softcal_converter() for
55 By default, the driver uses DMA to transfer analog input data to
56 memory. When DMA is enabled, not all triggering features are
59 Digital I/O may not work on 673x.
61 Note that the PCI-6143 is a simultaineous sampling device with 8 convertors.
62 With this board all of the convertors perform one simultaineous sample during
63 a scan interval. The period for a scan is used for the convert time in a
64 Comedi cmd. The convert trigger source is normally set to TRIG_NOW by default.
66 The RTSI trigger bus is supported on these cards on
67 subdevice 10. See the comedilib documentation for details.
69 Information (number of channels, bits, etc.) for some devices may be
70 incorrect. Please check this and submit a bug if there are problems
73 SCXI is probably broken for m-series boards.
76 - When DMA is enabled, COMEDI_EV_CONVERT does
81 The PCI-MIO E series driver was originally written by
82 Tomasz Motylewski <...>, and ported to comedi by ds.
86 341079b.pdf PCI E Series Register-Level Programmer Manual
87 340934b.pdf DAQ-STC reference manual
89 322080b.pdf 6711/6713/6715 User Manual
91 320945c.pdf PCI E Series User Manual
92 322138a.pdf PCI-6052E and DAQPad-6052E User Manual
96 need to deal with external reference for DAC, and other DAC
97 properties in board properties
99 deal with at-mio-16de-10 revision D to N changes, etc.
101 need to add other CALDAC type
103 need to slow down DAC loading. I don't trust NI's claim that
104 two writes to the PCI bus slows IO enough. I would prefer to
105 use udelay(). Timing specs: (clock)
113 #include <linux/delay.h>
115 #include "../comedidev.h"
117 #include <asm/byteorder.h>
122 /* #define PCI_DEBUG */
129 #define MAX_N_CALDACS (16+16+2)
131 #define DRV_NAME "ni_pcimio"
133 /* These are not all the possible ao ranges for 628x boards.
134 They can do OFFSET +- REFERENCE where OFFSET can be
135 0V, 5V, APFI<0,1>, or AO<0...3> and RANGE can
136 be 10V, 5V, 2V, 1V, APFI<0,1>, AO<0...3>. That's
137 63 different possibilities. An AO channel
138 can not act as it's own OFFSET or REFERENCE.
140 static const struct comedi_lrange range_ni_M_628x_ao = { 8, {
153 static const struct comedi_lrange range_ni_M_625x_ao = { 3, {
160 enum ni_pcimio_boardid {
161 BOARD_PCIMIO_16XE_50,
162 BOARD_PCIMIO_16XE_10,
220 static const struct ni_board_struct ni_boards[] = {
221 [BOARD_PCIMIO_16XE_50] = {
222 .name = "pci-mio-16xe-50",
225 .ai_fifo_depth = 2048,
227 .gainlkup = ai_gain_8,
231 .ao_range_table = &range_bipolar10,
233 .num_p0_dio_channels = 8,
234 .caldac = { dac8800, dac8043 },
236 [BOARD_PCIMIO_16XE_10] = {
237 .name = "pci-mio-16xe-10", /* aka pci-6030E */
240 .ai_fifo_depth = 512,
242 .gainlkup = ai_gain_14,
246 .ao_fifo_depth = 2048,
247 .ao_range_table = &range_ni_E_ao_ext,
250 .num_p0_dio_channels = 8,
251 .caldac = { dac8800, dac8043, ad8522 },
257 .ai_fifo_depth = 512,
259 .gainlkup = ai_gain_4,
263 .ao_range_table = &range_bipolar10,
265 .num_p0_dio_channels = 8,
266 .caldac = { ad8804_debug },
272 .ai_fifo_depth = 512,
274 .gainlkup = ai_gain_14,
278 .ao_fifo_depth = 2048,
279 .ao_range_table = &range_ni_E_ao_ext,
282 .num_p0_dio_channels = 8,
283 .caldac = { dac8800, dac8043, ad8522 },
285 [BOARD_PCIMIO_16E_1] = {
286 .name = "pci-mio-16e-1", /* aka pci-6070e */
289 .ai_fifo_depth = 512,
290 .gainlkup = ai_gain_16,
294 .ao_fifo_depth = 2048,
295 .ao_range_table = &range_ni_E_ao_ext,
298 .num_p0_dio_channels = 8,
299 .caldac = { mb88341 },
301 [BOARD_PCIMIO_16E_4] = {
302 .name = "pci-mio-16e-4", /* aka pci-6040e */
305 .ai_fifo_depth = 512,
306 .gainlkup = ai_gain_16,
308 * there have been reported problems with
309 * full speed on this board
314 .ao_fifo_depth = 512,
315 .ao_range_table = &range_ni_E_ao_ext,
318 .num_p0_dio_channels = 8,
319 .caldac = { ad8804_debug }, /* doc says mb88341 */
325 .ai_fifo_depth = 512,
326 .gainlkup = ai_gain_16,
330 .ao_fifo_depth = 512,
331 .ao_range_table = &range_ni_E_ao_ext,
334 .num_p0_dio_channels = 8,
335 .caldac = { mb88341 },
341 .ai_fifo_depth = 512,
343 .gainlkup = ai_gain_14,
347 .ao_fifo_depth = 2048,
348 .ao_range_table = &range_ni_E_ao_ext,
351 .num_p0_dio_channels = 8,
352 .caldac = { dac8800, dac8043, ad8522 },
358 .ai_fifo_depth = 512,
360 .gainlkup = ai_gain_14,
362 .num_p0_dio_channels = 8,
363 .caldac = { dac8800, dac8043, ad8522 },
369 .ai_fifo_depth = 512,
371 .gainlkup = ai_gain_14,
373 .num_p0_dio_channels = 8,
374 .caldac = { dac8800, dac8043, ad8522 },
380 .ai_fifo_depth = 512,
382 .gainlkup = ai_gain_16,
386 .ao_fifo_depth = 2048,
387 .ao_range_table = &range_ni_E_ao_ext,
390 .num_p0_dio_channels = 8,
391 .caldac = { ad8804_debug },
397 .ai_fifo_depth = 512,
398 .gainlkup = ai_gain_4,
400 .num_p0_dio_channels = 8,
401 .caldac = { ad8804_debug }, /* manual is wrong */
407 .ai_fifo_depth = 512,
408 .gainlkup = ai_gain_4,
412 .ao_range_table = &range_bipolar10,
414 .num_p0_dio_channels = 8,
415 .caldac = { ad8804_debug }, /* manual is wrong */
421 .ai_fifo_depth = 512,
422 .gainlkup = ai_gain_4,
426 .ao_range_table = &range_bipolar10,
428 .num_p0_dio_channels = 8,
429 .caldac = { ad8804_debug }, /* manual is wrong */
436 .ai_fifo_depth = 512,
437 .gainlkup = ai_gain_4,
441 .ao_range_table = &range_ni_E_ao_ext,
444 .num_p0_dio_channels = 8,
445 .caldac = { ad8804_debug }, /* manual is wrong */
452 .ai_fifo_depth = 512,
454 .gainlkup = ai_gain_4,
456 .num_p0_dio_channels = 8,
457 .caldac = { ad8804_debug },
463 .ai_fifo_depth = 512,
465 .gainlkup = ai_gain_4,
469 .ao_range_table = &range_bipolar10,
471 .num_p0_dio_channels = 8,
472 .caldac = { ad8804_debug },
478 .ai_fifo_depth = 512,
480 .gainlkup = ai_gain_16,
485 .ao_fifo_depth = 2048,
486 .ao_range_table = &range_ni_E_ao_ext,
488 .num_p0_dio_channels = 8,
489 /* manual is wrong */
490 .caldac = { ad8804_debug, ad8804_debug, ad8522 },
496 .ai_fifo_depth = 8192,
498 .gainlkup = ai_gain_611x,
502 .reg_type = ni_reg_611x,
503 .ao_range_table = &range_bipolar10,
504 .ao_fifo_depth = 2048,
506 .num_p0_dio_channels = 8,
507 .caldac = { ad8804, ad8804 },
513 .ai_fifo_depth = 8192,
514 .gainlkup = ai_gain_611x,
518 .reg_type = ni_reg_611x,
519 .ao_range_table = &range_bipolar10,
520 .ao_fifo_depth = 2048,
522 .num_p0_dio_channels = 8,
523 .caldac = { ad8804, ad8804 },
526 /* The 6115 boards probably need their own driver */
527 [BOARD_PCI6115] = { /* .device_id = 0x2ed0, */
531 .ai_fifo_depth = 8192,
532 .gainlkup = ai_gain_611x,
537 .ao_fifo_depth = 2048,
539 .num_p0_dio_channels = 8,
542 .caldac = { ad8804_debug, ad8804_debug, ad8804_debug },
546 [BOARD_PXI6115] = { /* .device_id = ????, */
550 .ai_fifo_depth = 8192,
551 .gainlkup = ai_gain_611x,
556 .ao_fifo_depth = 2048,
559 .num_p0_dio_channels = 8,
561 .caldac = { ad8804_debug, ad8804_debug, ad8804_debug },
568 /* data sheet says 8192, but fifo really holds 16384 samples */
569 .ao_fifo_depth = 16384,
570 .ao_range_table = &range_bipolar10,
572 .num_p0_dio_channels = 8,
573 .reg_type = ni_reg_6711,
574 .caldac = { ad8804_debug },
580 .ao_fifo_depth = 16384,
581 .ao_range_table = &range_bipolar10,
583 .num_p0_dio_channels = 8,
584 .reg_type = ni_reg_6711,
585 .caldac = { ad8804_debug },
591 .ao_fifo_depth = 16384,
592 .ao_range_table = &range_bipolar10,
594 .num_p0_dio_channels = 8,
595 .reg_type = ni_reg_6713,
596 .caldac = { ad8804_debug, ad8804_debug },
602 .ao_fifo_depth = 16384,
603 .ao_range_table = &range_bipolar10,
605 .num_p0_dio_channels = 8,
606 .reg_type = ni_reg_6713,
607 .caldac = { ad8804_debug, ad8804_debug },
613 .ao_fifo_depth = 8192,
614 .ao_range_table = &range_bipolar10,
616 .num_p0_dio_channels = 8,
617 .reg_type = ni_reg_6711,
618 .caldac = { ad8804_debug },
621 [BOARD_PXI6731] = { /* .device_id = ????, */
625 .ao_fifo_depth = 8192,
626 .ao_range_table = &range_bipolar10,
627 .num_p0_dio_channels = 8,
628 .reg_type = ni_reg_6711,
629 .caldac = { ad8804_debug },
636 .ao_fifo_depth = 16384,
637 .ao_range_table = &range_bipolar10,
639 .num_p0_dio_channels = 8,
640 .reg_type = ni_reg_6713,
641 .caldac = { ad8804_debug, ad8804_debug },
647 .ao_fifo_depth = 16384,
648 .ao_range_table = &range_bipolar10,
650 .num_p0_dio_channels = 8,
651 .reg_type = ni_reg_6713,
652 .caldac = { ad8804_debug, ad8804_debug },
658 .ai_fifo_depth = 512,
660 .gainlkup = ai_gain_16,
664 .ao_fifo_depth = 2048,
665 .ao_range_table = &range_ni_E_ao_ext,
668 .num_p0_dio_channels = 8,
669 .caldac = { ad8804_debug },
675 .ai_fifo_depth = 512,
677 .gainlkup = ai_gain_16,
681 .ao_fifo_depth = 2048,
682 .ao_range_table = &range_ni_E_ao_ext,
685 .num_p0_dio_channels = 8,
686 .caldac = { ad8804_debug },
692 .ai_fifo_depth = 512,
694 .gainlkup = ai_gain_16,
699 .ao_fifo_depth = 2048,
700 .ao_range_table = &range_ni_E_ao_ext,
702 .num_p0_dio_channels = 8,
703 .caldac = { mb88341, mb88341, ad8522 },
709 .ai_fifo_depth = 512,
711 .gainlkup = ai_gain_14,
715 .ao_fifo_depth = 2048,
716 .ao_range_table = &range_ni_E_ao_ext,
719 .num_p0_dio_channels = 8,
720 .caldac = { dac8800, dac8043, ad8522 },
726 .ai_fifo_depth = 512,
728 .gainlkup = ai_gain_4,
732 .ao_range_table = &range_bipolar10,
734 .num_p0_dio_channels = 8,
735 .caldac = { ad8804_debug },
741 .ai_fifo_depth = 512, /* FIXME: guess */
742 .gainlkup = ai_gain_622x,
744 .num_p0_dio_channels = 8,
745 .reg_type = ni_reg_622x,
746 .caldac = { caldac_none },
752 .ai_fifo_depth = 4095,
753 .gainlkup = ai_gain_622x,
757 .ao_fifo_depth = 8191,
758 .ao_range_table = &range_bipolar10,
759 .reg_type = ni_reg_622x,
761 .num_p0_dio_channels = 8,
762 .caldac = { caldac_none },
764 [BOARD_PCI6221_37PIN] = {
765 .name = "pci-6221_37pin",
768 .ai_fifo_depth = 4095,
769 .gainlkup = ai_gain_622x,
773 .ao_fifo_depth = 8191,
774 .ao_range_table = &range_bipolar10,
775 .reg_type = ni_reg_622x,
777 .num_p0_dio_channels = 8,
778 .caldac = { caldac_none },
784 .ai_fifo_depth = 4095,
785 .gainlkup = ai_gain_622x,
787 .reg_type = ni_reg_622x,
788 .num_p0_dio_channels = 32,
789 .caldac = { caldac_none },
795 .ai_fifo_depth = 4095,
796 .gainlkup = ai_gain_622x,
798 .reg_type = ni_reg_622x,
799 .num_p0_dio_channels = 32,
800 .caldac = { caldac_none },
806 .ai_fifo_depth = 4095,
807 .gainlkup = ai_gain_622x,
811 .ao_fifo_depth = 8191,
812 .ao_range_table = &range_bipolar10,
813 .reg_type = ni_reg_622x,
815 .num_p0_dio_channels = 32,
816 .caldac = { caldac_none },
822 .ai_fifo_depth = 4095,
823 .gainlkup = ai_gain_622x,
827 .ao_fifo_depth = 8191,
828 .ao_range_table = &range_bipolar10,
829 .reg_type = ni_reg_622x,
831 .num_p0_dio_channels = 32,
832 .caldac = { caldac_none },
838 .ai_fifo_depth = 4095,
839 .gainlkup = ai_gain_622x,
843 .ao_fifo_depth = 8191,
844 .ao_range_table = &range_bipolar10,
845 .reg_type = ni_reg_622x,
847 .num_p0_dio_channels = 32,
848 .caldac = { caldac_none },
854 .ai_fifo_depth = 4095,
855 .gainlkup = ai_gain_628x,
857 .reg_type = ni_reg_625x,
858 .num_p0_dio_channels = 8,
859 .caldac = { caldac_none },
865 .ai_fifo_depth = 4095,
866 .gainlkup = ai_gain_628x,
870 .ao_fifo_depth = 8191,
871 .ao_range_table = &range_ni_M_625x_ao,
872 .reg_type = ni_reg_625x,
874 .num_p0_dio_channels = 8,
875 .caldac = { caldac_none },
881 .ai_fifo_depth = 4095,
882 .gainlkup = ai_gain_628x,
886 .ao_fifo_depth = 8191,
887 .ao_range_table = &range_ni_M_625x_ao,
888 .reg_type = ni_reg_625x,
890 .num_p0_dio_channels = 8,
891 .caldac = { caldac_none },
897 .ai_fifo_depth = 4095,
898 .gainlkup = ai_gain_628x,
902 .ao_fifo_depth = 8191,
903 .ao_range_table = &range_ni_M_625x_ao,
904 .reg_type = ni_reg_625x,
906 .num_p0_dio_channels = 8,
907 .caldac = { caldac_none },
913 .ai_fifo_depth = 4095,
914 .gainlkup = ai_gain_628x,
916 .reg_type = ni_reg_625x,
917 .num_p0_dio_channels = 32,
918 .caldac = { caldac_none },
924 .ai_fifo_depth = 4095,
925 .gainlkup = ai_gain_628x,
929 .ao_fifo_depth = 8191,
930 .ao_range_table = &range_ni_M_625x_ao,
931 .reg_type = ni_reg_625x,
933 .num_p0_dio_channels = 32,
934 .caldac = { caldac_none },
940 .ai_fifo_depth = 4095,
941 .gainlkup = ai_gain_628x,
945 .ao_fifo_depth = 8191,
946 .ao_range_table = &range_ni_M_625x_ao,
947 .reg_type = ni_reg_625x,
949 .num_p0_dio_channels = 32,
950 .caldac = { caldac_none },
956 .ai_fifo_depth = 2047,
957 .gainlkup = ai_gain_628x,
959 .ao_fifo_depth = 8191,
960 .reg_type = ni_reg_628x,
961 .num_p0_dio_channels = 8,
962 .caldac = { caldac_none },
968 .ai_fifo_depth = 2047,
969 .gainlkup = ai_gain_628x,
973 .ao_fifo_depth = 8191,
974 .ao_range_table = &range_ni_M_628x_ao,
975 .reg_type = ni_reg_628x,
978 .num_p0_dio_channels = 8,
979 .caldac = { caldac_none },
985 .ai_fifo_depth = 2047,
986 .gainlkup = ai_gain_628x,
990 .ao_fifo_depth = 8191,
991 .ao_range_table = &range_ni_M_628x_ao,
992 .reg_type = ni_reg_628x,
995 .num_p0_dio_channels = 8,
996 .caldac = { caldac_none },
1002 .ai_fifo_depth = 2047,
1003 .gainlkup = ai_gain_628x,
1005 .reg_type = ni_reg_628x,
1006 .num_p0_dio_channels = 32,
1007 .caldac = { caldac_none },
1013 .ai_fifo_depth = 2047,
1014 .gainlkup = ai_gain_628x,
1018 .ao_fifo_depth = 8191,
1019 .ao_range_table = &range_ni_M_628x_ao,
1020 .reg_type = ni_reg_628x,
1023 .num_p0_dio_channels = 32,
1024 .caldac = { caldac_none },
1030 .ai_fifo_depth = 1024,
1031 .gainlkup = ai_gain_6143,
1033 .reg_type = ni_reg_6143,
1034 .num_p0_dio_channels = 8,
1035 .caldac = { ad8804_debug, ad8804_debug },
1041 .ai_fifo_depth = 1024,
1042 .gainlkup = ai_gain_6143,
1044 .reg_type = ni_reg_6143,
1045 .num_p0_dio_channels = 8,
1046 .caldac = { ad8804_debug, ad8804_debug },
1053 /* How we access registers */
1055 #define ni_writel(a, b) (writel((a), devpriv->mite->daq_io_addr + (b)))
1056 #define ni_readl(a) (readl(devpriv->mite->daq_io_addr + (a)))
1057 #define ni_writew(a, b) (writew((a), devpriv->mite->daq_io_addr + (b)))
1058 #define ni_readw(a) (readw(devpriv->mite->daq_io_addr + (a)))
1059 #define ni_writeb(a, b) (writeb((a), devpriv->mite->daq_io_addr + (b)))
1060 #define ni_readb(a) (readb(devpriv->mite->daq_io_addr + (a)))
1062 /* How we access STC registers */
1064 /* We automatically take advantage of STC registers that can be
1065 * read/written directly in the I/O space of the board. Most
1066 * PCIMIO devices map the low 8 STC registers to iobase+addr*2.
1067 * The 611x devices map the write registers to iobase+addr*2, and
1068 * the read registers to iobase+(addr-1)*2. */
1069 /* However, the 611x boards still aren't working, so I'm disabling
1070 * non-windowed STC access temporarily */
1072 static void e_series_win_out(struct comedi_device *dev, uint16_t data, int reg)
1074 struct ni_private *devpriv = dev->private;
1075 unsigned long flags;
1077 spin_lock_irqsave(&devpriv->window_lock, flags);
1078 ni_writew(reg, Window_Address);
1079 ni_writew(data, Window_Data);
1080 spin_unlock_irqrestore(&devpriv->window_lock, flags);
1083 static uint16_t e_series_win_in(struct comedi_device *dev, int reg)
1085 struct ni_private *devpriv = dev->private;
1086 unsigned long flags;
1089 spin_lock_irqsave(&devpriv->window_lock, flags);
1090 ni_writew(reg, Window_Address);
1091 ret = ni_readw(Window_Data);
1092 spin_unlock_irqrestore(&devpriv->window_lock, flags);
1097 static void m_series_stc_writew(struct comedi_device *dev, uint16_t data,
1100 struct ni_private *devpriv = dev->private;
1104 case ADC_FIFO_Clear:
1105 offset = M_Offset_AI_FIFO_Clear;
1107 case AI_Command_1_Register:
1108 offset = M_Offset_AI_Command_1;
1110 case AI_Command_2_Register:
1111 offset = M_Offset_AI_Command_2;
1113 case AI_Mode_1_Register:
1114 offset = M_Offset_AI_Mode_1;
1116 case AI_Mode_2_Register:
1117 offset = M_Offset_AI_Mode_2;
1119 case AI_Mode_3_Register:
1120 offset = M_Offset_AI_Mode_3;
1122 case AI_Output_Control_Register:
1123 offset = M_Offset_AI_Output_Control;
1125 case AI_Personal_Register:
1126 offset = M_Offset_AI_Personal;
1128 case AI_SI2_Load_A_Register:
1129 /* this is actually a 32 bit register on m series boards */
1130 ni_writel(data, M_Offset_AI_SI2_Load_A);
1133 case AI_SI2_Load_B_Register:
1134 /* this is actually a 32 bit register on m series boards */
1135 ni_writel(data, M_Offset_AI_SI2_Load_B);
1138 case AI_START_STOP_Select_Register:
1139 offset = M_Offset_AI_START_STOP_Select;
1141 case AI_Trigger_Select_Register:
1142 offset = M_Offset_AI_Trigger_Select;
1144 case Analog_Trigger_Etc_Register:
1145 offset = M_Offset_Analog_Trigger_Etc;
1147 case AO_Command_1_Register:
1148 offset = M_Offset_AO_Command_1;
1150 case AO_Command_2_Register:
1151 offset = M_Offset_AO_Command_2;
1153 case AO_Mode_1_Register:
1154 offset = M_Offset_AO_Mode_1;
1156 case AO_Mode_2_Register:
1157 offset = M_Offset_AO_Mode_2;
1159 case AO_Mode_3_Register:
1160 offset = M_Offset_AO_Mode_3;
1162 case AO_Output_Control_Register:
1163 offset = M_Offset_AO_Output_Control;
1165 case AO_Personal_Register:
1166 offset = M_Offset_AO_Personal;
1168 case AO_Start_Select_Register:
1169 offset = M_Offset_AO_Start_Select;
1171 case AO_Trigger_Select_Register:
1172 offset = M_Offset_AO_Trigger_Select;
1174 case Clock_and_FOUT_Register:
1175 offset = M_Offset_Clock_and_FOUT;
1177 case Configuration_Memory_Clear:
1178 offset = M_Offset_Configuration_Memory_Clear;
1180 case DAC_FIFO_Clear:
1181 offset = M_Offset_AO_FIFO_Clear;
1183 case DIO_Control_Register:
1185 ("%s: FIXME: register 0x%x does not map cleanly on to m-series boards.\n",
1189 case G_Autoincrement_Register(0):
1190 offset = M_Offset_G0_Autoincrement;
1192 case G_Autoincrement_Register(1):
1193 offset = M_Offset_G1_Autoincrement;
1195 case G_Command_Register(0):
1196 offset = M_Offset_G0_Command;
1198 case G_Command_Register(1):
1199 offset = M_Offset_G1_Command;
1201 case G_Input_Select_Register(0):
1202 offset = M_Offset_G0_Input_Select;
1204 case G_Input_Select_Register(1):
1205 offset = M_Offset_G1_Input_Select;
1207 case G_Mode_Register(0):
1208 offset = M_Offset_G0_Mode;
1210 case G_Mode_Register(1):
1211 offset = M_Offset_G1_Mode;
1213 case Interrupt_A_Ack_Register:
1214 offset = M_Offset_Interrupt_A_Ack;
1216 case Interrupt_A_Enable_Register:
1217 offset = M_Offset_Interrupt_A_Enable;
1219 case Interrupt_B_Ack_Register:
1220 offset = M_Offset_Interrupt_B_Ack;
1222 case Interrupt_B_Enable_Register:
1223 offset = M_Offset_Interrupt_B_Enable;
1225 case Interrupt_Control_Register:
1226 offset = M_Offset_Interrupt_Control;
1228 case IO_Bidirection_Pin_Register:
1229 offset = M_Offset_IO_Bidirection_Pin;
1231 case Joint_Reset_Register:
1232 offset = M_Offset_Joint_Reset;
1234 case RTSI_Trig_A_Output_Register:
1235 offset = M_Offset_RTSI_Trig_A_Output;
1237 case RTSI_Trig_B_Output_Register:
1238 offset = M_Offset_RTSI_Trig_B_Output;
1240 case RTSI_Trig_Direction_Register:
1241 offset = M_Offset_RTSI_Trig_Direction;
1243 /* FIXME: DIO_Output_Register (16 bit reg) is replaced by M_Offset_Static_Digital_Output (32 bit)
1244 and M_Offset_SCXI_Serial_Data_Out (8 bit) */
1246 dev_warn(dev->class_dev,
1247 "%s: bug! unhandled register=0x%x in switch.\n",
1253 ni_writew(data, offset);
1256 static uint16_t m_series_stc_readw(struct comedi_device *dev, int reg)
1258 struct ni_private *devpriv = dev->private;
1262 case AI_Status_1_Register:
1263 offset = M_Offset_AI_Status_1;
1265 case AO_Status_1_Register:
1266 offset = M_Offset_AO_Status_1;
1268 case AO_Status_2_Register:
1269 offset = M_Offset_AO_Status_2;
1271 case DIO_Serial_Input_Register:
1272 return ni_readb(M_Offset_SCXI_Serial_Data_In);
1274 case Joint_Status_1_Register:
1275 offset = M_Offset_Joint_Status_1;
1277 case Joint_Status_2_Register:
1278 offset = M_Offset_Joint_Status_2;
1280 case G_Status_Register:
1281 offset = M_Offset_G01_Status;
1284 dev_warn(dev->class_dev,
1285 "%s: bug! unhandled register=0x%x in switch.\n",
1291 return ni_readw(offset);
1294 static void m_series_stc_writel(struct comedi_device *dev, uint32_t data,
1297 struct ni_private *devpriv = dev->private;
1301 case AI_SC_Load_A_Registers:
1302 offset = M_Offset_AI_SC_Load_A;
1304 case AI_SI_Load_A_Registers:
1305 offset = M_Offset_AI_SI_Load_A;
1307 case AO_BC_Load_A_Register:
1308 offset = M_Offset_AO_BC_Load_A;
1310 case AO_UC_Load_A_Register:
1311 offset = M_Offset_AO_UC_Load_A;
1313 case AO_UI_Load_A_Register:
1314 offset = M_Offset_AO_UI_Load_A;
1316 case G_Load_A_Register(0):
1317 offset = M_Offset_G0_Load_A;
1319 case G_Load_A_Register(1):
1320 offset = M_Offset_G1_Load_A;
1322 case G_Load_B_Register(0):
1323 offset = M_Offset_G0_Load_B;
1325 case G_Load_B_Register(1):
1326 offset = M_Offset_G1_Load_B;
1329 dev_warn(dev->class_dev,
1330 "%s: bug! unhandled register=0x%x in switch.\n",
1336 ni_writel(data, offset);
1339 static uint32_t m_series_stc_readl(struct comedi_device *dev, int reg)
1341 struct ni_private *devpriv = dev->private;
1345 case G_HW_Save_Register(0):
1346 offset = M_Offset_G0_HW_Save;
1348 case G_HW_Save_Register(1):
1349 offset = M_Offset_G1_HW_Save;
1351 case G_Save_Register(0):
1352 offset = M_Offset_G0_Save;
1354 case G_Save_Register(1):
1355 offset = M_Offset_G1_Save;
1358 dev_warn(dev->class_dev,
1359 "%s: bug! unhandled register=0x%x in switch.\n",
1365 return ni_readl(offset);
1368 #define interrupt_pin(a) 0
1369 #define IRQ_POLARITY 1
1371 #define NI_E_IRQ_FLAGS IRQF_SHARED
1373 #include "ni_mio_common.c"
1375 static int pcimio_ai_change(struct comedi_device *dev,
1376 struct comedi_subdevice *s, unsigned long new_size);
1377 static int pcimio_ao_change(struct comedi_device *dev,
1378 struct comedi_subdevice *s, unsigned long new_size);
1379 static int pcimio_gpct0_change(struct comedi_device *dev,
1380 struct comedi_subdevice *s,
1381 unsigned long new_size);
1382 static int pcimio_gpct1_change(struct comedi_device *dev,
1383 struct comedi_subdevice *s,
1384 unsigned long new_size);
1385 static int pcimio_dio_change(struct comedi_device *dev,
1386 struct comedi_subdevice *s,
1387 unsigned long new_size);
1389 static void m_series_init_eeprom_buffer(struct comedi_device *dev)
1391 struct ni_private *devpriv = dev->private;
1392 static const int Start_Cal_EEPROM = 0x400;
1393 static const unsigned window_size = 10;
1394 static const int serial_number_eeprom_offset = 0x4;
1395 static const int serial_number_eeprom_length = 0x4;
1396 unsigned old_iodwbsr_bits;
1397 unsigned old_iodwbsr1_bits;
1398 unsigned old_iodwcr1_bits;
1401 old_iodwbsr_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR);
1402 old_iodwbsr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1403 old_iodwcr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1404 writel(0x0, devpriv->mite->mite_io_addr + MITE_IODWBSR);
1405 writel(((0x80 | window_size) | devpriv->mite->daq_phys_addr),
1406 devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1407 writel(0x1 | old_iodwcr1_bits,
1408 devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1409 writel(0xf, devpriv->mite->mite_io_addr + 0x30);
1411 BUG_ON(serial_number_eeprom_length > sizeof(devpriv->serial_number));
1412 for (i = 0; i < serial_number_eeprom_length; ++i) {
1413 char *byte_ptr = (char *)&devpriv->serial_number + i;
1414 *byte_ptr = ni_readb(serial_number_eeprom_offset + i);
1416 devpriv->serial_number = be32_to_cpu(devpriv->serial_number);
1418 for (i = 0; i < M_SERIES_EEPROM_SIZE; ++i)
1419 devpriv->eeprom_buffer[i] = ni_readb(Start_Cal_EEPROM + i);
1421 writel(old_iodwbsr1_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1422 writel(old_iodwbsr_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR);
1423 writel(old_iodwcr1_bits, devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1424 writel(0x0, devpriv->mite->mite_io_addr + 0x30);
1427 static void init_6143(struct comedi_device *dev)
1429 const struct ni_board_struct *board = comedi_board(dev);
1430 struct ni_private *devpriv = dev->private;
1432 /* Disable interrupts */
1433 devpriv->stc_writew(dev, 0, Interrupt_Control_Register);
1435 /* Initialise 6143 AI specific bits */
1436 ni_writeb(0x00, Magic_6143); /* Set G0,G1 DMA mode to E series version */
1437 ni_writeb(0x80, PipelineDelay_6143); /* Set EOCMode, ADCMode and pipelinedelay */
1438 ni_writeb(0x00, EOC_Set_6143); /* Set EOC Delay */
1440 /* Set the FIFO half full level */
1441 ni_writel(board->ai_fifo_depth / 2, AIFIFO_Flag_6143);
1443 /* Strobe Relay disable bit */
1444 devpriv->ai_calib_source_enabled = 0;
1445 ni_writew(devpriv->ai_calib_source | Calibration_Channel_6143_RelayOff,
1446 Calibration_Channel_6143);
1447 ni_writew(devpriv->ai_calib_source, Calibration_Channel_6143);
1450 static void pcimio_detach(struct comedi_device *dev)
1452 struct ni_private *devpriv = dev->private;
1454 mio_common_detach(dev);
1456 free_irq(dev->irq, dev);
1458 mite_free_ring(devpriv->ai_mite_ring);
1459 mite_free_ring(devpriv->ao_mite_ring);
1460 mite_free_ring(devpriv->cdo_mite_ring);
1461 mite_free_ring(devpriv->gpct_mite_ring[0]);
1462 mite_free_ring(devpriv->gpct_mite_ring[1]);
1463 if (devpriv->mite) {
1464 mite_unsetup(devpriv->mite);
1465 mite_free(devpriv->mite);
1468 comedi_pci_disable(dev);
1471 static int pcimio_auto_attach(struct comedi_device *dev,
1472 unsigned long context)
1474 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1475 const struct ni_board_struct *board = NULL;
1476 struct ni_private *devpriv;
1479 if (context < ARRAY_SIZE(ni_boards))
1480 board = &ni_boards[context];
1483 dev->board_ptr = board;
1484 dev->board_name = board->name;
1486 ret = comedi_pci_enable(dev);
1490 ret = ni_alloc_private(dev);
1493 devpriv = dev->private;
1495 devpriv->mite = mite_alloc(pcidev);
1499 if (board->reg_type & ni_reg_m_series_mask) {
1500 devpriv->stc_writew = &m_series_stc_writew;
1501 devpriv->stc_readw = &m_series_stc_readw;
1502 devpriv->stc_writel = &m_series_stc_writel;
1503 devpriv->stc_readl = &m_series_stc_readl;
1505 devpriv->stc_writew = &e_series_win_out;
1506 devpriv->stc_readw = &e_series_win_in;
1507 devpriv->stc_writel = &win_out2;
1508 devpriv->stc_readl = &win_in2;
1511 ret = mite_setup(devpriv->mite);
1513 pr_warn("error setting up mite\n");
1517 devpriv->ai_mite_ring = mite_alloc_ring(devpriv->mite);
1518 if (devpriv->ai_mite_ring == NULL)
1520 devpriv->ao_mite_ring = mite_alloc_ring(devpriv->mite);
1521 if (devpriv->ao_mite_ring == NULL)
1523 devpriv->cdo_mite_ring = mite_alloc_ring(devpriv->mite);
1524 if (devpriv->cdo_mite_ring == NULL)
1526 devpriv->gpct_mite_ring[0] = mite_alloc_ring(devpriv->mite);
1527 if (devpriv->gpct_mite_ring[0] == NULL)
1529 devpriv->gpct_mite_ring[1] = mite_alloc_ring(devpriv->mite);
1530 if (devpriv->gpct_mite_ring[1] == NULL)
1533 if (board->reg_type & ni_reg_m_series_mask)
1534 m_series_init_eeprom_buffer(dev);
1535 if (board->reg_type == ni_reg_6143)
1538 dev->irq = mite_irq(devpriv->mite);
1540 if (dev->irq == 0) {
1541 pr_warn("unknown irq (bad)\n");
1543 pr_debug("( irq = %u )\n", dev->irq);
1544 ret = request_irq(dev->irq, ni_E_interrupt, NI_E_IRQ_FLAGS,
1547 pr_warn("irq not available\n");
1552 ret = ni_E_init(dev);
1556 dev->subdevices[NI_AI_SUBDEV].buf_change = &pcimio_ai_change;
1557 dev->subdevices[NI_AO_SUBDEV].buf_change = &pcimio_ao_change;
1558 dev->subdevices[NI_GPCT_SUBDEV(0)].buf_change = &pcimio_gpct0_change;
1559 dev->subdevices[NI_GPCT_SUBDEV(1)].buf_change = &pcimio_gpct1_change;
1560 dev->subdevices[NI_DIO_SUBDEV].buf_change = &pcimio_dio_change;
1565 static int pcimio_ai_change(struct comedi_device *dev,
1566 struct comedi_subdevice *s, unsigned long new_size)
1568 struct ni_private *devpriv = dev->private;
1571 ret = mite_buf_change(devpriv->ai_mite_ring, s->async);
1578 static int pcimio_ao_change(struct comedi_device *dev,
1579 struct comedi_subdevice *s, unsigned long new_size)
1581 struct ni_private *devpriv = dev->private;
1584 ret = mite_buf_change(devpriv->ao_mite_ring, s->async);
1591 static int pcimio_gpct0_change(struct comedi_device *dev,
1592 struct comedi_subdevice *s,
1593 unsigned long new_size)
1595 struct ni_private *devpriv = dev->private;
1598 ret = mite_buf_change(devpriv->gpct_mite_ring[0], s->async);
1605 static int pcimio_gpct1_change(struct comedi_device *dev,
1606 struct comedi_subdevice *s,
1607 unsigned long new_size)
1609 struct ni_private *devpriv = dev->private;
1612 ret = mite_buf_change(devpriv->gpct_mite_ring[1], s->async);
1619 static int pcimio_dio_change(struct comedi_device *dev,
1620 struct comedi_subdevice *s, unsigned long new_size)
1622 struct ni_private *devpriv = dev->private;
1625 ret = mite_buf_change(devpriv->cdo_mite_ring, s->async);
1632 static struct comedi_driver ni_pcimio_driver = {
1633 .driver_name = "ni_pcimio",
1634 .module = THIS_MODULE,
1635 .auto_attach = pcimio_auto_attach,
1636 .detach = pcimio_detach,
1639 static int ni_pcimio_pci_probe(struct pci_dev *dev,
1640 const struct pci_device_id *id)
1642 return comedi_pci_auto_config(dev, &ni_pcimio_driver, id->driver_data);
1645 static DEFINE_PCI_DEVICE_TABLE(ni_pcimio_pci_table) = {
1646 { PCI_VDEVICE(NI, 0x0162), BOARD_PCIMIO_16XE_50 }, /* 0x1620? */
1647 { PCI_VDEVICE(NI, 0x1170), BOARD_PCIMIO_16XE_10 },
1648 { PCI_VDEVICE(NI, 0x1180), BOARD_PCIMIO_16E_1 },
1649 { PCI_VDEVICE(NI, 0x1190), BOARD_PCIMIO_16E_4 },
1650 { PCI_VDEVICE(NI, 0x11b0), BOARD_PXI6070E },
1651 { PCI_VDEVICE(NI, 0x11c0), BOARD_PXI6040E },
1652 { PCI_VDEVICE(NI, 0x11d0), BOARD_PXI6030E },
1653 { PCI_VDEVICE(NI, 0x1270), BOARD_PCI6032E },
1654 { PCI_VDEVICE(NI, 0x1330), BOARD_PCI6031E },
1655 { PCI_VDEVICE(NI, 0x1340), BOARD_PCI6033E },
1656 { PCI_VDEVICE(NI, 0x1350), BOARD_PCI6071E },
1657 { PCI_VDEVICE(NI, 0x14e0), BOARD_PCI6110 },
1658 { PCI_VDEVICE(NI, 0x14f0), BOARD_PCI6111 },
1659 { PCI_VDEVICE(NI, 0x1580), BOARD_PXI6031E },
1660 { PCI_VDEVICE(NI, 0x15b0), BOARD_PXI6071E },
1661 { PCI_VDEVICE(NI, 0x1880), BOARD_PCI6711 },
1662 { PCI_VDEVICE(NI, 0x1870), BOARD_PCI6713 },
1663 { PCI_VDEVICE(NI, 0x18b0), BOARD_PCI6052E },
1664 { PCI_VDEVICE(NI, 0x18c0), BOARD_PXI6052E },
1665 { PCI_VDEVICE(NI, 0x2410), BOARD_PCI6733 },
1666 { PCI_VDEVICE(NI, 0x2420), BOARD_PXI6733 },
1667 { PCI_VDEVICE(NI, 0x2430), BOARD_PCI6731 },
1668 { PCI_VDEVICE(NI, 0x2890), BOARD_PCI6036E },
1669 { PCI_VDEVICE(NI, 0x28c0), BOARD_PCI6014 },
1670 { PCI_VDEVICE(NI, 0x2a60), BOARD_PCI6023E },
1671 { PCI_VDEVICE(NI, 0x2a70), BOARD_PCI6024E },
1672 { PCI_VDEVICE(NI, 0x2a80), BOARD_PCI6025E },
1673 { PCI_VDEVICE(NI, 0x2ab0), BOARD_PXI6025E },
1674 { PCI_VDEVICE(NI, 0x2b80), BOARD_PXI6713 },
1675 { PCI_VDEVICE(NI, 0x2b90), BOARD_PXI6711 },
1676 { PCI_VDEVICE(NI, 0x2c80), BOARD_PCI6035E },
1677 { PCI_VDEVICE(NI, 0x2ca0), BOARD_PCI6034E },
1678 { PCI_VDEVICE(NI, 0x70aa), BOARD_PCI6229 },
1679 { PCI_VDEVICE(NI, 0x70ab), BOARD_PCI6259 },
1680 { PCI_VDEVICE(NI, 0x70ac), BOARD_PCI6289 },
1681 { PCI_VDEVICE(NI, 0x70af), BOARD_PCI6221 },
1682 { PCI_VDEVICE(NI, 0x70b0), BOARD_PCI6220 },
1683 { PCI_VDEVICE(NI, 0x70b4), BOARD_PCI6250 },
1684 { PCI_VDEVICE(NI, 0x70b6), BOARD_PCI6280 },
1685 { PCI_VDEVICE(NI, 0x70b7), BOARD_PCI6254 },
1686 { PCI_VDEVICE(NI, 0x70b8), BOARD_PCI6251 },
1687 { PCI_VDEVICE(NI, 0x70bc), BOARD_PCI6284 },
1688 { PCI_VDEVICE(NI, 0x70bd), BOARD_PCI6281 },
1689 { PCI_VDEVICE(NI, 0x70bf), BOARD_PXI6281 },
1690 { PCI_VDEVICE(NI, 0x70c0), BOARD_PCI6143 },
1691 { PCI_VDEVICE(NI, 0x70f2), BOARD_PCI6224 },
1692 { PCI_VDEVICE(NI, 0x70f3), BOARD_PXI6224 },
1693 { PCI_VDEVICE(NI, 0x710d), BOARD_PXI6143 },
1694 { PCI_VDEVICE(NI, 0x716c), BOARD_PCI6225 },
1695 { PCI_VDEVICE(NI, 0x716d), BOARD_PXI6225 },
1696 { PCI_VDEVICE(NI, 0x717f), BOARD_PCIE6259 },
1697 { PCI_VDEVICE(NI, 0x71bc), BOARD_PCI6221_37PIN },
1698 { PCI_VDEVICE(NI, 0x717d), BOARD_PCIE6251 },
1699 { PCI_VDEVICE(NI, 0x72e8), BOARD_PXIE6251 },
1702 MODULE_DEVICE_TABLE(pci, ni_pcimio_pci_table);
1704 static struct pci_driver ni_pcimio_pci_driver = {
1705 .name = "ni_pcimio",
1706 .id_table = ni_pcimio_pci_table,
1707 .probe = ni_pcimio_pci_probe,
1708 .remove = comedi_pci_auto_unconfig,
1710 module_comedi_pci_driver(ni_pcimio_driver, ni_pcimio_pci_driver);
1712 MODULE_AUTHOR("Comedi http://www.comedi.org");
1713 MODULE_DESCRIPTION("Comedi low-level driver");
1714 MODULE_LICENSE("GPL");