2 drivers/ni_tio_internal.h
3 Header file for NI general purpose counter support code (ni_tio.c and
6 COMEDI - Linux Control and Measurement Device Interface
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #ifndef _COMEDI_NI_TIO_INTERNAL_H
25 #define _COMEDI_NI_TIO_INTERNAL_H
29 static inline enum ni_gpct_register NITIO_Gi_Autoincrement_Reg(unsigned
32 switch (counter_index) {
34 return NITIO_G0_Autoincrement_Reg;
37 return NITIO_G1_Autoincrement_Reg;
40 return NITIO_G2_Autoincrement_Reg;
43 return NITIO_G3_Autoincrement_Reg;
52 static inline enum ni_gpct_register NITIO_Gi_Command_Reg(unsigned counter_index)
54 switch (counter_index) {
56 return NITIO_G0_Command_Reg;
59 return NITIO_G1_Command_Reg;
62 return NITIO_G2_Command_Reg;
65 return NITIO_G3_Command_Reg;
74 static inline enum ni_gpct_register NITIO_Gi_Counting_Mode_Reg(unsigned
77 switch (counter_index) {
79 return NITIO_G0_Counting_Mode_Reg;
82 return NITIO_G1_Counting_Mode_Reg;
85 return NITIO_G2_Counting_Mode_Reg;
88 return NITIO_G3_Counting_Mode_Reg;
97 static inline enum ni_gpct_register NITIO_Gi_Input_Select_Reg(unsigned
100 switch (counter_index) {
102 return NITIO_G0_Input_Select_Reg;
105 return NITIO_G1_Input_Select_Reg;
108 return NITIO_G2_Input_Select_Reg;
111 return NITIO_G3_Input_Select_Reg;
120 static inline enum ni_gpct_register NITIO_Gxx_Joint_Reset_Reg(unsigned
123 switch (counter_index) {
126 return NITIO_G01_Joint_Reset_Reg;
130 return NITIO_G23_Joint_Reset_Reg;
139 static inline enum ni_gpct_register NITIO_Gxx_Joint_Status1_Reg(unsigned
142 switch (counter_index) {
145 return NITIO_G01_Joint_Status1_Reg;
149 return NITIO_G23_Joint_Status1_Reg;
158 static inline enum ni_gpct_register NITIO_Gxx_Joint_Status2_Reg(unsigned
161 switch (counter_index) {
164 return NITIO_G01_Joint_Status2_Reg;
168 return NITIO_G23_Joint_Status2_Reg;
177 static inline enum ni_gpct_register NITIO_Gxx_Status_Reg(unsigned counter_index)
179 switch (counter_index) {
182 return NITIO_G01_Status_Reg;
186 return NITIO_G23_Status_Reg;
195 static inline enum ni_gpct_register NITIO_Gi_LoadA_Reg(unsigned counter_index)
197 switch (counter_index) {
199 return NITIO_G0_LoadA_Reg;
202 return NITIO_G1_LoadA_Reg;
205 return NITIO_G2_LoadA_Reg;
208 return NITIO_G3_LoadA_Reg;
217 static inline enum ni_gpct_register NITIO_Gi_LoadB_Reg(unsigned counter_index)
219 switch (counter_index) {
221 return NITIO_G0_LoadB_Reg;
224 return NITIO_G1_LoadB_Reg;
227 return NITIO_G2_LoadB_Reg;
230 return NITIO_G3_LoadB_Reg;
239 static inline enum ni_gpct_register NITIO_Gi_Mode_Reg(unsigned counter_index)
241 switch (counter_index) {
243 return NITIO_G0_Mode_Reg;
246 return NITIO_G1_Mode_Reg;
249 return NITIO_G2_Mode_Reg;
252 return NITIO_G3_Mode_Reg;
261 static inline enum ni_gpct_register NITIO_Gi_SW_Save_Reg(int counter_index)
263 switch (counter_index) {
265 return NITIO_G0_SW_Save_Reg;
268 return NITIO_G1_SW_Save_Reg;
271 return NITIO_G2_SW_Save_Reg;
274 return NITIO_G3_SW_Save_Reg;
283 static inline enum ni_gpct_register NITIO_Gi_Second_Gate_Reg(int counter_index)
285 switch (counter_index) {
287 return NITIO_G0_Second_Gate_Reg;
290 return NITIO_G1_Second_Gate_Reg;
293 return NITIO_G2_Second_Gate_Reg;
296 return NITIO_G3_Second_Gate_Reg;
305 static inline enum ni_gpct_register NITIO_Gi_DMA_Config_Reg(int counter_index)
307 switch (counter_index) {
309 return NITIO_G0_DMA_Config_Reg;
312 return NITIO_G1_DMA_Config_Reg;
315 return NITIO_G2_DMA_Config_Reg;
318 return NITIO_G3_DMA_Config_Reg;
327 static inline enum ni_gpct_register NITIO_Gi_DMA_Status_Reg(int counter_index)
329 switch (counter_index) {
331 return NITIO_G0_DMA_Status_Reg;
334 return NITIO_G1_DMA_Status_Reg;
337 return NITIO_G2_DMA_Status_Reg;
340 return NITIO_G3_DMA_Status_Reg;
349 static inline enum ni_gpct_register NITIO_Gi_ABZ_Reg(int counter_index)
351 switch (counter_index) {
353 return NITIO_G0_ABZ_Reg;
356 return NITIO_G1_ABZ_Reg;
365 static inline enum ni_gpct_register NITIO_Gi_Interrupt_Acknowledge_Reg(
368 switch (counter_index) {
370 return NITIO_G0_Interrupt_Acknowledge_Reg;
373 return NITIO_G1_Interrupt_Acknowledge_Reg;
376 return NITIO_G2_Interrupt_Acknowledge_Reg;
379 return NITIO_G3_Interrupt_Acknowledge_Reg;
388 static inline enum ni_gpct_register NITIO_Gi_Status_Reg(int counter_index)
390 switch (counter_index) {
392 return NITIO_G0_Status_Reg;
395 return NITIO_G1_Status_Reg;
398 return NITIO_G2_Status_Reg;
401 return NITIO_G3_Status_Reg;
410 static inline enum ni_gpct_register NITIO_Gi_Interrupt_Enable_Reg(
413 switch (counter_index) {
415 return NITIO_G0_Interrupt_Enable_Reg;
418 return NITIO_G1_Interrupt_Enable_Reg;
421 return NITIO_G2_Interrupt_Enable_Reg;
424 return NITIO_G3_Interrupt_Enable_Reg;
433 enum Gi_Auto_Increment_Reg_Bits {
434 Gi_Auto_Increment_Mask = 0xff
437 #define Gi_Up_Down_Shift 5
438 enum Gi_Command_Reg_Bits {
440 Gi_Save_Trace_Bit = 0x2,
442 Gi_Disarm_Bit = 0x10,
443 Gi_Up_Down_Mask = 0x3 << Gi_Up_Down_Shift,
444 Gi_Always_Down_Bits = 0x0 << Gi_Up_Down_Shift,
445 Gi_Always_Up_Bits = 0x1 << Gi_Up_Down_Shift,
446 Gi_Up_Down_Hardware_IO_Bits = 0x2 << Gi_Up_Down_Shift,
447 Gi_Up_Down_Hardware_Gate_Bits = 0x3 << Gi_Up_Down_Shift,
448 Gi_Write_Switch_Bit = 0x80,
449 Gi_Synchronize_Gate_Bit = 0x100,
450 Gi_Little_Big_Endian_Bit = 0x200,
451 Gi_Bank_Switch_Start_Bit = 0x400,
452 Gi_Bank_Switch_Mode_Bit = 0x800,
453 Gi_Bank_Switch_Enable_Bit = 0x1000,
454 Gi_Arm_Copy_Bit = 0x2000,
455 Gi_Save_Trace_Copy_Bit = 0x4000,
456 Gi_Disarm_Copy_Bit = 0x8000
459 #define Gi_Index_Phase_Bitshift 5
460 #define Gi_HW_Arm_Select_Shift 8
461 enum Gi_Counting_Mode_Reg_Bits {
462 Gi_Counting_Mode_Mask = 0x7,
463 Gi_Counting_Mode_Normal_Bits = 0x0,
464 Gi_Counting_Mode_QuadratureX1_Bits = 0x1,
465 Gi_Counting_Mode_QuadratureX2_Bits = 0x2,
466 Gi_Counting_Mode_QuadratureX4_Bits = 0x3,
467 Gi_Counting_Mode_Two_Pulse_Bits = 0x4,
468 Gi_Counting_Mode_Sync_Source_Bits = 0x6,
469 Gi_Index_Mode_Bit = 0x10,
470 Gi_Index_Phase_Mask = 0x3 << Gi_Index_Phase_Bitshift,
471 Gi_Index_Phase_LowA_LowB = 0x0 << Gi_Index_Phase_Bitshift,
472 Gi_Index_Phase_LowA_HighB = 0x1 << Gi_Index_Phase_Bitshift,
473 Gi_Index_Phase_HighA_LowB = 0x2 << Gi_Index_Phase_Bitshift,
474 Gi_Index_Phase_HighA_HighB = 0x3 << Gi_Index_Phase_Bitshift,
475 /* from m-series example code, not documented in 660x register level
477 Gi_HW_Arm_Enable_Bit = 0x80,
478 /* from m-series example code, not documented in 660x register level
480 Gi_660x_HW_Arm_Select_Mask = 0x7 << Gi_HW_Arm_Select_Shift,
481 Gi_660x_Prescale_X8_Bit = 0x1000,
482 Gi_M_Series_Prescale_X8_Bit = 0x2000,
483 Gi_M_Series_HW_Arm_Select_Mask = 0x1f << Gi_HW_Arm_Select_Shift,
484 /* must be set for clocks over 40MHz, which includes synchronous
485 * counting and quadrature modes */
486 Gi_660x_Alternate_Sync_Bit = 0x2000,
487 Gi_M_Series_Alternate_Sync_Bit = 0x4000,
488 /* from m-series example code, not documented in 660x register level
490 Gi_660x_Prescale_X2_Bit = 0x4000,
491 Gi_M_Series_Prescale_X2_Bit = 0x8000,
494 #define Gi_Source_Select_Shift 2
495 #define Gi_Gate_Select_Shift 7
496 enum Gi_Input_Select_Bits {
497 Gi_Read_Acknowledges_Irq = 0x1, /* not present on 660x */
498 Gi_Write_Acknowledges_Irq = 0x2, /* not present on 660x */
499 Gi_Source_Select_Mask = 0x7c,
500 Gi_Gate_Select_Mask = 0x1f << Gi_Gate_Select_Shift,
501 Gi_Gate_Select_Load_Source_Bit = 0x1000,
502 Gi_Or_Gate_Bit = 0x2000,
503 Gi_Output_Polarity_Bit = 0x4000, /* set to invert */
504 Gi_Source_Polarity_Bit = 0x8000 /* set to invert */
508 Gi_Gating_Mode_Mask = 0x3,
509 Gi_Gating_Disabled_Bits = 0x0,
510 Gi_Level_Gating_Bits = 0x1,
511 Gi_Rising_Edge_Gating_Bits = 0x2,
512 Gi_Falling_Edge_Gating_Bits = 0x3,
513 Gi_Gate_On_Both_Edges_Bit = 0x4, /* used in conjunction with
514 * rising edge gating mode */
515 Gi_Trigger_Mode_for_Edge_Gate_Mask = 0x18,
516 Gi_Edge_Gate_Starts_Stops_Bits = 0x0,
517 Gi_Edge_Gate_Stops_Starts_Bits = 0x8,
518 Gi_Edge_Gate_Starts_Bits = 0x10,
519 Gi_Edge_Gate_No_Starts_or_Stops_Bits = 0x18,
520 Gi_Stop_Mode_Mask = 0x60,
521 Gi_Stop_on_Gate_Bits = 0x00,
522 Gi_Stop_on_Gate_or_TC_Bits = 0x20,
523 Gi_Stop_on_Gate_or_Second_TC_Bits = 0x40,
524 Gi_Load_Source_Select_Bit = 0x80,
525 Gi_Output_Mode_Mask = 0x300,
526 Gi_Output_TC_Pulse_Bits = 0x100,
527 Gi_Output_TC_Toggle_Bits = 0x200,
528 Gi_Output_TC_or_Gate_Toggle_Bits = 0x300,
529 Gi_Counting_Once_Mask = 0xc00,
530 Gi_No_Hardware_Disarm_Bits = 0x000,
531 Gi_Disarm_at_TC_Bits = 0x400,
532 Gi_Disarm_at_Gate_Bits = 0x800,
533 Gi_Disarm_at_TC_or_Gate_Bits = 0xc00,
534 Gi_Loading_On_TC_Bit = 0x1000,
535 Gi_Gate_Polarity_Bit = 0x2000,
536 Gi_Loading_On_Gate_Bit = 0x4000,
537 Gi_Reload_Source_Switching_Bit = 0x8000
540 #define Gi_Second_Gate_Select_Shift 7
541 /*FIXME: m-series has a second gate subselect bit */
542 /*FIXME: m-series second gate sources are undocumented (by NI)*/
543 enum Gi_Second_Gate_Bits {
544 Gi_Second_Gate_Mode_Bit = 0x1,
545 Gi_Second_Gate_Select_Mask = 0x1f << Gi_Second_Gate_Select_Shift,
546 Gi_Second_Gate_Polarity_Bit = 0x2000,
547 Gi_Second_Gate_Subselect_Bit = 0x4000, /* m-series only */
548 Gi_Source_Subselect_Bit = 0x8000 /* m-series only */
550 static inline unsigned Gi_Second_Gate_Select_Bits(unsigned second_gate_select)
552 return (second_gate_select << Gi_Second_Gate_Select_Shift) &
553 Gi_Second_Gate_Select_Mask;
556 enum Gxx_Status_Bits {
559 G0_Counting_Bit = 0x4,
560 G1_Counting_Bit = 0x8,
561 G0_Next_Load_Source_Bit = 0x10,
562 G1_Next_Load_Source_Bit = 0x20,
563 G0_Stale_Data_Bit = 0x40,
564 G1_Stale_Data_Bit = 0x80,
565 G0_Armed_Bit = 0x100,
566 G1_Armed_Bit = 0x200,
567 G0_No_Load_Between_Gates_Bit = 0x400,
568 G1_No_Load_Between_Gates_Bit = 0x800,
569 G0_TC_Error_Bit = 0x1000,
570 G1_TC_Error_Bit = 0x2000,
571 G0_Gate_Error_Bit = 0x4000,
572 G1_Gate_Error_Bit = 0x8000
574 static inline enum Gxx_Status_Bits Gi_Counting_Bit(unsigned counter_index)
576 if (counter_index % 2)
577 return G1_Counting_Bit;
578 return G0_Counting_Bit;
581 static inline enum Gxx_Status_Bits Gi_Armed_Bit(unsigned counter_index)
583 if (counter_index % 2)
588 static inline enum Gxx_Status_Bits Gi_Next_Load_Source_Bit(unsigned
591 if (counter_index % 2)
592 return G1_Next_Load_Source_Bit;
593 return G0_Next_Load_Source_Bit;
596 static inline enum Gxx_Status_Bits Gi_Stale_Data_Bit(unsigned counter_index)
598 if (counter_index % 2)
599 return G1_Stale_Data_Bit;
600 return G0_Stale_Data_Bit;
603 static inline enum Gxx_Status_Bits Gi_TC_Error_Bit(unsigned counter_index)
605 if (counter_index % 2)
606 return G1_TC_Error_Bit;
607 return G0_TC_Error_Bit;
610 static inline enum Gxx_Status_Bits Gi_Gate_Error_Bit(unsigned counter_index)
612 if (counter_index % 2)
613 return G1_Gate_Error_Bit;
614 return G0_Gate_Error_Bit;
617 /* joint reset register bits */
618 static inline unsigned Gi_Reset_Bit(unsigned counter_index)
620 return 0x1 << (2 + (counter_index % 2));
623 enum Gxx_Joint_Status2_Bits {
626 G0_HW_Save_Bit = 0x1000,
627 G1_HW_Save_Bit = 0x2000,
628 G0_Permanent_Stale_Bit = 0x4000,
629 G1_Permanent_Stale_Bit = 0x8000
631 static inline enum Gxx_Joint_Status2_Bits Gi_Permanent_Stale_Bit(unsigned
634 if (counter_index % 2)
635 return G1_Permanent_Stale_Bit;
636 return G0_Permanent_Stale_Bit;
639 enum Gi_DMA_Config_Reg_Bits {
640 Gi_DMA_Enable_Bit = 0x1,
641 Gi_DMA_Write_Bit = 0x2,
645 enum Gi_DMA_Status_Reg_Bits {
646 Gi_DMA_Readbank_Bit = 0x2000,
647 Gi_DRQ_Error_Bit = 0x4000,
648 Gi_DRQ_Status_Bit = 0x8000
651 enum G02_Interrupt_Acknowledge_Bits {
652 G0_Gate_Error_Confirm_Bit = 0x20,
653 G0_TC_Error_Confirm_Bit = 0x40
655 enum G13_Interrupt_Acknowledge_Bits {
656 G1_Gate_Error_Confirm_Bit = 0x2,
657 G1_TC_Error_Confirm_Bit = 0x4
659 static inline unsigned Gi_Gate_Error_Confirm_Bit(unsigned counter_index)
661 if (counter_index % 2)
662 return G1_Gate_Error_Confirm_Bit;
663 return G0_Gate_Error_Confirm_Bit;
666 static inline unsigned Gi_TC_Error_Confirm_Bit(unsigned counter_index)
668 if (counter_index % 2)
669 return G1_TC_Error_Confirm_Bit;
670 return G0_TC_Error_Confirm_Bit;
673 /* bits that are the same in G0/G2 and G1/G3 interrupt acknowledge registers */
674 enum Gxx_Interrupt_Acknowledge_Bits {
675 Gi_TC_Interrupt_Ack_Bit = 0x4000,
676 Gi_Gate_Interrupt_Ack_Bit = 0x8000
679 enum Gi_Status_Bits {
680 Gi_Gate_Interrupt_Bit = 0x4,
682 Gi_Interrupt_Bit = 0x8000
685 enum G02_Interrupt_Enable_Bits {
686 G0_TC_Interrupt_Enable_Bit = 0x40,
687 G0_Gate_Interrupt_Enable_Bit = 0x100
689 enum G13_Interrupt_Enable_Bits {
690 G1_TC_Interrupt_Enable_Bit = 0x200,
691 G1_Gate_Interrupt_Enable_Bit = 0x400
693 static inline unsigned Gi_Gate_Interrupt_Enable_Bit(unsigned counter_index)
697 if (counter_index % 2)
698 bit = G1_Gate_Interrupt_Enable_Bit;
700 bit = G0_Gate_Interrupt_Enable_Bit;
704 static inline void write_register(struct ni_gpct *counter, unsigned bits,
705 enum ni_gpct_register reg)
707 BUG_ON(reg >= NITIO_Num_Registers);
708 counter->counter_dev->write_register(counter, bits, reg);
711 static inline unsigned read_register(struct ni_gpct *counter,
712 enum ni_gpct_register reg)
714 BUG_ON(reg >= NITIO_Num_Registers);
715 return counter->counter_dev->read_register(counter, reg);
718 static inline int ni_tio_counting_mode_registers_present(const struct
722 switch (counter_dev->variant) {
723 case ni_gpct_variant_e_series:
726 case ni_gpct_variant_m_series:
727 case ni_gpct_variant_660x:
737 static inline void ni_tio_set_bits_transient(struct ni_gpct *counter,
738 enum ni_gpct_register
739 register_index, unsigned bit_mask,
741 unsigned transient_bit_values)
743 struct ni_gpct_device *counter_dev = counter->counter_dev;
746 BUG_ON(register_index >= NITIO_Num_Registers);
747 spin_lock_irqsave(&counter_dev->regs_lock, flags);
748 counter_dev->regs[register_index] &= ~bit_mask;
749 counter_dev->regs[register_index] |= (bit_values & bit_mask);
750 write_register(counter,
751 counter_dev->regs[register_index] | transient_bit_values,
754 spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
757 /* ni_tio_set_bits( ) is for safely writing to registers whose bits may be
758 * twiddled in interrupt context, or whose software copy may be read in
761 static inline void ni_tio_set_bits(struct ni_gpct *counter,
762 enum ni_gpct_register register_index,
763 unsigned bit_mask, unsigned bit_values)
765 ni_tio_set_bits_transient(counter, register_index, bit_mask, bit_values,
769 /* ni_tio_get_soft_copy( ) is for safely reading the software copy of a register
770 whose bits might be modified in interrupt context, or whose software copy
771 might need to be read in interrupt context.
773 static inline unsigned ni_tio_get_soft_copy(const struct ni_gpct *counter,
774 enum ni_gpct_register
777 struct ni_gpct_device *counter_dev = counter->counter_dev;
781 BUG_ON(register_index >= NITIO_Num_Registers);
782 spin_lock_irqsave(&counter_dev->regs_lock, flags);
783 value = counter_dev->regs[register_index];
784 spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
788 int ni_tio_arm(struct ni_gpct *counter, int arm, unsigned start_trigger);
789 int ni_tio_set_gate_src(struct ni_gpct *counter, unsigned gate_index,
790 unsigned int gate_source);
792 #endif /* _COMEDI_NI_TIO_INTERNAL_H */