3 * Comedi driver for Winsystems PC-104 based 48/96-channel DIO boards.
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 2006 Calin A. Culianu <calin@ajvar.org>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
21 * Description: Winsystems PC-104 based 48/96-channel DIO boards.
22 * Devices: (Winsystems) PCM-UIO48A [pcmuio48]
23 * (Winsystems) PCM-UIO96A [pcmuio96]
24 * Author: Calin Culianu <calin@ajvar.org>
25 * Updated: Fri, 13 Jan 2006 12:01:01 -0500
28 * A driver for the relatively straightforward-to-program PCM-UIO48A and
29 * PCM-UIO96A boards from Winsystems. These boards use either one or two
30 * (in the 96-DIO version) WS16C48 ASIC HighDensity I/O Chips (HDIO). This
31 * chip is interesting in that each I/O line is individually programmable
32 * for INPUT or OUTPUT (thus comedi_dio_config can be done on a per-channel
33 * basis). Also, each chip supports edge-triggered interrupts for the first
34 * 24 I/O lines. Of course, since the 96-channel version of the board has
35 * two ASICs, it can detect polarity changes on up to 48 I/O lines. Since
36 * this is essentially an (non-PnP) ISA board, I/O Address and IRQ selection
37 * are done through jumpers on the board. You need to pass that information
38 * to this driver as the first and second comedi_config option, respectively.
39 * Note that the 48-channel version uses 16 bytes of IO memory and the 96-
40 * channel version uses 32-bytes (in case you are worried about conflicts).
41 * The 48-channel board is split into two 24-channel comedi subdevices. The
42 * 96-channel board is split into 4 24-channel DIO subdevices.
44 * Note that IRQ support has been added, but it is untested.
46 * To use edge-detection IRQ support, pass the IRQs of both ASICS (for the
47 * 96 channel version) or just 1 ASIC (for 48-channel version). Then, use
48 * comedi_commands with TRIG_NOW. Your callback will be called each time an
49 * edge is triggered, and the data values will be two sample_t's, which
50 * should be concatenated to form one 32-bit unsigned int. This value is
51 * the mask of channels that had edges detected from your channel list. Note
52 * that the bits positions in the mask correspond to positions in your
53 * chanlist when you specified the command and *not* channel id's!
55 * To set the polarity of the edge-detection interrupts pass a nonzero value
56 * for either CR_RANGE or CR_AREF for edge-up polarity, or a zero value for
57 * both CR_RANGE and CR_AREF if you want edge-down polarity.
59 * In the 48-channel version:
61 * On subdev 0, the first 24 channels channels are edge-detect channels.
63 * In the 96-channel board you have the following channels that can do edge
66 * subdev 0, channels 0-24 (first 24 channels of 1st ASIC)
67 * subdev 2, channels 0-24 (first 24 channels of 2nd ASIC)
69 * Configuration Options:
70 * [0] - I/O port base address
71 * [1] - IRQ (for first ASIC, or first 24 channels)
72 * [2] - IRQ (for second ASIC, pcmuio96 only - IRQ for chans 48-72
73 * can be the same as first irq!)
76 #include <linux/interrupt.h>
77 #include <linux/slab.h>
79 #include "../comedidev.h"
81 #include "comedi_fc.h"
83 #define CHANS_PER_PORT 8
84 #define PORTS_PER_ASIC 6
85 #define INTR_PORTS_PER_ASIC 3
86 /* number of channels per comedi subdevice */
87 #define MAX_CHANS_PER_SUBDEV 24
88 #define PORTS_PER_SUBDEV (MAX_CHANS_PER_SUBDEV / CHANS_PER_PORT)
89 #define CHANS_PER_ASIC (CHANS_PER_PORT * PORTS_PER_ASIC)
90 #define INTR_CHANS_PER_ASIC 24
91 #define INTR_PORTS_PER_SUBDEV (INTR_CHANS_PER_ASIC / CHANS_PER_PORT)
92 #define MAX_DIO_CHANS (PORTS_PER_ASIC * 2 * CHANS_PER_PORT)
93 #define MAX_ASICS (MAX_DIO_CHANS / CHANS_PER_ASIC)
96 #define ASIC_IOSIZE 0x10
97 #define PCMUIO48_IOSIZE ASIC_IOSIZE
98 #define PCMUIO96_IOSIZE (ASIC_IOSIZE * 2)
101 * Some offsets - these are all in the 16byte IO memory offset from
102 * the base address. Note that there is a paging scheme to swap out
103 * offsets 0x8-0xA using the PAGELOCK register. See the table below.
105 * Register(s) Pages R/W? Description
106 * --------------------------------------------------------------------------
107 * REG_PORTx All R/W Read/Write/Configure IO
108 * REG_INT_PENDING All ReadOnly Which INT_IDx has int.
109 * REG_PAGELOCK All WriteOnly Select a page
110 * REG_POLx Pg. 1 only WriteOnly Select edge-detection polarity
111 * REG_ENABx Pg. 2 only WriteOnly Enable/Disable edge-detect int.
112 * REG_INT_IDx Pg. 3 only R/W See which ports/bits have ints.
114 #define REG_PORT0 0x0
115 #define REG_PORT1 0x1
116 #define REG_PORT2 0x2
117 #define REG_PORT3 0x3
118 #define REG_PORT4 0x4
119 #define REG_PORT5 0x5
120 #define REG_INT_PENDING 0x6
122 * page selector register
123 * Upper 2 bits select a page and bits 0-5 are used to
124 * 'lock down' a particular port above to make it readonly.
126 #define REG_PAGELOCK 0x7
130 #define REG_ENAB0 0x8
131 #define REG_ENAB1 0x9
132 #define REG_ENAB2 0xa
133 #define REG_INT_ID0 0x8
134 #define REG_INT_ID1 0x9
135 #define REG_INT_ID2 0xa
137 #define NUM_PAGED_REGS 3
139 #define FIRST_PAGED_REG 0x8
140 #define REG_PAGE_BITOFFSET 6
141 #define REG_LOCK_BITOFFSET 0
142 #define REG_PAGE_MASK (~((0x1 << REG_PAGE_BITOFFSET) - 1))
143 #define REG_LOCK_MASK ~(REG_PAGE_MASK)
146 #define PAGE_INT_ID 3
148 struct pcmuio_board {
151 const int num_channels_per_port;
155 static const struct pcmuio_board pcmuio_boards[] = {
167 struct pcmuio_subdev_private {
168 /* mapping of halfwords (bytes) in port/chanarray to iobase */
169 unsigned long iobases[PORTS_PER_SUBDEV];
171 /* The below is only used for intr subdevices */
173 /* if non-negative, this subdev has an interrupt asic */
175 /* if nonnegative, the first channel id for interrupts */
178 * the number of asic channels in this
179 * subdev that have interrutps
183 * if nonnegative, the first channel id with
184 * respect to the asic that has interrupts
188 * subdev-relative channel mask for channels
189 * we are interested in
199 struct pcmuio_private {
201 /* current page and lock */
202 unsigned char pagelock;
203 /* shadow of POLx registers */
204 unsigned char pol[NUM_PAGED_REGS];
205 /* shadow of ENABx registers */
206 unsigned char enab[NUM_PAGED_REGS];
208 unsigned long iobase;
212 struct pcmuio_subdev_private *sprivs;
215 static int pcmuio_dio_insn_bits(struct comedi_device *dev,
216 struct comedi_subdevice *s,
217 struct comedi_insn *insn, unsigned int *data)
219 struct pcmuio_subdev_private *subpriv = s->private;
223 reading a 0 means this channel was high
224 writine a 0 sets the channel high
225 reading a 1 means this channel was low
226 writing a 1 means set this channel low
228 Therefore everything is always inverted. */
230 /* The insn data is a mask in data[0] and the new data
231 * in data[1], each channel cooresponding to a bit. */
235 for (byte_no = 0; byte_no < s->n_chan / CHANS_PER_PORT; ++byte_no) {
236 /* address of 8-bit port */
237 unsigned long ioaddr = subpriv->iobases[byte_no],
238 /* bit offset of port in 32-bit doubleword */
239 offset = byte_no * 8;
240 /* this 8-bit port's data */
241 unsigned char byte = 0,
242 /* The write mask for this port (if any) */
243 write_mask_byte = (data[0] >> offset) & 0xff,
244 /* The data byte for this port */
245 data_byte = (data[1] >> offset) & 0xff;
247 byte = inb(ioaddr); /* read all 8-bits for this port */
249 if (write_mask_byte) {
250 byte &= ~write_mask_byte;
251 byte |= ~data_byte & write_mask_byte;
254 /* save the digital input lines for this byte.. */
255 s->state |= ((unsigned int)byte) << offset;
258 /* now return the DIO lines to data[1] - note they came inverted! */
264 static int pcmuio_dio_insn_config(struct comedi_device *dev,
265 struct comedi_subdevice *s,
266 struct comedi_insn *insn, unsigned int *data)
268 struct pcmuio_subdev_private *subpriv = s->private;
269 int chan = CR_CHAN(insn->chanspec), byte_no = chan / 8, bit_no =
271 unsigned long ioaddr;
274 /* Compute ioaddr for this channel */
275 ioaddr = subpriv->iobases[byte_no];
278 writing a 0 an IO channel's bit sets the channel to INPUT
279 and pulls the line high as well
281 writing a 1 to an IO channel's bit pulls the line low
283 All channels are implicitly always in OUTPUT mode -- but when
284 they are high they can be considered to be in INPUT mode..
286 Thus, we only force channels low if the config request was INPUT,
287 otherwise we do nothing to the hardware. */
290 case INSN_CONFIG_DIO_OUTPUT:
291 /* save to io_bits -- don't actually do anything since
292 all input channels are also output channels... */
293 s->io_bits |= 1 << chan;
295 case INSN_CONFIG_DIO_INPUT:
296 /* write a 0 to the actual register representing the channel
297 to set it to 'input'. 0 means "float high". */
299 byte &= ~(1 << bit_no);
300 /**< set input channel to '0' */
304 * This is the only time we actually affect the hardware
305 * as all channels are implicitly output -- but input
306 * channels are set to float-high.
310 /* save to io_bits */
311 s->io_bits &= ~(1 << chan);
314 case INSN_CONFIG_DIO_QUERY:
315 /* retrieve from shadow register */
317 (s->io_bits & (1 << chan)) ? COMEDI_OUTPUT : COMEDI_INPUT;
329 static void switch_page(struct comedi_device *dev, int asic, int page)
331 const struct pcmuio_board *board = comedi_board(dev);
332 struct pcmuio_private *devpriv = dev->private;
334 if (asic < 0 || asic >= board->num_asics)
335 return; /* paranoia */
336 if (page < 0 || page >= NUM_PAGES)
337 return; /* more paranoia */
339 devpriv->asics[asic].pagelock &= ~REG_PAGE_MASK;
340 devpriv->asics[asic].pagelock |= page << REG_PAGE_BITOFFSET;
342 /* now write out the shadow register */
343 outb(devpriv->asics[asic].pagelock,
344 dev->iobase + ASIC_IOSIZE * asic + REG_PAGELOCK);
347 static void init_asics(struct comedi_device *dev)
349 ASIC chip to defaults */
350 const struct pcmuio_board *board = comedi_board(dev);
353 for (asic = 0; asic < board->num_asics; ++asic) {
355 unsigned long baseaddr = dev->iobase + asic * ASIC_IOSIZE;
357 switch_page(dev, asic, 0); /* switch back to page 0 */
359 /* first, clear all the DIO port bits */
360 for (port = 0; port < PORTS_PER_ASIC; ++port)
361 outb(0, baseaddr + REG_PORT0 + port);
363 /* Next, clear all the paged registers for each page */
364 for (page = 1; page < NUM_PAGES; ++page) {
366 /* now clear all the paged registers */
367 switch_page(dev, asic, page);
368 for (reg = FIRST_PAGED_REG;
369 reg < FIRST_PAGED_REG + NUM_PAGED_REGS; ++reg)
370 outb(0, baseaddr + reg);
373 /* DEBUG set rising edge interrupts on port0 of both asics */
374 /*switch_page(dev, asic, PAGE_POL);
375 outb(0xff, baseaddr + REG_POL0);
376 switch_page(dev, asic, PAGE_ENAB);
377 outb(0xff, baseaddr + REG_ENAB0); */
380 /* switch back to default page 0 */
381 switch_page(dev, asic, 0);
386 static void lock_port(struct comedi_device *dev, int asic, int port)
388 const struct pcmuio_board *board = comedi_board(dev);
389 struct pcmuio_private *devpriv = dev->private;
391 if (asic < 0 || asic >= board->num_asics)
392 return; /* paranoia */
393 if (port < 0 || port >= PORTS_PER_ASIC)
394 return; /* more paranoia */
396 devpriv->asics[asic].pagelock |= 0x1 << port;
397 /* now write out the shadow register */
398 outb(devpriv->asics[asic].pagelock,
399 dev->iobase + ASIC_IOSIZE * asic + REG_PAGELOCK);
402 static void unlock_port(struct comedi_device *dev, int asic, int port)
404 const struct pcmuio_board *board = comedi_board(dev);
405 struct pcmuio_private *devpriv = dev->private;
407 if (asic < 0 || asic >= board->num_asics)
408 return; /* paranoia */
409 if (port < 0 || port >= PORTS_PER_ASIC)
410 return; /* more paranoia */
411 devpriv->asics[asic].pagelock &= ~(0x1 << port) | REG_LOCK_MASK;
412 /* now write out the shadow register */
413 outb(devpriv->asics[asic].pagelock,
414 dev->iobase + ASIC_IOSIZE * asic + REG_PAGELOCK);
418 static void pcmuio_stop_intr(struct comedi_device *dev,
419 struct comedi_subdevice *s)
421 struct pcmuio_private *devpriv = dev->private;
422 struct pcmuio_subdev_private *subpriv = s->private;
423 int nports, firstport, asic, port;
425 asic = subpriv->intr.asic;
427 return; /* not an interrupt subdev */
429 subpriv->intr.enabled_mask = 0;
430 subpriv->intr.active = 0;
431 s->async->inttrig = NULL;
432 nports = subpriv->intr.num_asic_chans / CHANS_PER_PORT;
433 firstport = subpriv->intr.asic_chan / CHANS_PER_PORT;
434 switch_page(dev, asic, PAGE_ENAB);
435 for (port = firstport; port < firstport + nports; ++port) {
436 /* disable all intrs for this subdev.. */
437 outb(0, devpriv->asics[asic].iobase + REG_ENAB0 + port);
441 static void pcmuio_handle_intr_subdev(struct comedi_device *dev,
442 struct comedi_subdevice *s,
445 struct pcmuio_subdev_private *subpriv = s->private;
446 unsigned int len = s->async->cmd.chanlist_len;
447 unsigned oldevents = s->async->events;
448 unsigned int val = 0;
453 spin_lock_irqsave(&subpriv->intr.spinlock, flags);
455 if (!subpriv->intr.active)
458 mytrig = triggered >> subpriv->intr.asic_chan;
459 mytrig &= ((0x1 << subpriv->intr.num_asic_chans) - 1);
460 mytrig <<= subpriv->intr.first_chan;
462 if (!(mytrig & subpriv->intr.enabled_mask))
465 for (i = 0; i < len; i++) {
466 unsigned int chan = CR_CHAN(s->async->cmd.chanlist[i]);
467 if (mytrig & (1U << chan))
471 /* Write the scan to the buffer. */
472 if (comedi_buf_put(s->async, ((short *)&val)[0]) &&
473 comedi_buf_put(s->async, ((short *)&val)[1])) {
474 s->async->events |= (COMEDI_CB_BLOCK | COMEDI_CB_EOS);
476 /* Overflow! Stop acquisition!! */
477 /* TODO: STOP_ACQUISITION_CALL_HERE!! */
478 pcmuio_stop_intr(dev, s);
481 /* Check for end of acquisition. */
482 if (!subpriv->intr.continuous) {
483 /* stop_src == TRIG_COUNT */
484 if (subpriv->intr.stop_count > 0) {
485 subpriv->intr.stop_count--;
486 if (subpriv->intr.stop_count == 0) {
487 s->async->events |= COMEDI_CB_EOA;
488 /* TODO: STOP_ACQUISITION_CALL_HERE!! */
489 pcmuio_stop_intr(dev, s);
495 spin_unlock_irqrestore(&subpriv->intr.spinlock, flags);
497 if (oldevents != s->async->events)
498 comedi_event(dev, s);
501 static int pcmuio_handle_asic_interrupt(struct comedi_device *dev, int asic)
503 struct pcmuio_private *devpriv = dev->private;
504 struct pcmuio_subdev_private *subpriv;
505 unsigned long iobase = devpriv->asics[asic].iobase;
506 unsigned triggered = 0;
509 unsigned char int_pend;
512 spin_lock_irqsave(&devpriv->asics[asic].spinlock, flags);
514 int_pend = inb(iobase + REG_INT_PENDING) & 0x07;
516 for (i = 0; i < INTR_PORTS_PER_ASIC; ++i) {
517 if (int_pend & (0x1 << i)) {
520 switch_page(dev, asic, PAGE_INT_ID);
521 val = inb(iobase + REG_INT_ID0 + i);
523 /* clear pending interrupt */
524 outb(0, iobase + REG_INT_ID0 + i);
526 triggered |= (val << (i * 8));
533 spin_unlock_irqrestore(&devpriv->asics[asic].spinlock, flags);
536 struct comedi_subdevice *s;
537 /* TODO here: dispatch io lines to subdevs with commands.. */
538 for (i = 0; i < dev->n_subdevices; i++) {
539 s = &dev->subdevices[i];
540 subpriv = s->private;
541 if (subpriv->intr.asic == asic) {
543 * This is an interrupt subdev, and it
546 pcmuio_handle_intr_subdev(dev, s,
554 static irqreturn_t interrupt_pcmuio(int irq, void *d)
556 struct comedi_device *dev = d;
557 struct pcmuio_private *devpriv = dev->private;
561 for (asic = 0; asic < MAX_ASICS; ++asic) {
562 if (irq == devpriv->asics[asic].irq) {
563 /* it is an interrupt for ASIC #asic */
564 if (pcmuio_handle_asic_interrupt(dev, asic))
569 return IRQ_NONE; /* interrupt from other source */
573 static int pcmuio_start_intr(struct comedi_device *dev,
574 struct comedi_subdevice *s)
576 struct pcmuio_private *devpriv = dev->private;
577 struct pcmuio_subdev_private *subpriv = s->private;
579 if (!subpriv->intr.continuous && subpriv->intr.stop_count == 0) {
580 /* An empty acquisition! */
581 s->async->events |= COMEDI_CB_EOA;
582 subpriv->intr.active = 0;
585 unsigned bits = 0, pol_bits = 0, n;
586 int nports, firstport, asic, port;
587 struct comedi_cmd *cmd = &s->async->cmd;
589 asic = subpriv->intr.asic;
591 return 1; /* not an interrupt
593 subpriv->intr.enabled_mask = 0;
594 subpriv->intr.active = 1;
595 nports = subpriv->intr.num_asic_chans / CHANS_PER_PORT;
596 firstport = subpriv->intr.asic_chan / CHANS_PER_PORT;
598 for (n = 0; n < cmd->chanlist_len; n++) {
599 bits |= (1U << CR_CHAN(cmd->chanlist[n]));
600 pol_bits |= (CR_AREF(cmd->chanlist[n])
602 chanlist[n]) ? 1U : 0U)
603 << CR_CHAN(cmd->chanlist[n]);
606 bits &= ((0x1 << subpriv->intr.num_asic_chans) -
607 1) << subpriv->intr.first_chan;
608 subpriv->intr.enabled_mask = bits;
610 switch_page(dev, asic, PAGE_ENAB);
611 for (port = firstport; port < firstport + nports; ++port) {
613 bits >> (subpriv->intr.first_chan + (port -
616 pol_bits >> (subpriv->intr.first_chan +
617 (port - firstport) * 8) & 0xff;
618 /* set enab intrs for this subdev.. */
620 devpriv->asics[asic].iobase + REG_ENAB0 + port);
621 switch_page(dev, asic, PAGE_POL);
623 devpriv->asics[asic].iobase + REG_ENAB0 + port);
629 static int pcmuio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
631 struct pcmuio_subdev_private *subpriv = s->private;
634 spin_lock_irqsave(&subpriv->intr.spinlock, flags);
635 if (subpriv->intr.active)
636 pcmuio_stop_intr(dev, s);
637 spin_unlock_irqrestore(&subpriv->intr.spinlock, flags);
643 * Internal trigger function to start acquisition for an 'INTERRUPT' subdevice.
646 pcmuio_inttrig_start_intr(struct comedi_device *dev, struct comedi_subdevice *s,
647 unsigned int trignum)
649 struct pcmuio_subdev_private *subpriv = s->private;
656 spin_lock_irqsave(&subpriv->intr.spinlock, flags);
657 s->async->inttrig = NULL;
658 if (subpriv->intr.active)
659 event = pcmuio_start_intr(dev, s);
661 spin_unlock_irqrestore(&subpriv->intr.spinlock, flags);
664 comedi_event(dev, s);
670 * 'do_cmd' function for an 'INTERRUPT' subdevice.
672 static int pcmuio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
674 struct pcmuio_subdev_private *subpriv = s->private;
675 struct comedi_cmd *cmd = &s->async->cmd;
679 spin_lock_irqsave(&subpriv->intr.spinlock, flags);
680 subpriv->intr.active = 1;
682 /* Set up end of acquisition. */
683 switch (cmd->stop_src) {
685 subpriv->intr.continuous = 0;
686 subpriv->intr.stop_count = cmd->stop_arg;
690 subpriv->intr.continuous = 1;
691 subpriv->intr.stop_count = 0;
695 /* Set up start of acquisition. */
696 switch (cmd->start_src) {
698 s->async->inttrig = pcmuio_inttrig_start_intr;
702 event = pcmuio_start_intr(dev, s);
705 spin_unlock_irqrestore(&subpriv->intr.spinlock, flags);
708 comedi_event(dev, s);
713 static int pcmuio_cmdtest(struct comedi_device *dev,
714 struct comedi_subdevice *s,
715 struct comedi_cmd *cmd)
719 /* Step 1 : check if triggers are trivially valid */
721 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_INT);
722 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
723 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
724 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
725 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
730 /* Step 2a : make sure trigger sources are unique */
732 err |= cfc_check_trigger_is_unique(cmd->start_src);
733 err |= cfc_check_trigger_is_unique(cmd->stop_src);
735 /* Step 2b : and mutually compatible */
740 /* Step 3: check if arguments are trivially valid */
742 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
743 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
744 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
745 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
747 switch (cmd->stop_src) {
749 /* any count allowed */
752 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
761 /* step 4: fix up any arguments */
763 /* if (err) return 4; */
768 static int pcmuio_attach(struct comedi_device *dev, struct comedi_devconfig *it)
770 const struct pcmuio_board *board = comedi_board(dev);
771 struct comedi_subdevice *s;
772 struct pcmuio_private *devpriv;
773 struct pcmuio_subdev_private *subpriv;
774 int sdev_no, chans_left, n_subdevs, port, asic, thisasic_chanct = 0;
775 unsigned int irq[MAX_ASICS];
778 irq[0] = it->options[1];
779 irq[1] = it->options[2];
781 ret = comedi_request_region(dev, it->options[0],
782 board->num_asics * ASIC_IOSIZE);
786 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
789 dev->private = devpriv;
791 for (asic = 0; asic < MAX_ASICS; ++asic) {
792 devpriv->asics[asic].num = asic;
793 devpriv->asics[asic].iobase = dev->iobase + asic * ASIC_IOSIZE;
794 spin_lock_init(&devpriv->asics[asic].spinlock);
797 chans_left = CHANS_PER_ASIC * board->num_asics;
798 n_subdevs = (chans_left / MAX_CHANS_PER_SUBDEV) +
799 (!!(chans_left % MAX_CHANS_PER_SUBDEV));
800 devpriv->sprivs = kcalloc(n_subdevs,
801 sizeof(struct pcmuio_subdev_private),
803 if (!devpriv->sprivs)
806 ret = comedi_alloc_subdevices(dev, n_subdevs);
812 for (sdev_no = 0; sdev_no < (int)dev->n_subdevices; ++sdev_no) {
815 s = &dev->subdevices[sdev_no];
816 subpriv = &devpriv->sprivs[sdev_no];
817 s->private = subpriv;
819 s->range_table = &range_digital;
820 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
821 s->type = COMEDI_SUBD_DIO;
822 s->insn_bits = pcmuio_dio_insn_bits;
823 s->insn_config = pcmuio_dio_insn_config;
824 s->n_chan = min(chans_left, MAX_CHANS_PER_SUBDEV);
825 subpriv->intr.asic = -1;
826 subpriv->intr.first_chan = -1;
827 subpriv->intr.asic_chan = -1;
828 subpriv->intr.num_asic_chans = -1;
829 subpriv->intr.active = 0;
832 /* save the ioport address for each 'port' of 8 channels in the
834 for (byte_no = 0; byte_no < PORTS_PER_SUBDEV;
836 if (port >= PORTS_PER_ASIC) {
841 subpriv->iobases[byte_no] =
842 devpriv->asics[asic].iobase + port;
844 if (thisasic_chanct <
845 CHANS_PER_PORT * INTR_PORTS_PER_ASIC
846 && subpriv->intr.asic < 0) {
847 /* setup the interrupt subdevice */
848 subpriv->intr.asic = asic;
849 subpriv->intr.active = 0;
850 subpriv->intr.stop_count = 0;
851 subpriv->intr.first_chan = byte_no * 8;
852 subpriv->intr.asic_chan = thisasic_chanct;
853 subpriv->intr.num_asic_chans =
854 s->n_chan - subpriv->intr.first_chan;
855 dev->read_subdev = s;
856 s->subdev_flags |= SDF_CMD_READ;
857 s->cancel = pcmuio_cancel;
858 s->do_cmd = pcmuio_cmd;
859 s->do_cmdtest = pcmuio_cmdtest;
860 s->len_chanlist = subpriv->intr.num_asic_chans;
862 thisasic_chanct += CHANS_PER_PORT;
864 spin_lock_init(&subpriv->intr.spinlock);
866 chans_left -= s->n_chan;
869 /* reset to our first asic, to do intr subdevs */
876 init_asics(dev); /* clear out all the registers, basically */
878 for (asic = 0; irq[0] && asic < MAX_ASICS; ++asic) {
880 && request_irq(irq[asic], interrupt_pcmuio,
881 IRQF_SHARED, board->name, dev)) {
883 /* unroll the allocated irqs.. */
884 for (i = asic - 1; i >= 0; --i) {
885 free_irq(irq[i], dev);
886 devpriv->asics[i].irq = irq[i] = 0;
890 devpriv->asics[asic].irq = irq[asic];
894 dev_dbg(dev->class_dev, "irq: %u\n", irq[0]);
895 if (irq[1] && board->num_asics == 2)
896 dev_dbg(dev->class_dev, "second ASIC irq: %u\n",
899 dev_dbg(dev->class_dev, "(IRQ mode disabled)\n");
906 static void pcmuio_detach(struct comedi_device *dev)
908 struct pcmuio_private *devpriv = dev->private;
911 for (i = 0; i < MAX_ASICS; ++i) {
912 if (devpriv->asics[i].irq)
913 free_irq(devpriv->asics[i].irq, dev);
915 if (devpriv && devpriv->sprivs)
916 kfree(devpriv->sprivs);
917 comedi_legacy_detach(dev);
920 static struct comedi_driver pcmuio_driver = {
921 .driver_name = "pcmuio",
922 .module = THIS_MODULE,
923 .attach = pcmuio_attach,
924 .detach = pcmuio_detach,
925 .board_name = &pcmuio_boards[0].name,
926 .offset = sizeof(struct pcmuio_board),
927 .num_names = ARRAY_SIZE(pcmuio_boards),
929 module_comedi_driver(pcmuio_driver);
931 MODULE_AUTHOR("Comedi http://www.comedi.org");
932 MODULE_DESCRIPTION("Comedi low-level driver");
933 MODULE_LICENSE("GPL");