3 * Comedi driver for Winsystems PC-104 based 48/96-channel DIO boards.
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 2006 Calin A. Culianu <calin@ajvar.org>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
21 * Description: Winsystems PC-104 based 48/96-channel DIO boards.
22 * Devices: (Winsystems) PCM-UIO48A [pcmuio48]
23 * (Winsystems) PCM-UIO96A [pcmuio96]
24 * Author: Calin Culianu <calin@ajvar.org>
25 * Updated: Fri, 13 Jan 2006 12:01:01 -0500
28 * A driver for the relatively straightforward-to-program PCM-UIO48A and
29 * PCM-UIO96A boards from Winsystems. These boards use either one or two
30 * (in the 96-DIO version) WS16C48 ASIC HighDensity I/O Chips (HDIO). This
31 * chip is interesting in that each I/O line is individually programmable
32 * for INPUT or OUTPUT (thus comedi_dio_config can be done on a per-channel
33 * basis). Also, each chip supports edge-triggered interrupts for the first
34 * 24 I/O lines. Of course, since the 96-channel version of the board has
35 * two ASICs, it can detect polarity changes on up to 48 I/O lines. Since
36 * this is essentially an (non-PnP) ISA board, I/O Address and IRQ selection
37 * are done through jumpers on the board. You need to pass that information
38 * to this driver as the first and second comedi_config option, respectively.
39 * Note that the 48-channel version uses 16 bytes of IO memory and the 96-
40 * channel version uses 32-bytes (in case you are worried about conflicts).
41 * The 48-channel board is split into two 24-channel comedi subdevices. The
42 * 96-channel board is split into 4 24-channel DIO subdevices.
44 * Note that IRQ support has been added, but it is untested.
46 * To use edge-detection IRQ support, pass the IRQs of both ASICS (for the
47 * 96 channel version) or just 1 ASIC (for 48-channel version). Then, use
48 * comedi_commands with TRIG_NOW. Your callback will be called each time an
49 * edge is triggered, and the data values will be two sample_t's, which
50 * should be concatenated to form one 32-bit unsigned int. This value is
51 * the mask of channels that had edges detected from your channel list. Note
52 * that the bits positions in the mask correspond to positions in your
53 * chanlist when you specified the command and *not* channel id's!
55 * To set the polarity of the edge-detection interrupts pass a nonzero value
56 * for either CR_RANGE or CR_AREF for edge-up polarity, or a zero value for
57 * both CR_RANGE and CR_AREF if you want edge-down polarity.
59 * In the 48-channel version:
61 * On subdev 0, the first 24 channels channels are edge-detect channels.
63 * In the 96-channel board you have the following channels that can do edge
66 * subdev 0, channels 0-24 (first 24 channels of 1st ASIC)
67 * subdev 2, channels 0-24 (first 24 channels of 2nd ASIC)
69 * Configuration Options:
70 * [0] - I/O port base address
71 * [1] - IRQ (for first ASIC, or first 24 channels)
72 * [2] - IRQ (for second ASIC, pcmuio96 only - IRQ for chans 48-72
73 * can be the same as first irq!)
76 #include <linux/interrupt.h>
77 #include <linux/slab.h>
79 #include "../comedidev.h"
81 #include "comedi_fc.h"
86 * Offset Page 0 Page 1 Page 2 Page 3
87 * ------ ----------- ----------- ----------- -----------
88 * 0x00 Port 0 I/O Port 0 I/O Port 0 I/O Port 0 I/O
89 * 0x01 Port 1 I/O Port 1 I/O Port 1 I/O Port 1 I/O
90 * 0x02 Port 2 I/O Port 2 I/O Port 2 I/O Port 2 I/O
91 * 0x03 Port 3 I/O Port 3 I/O Port 3 I/O Port 3 I/O
92 * 0x04 Port 4 I/O Port 4 I/O Port 4 I/O Port 4 I/O
93 * 0x05 Port 5 I/O Port 5 I/O Port 5 I/O Port 5 I/O
94 * 0x06 INT_PENDING INT_PENDING INT_PENDING INT_PENDING
95 * 0x07 Page/Lock Page/Lock Page/Lock Page/Lock
96 * 0x08 N/A POL_0 ENAB_0 INT_ID0
97 * 0x09 N/A POL_1 ENAB_1 INT_ID1
98 * 0x0a N/A POL_2 ENAB_2 INT_ID2
100 #define PCMUIO_PORT_REG(x) (0x00 + (x))
101 #define PCMUIO_INT_PENDING_REG 0x06
102 #define PCMUIO_PAGE_LOCK_REG 0x07
103 #define PCMUIO_LOCK_PORT(x) ((1 << (x)) & 0x3f)
104 #define PCMUIO_PAGE(x) (((x) & 0x3) << 6)
105 #define PCMUIO_PAGE_MASK PCMUIO_PAGE(3)
106 #define PCMUIO_PAGE_POL 1
107 #define PCMUIO_PAGE_ENAB 2
108 #define PCMUIO_PAGE_INT_ID 3
109 #define PCMUIO_PAGE_REG(x) (0x08 + (x))
111 #define CHANS_PER_PORT 8
112 #define PORTS_PER_ASIC 6
113 #define INTR_PORTS_PER_ASIC 3
114 /* number of channels per comedi subdevice */
115 #define MAX_CHANS_PER_SUBDEV 24
116 #define PORTS_PER_SUBDEV (MAX_CHANS_PER_SUBDEV / CHANS_PER_PORT)
117 #define CHANS_PER_ASIC (CHANS_PER_PORT * PORTS_PER_ASIC)
118 #define INTR_CHANS_PER_ASIC 24
119 #define INTR_PORTS_PER_SUBDEV (INTR_CHANS_PER_ASIC / CHANS_PER_PORT)
120 #define MAX_DIO_CHANS (PORTS_PER_ASIC * 2 * CHANS_PER_PORT)
121 #define MAX_ASICS (MAX_DIO_CHANS / CHANS_PER_ASIC)
123 /* IO Memory sizes */
124 #define ASIC_IOSIZE 0x10
125 #define PCMUIO48_IOSIZE ASIC_IOSIZE
126 #define PCMUIO96_IOSIZE (ASIC_IOSIZE * 2)
128 #define NUM_PAGED_REGS 3
130 struct pcmuio_board {
133 const int num_channels_per_port;
137 static const struct pcmuio_board pcmuio_boards[] = {
149 struct pcmuio_subdev_private {
150 /* mapping of halfwords (bytes) in port/chanarray to iobase */
151 unsigned long iobases[PORTS_PER_SUBDEV];
153 /* The below is only used for intr subdevices */
155 /* if non-negative, this subdev has an interrupt asic */
157 /* if nonnegative, the first channel id for interrupts */
160 * the number of asic channels in this
161 * subdev that have interrutps
165 * if nonnegative, the first channel id with
166 * respect to the asic that has interrupts
170 * subdev-relative channel mask for channels
171 * we are interested in
181 struct pcmuio_private {
183 /* shadow of POLx registers */
184 unsigned char pol[NUM_PAGED_REGS];
185 /* shadow of ENABx registers */
186 unsigned char enab[NUM_PAGED_REGS];
188 unsigned long iobase;
192 struct pcmuio_subdev_private *sprivs;
195 static void pcmuio_write(struct comedi_device *dev, unsigned int val,
196 int asic, int page, int port)
198 unsigned long iobase = dev->iobase + (asic * ASIC_IOSIZE);
201 /* Port registers are valid for any page */
202 outb(val & 0xff, iobase + PCMUIO_PORT_REG(port + 0));
203 outb((val >> 8) & 0xff, iobase + PCMUIO_PORT_REG(port + 1));
204 outb((val >> 16) & 0xff, iobase + PCMUIO_PORT_REG(port + 2));
206 outb(PCMUIO_PAGE(page), iobase + PCMUIO_PAGE_LOCK_REG);
207 outb(val & 0xff, iobase + PCMUIO_PAGE_REG(0));
208 outb((val >> 8) & 0xff, iobase + PCMUIO_PAGE_REG(1));
209 outb((val >> 16) & 0xff, iobase + PCMUIO_PAGE_REG(2));
213 static int pcmuio_dio_insn_bits(struct comedi_device *dev,
214 struct comedi_subdevice *s,
215 struct comedi_insn *insn, unsigned int *data)
217 struct pcmuio_subdev_private *subpriv = s->private;
221 reading a 0 means this channel was high
222 writine a 0 sets the channel high
223 reading a 1 means this channel was low
224 writing a 1 means set this channel low
226 Therefore everything is always inverted. */
228 /* The insn data is a mask in data[0] and the new data
229 * in data[1], each channel cooresponding to a bit. */
233 for (byte_no = 0; byte_no < s->n_chan / CHANS_PER_PORT; ++byte_no) {
234 /* address of 8-bit port */
235 unsigned long ioaddr = subpriv->iobases[byte_no],
236 /* bit offset of port in 32-bit doubleword */
237 offset = byte_no * 8;
238 /* this 8-bit port's data */
239 unsigned char byte = 0,
240 /* The write mask for this port (if any) */
241 write_mask_byte = (data[0] >> offset) & 0xff,
242 /* The data byte for this port */
243 data_byte = (data[1] >> offset) & 0xff;
245 byte = inb(ioaddr); /* read all 8-bits for this port */
247 if (write_mask_byte) {
248 byte &= ~write_mask_byte;
249 byte |= ~data_byte & write_mask_byte;
252 /* save the digital input lines for this byte.. */
253 s->state |= ((unsigned int)byte) << offset;
256 /* now return the DIO lines to data[1] - note they came inverted! */
262 static int pcmuio_dio_insn_config(struct comedi_device *dev,
263 struct comedi_subdevice *s,
264 struct comedi_insn *insn, unsigned int *data)
266 struct pcmuio_subdev_private *subpriv = s->private;
267 int chan = CR_CHAN(insn->chanspec), byte_no = chan / 8, bit_no =
269 unsigned long ioaddr;
272 /* Compute ioaddr for this channel */
273 ioaddr = subpriv->iobases[byte_no];
276 writing a 0 an IO channel's bit sets the channel to INPUT
277 and pulls the line high as well
279 writing a 1 to an IO channel's bit pulls the line low
281 All channels are implicitly always in OUTPUT mode -- but when
282 they are high they can be considered to be in INPUT mode..
284 Thus, we only force channels low if the config request was INPUT,
285 otherwise we do nothing to the hardware. */
288 case INSN_CONFIG_DIO_OUTPUT:
289 /* save to io_bits -- don't actually do anything since
290 all input channels are also output channels... */
291 s->io_bits |= 1 << chan;
293 case INSN_CONFIG_DIO_INPUT:
294 /* write a 0 to the actual register representing the channel
295 to set it to 'input'. 0 means "float high". */
297 byte &= ~(1 << bit_no);
298 /**< set input channel to '0' */
302 * This is the only time we actually affect the hardware
303 * as all channels are implicitly output -- but input
304 * channels are set to float-high.
308 /* save to io_bits */
309 s->io_bits &= ~(1 << chan);
312 case INSN_CONFIG_DIO_QUERY:
313 /* retrieve from shadow register */
315 (s->io_bits & (1 << chan)) ? COMEDI_OUTPUT : COMEDI_INPUT;
327 static void switch_page(struct comedi_device *dev, int asic, int page)
329 outb(PCMUIO_PAGE(page),
330 dev->iobase + ASIC_IOSIZE * asic + PCMUIO_PAGE_LOCK_REG);
333 static void init_asics(struct comedi_device *dev)
335 const struct pcmuio_board *board = comedi_board(dev);
338 for (asic = 0; asic < board->num_asics; ++asic) {
339 /* first, clear all the DIO port bits */
340 pcmuio_write(dev, 0, asic, 0, 0);
341 pcmuio_write(dev, 0, asic, 0, 3);
343 /* Next, clear all the paged registers for each page */
344 pcmuio_write(dev, 0, asic, PCMUIO_PAGE_POL, 0);
345 pcmuio_write(dev, 0, asic, PCMUIO_PAGE_ENAB, 0);
346 pcmuio_write(dev, 0, asic, PCMUIO_PAGE_INT_ID, 0);
350 static void pcmuio_stop_intr(struct comedi_device *dev,
351 struct comedi_subdevice *s)
353 struct pcmuio_subdev_private *subpriv = s->private;
356 asic = subpriv->intr.asic;
358 return; /* not an interrupt subdev */
360 subpriv->intr.enabled_mask = 0;
361 subpriv->intr.active = 0;
362 s->async->inttrig = NULL;
364 /* disable all intrs for this subdev.. */
365 pcmuio_write(dev, 0, asic, PCMUIO_PAGE_ENAB, 0);
368 static void pcmuio_handle_intr_subdev(struct comedi_device *dev,
369 struct comedi_subdevice *s,
372 struct pcmuio_subdev_private *subpriv = s->private;
373 unsigned int len = s->async->cmd.chanlist_len;
374 unsigned oldevents = s->async->events;
375 unsigned int val = 0;
380 spin_lock_irqsave(&subpriv->intr.spinlock, flags);
382 if (!subpriv->intr.active)
385 mytrig = triggered >> subpriv->intr.asic_chan;
386 mytrig &= ((0x1 << subpriv->intr.num_asic_chans) - 1);
387 mytrig <<= subpriv->intr.first_chan;
389 if (!(mytrig & subpriv->intr.enabled_mask))
392 for (i = 0; i < len; i++) {
393 unsigned int chan = CR_CHAN(s->async->cmd.chanlist[i]);
394 if (mytrig & (1U << chan))
398 /* Write the scan to the buffer. */
399 if (comedi_buf_put(s->async, ((short *)&val)[0]) &&
400 comedi_buf_put(s->async, ((short *)&val)[1])) {
401 s->async->events |= (COMEDI_CB_BLOCK | COMEDI_CB_EOS);
403 /* Overflow! Stop acquisition!! */
404 /* TODO: STOP_ACQUISITION_CALL_HERE!! */
405 pcmuio_stop_intr(dev, s);
408 /* Check for end of acquisition. */
409 if (!subpriv->intr.continuous) {
410 /* stop_src == TRIG_COUNT */
411 if (subpriv->intr.stop_count > 0) {
412 subpriv->intr.stop_count--;
413 if (subpriv->intr.stop_count == 0) {
414 s->async->events |= COMEDI_CB_EOA;
415 /* TODO: STOP_ACQUISITION_CALL_HERE!! */
416 pcmuio_stop_intr(dev, s);
422 spin_unlock_irqrestore(&subpriv->intr.spinlock, flags);
424 if (oldevents != s->async->events)
425 comedi_event(dev, s);
428 static int pcmuio_handle_asic_interrupt(struct comedi_device *dev, int asic)
430 struct pcmuio_private *devpriv = dev->private;
431 struct pcmuio_subdev_private *subpriv;
432 unsigned long iobase = devpriv->asics[asic].iobase;
433 unsigned triggered = 0;
436 unsigned char int_pend;
439 spin_lock_irqsave(&devpriv->asics[asic].spinlock, flags);
441 int_pend = inb(iobase + PCMUIO_INT_PENDING_REG) & 0x07;
443 for (i = 0; i < INTR_PORTS_PER_ASIC; ++i) {
444 if (int_pend & (0x1 << i)) {
447 switch_page(dev, asic, PCMUIO_PAGE_INT_ID);
448 val = inb(iobase + PCMUIO_PAGE_REG(i));
450 /* clear pending interrupt */
451 outb(0, iobase + PCMUIO_PAGE_REG(i));
453 triggered |= (val << (i * 8));
460 spin_unlock_irqrestore(&devpriv->asics[asic].spinlock, flags);
463 struct comedi_subdevice *s;
464 /* TODO here: dispatch io lines to subdevs with commands.. */
465 for (i = 0; i < dev->n_subdevices; i++) {
466 s = &dev->subdevices[i];
467 subpriv = s->private;
468 if (subpriv->intr.asic == asic) {
470 * This is an interrupt subdev, and it
473 pcmuio_handle_intr_subdev(dev, s,
481 static irqreturn_t interrupt_pcmuio(int irq, void *d)
483 struct comedi_device *dev = d;
484 struct pcmuio_private *devpriv = dev->private;
488 for (asic = 0; asic < MAX_ASICS; ++asic) {
489 if (irq == devpriv->asics[asic].irq) {
490 /* it is an interrupt for ASIC #asic */
491 if (pcmuio_handle_asic_interrupt(dev, asic))
496 return IRQ_NONE; /* interrupt from other source */
500 static int pcmuio_start_intr(struct comedi_device *dev,
501 struct comedi_subdevice *s)
503 struct pcmuio_subdev_private *subpriv = s->private;
505 if (!subpriv->intr.continuous && subpriv->intr.stop_count == 0) {
506 /* An empty acquisition! */
507 s->async->events |= COMEDI_CB_EOA;
508 subpriv->intr.active = 0;
511 unsigned bits = 0, pol_bits = 0, n;
513 struct comedi_cmd *cmd = &s->async->cmd;
515 asic = subpriv->intr.asic;
517 return 1; /* not an interrupt
519 subpriv->intr.enabled_mask = 0;
520 subpriv->intr.active = 1;
522 for (n = 0; n < cmd->chanlist_len; n++) {
523 bits |= (1U << CR_CHAN(cmd->chanlist[n]));
524 pol_bits |= (CR_AREF(cmd->chanlist[n])
526 chanlist[n]) ? 1U : 0U)
527 << CR_CHAN(cmd->chanlist[n]);
530 bits &= ((0x1 << subpriv->intr.num_asic_chans) -
531 1) << subpriv->intr.first_chan;
532 subpriv->intr.enabled_mask = bits;
534 /* set pol and enab intrs for this subdev.. */
535 pcmuio_write(dev, pol_bits, asic, PCMUIO_PAGE_POL, 0);
536 pcmuio_write(dev, bits, asic, PCMUIO_PAGE_ENAB, 0);
541 static int pcmuio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
543 struct pcmuio_subdev_private *subpriv = s->private;
546 spin_lock_irqsave(&subpriv->intr.spinlock, flags);
547 if (subpriv->intr.active)
548 pcmuio_stop_intr(dev, s);
549 spin_unlock_irqrestore(&subpriv->intr.spinlock, flags);
555 * Internal trigger function to start acquisition for an 'INTERRUPT' subdevice.
558 pcmuio_inttrig_start_intr(struct comedi_device *dev, struct comedi_subdevice *s,
559 unsigned int trignum)
561 struct pcmuio_subdev_private *subpriv = s->private;
568 spin_lock_irqsave(&subpriv->intr.spinlock, flags);
569 s->async->inttrig = NULL;
570 if (subpriv->intr.active)
571 event = pcmuio_start_intr(dev, s);
573 spin_unlock_irqrestore(&subpriv->intr.spinlock, flags);
576 comedi_event(dev, s);
582 * 'do_cmd' function for an 'INTERRUPT' subdevice.
584 static int pcmuio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
586 struct pcmuio_subdev_private *subpriv = s->private;
587 struct comedi_cmd *cmd = &s->async->cmd;
591 spin_lock_irqsave(&subpriv->intr.spinlock, flags);
592 subpriv->intr.active = 1;
594 /* Set up end of acquisition. */
595 switch (cmd->stop_src) {
597 subpriv->intr.continuous = 0;
598 subpriv->intr.stop_count = cmd->stop_arg;
602 subpriv->intr.continuous = 1;
603 subpriv->intr.stop_count = 0;
607 /* Set up start of acquisition. */
608 switch (cmd->start_src) {
610 s->async->inttrig = pcmuio_inttrig_start_intr;
614 event = pcmuio_start_intr(dev, s);
617 spin_unlock_irqrestore(&subpriv->intr.spinlock, flags);
620 comedi_event(dev, s);
625 static int pcmuio_cmdtest(struct comedi_device *dev,
626 struct comedi_subdevice *s,
627 struct comedi_cmd *cmd)
631 /* Step 1 : check if triggers are trivially valid */
633 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_INT);
634 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
635 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
636 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
637 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
642 /* Step 2a : make sure trigger sources are unique */
644 err |= cfc_check_trigger_is_unique(cmd->start_src);
645 err |= cfc_check_trigger_is_unique(cmd->stop_src);
647 /* Step 2b : and mutually compatible */
652 /* Step 3: check if arguments are trivially valid */
654 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
655 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
656 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
657 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
659 switch (cmd->stop_src) {
661 /* any count allowed */
664 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
673 /* step 4: fix up any arguments */
675 /* if (err) return 4; */
680 static int pcmuio_attach(struct comedi_device *dev, struct comedi_devconfig *it)
682 const struct pcmuio_board *board = comedi_board(dev);
683 struct comedi_subdevice *s;
684 struct pcmuio_private *devpriv;
685 struct pcmuio_subdev_private *subpriv;
686 int sdev_no, chans_left, n_subdevs, port, asic, thisasic_chanct = 0;
687 unsigned int irq[MAX_ASICS];
690 irq[0] = it->options[1];
691 irq[1] = it->options[2];
693 ret = comedi_request_region(dev, it->options[0],
694 board->num_asics * ASIC_IOSIZE);
698 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
701 dev->private = devpriv;
703 for (asic = 0; asic < MAX_ASICS; ++asic) {
704 devpriv->asics[asic].num = asic;
705 devpriv->asics[asic].iobase = dev->iobase + asic * ASIC_IOSIZE;
706 spin_lock_init(&devpriv->asics[asic].spinlock);
709 chans_left = CHANS_PER_ASIC * board->num_asics;
710 n_subdevs = (chans_left / MAX_CHANS_PER_SUBDEV) +
711 (!!(chans_left % MAX_CHANS_PER_SUBDEV));
712 devpriv->sprivs = kcalloc(n_subdevs,
713 sizeof(struct pcmuio_subdev_private),
715 if (!devpriv->sprivs)
718 ret = comedi_alloc_subdevices(dev, n_subdevs);
724 for (sdev_no = 0; sdev_no < (int)dev->n_subdevices; ++sdev_no) {
727 s = &dev->subdevices[sdev_no];
728 subpriv = &devpriv->sprivs[sdev_no];
729 s->private = subpriv;
731 s->range_table = &range_digital;
732 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
733 s->type = COMEDI_SUBD_DIO;
734 s->insn_bits = pcmuio_dio_insn_bits;
735 s->insn_config = pcmuio_dio_insn_config;
736 s->n_chan = min(chans_left, MAX_CHANS_PER_SUBDEV);
737 subpriv->intr.asic = -1;
738 subpriv->intr.first_chan = -1;
739 subpriv->intr.asic_chan = -1;
740 subpriv->intr.num_asic_chans = -1;
741 subpriv->intr.active = 0;
744 /* save the ioport address for each 'port' of 8 channels in the
746 for (byte_no = 0; byte_no < PORTS_PER_SUBDEV;
748 if (port >= PORTS_PER_ASIC) {
753 subpriv->iobases[byte_no] =
754 devpriv->asics[asic].iobase + port;
756 if (thisasic_chanct <
757 CHANS_PER_PORT * INTR_PORTS_PER_ASIC
758 && subpriv->intr.asic < 0) {
759 /* setup the interrupt subdevice */
760 subpriv->intr.asic = asic;
761 subpriv->intr.active = 0;
762 subpriv->intr.stop_count = 0;
763 subpriv->intr.first_chan = byte_no * 8;
764 subpriv->intr.asic_chan = thisasic_chanct;
765 subpriv->intr.num_asic_chans =
766 s->n_chan - subpriv->intr.first_chan;
767 dev->read_subdev = s;
768 s->subdev_flags |= SDF_CMD_READ;
769 s->cancel = pcmuio_cancel;
770 s->do_cmd = pcmuio_cmd;
771 s->do_cmdtest = pcmuio_cmdtest;
772 s->len_chanlist = subpriv->intr.num_asic_chans;
774 thisasic_chanct += CHANS_PER_PORT;
776 spin_lock_init(&subpriv->intr.spinlock);
778 chans_left -= s->n_chan;
781 /* reset to our first asic, to do intr subdevs */
788 init_asics(dev); /* clear out all the registers, basically */
790 for (asic = 0; irq[0] && asic < MAX_ASICS; ++asic) {
792 && request_irq(irq[asic], interrupt_pcmuio,
793 IRQF_SHARED, board->name, dev)) {
795 /* unroll the allocated irqs.. */
796 for (i = asic - 1; i >= 0; --i) {
797 free_irq(irq[i], dev);
798 devpriv->asics[i].irq = irq[i] = 0;
802 devpriv->asics[asic].irq = irq[asic];
806 dev_dbg(dev->class_dev, "irq: %u\n", irq[0]);
807 if (irq[1] && board->num_asics == 2)
808 dev_dbg(dev->class_dev, "second ASIC irq: %u\n",
811 dev_dbg(dev->class_dev, "(IRQ mode disabled)\n");
818 static void pcmuio_detach(struct comedi_device *dev)
820 struct pcmuio_private *devpriv = dev->private;
823 for (i = 0; i < MAX_ASICS; ++i) {
824 if (devpriv->asics[i].irq)
825 free_irq(devpriv->asics[i].irq, dev);
827 if (devpriv && devpriv->sprivs)
828 kfree(devpriv->sprivs);
829 comedi_legacy_detach(dev);
832 static struct comedi_driver pcmuio_driver = {
833 .driver_name = "pcmuio",
834 .module = THIS_MODULE,
835 .attach = pcmuio_attach,
836 .detach = pcmuio_detach,
837 .board_name = &pcmuio_boards[0].name,
838 .offset = sizeof(struct pcmuio_board),
839 .num_names = ARRAY_SIZE(pcmuio_boards),
841 module_comedi_driver(pcmuio_driver);
843 MODULE_AUTHOR("Comedi http://www.comedi.org");
844 MODULE_DESCRIPTION("Comedi low-level driver");
845 MODULE_LICENSE("GPL");