2 * comedi/drivers/rtd520.c
3 * Comedi driver for Real Time Devices (RTD) PCI4520/DM7520
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 2001 David A. Schleef <ds@schleef.org>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
21 * Description: Real Time Devices PCI4520/DM7520
22 * Devices: [Real Time Devices] DM7520HR-1 (DM7520), DM7520HR-8,
23 * PCI4520 (PCI4520), PCI4520-8
24 * Author: Dan Christian
25 * Status: Works. Only tested on DM7520-8. Not SMP safe.
27 * Configuration options: not applicable, uses PCI auto config
31 * Created by Dan Christian, NASA Ames Research Center.
33 * The PCI4520 is a PCI card. The DM7520 is a PC/104-plus card.
35 * 8/16 12 bit ADC with FIFO and channel gain table
36 * 8 bits high speed digital out (for external MUX) (or 8 in or 8 out)
37 * 8 bits high speed digital in with FIFO and interrupt on change (or 8 IO)
38 * 2 12 bit DACs with FIFOs
42 * timers: ADC sample, pacer, burst, about, delay, DA1, DA2
44 * 3 user timer/counters (8254)
47 * The DM7520 has slightly fewer features (fewer gain steps).
49 * These boards can support external multiplexors and multi-board
50 * synchronization, but this driver doesn't support that.
52 * Board docs: http://www.rtdusa.com/PC104/DM/analog%20IO/dm7520.htm
53 * Data sheet: http://www.rtdusa.com/pdf/dm7520.pdf
54 * Example source: http://www.rtdusa.com/examples/dm/dm7520.zip
55 * Call them and ask for the register level manual.
56 * PCI chip: http://www.plxtech.com/products/io/pci9080
59 * This board is memory mapped. There is some IO stuff, but it isn't needed.
61 * I use a pretty loose naming style within the driver (rtd_blah).
62 * All externally visible names should be rtd520_blah.
63 * I use camelCase for structures (and inside them).
64 * I may also use upper CamelCase for function names (old habit).
66 * This board is somewhat related to the RTD PCI4400 board.
68 * I borrowed heavily from the ni_mio_common, ni_atmio16d, mite, and
69 * das1800, since they have the best documented code. Driver cb_pcidas64.c
70 * uses the same DMA controller.
72 * As far as I can tell, the About interrupt doesn't work if Sample is
73 * also enabled. It turns out that About really isn't needed, since
74 * we always count down samples read.
76 * There was some timer/counter code, but it didn't follow the right API.
82 * Analog-In supports instruction and command mode.
84 * With DMA, you can sample at 1.15Mhz with 70% idle on a 400Mhz K6-2
85 * (single channel, 64K read buffer). I get random system lockups when
86 * using DMA with ALI-15xx based systems. I haven't been able to test
87 * any other chipsets. The lockups happen soon after the start of an
88 * acquistion, not in the middle of a long run.
90 * Without DMA, you can do 620Khz sampling with 20% idle on a 400Mhz K6-2
91 * (with a 256K read buffer).
93 * Digital-IO and Analog-Out only support instruction mode.
96 #include <linux/module.h>
97 #include <linux/delay.h>
98 #include <linux/interrupt.h>
100 #include "../comedi_pci.h"
105 * Local Address Space 0 Offsets
107 #define LAS0_USER_IO 0x0008 /* User I/O */
108 #define LAS0_ADC 0x0010 /* FIFO Status/Software A/D Start */
109 #define FS_DAC1_NOT_EMPTY BIT(0) /* DAC1 FIFO not empty */
110 #define FS_DAC1_HEMPTY BIT(1) /* DAC1 FIFO half empty */
111 #define FS_DAC1_NOT_FULL BIT(2) /* DAC1 FIFO not full */
112 #define FS_DAC2_NOT_EMPTY BIT(4) /* DAC2 FIFO not empty */
113 #define FS_DAC2_HEMPTY BIT(5) /* DAC2 FIFO half empty */
114 #define FS_DAC2_NOT_FULL BIT(6) /* DAC2 FIFO not full */
115 #define FS_ADC_NOT_EMPTY BIT(8) /* ADC FIFO not empty */
116 #define FS_ADC_HEMPTY BIT(9) /* ADC FIFO half empty */
117 #define FS_ADC_NOT_FULL BIT(10) /* ADC FIFO not full */
118 #define FS_DIN_NOT_EMPTY BIT(12) /* DIN FIFO not empty */
119 #define FS_DIN_HEMPTY BIT(13) /* DIN FIFO half empty */
120 #define FS_DIN_NOT_FULL BIT(14) /* DIN FIFO not full */
121 #define LAS0_DAC1 0x0014 /* Software D/A1 Update (w) */
122 #define LAS0_DAC2 0x0018 /* Software D/A2 Update (w) */
123 #define LAS0_DAC 0x0024 /* Software Simultaneous Update (w) */
124 #define LAS0_PACER 0x0028 /* Software Pacer Start/Stop */
125 #define LAS0_TIMER 0x002c /* Timer Status/HDIN Software Trig. */
126 #define LAS0_IT 0x0030 /* Interrupt Status/Enable */
127 #define IRQM_ADC_FIFO_WRITE BIT(0) /* ADC FIFO Write */
128 #define IRQM_CGT_RESET BIT(1) /* Reset CGT */
129 #define IRQM_CGT_PAUSE BIT(3) /* Pause CGT */
130 #define IRQM_ADC_ABOUT_CNT BIT(4) /* About Counter out */
131 #define IRQM_ADC_DELAY_CNT BIT(5) /* Delay Counter out */
132 #define IRQM_ADC_SAMPLE_CNT BIT(6) /* ADC Sample Counter */
133 #define IRQM_DAC1_UCNT BIT(7) /* DAC1 Update Counter */
134 #define IRQM_DAC2_UCNT BIT(8) /* DAC2 Update Counter */
135 #define IRQM_UTC1 BIT(9) /* User TC1 out */
136 #define IRQM_UTC1_INV BIT(10) /* User TC1 out, inverted */
137 #define IRQM_UTC2 BIT(11) /* User TC2 out */
138 #define IRQM_DIGITAL_IT BIT(12) /* Digital Interrupt */
139 #define IRQM_EXTERNAL_IT BIT(13) /* External Interrupt */
140 #define IRQM_ETRIG_RISING BIT(14) /* Ext Trigger rising-edge */
141 #define IRQM_ETRIG_FALLING BIT(15) /* Ext Trigger falling-edge */
142 #define LAS0_CLEAR 0x0034 /* Clear/Set Interrupt Clear Mask */
143 #define LAS0_OVERRUN 0x0038 /* Pending interrupts/Clear Overrun */
144 #define LAS0_PCLK 0x0040 /* Pacer Clock (24bit) */
145 #define LAS0_BCLK 0x0044 /* Burst Clock (10bit) */
146 #define LAS0_ADC_SCNT 0x0048 /* A/D Sample counter (10bit) */
147 #define LAS0_DAC1_UCNT 0x004c /* D/A1 Update counter (10 bit) */
148 #define LAS0_DAC2_UCNT 0x0050 /* D/A2 Update counter (10 bit) */
149 #define LAS0_DCNT 0x0054 /* Delay counter (16 bit) */
150 #define LAS0_ACNT 0x0058 /* About counter (16 bit) */
151 #define LAS0_DAC_CLK 0x005c /* DAC clock (16bit) */
152 #define LAS0_UTC0 0x0060 /* 8254 TC Counter 0 */
153 #define LAS0_UTC1 0x0064 /* 8254 TC Counter 1 */
154 #define LAS0_UTC2 0x0068 /* 8254 TC Counter 2 */
155 #define LAS0_UTC_CTRL 0x006c /* 8254 TC Control */
156 #define LAS0_DIO0 0x0070 /* Digital I/O Port 0 */
157 #define LAS0_DIO1 0x0074 /* Digital I/O Port 1 */
158 #define LAS0_DIO0_CTRL 0x0078 /* Digital I/O Control */
159 #define LAS0_DIO_STATUS 0x007c /* Digital I/O Status */
160 #define LAS0_BOARD_RESET 0x0100 /* Board reset */
161 #define LAS0_DMA0_SRC 0x0104 /* DMA 0 Sources select */
162 #define LAS0_DMA1_SRC 0x0108 /* DMA 1 Sources select */
163 #define LAS0_ADC_CONVERSION 0x010c /* A/D Conversion Signal select */
164 #define LAS0_BURST_START 0x0110 /* Burst Clock Start Trigger select */
165 #define LAS0_PACER_START 0x0114 /* Pacer Clock Start Trigger select */
166 #define LAS0_PACER_STOP 0x0118 /* Pacer Clock Stop Trigger select */
167 #define LAS0_ACNT_STOP_ENABLE 0x011c /* About Counter Stop Enable */
168 #define LAS0_PACER_REPEAT 0x0120 /* Pacer Start Trigger Mode select */
169 #define LAS0_DIN_START 0x0124 /* HiSpd DI Sampling Signal select */
170 #define LAS0_DIN_FIFO_CLEAR 0x0128 /* Digital Input FIFO Clear */
171 #define LAS0_ADC_FIFO_CLEAR 0x012c /* A/D FIFO Clear */
172 #define LAS0_CGT_WRITE 0x0130 /* Channel Gain Table Write */
173 #define LAS0_CGL_WRITE 0x0134 /* Channel Gain Latch Write */
174 #define LAS0_CG_DATA 0x0138 /* Digital Table Write */
175 #define LAS0_CGT_ENABLE 0x013c /* Channel Gain Table Enable */
176 #define LAS0_CG_ENABLE 0x0140 /* Digital Table Enable */
177 #define LAS0_CGT_PAUSE 0x0144 /* Table Pause Enable */
178 #define LAS0_CGT_RESET 0x0148 /* Reset Channel Gain Table */
179 #define LAS0_CGT_CLEAR 0x014c /* Clear Channel Gain Table */
180 #define LAS0_DAC1_CTRL 0x0150 /* D/A1 output type/range */
181 #define LAS0_DAC1_SRC 0x0154 /* D/A1 update source */
182 #define LAS0_DAC1_CYCLE 0x0158 /* D/A1 cycle mode */
183 #define LAS0_DAC1_RESET 0x015c /* D/A1 FIFO reset */
184 #define LAS0_DAC1_FIFO_CLEAR 0x0160 /* D/A1 FIFO clear */
185 #define LAS0_DAC2_CTRL 0x0164 /* D/A2 output type/range */
186 #define LAS0_DAC2_SRC 0x0168 /* D/A2 update source */
187 #define LAS0_DAC2_CYCLE 0x016c /* D/A2 cycle mode */
188 #define LAS0_DAC2_RESET 0x0170 /* D/A2 FIFO reset */
189 #define LAS0_DAC2_FIFO_CLEAR 0x0174 /* D/A2 FIFO clear */
190 #define LAS0_ADC_SCNT_SRC 0x0178 /* A/D Sample Counter Source select */
191 #define LAS0_PACER_SELECT 0x0180 /* Pacer Clock select */
192 #define LAS0_SBUS0_SRC 0x0184 /* SyncBus 0 Source select */
193 #define LAS0_SBUS0_ENABLE 0x0188 /* SyncBus 0 enable */
194 #define LAS0_SBUS1_SRC 0x018c /* SyncBus 1 Source select */
195 #define LAS0_SBUS1_ENABLE 0x0190 /* SyncBus 1 enable */
196 #define LAS0_SBUS2_SRC 0x0198 /* SyncBus 2 Source select */
197 #define LAS0_SBUS2_ENABLE 0x019c /* SyncBus 2 enable */
198 #define LAS0_ETRG_POLARITY 0x01a4 /* Ext. Trigger polarity select */
199 #define LAS0_EINT_POLARITY 0x01a8 /* Ext. Interrupt polarity select */
200 #define LAS0_UTC0_CLOCK 0x01ac /* UTC0 Clock select */
201 #define LAS0_UTC0_GATE 0x01b0 /* UTC0 Gate select */
202 #define LAS0_UTC1_CLOCK 0x01b4 /* UTC1 Clock select */
203 #define LAS0_UTC1_GATE 0x01b8 /* UTC1 Gate select */
204 #define LAS0_UTC2_CLOCK 0x01bc /* UTC2 Clock select */
205 #define LAS0_UTC2_GATE 0x01c0 /* UTC2 Gate select */
206 #define LAS0_UOUT0_SELECT 0x01c4 /* User Output 0 source select */
207 #define LAS0_UOUT1_SELECT 0x01c8 /* User Output 1 source select */
208 #define LAS0_DMA0_RESET 0x01cc /* DMA0 Request state machine reset */
209 #define LAS0_DMA1_RESET 0x01d0 /* DMA1 Request state machine reset */
212 * Local Address Space 1 Offsets
214 #define LAS1_ADC_FIFO 0x0000 /* A/D FIFO (16bit) */
215 #define LAS1_HDIO_FIFO 0x0004 /* HiSpd DI FIFO (16bit) */
216 #define LAS1_DAC1_FIFO 0x0008 /* D/A1 FIFO (16bit) */
217 #define LAS1_DAC2_FIFO 0x000c /* D/A2 FIFO (16bit) */
219 /*======================================================================
220 Driver specific stuff (tunable)
221 ======================================================================*/
223 /* We really only need 2 buffers. More than that means being much
224 smarter about knowing which ones are full. */
225 #define DMA_CHAIN_COUNT 2 /* max DMA segments/buffers in a ring (min 2) */
227 /* Target period for periodic transfers. This sets the user read latency. */
228 /* Note: There are certain rates where we give this up and transfer 1/2 FIFO */
229 /* If this is too low, efficiency is poor */
230 #define TRANS_TARGET_PERIOD 10000000 /* 10 ms (in nanoseconds) */
232 /* Set a practical limit on how long a list to support (affects memory use) */
233 /* The board support a channel list up to the FIFO length (1K or 8K) */
234 #define RTD_MAX_CHANLIST 128 /* max channel list that we allow */
236 /*======================================================================
238 ======================================================================*/
240 #define RTD_CLOCK_RATE 8000000 /* 8Mhz onboard clock */
241 #define RTD_CLOCK_BASE 125 /* clock period in ns */
243 /* Note: these speed are slower than the spec, but fit the counter resolution*/
244 #define RTD_MAX_SPEED 1625 /* when sampling, in nanoseconds */
245 /* max speed if we don't have to wait for settling */
246 #define RTD_MAX_SPEED_1 875 /* if single channel, in nanoseconds */
248 #define RTD_MIN_SPEED 2097151875 /* (24bit counter) in nanoseconds */
249 /* min speed when only 1 channel (no burst counter) */
250 #define RTD_MIN_SPEED_1 5000000 /* 200Hz, in nanoseconds */
252 /* Setup continuous ring of 1/2 FIFO transfers. See RTD manual p91 */
253 #define DMA_MODE_BITS (\
254 PLX_LOCAL_BUS_16_WIDE_BITS \
255 | PLX_DMA_EN_READYIN_BIT \
256 | PLX_DMA_LOCAL_BURST_EN_BIT \
258 | PLX_DMA_INTR_PCI_BIT \
259 | PLX_LOCAL_ADDR_CONST_BIT \
260 | PLX_DEMAND_MODE_BIT)
262 #define DMA_TRANSFER_BITS (\
263 /* descriptors in PCI memory*/ PLX_DESC_IN_PCI_BIT \
264 /* interrupt at end of block */ | PLX_INTR_TERM_COUNT \
265 /* from board to PCI */ | PLX_XFER_LOCAL_TO_PCI)
267 /*======================================================================
268 Comedi specific stuff
269 ======================================================================*/
272 * The board has 3 input modes and the gains of 1,2,4,...32 (, 64, 128)
274 static const struct comedi_lrange rtd_ai_7520_range = {
276 /* +-5V input range gain steps */
283 /* +-10V input range gain steps */
288 BIP_RANGE(10.0 / 16),
289 BIP_RANGE(10.0 / 32),
290 /* +10V input range gain steps */
295 UNI_RANGE(10.0 / 16),
296 UNI_RANGE(10.0 / 32),
300 /* PCI4520 has two more gains (6 more entries) */
301 static const struct comedi_lrange rtd_ai_4520_range = {
303 /* +-5V input range gain steps */
311 BIP_RANGE(5.0 / 128),
312 /* +-10V input range gain steps */
317 BIP_RANGE(10.0 / 16),
318 BIP_RANGE(10.0 / 32),
319 BIP_RANGE(10.0 / 64),
320 BIP_RANGE(10.0 / 128),
321 /* +10V input range gain steps */
326 UNI_RANGE(10.0 / 16),
327 UNI_RANGE(10.0 / 32),
328 UNI_RANGE(10.0 / 64),
329 UNI_RANGE(10.0 / 128),
333 /* Table order matches range values */
334 static const struct comedi_lrange rtd_ao_range = {
348 struct rtd_boardinfo {
350 int range_bip10; /* start of +-10V range */
351 int range_uni10; /* start of +10V range */
352 const struct comedi_lrange *ai_range;
355 static const struct rtd_boardinfo rtd520Boards[] = {
360 .ai_range = &rtd_ai_7520_range,
366 .ai_range = &rtd_ai_4520_range,
371 /* memory mapped board structures */
375 long ai_count; /* total transfer size (samples) */
376 int xfer_count; /* # to transfer data. 0->1/2FIFO */
377 int flags; /* flag event modes */
381 /* bit defines for "flags" */
382 #define SEND_EOS 0x01 /* send End Of Scan events */
383 #define DMA0_ACTIVE 0x02 /* DMA0 is active */
384 #define DMA1_ACTIVE 0x04 /* DMA1 is active */
387 Given a desired period and the clock period (both in ns),
388 return the proper counter value (divider-1).
389 Sets the original period to be the true value.
390 Note: you have to check if the value is larger than the counter range!
392 static int rtd_ns_to_timer_base(unsigned int *nanosec,
393 unsigned int flags, int base)
397 switch (flags & CMDF_ROUND_MASK) {
398 case CMDF_ROUND_NEAREST:
400 divider = (*nanosec + base / 2) / base;
402 case CMDF_ROUND_DOWN:
403 divider = (*nanosec) / base;
406 divider = (*nanosec + base - 1) / base;
410 divider = 2; /* min is divide by 2 */
412 /* Note: we don't check for max, because different timers
413 have different ranges */
415 *nanosec = base * divider;
416 return divider - 1; /* countdown is divisor+1 */
420 Given a desired period (in ns),
421 return the proper counter value (divider-1) for the internal clock.
422 Sets the original period to be the true value.
424 static int rtd_ns_to_timer(unsigned int *ns, unsigned int flags)
426 return rtd_ns_to_timer_base(ns, flags, RTD_CLOCK_BASE);
430 Convert a single comedi channel-gain entry to a RTD520 table entry
432 static unsigned short rtd_convert_chan_gain(struct comedi_device *dev,
433 unsigned int chanspec, int index)
435 const struct rtd_boardinfo *board = dev->board_ptr;
436 unsigned int chan = CR_CHAN(chanspec);
437 unsigned int range = CR_RANGE(chanspec);
438 unsigned int aref = CR_AREF(chanspec);
439 unsigned short r = 0;
443 /* Note: we also setup the channel list bipolar flag array */
444 if (range < board->range_bip10) {
447 r |= (range & 0x7) << 4;
448 } else if (range < board->range_uni10) {
451 r |= ((range - board->range_bip10) & 0x7) << 4;
455 r |= ((range - board->range_uni10) & 0x7) << 4;
459 case AREF_GROUND: /* on-board ground */
463 r |= 0x80; /* ref external analog common */
467 r |= 0x400; /* differential inputs */
470 case AREF_OTHER: /* ??? */
477 Setup the channel-gain table from a comedi list
479 static void rtd_load_channelgain_list(struct comedi_device *dev,
480 unsigned int n_chan, unsigned int *list)
482 if (n_chan > 1) { /* setup channel gain table */
485 writel(0, dev->mmio + LAS0_CGT_CLEAR);
486 writel(1, dev->mmio + LAS0_CGT_ENABLE);
487 for (ii = 0; ii < n_chan; ii++) {
488 writel(rtd_convert_chan_gain(dev, list[ii], ii),
489 dev->mmio + LAS0_CGT_WRITE);
491 } else { /* just use the channel gain latch */
492 writel(0, dev->mmio + LAS0_CGT_ENABLE);
493 writel(rtd_convert_chan_gain(dev, list[0], 0),
494 dev->mmio + LAS0_CGL_WRITE);
498 /* determine fifo size by doing adc conversions until the fifo half
499 empty status flag clears */
500 static int rtd520_probe_fifo_depth(struct comedi_device *dev)
502 unsigned int chanspec = CR_PACK(0, 0, AREF_GROUND);
504 static const unsigned limit = 0x2000;
505 unsigned fifo_size = 0;
507 writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR);
508 rtd_load_channelgain_list(dev, 1, &chanspec);
509 /* ADC conversion trigger source: SOFTWARE */
510 writel(0, dev->mmio + LAS0_ADC_CONVERSION);
511 /* convert samples */
512 for (i = 0; i < limit; ++i) {
513 unsigned fifo_status;
514 /* trigger conversion */
515 writew(0, dev->mmio + LAS0_ADC);
517 fifo_status = readl(dev->mmio + LAS0_ADC);
518 if ((fifo_status & FS_ADC_HEMPTY) == 0) {
524 dev_info(dev->class_dev, "failed to probe fifo size.\n");
527 writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR);
528 if (fifo_size != 0x400 && fifo_size != 0x2000) {
529 dev_info(dev->class_dev,
530 "unexpected fifo size of %i, expected 1024 or 8192.\n",
537 static int rtd_ai_eoc(struct comedi_device *dev,
538 struct comedi_subdevice *s,
539 struct comedi_insn *insn,
540 unsigned long context)
544 status = readl(dev->mmio + LAS0_ADC);
545 if (status & FS_ADC_NOT_EMPTY)
550 static int rtd_ai_rinsn(struct comedi_device *dev,
551 struct comedi_subdevice *s, struct comedi_insn *insn,
554 struct rtd_private *devpriv = dev->private;
555 unsigned int range = CR_RANGE(insn->chanspec);
559 /* clear any old fifo data */
560 writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR);
562 /* write channel to multiplexer and clear channel gain table */
563 rtd_load_channelgain_list(dev, 1, &insn->chanspec);
565 /* ADC conversion trigger source: SOFTWARE */
566 writel(0, dev->mmio + LAS0_ADC_CONVERSION);
568 /* convert n samples */
569 for (n = 0; n < insn->n; n++) {
571 /* trigger conversion */
572 writew(0, dev->mmio + LAS0_ADC);
574 ret = comedi_timeout(dev, s, insn, rtd_ai_eoc, 0);
579 d = readw(devpriv->las1 + LAS1_ADC_FIFO);
580 d >>= 3; /* low 3 bits are marker lines */
582 /* convert bipolar data to comedi unsigned data */
583 if (comedi_range_is_bipolar(s, range))
584 d = comedi_offset_munge(s, d);
586 data[n] = d & s->maxdata;
589 /* return the number of samples read/written */
594 Get what we know is there.... Fast!
595 This uses 1/2 the bus cycles of read_dregs (below).
597 The manual claims that we can do a lword read, but it doesn't work here.
599 static int ai_read_n(struct comedi_device *dev, struct comedi_subdevice *s,
602 struct rtd_private *devpriv = dev->private;
603 struct comedi_async *async = s->async;
604 struct comedi_cmd *cmd = &async->cmd;
607 for (ii = 0; ii < count; ii++) {
608 unsigned int range = CR_RANGE(cmd->chanlist[async->cur_chan]);
611 if (0 == devpriv->ai_count) { /* done */
612 d = readw(devpriv->las1 + LAS1_ADC_FIFO);
616 d = readw(devpriv->las1 + LAS1_ADC_FIFO);
617 d >>= 3; /* low 3 bits are marker lines */
619 /* convert bipolar data to comedi unsigned data */
620 if (comedi_range_is_bipolar(s, range))
621 d = comedi_offset_munge(s, d);
624 if (!comedi_buf_write_samples(s, &d, 1))
627 if (devpriv->ai_count > 0) /* < 0, means read forever */
634 Handle all rtd520 interrupts.
635 Runs atomically and is never re-entered.
636 This is a "slow handler"; other interrupts may be active.
637 The data conversion may someday happen in a "bottom half".
639 static irqreturn_t rtd_interrupt(int irq, void *d)
641 struct comedi_device *dev = d;
642 struct comedi_subdevice *s = dev->read_subdev;
643 struct rtd_private *devpriv = dev->private;
651 fifo_status = readl(dev->mmio + LAS0_ADC);
652 /* check for FIFO full, this automatically halts the ADC! */
653 if (!(fifo_status & FS_ADC_NOT_FULL)) /* 0 -> full */
656 status = readw(dev->mmio + LAS0_IT);
657 /* if interrupt was not caused by our board, or handled above */
661 if (status & IRQM_ADC_ABOUT_CNT) { /* sample count -> read FIFO */
663 * since the priority interrupt controller may have queued
664 * a sample counter interrupt, even though we have already
665 * finished, we must handle the possibility that there is
668 if (!(fifo_status & FS_ADC_HEMPTY)) {
670 if (ai_read_n(dev, s, devpriv->fifosz / 2) < 0)
673 if (0 == devpriv->ai_count)
675 } else if (devpriv->xfer_count > 0) {
676 if (fifo_status & FS_ADC_NOT_EMPTY) {
678 if (ai_read_n(dev, s, devpriv->xfer_count) < 0)
681 if (0 == devpriv->ai_count)
687 overrun = readl(dev->mmio + LAS0_OVERRUN) & 0xffff;
691 /* clear the interrupt */
692 writew(status, dev->mmio + LAS0_CLEAR);
693 readw(dev->mmio + LAS0_CLEAR);
695 comedi_handle_events(dev, s);
700 s->async->events |= COMEDI_CB_ERROR;
703 s->async->events |= COMEDI_CB_EOA;
705 /* clear the interrupt */
706 status = readw(dev->mmio + LAS0_IT);
707 writew(status, dev->mmio + LAS0_CLEAR);
708 readw(dev->mmio + LAS0_CLEAR);
710 fifo_status = readl(dev->mmio + LAS0_ADC);
711 overrun = readl(dev->mmio + LAS0_OVERRUN) & 0xffff;
713 comedi_handle_events(dev, s);
719 cmdtest tests a particular command to see if it is valid.
720 Using the cmdtest ioctl, a user can create a valid cmd
721 and then have it executed by the cmd ioctl (asynchronously).
723 cmdtest returns 1,2,3,4 or 0, depending on which tests
727 static int rtd_ai_cmdtest(struct comedi_device *dev,
728 struct comedi_subdevice *s, struct comedi_cmd *cmd)
733 /* Step 1 : check if triggers are trivially valid */
735 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW);
736 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
737 TRIG_TIMER | TRIG_EXT);
738 err |= comedi_check_trigger_src(&cmd->convert_src,
739 TRIG_TIMER | TRIG_EXT);
740 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
741 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
746 /* Step 2a : make sure trigger sources are unique */
748 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
749 err |= comedi_check_trigger_is_unique(cmd->convert_src);
750 err |= comedi_check_trigger_is_unique(cmd->stop_src);
752 /* Step 2b : and mutually compatible */
757 /* Step 3: check if arguments are trivially valid */
759 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
761 if (cmd->scan_begin_src == TRIG_TIMER) {
762 /* Note: these are time periods, not actual rates */
763 if (1 == cmd->chanlist_len) { /* no scanning */
764 if (comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
766 rtd_ns_to_timer(&cmd->scan_begin_arg,
770 if (comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
772 rtd_ns_to_timer(&cmd->scan_begin_arg,
777 if (comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
779 rtd_ns_to_timer(&cmd->scan_begin_arg,
783 if (comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
785 rtd_ns_to_timer(&cmd->scan_begin_arg,
791 /* external trigger */
792 /* should be level/edge, hi/lo specification here */
793 /* should specify multiple external triggers */
794 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg, 9);
797 if (cmd->convert_src == TRIG_TIMER) {
798 if (1 == cmd->chanlist_len) { /* no scanning */
799 if (comedi_check_trigger_arg_min(&cmd->convert_arg,
801 rtd_ns_to_timer(&cmd->convert_arg,
805 if (comedi_check_trigger_arg_max(&cmd->convert_arg,
807 rtd_ns_to_timer(&cmd->convert_arg,
812 if (comedi_check_trigger_arg_min(&cmd->convert_arg,
814 rtd_ns_to_timer(&cmd->convert_arg,
818 if (comedi_check_trigger_arg_max(&cmd->convert_arg,
820 rtd_ns_to_timer(&cmd->convert_arg,
826 /* external trigger */
828 err |= comedi_check_trigger_arg_max(&cmd->convert_arg, 9);
831 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
834 if (cmd->stop_src == TRIG_COUNT)
835 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
837 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
842 /* step 4: fix up any arguments */
844 if (cmd->scan_begin_src == TRIG_TIMER) {
845 arg = cmd->scan_begin_arg;
846 rtd_ns_to_timer(&arg, cmd->flags);
847 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, arg);
850 if (cmd->convert_src == TRIG_TIMER) {
851 arg = cmd->convert_arg;
852 rtd_ns_to_timer(&arg, cmd->flags);
853 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, arg);
855 if (cmd->scan_begin_src == TRIG_TIMER) {
856 arg = cmd->convert_arg * cmd->scan_end_arg;
857 err |= comedi_check_trigger_arg_min(&cmd->
870 Execute a analog in command with many possible triggering options.
871 The data get stored in the async structure of the subdevice.
872 This is usually done by an interrupt handler.
873 Userland gets to the data using read calls.
875 static int rtd_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
877 struct rtd_private *devpriv = dev->private;
878 struct comedi_cmd *cmd = &s->async->cmd;
881 /* stop anything currently running */
882 /* pacer stop source: SOFTWARE */
883 writel(0, dev->mmio + LAS0_PACER_STOP);
884 writel(0, dev->mmio + LAS0_PACER); /* stop pacer */
885 writel(0, dev->mmio + LAS0_ADC_CONVERSION);
886 writew(0, dev->mmio + LAS0_IT);
887 writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR);
888 writel(0, dev->mmio + LAS0_OVERRUN);
890 /* start configuration */
891 /* load channel list and reset CGT */
892 rtd_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist);
894 /* setup the common case and override if needed */
895 if (cmd->chanlist_len > 1) {
896 /* pacer start source: SOFTWARE */
897 writel(0, dev->mmio + LAS0_PACER_START);
898 /* burst trigger source: PACER */
899 writel(1, dev->mmio + LAS0_BURST_START);
900 /* ADC conversion trigger source: BURST */
901 writel(2, dev->mmio + LAS0_ADC_CONVERSION);
902 } else { /* single channel */
903 /* pacer start source: SOFTWARE */
904 writel(0, dev->mmio + LAS0_PACER_START);
905 /* ADC conversion trigger source: PACER */
906 writel(1, dev->mmio + LAS0_ADC_CONVERSION);
908 writel((devpriv->fifosz / 2 - 1) & 0xffff, dev->mmio + LAS0_ACNT);
910 if (TRIG_TIMER == cmd->scan_begin_src) {
911 /* scan_begin_arg is in nanoseconds */
912 /* find out how many samples to wait before transferring */
913 if (cmd->flags & CMDF_WAKE_EOS) {
915 * this may generate un-sustainable interrupt rates
916 * the application is responsible for doing the
919 devpriv->xfer_count = cmd->chanlist_len;
920 devpriv->flags |= SEND_EOS;
922 /* arrange to transfer data periodically */
923 devpriv->xfer_count =
924 (TRANS_TARGET_PERIOD * cmd->chanlist_len) /
926 if (devpriv->xfer_count < cmd->chanlist_len) {
927 /* transfer after each scan (and avoid 0) */
928 devpriv->xfer_count = cmd->chanlist_len;
929 } else { /* make a multiple of scan length */
930 devpriv->xfer_count =
931 (devpriv->xfer_count +
932 cmd->chanlist_len - 1)
934 devpriv->xfer_count *= cmd->chanlist_len;
936 devpriv->flags |= SEND_EOS;
938 if (devpriv->xfer_count >= (devpriv->fifosz / 2)) {
939 /* out of counter range, use 1/2 fifo instead */
940 devpriv->xfer_count = 0;
941 devpriv->flags &= ~SEND_EOS;
943 /* interrupt for each transfer */
944 writel((devpriv->xfer_count - 1) & 0xffff,
945 dev->mmio + LAS0_ACNT);
947 } else { /* unknown timing, just use 1/2 FIFO */
948 devpriv->xfer_count = 0;
949 devpriv->flags &= ~SEND_EOS;
951 /* pacer clock source: INTERNAL 8MHz */
952 writel(1, dev->mmio + LAS0_PACER_SELECT);
953 /* just interrupt, don't stop */
954 writel(1, dev->mmio + LAS0_ACNT_STOP_ENABLE);
956 /* BUG??? these look like enumerated values, but they are bit fields */
958 /* First, setup when to stop */
959 switch (cmd->stop_src) {
960 case TRIG_COUNT: /* stop after N scans */
961 devpriv->ai_count = cmd->stop_arg * cmd->chanlist_len;
962 if ((devpriv->xfer_count > 0) &&
963 (devpriv->xfer_count > devpriv->ai_count)) {
964 devpriv->xfer_count = devpriv->ai_count;
968 case TRIG_NONE: /* stop when cancel is called */
969 devpriv->ai_count = -1; /* read forever */
974 switch (cmd->scan_begin_src) {
975 case TRIG_TIMER: /* periodic scanning */
976 timer = rtd_ns_to_timer(&cmd->scan_begin_arg,
978 /* set PACER clock */
979 writel(timer & 0xffffff, dev->mmio + LAS0_PCLK);
984 /* pacer start source: EXTERNAL */
985 writel(1, dev->mmio + LAS0_PACER_START);
989 /* Sample timing within a scan */
990 switch (cmd->convert_src) {
991 case TRIG_TIMER: /* periodic */
992 if (cmd->chanlist_len > 1) {
993 /* only needed for multi-channel */
994 timer = rtd_ns_to_timer(&cmd->convert_arg,
996 /* setup BURST clock */
997 writel(timer & 0x3ff, dev->mmio + LAS0_BCLK);
1002 case TRIG_EXT: /* external */
1003 /* burst trigger source: EXTERNAL */
1004 writel(2, dev->mmio + LAS0_BURST_START);
1007 /* end configuration */
1009 /* This doesn't seem to work. There is no way to clear an interrupt
1010 that the priority controller has queued! */
1011 writew(~0, dev->mmio + LAS0_CLEAR);
1012 readw(dev->mmio + LAS0_CLEAR);
1014 /* TODO: allow multiple interrupt sources */
1015 /* transfer every N samples */
1016 writew(IRQM_ADC_ABOUT_CNT, dev->mmio + LAS0_IT);
1018 /* BUG: start_src is ASSUMED to be TRIG_NOW */
1019 /* BUG? it seems like things are running before the "start" */
1020 readl(dev->mmio + LAS0_PACER); /* start pacer */
1025 Stop a running data acquisition.
1027 static int rtd_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
1029 struct rtd_private *devpriv = dev->private;
1031 /* pacer stop source: SOFTWARE */
1032 writel(0, dev->mmio + LAS0_PACER_STOP);
1033 writel(0, dev->mmio + LAS0_PACER); /* stop pacer */
1034 writel(0, dev->mmio + LAS0_ADC_CONVERSION);
1035 writew(0, dev->mmio + LAS0_IT);
1036 devpriv->ai_count = 0; /* stop and don't transfer any more */
1037 writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR);
1041 static int rtd_ao_eoc(struct comedi_device *dev,
1042 struct comedi_subdevice *s,
1043 struct comedi_insn *insn,
1044 unsigned long context)
1046 unsigned int chan = CR_CHAN(insn->chanspec);
1047 unsigned int bit = (chan == 0) ? FS_DAC1_NOT_EMPTY : FS_DAC2_NOT_EMPTY;
1048 unsigned int status;
1050 status = readl(dev->mmio + LAS0_ADC);
1056 static int rtd_ao_winsn(struct comedi_device *dev,
1057 struct comedi_subdevice *s, struct comedi_insn *insn,
1060 struct rtd_private *devpriv = dev->private;
1062 int chan = CR_CHAN(insn->chanspec);
1063 int range = CR_RANGE(insn->chanspec);
1066 /* Configure the output range (table index matches the range values) */
1068 dev->mmio + ((chan == 0) ? LAS0_DAC1_CTRL : LAS0_DAC2_CTRL));
1070 /* Writing a list of values to an AO channel is probably not
1071 * very useful, but that's how the interface is defined. */
1072 for (i = 0; i < insn->n; ++i) {
1073 int val = data[i] << 3;
1075 /* VERIFY: comedi range and offset conversions */
1077 if ((range > 1) && (data[i] < 2048)) { /* bipolar */
1078 /* offset and sign extend */
1079 val = (((int)data[i]) - 2048) << 3;
1080 } else { /* unipolor */
1084 /* a typical programming sequence */
1085 writew(val, devpriv->las1 +
1086 ((chan == 0) ? LAS1_DAC1_FIFO : LAS1_DAC2_FIFO));
1087 writew(0, dev->mmio + ((chan == 0) ? LAS0_DAC1 : LAS0_DAC2));
1089 s->readback[chan] = data[i];
1091 ret = comedi_timeout(dev, s, insn, rtd_ao_eoc, 0);
1096 /* return the number of samples read/written */
1100 static int rtd_dio_insn_bits(struct comedi_device *dev,
1101 struct comedi_subdevice *s,
1102 struct comedi_insn *insn,
1105 if (comedi_dio_update_state(s, data))
1106 writew(s->state & 0xff, dev->mmio + LAS0_DIO0);
1108 data[1] = readw(dev->mmio + LAS0_DIO0) & 0xff;
1113 static int rtd_dio_insn_config(struct comedi_device *dev,
1114 struct comedi_subdevice *s,
1115 struct comedi_insn *insn,
1120 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
1124 /* TODO support digital match interrupts and strobes */
1127 writew(0x01, dev->mmio + LAS0_DIO_STATUS);
1128 writew(s->io_bits & 0xff, dev->mmio + LAS0_DIO0_CTRL);
1130 /* clear interrupts */
1131 writew(0x00, dev->mmio + LAS0_DIO_STATUS);
1133 /* port1 can only be all input or all output */
1135 /* there are also 2 user input lines and 2 user output lines */
1140 static void rtd_reset(struct comedi_device *dev)
1142 struct rtd_private *devpriv = dev->private;
1144 writel(0, dev->mmio + LAS0_BOARD_RESET);
1145 udelay(100); /* needed? */
1146 writel(0, devpriv->lcfg + PLX_INTRCS_REG);
1147 writew(0, dev->mmio + LAS0_IT);
1148 writew(~0, dev->mmio + LAS0_CLEAR);
1149 readw(dev->mmio + LAS0_CLEAR);
1153 * initialize board, per RTD spec
1154 * also, initialize shadow registers
1156 static void rtd_init_board(struct comedi_device *dev)
1160 writel(0, dev->mmio + LAS0_OVERRUN);
1161 writel(0, dev->mmio + LAS0_CGT_CLEAR);
1162 writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR);
1163 writel(0, dev->mmio + LAS0_DAC1_RESET);
1164 writel(0, dev->mmio + LAS0_DAC2_RESET);
1165 /* clear digital IO fifo */
1166 writew(0, dev->mmio + LAS0_DIO_STATUS);
1167 writeb((0 << 6) | 0x30, dev->mmio + LAS0_UTC_CTRL);
1168 writeb((1 << 6) | 0x30, dev->mmio + LAS0_UTC_CTRL);
1169 writeb((2 << 6) | 0x30, dev->mmio + LAS0_UTC_CTRL);
1170 writeb((3 << 6) | 0x00, dev->mmio + LAS0_UTC_CTRL);
1171 /* TODO: set user out source ??? */
1174 /* The RTD driver does this */
1175 static void rtd_pci_latency_quirk(struct comedi_device *dev,
1176 struct pci_dev *pcidev)
1178 unsigned char pci_latency;
1180 pci_read_config_byte(pcidev, PCI_LATENCY_TIMER, &pci_latency);
1181 if (pci_latency < 32) {
1182 dev_info(dev->class_dev,
1183 "PCI latency changed from %d to %d\n",
1185 pci_write_config_byte(pcidev, PCI_LATENCY_TIMER, 32);
1189 static int rtd_auto_attach(struct comedi_device *dev,
1190 unsigned long context)
1192 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1193 const struct rtd_boardinfo *board = NULL;
1194 struct rtd_private *devpriv;
1195 struct comedi_subdevice *s;
1198 if (context < ARRAY_SIZE(rtd520Boards))
1199 board = &rtd520Boards[context];
1202 dev->board_ptr = board;
1203 dev->board_name = board->name;
1205 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
1209 ret = comedi_pci_enable(dev);
1213 dev->mmio = pci_ioremap_bar(pcidev, 2);
1214 devpriv->las1 = pci_ioremap_bar(pcidev, 3);
1215 devpriv->lcfg = pci_ioremap_bar(pcidev, 0);
1216 if (!dev->mmio || !devpriv->las1 || !devpriv->lcfg)
1219 rtd_pci_latency_quirk(dev, pcidev);
1222 ret = request_irq(pcidev->irq, rtd_interrupt, IRQF_SHARED,
1223 dev->board_name, dev);
1225 dev->irq = pcidev->irq;
1228 ret = comedi_alloc_subdevices(dev, 4);
1232 s = &dev->subdevices[0];
1233 /* analog input subdevice */
1234 s->type = COMEDI_SUBD_AI;
1235 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF;
1237 s->maxdata = 0x0fff;
1238 s->range_table = board->ai_range;
1239 s->len_chanlist = RTD_MAX_CHANLIST;
1240 s->insn_read = rtd_ai_rinsn;
1242 dev->read_subdev = s;
1243 s->subdev_flags |= SDF_CMD_READ;
1244 s->do_cmd = rtd_ai_cmd;
1245 s->do_cmdtest = rtd_ai_cmdtest;
1246 s->cancel = rtd_ai_cancel;
1249 s = &dev->subdevices[1];
1250 /* analog output subdevice */
1251 s->type = COMEDI_SUBD_AO;
1252 s->subdev_flags = SDF_WRITABLE;
1254 s->maxdata = 0x0fff;
1255 s->range_table = &rtd_ao_range;
1256 s->insn_write = rtd_ao_winsn;
1258 ret = comedi_alloc_subdev_readback(s);
1262 s = &dev->subdevices[2];
1263 /* digital i/o subdevice */
1264 s->type = COMEDI_SUBD_DIO;
1265 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1266 /* we only support port 0 right now. Ignoring port 1 and user IO */
1269 s->range_table = &range_digital;
1270 s->insn_bits = rtd_dio_insn_bits;
1271 s->insn_config = rtd_dio_insn_config;
1273 /* timer/counter subdevices (not currently supported) */
1274 s = &dev->subdevices[3];
1275 s->type = COMEDI_SUBD_COUNTER;
1276 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1278 s->maxdata = 0xffff;
1280 rtd_init_board(dev);
1282 ret = rtd520_probe_fifo_depth(dev);
1285 devpriv->fifosz = ret;
1288 writel(ICS_PIE | ICS_PLIE, devpriv->lcfg + PLX_INTRCS_REG);
1293 static void rtd_detach(struct comedi_device *dev)
1295 struct rtd_private *devpriv = dev->private;
1298 /* Shut down any board ops by resetting it */
1299 if (dev->mmio && devpriv->lcfg)
1302 free_irq(dev->irq, dev);
1306 iounmap(devpriv->las1);
1308 iounmap(devpriv->lcfg);
1310 comedi_pci_disable(dev);
1313 static struct comedi_driver rtd520_driver = {
1314 .driver_name = "rtd520",
1315 .module = THIS_MODULE,
1316 .auto_attach = rtd_auto_attach,
1317 .detach = rtd_detach,
1320 static int rtd520_pci_probe(struct pci_dev *dev,
1321 const struct pci_device_id *id)
1323 return comedi_pci_auto_config(dev, &rtd520_driver, id->driver_data);
1326 static const struct pci_device_id rtd520_pci_table[] = {
1327 { PCI_VDEVICE(RTD, 0x7520), BOARD_DM7520 },
1328 { PCI_VDEVICE(RTD, 0x4520), BOARD_PCI4520 },
1331 MODULE_DEVICE_TABLE(pci, rtd520_pci_table);
1333 static struct pci_driver rtd520_pci_driver = {
1335 .id_table = rtd520_pci_table,
1336 .probe = rtd520_pci_probe,
1337 .remove = comedi_pci_auto_unconfig,
1339 module_comedi_pci_driver(rtd520_driver, rtd520_pci_driver);
1341 MODULE_AUTHOR("Comedi http://www.comedi.org");
1342 MODULE_DESCRIPTION("Comedi low-level driver");
1343 MODULE_LICENSE("GPL");