2 * comedi/drivers/s626.c
3 * Sensoray s626 Comedi driver
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 2000 David A. Schleef <ds@schleef.org>
8 * Based on Sensoray Model 626 Linux driver Version 0.2
9 * Copyright (C) 2002-2004 Sensoray Co., Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
24 * Description: Sensoray 626 driver
25 * Devices: [Sensoray] 626 (s626)
26 * Authors: Gianluca Palli <gpalli@deis.unibo.it>,
27 * Updated: Fri, 15 Feb 2008 10:28:42 +0000
28 * Status: experimental
30 * Configuration options: not applicable, uses PCI auto config
32 * INSN_CONFIG instructions:
40 * s626 has 3 dio subdevices (2,3 and 4) each with 16 i/o channels
41 * supported configuration options:
42 * INSN_CONFIG_DIO_QUERY
47 * Every channel must be configured before reading.
51 * insn.insn=INSN_CONFIG; //configuration instruction
52 * insn.n=1; //number of operation (must be 1)
53 * insn.data=&initialvalue; //initial value loaded into encoder
54 * //during configuration
55 * insn.subdev=5; //encoder subdevice
56 * insn.chanspec=CR_PACK(encoder_channel,0,AREF_OTHER); //encoder_channel
59 * comedi_do_insn(cf,&insn); //executing configuration
62 #include <linux/module.h>
63 #include <linux/delay.h>
64 #include <linux/pci.h>
65 #include <linux/interrupt.h>
66 #include <linux/kernel.h>
67 #include <linux/types.h>
69 #include "../comedidev.h"
71 #include "comedi_fc.h"
74 struct s626_buffer_dma {
75 dma_addr_t physical_base;
81 uint8_t ai_cmd_running; /* ai_cmd is running */
82 uint8_t ai_continuous; /* continuous acquisition */
83 int ai_sample_count; /* number of samples to acquire */
84 unsigned int ai_sample_timer; /* time between samples in
85 * units of the timer */
86 int ai_convert_count; /* conversion counter */
87 unsigned int ai_convert_timer; /* time between conversion in
88 * units of the timer */
89 uint16_t counter_int_enabs; /* counter interrupt enable mask
90 * for MISC2 register */
91 uint8_t adc_items; /* number of items in ADC poll list */
92 struct s626_buffer_dma rps_buf; /* DMA buffer used to hold ADC (RPS1)
94 struct s626_buffer_dma ana_buf; /* DMA buffer used to receive ADC data
95 * and hold DAC data */
96 uint32_t *dac_wbuf; /* pointer to logical adrs of DMA buffer
97 * used to hold DAC data */
98 uint16_t dacpol; /* image of DAC polarity register */
99 uint8_t trim_setpoint[12]; /* images of TrimDAC setpoints */
100 uint32_t i2c_adrs; /* I2C device address for onboard EEPROM
101 * (board rev dependent) */
102 unsigned int ao_readback[S626_DAC_CHANNELS];
105 /* COUNTER OBJECT ------------------------------------------------ */
106 struct s626_enc_info {
107 /* Pointers to functions that differ for A and B counters: */
108 /* Return clock enable. */
109 uint16_t (*get_enable)(struct comedi_device *dev,
110 const struct s626_enc_info *k);
111 /* Return interrupt source. */
112 uint16_t (*get_int_src)(struct comedi_device *dev,
113 const struct s626_enc_info *k);
114 /* Return preload trigger source. */
115 uint16_t (*get_load_trig)(struct comedi_device *dev,
116 const struct s626_enc_info *k);
117 /* Return standardized operating mode. */
118 uint16_t (*get_mode)(struct comedi_device *dev,
119 const struct s626_enc_info *k);
120 /* Generate soft index strobe. */
121 void (*pulse_index)(struct comedi_device *dev,
122 const struct s626_enc_info *k);
123 /* Program clock enable. */
124 void (*set_enable)(struct comedi_device *dev,
125 const struct s626_enc_info *k, uint16_t enab);
126 /* Program interrupt source. */
127 void (*set_int_src)(struct comedi_device *dev,
128 const struct s626_enc_info *k, uint16_t int_source);
129 /* Program preload trigger source. */
130 void (*set_load_trig)(struct comedi_device *dev,
131 const struct s626_enc_info *k, uint16_t trig);
132 /* Program standardized operating mode. */
133 void (*set_mode)(struct comedi_device *dev,
134 const struct s626_enc_info *k, uint16_t setup,
135 uint16_t disable_int_src);
136 /* Reset event capture flags. */
137 void (*reset_cap_flags)(struct comedi_device *dev,
138 const struct s626_enc_info *k);
140 uint16_t my_cra; /* address of CRA register */
141 uint16_t my_crb; /* address of CRB register */
142 uint16_t my_latch_lsw; /* address of Latch least-significant-word
144 uint16_t my_event_bits[4]; /* bit translations for IntSrc -->RDMISC2 */
147 /* Counter overflow/index event flag masks for RDMISC2. */
148 #define S626_INDXMASK(C) (1 << (((C) > 2) ? ((C) * 2 - 1) : ((C) * 2 + 4)))
149 #define S626_OVERMASK(C) (1 << (((C) > 2) ? ((C) * 2 + 5) : ((C) * 2 + 10)))
150 #define S626_EVBITS(C) { 0, S626_OVERMASK(C), S626_INDXMASK(C), \
151 S626_OVERMASK(C) | S626_INDXMASK(C) }
154 * Translation table to map IntSrc into equivalent RDMISC2 event flag bits.
155 * static const uint16_t s626_event_bits[][4] =
156 * { S626_EVBITS(0), S626_EVBITS(1), S626_EVBITS(2), S626_EVBITS(3),
157 * S626_EVBITS(4), S626_EVBITS(5) };
161 * Enable/disable a function or test status bit(s) that are accessed
162 * through Main Control Registers 1 or 2.
164 static void s626_mc_enable(struct comedi_device *dev,
165 unsigned int cmd, unsigned int reg)
167 struct s626_private *devpriv = dev->private;
168 unsigned int val = (cmd << 16) | cmd;
171 writel(val, devpriv->mmio + reg);
174 static void s626_mc_disable(struct comedi_device *dev,
175 unsigned int cmd, unsigned int reg)
177 struct s626_private *devpriv = dev->private;
179 writel(cmd << 16 , devpriv->mmio + reg);
183 static bool s626_mc_test(struct comedi_device *dev,
184 unsigned int cmd, unsigned int reg)
186 struct s626_private *devpriv = dev->private;
189 val = readl(devpriv->mmio + reg);
191 return (val & cmd) ? true : false;
194 #define S626_BUGFIX_STREG(REGADRS) ((REGADRS) - 4)
196 /* Write a time slot control record to TSL2. */
197 #define S626_VECTPORT(VECTNUM) (S626_P_TSL2 + ((VECTNUM) << 2))
199 static const struct comedi_lrange s626_range_table = {
207 * Execute a DEBI transfer. This must be called from within a critical section.
209 static void s626_debi_transfer(struct comedi_device *dev)
211 struct s626_private *devpriv = dev->private;
212 static const int timeout = 10000;
215 /* Initiate upload of shadow RAM to DEBI control register */
216 s626_mc_enable(dev, S626_MC2_UPLD_DEBI, S626_P_MC2);
219 * Wait for completion of upload from shadow RAM to
220 * DEBI control register.
222 for (i = 0; i < timeout; i++) {
223 if (s626_mc_test(dev, S626_MC2_UPLD_DEBI, S626_P_MC2))
229 "Timeout while uploading to DEBI control register.");
231 /* Wait until DEBI transfer is done */
232 for (i = 0; i < timeout; i++) {
233 if (!(readl(devpriv->mmio + S626_P_PSR) & S626_PSR_DEBI_S))
238 comedi_error(dev, "DEBI transfer timeout.");
242 * Read a value from a gate array register.
244 static uint16_t s626_debi_read(struct comedi_device *dev, uint16_t addr)
246 struct s626_private *devpriv = dev->private;
248 /* Set up DEBI control register value in shadow RAM */
249 writel(S626_DEBI_CMD_RDWORD | addr, devpriv->mmio + S626_P_DEBICMD);
251 /* Execute the DEBI transfer. */
252 s626_debi_transfer(dev);
254 return readl(devpriv->mmio + S626_P_DEBIAD);
258 * Write a value to a gate array register.
260 static void s626_debi_write(struct comedi_device *dev, uint16_t addr,
263 struct s626_private *devpriv = dev->private;
265 /* Set up DEBI control register value in shadow RAM */
266 writel(S626_DEBI_CMD_WRWORD | addr, devpriv->mmio + S626_P_DEBICMD);
267 writel(wdata, devpriv->mmio + S626_P_DEBIAD);
269 /* Execute the DEBI transfer. */
270 s626_debi_transfer(dev);
274 * Replace the specified bits in a gate array register. Imports: mask
275 * specifies bits that are to be preserved, wdata is new value to be
276 * or'd with the masked original.
278 static void s626_debi_replace(struct comedi_device *dev, unsigned int addr,
279 unsigned int mask, unsigned int wdata)
281 struct s626_private *devpriv = dev->private;
285 writel(S626_DEBI_CMD_RDWORD | addr, devpriv->mmio + S626_P_DEBICMD);
286 s626_debi_transfer(dev);
288 writel(S626_DEBI_CMD_WRWORD | addr, devpriv->mmio + S626_P_DEBICMD);
289 val = readl(devpriv->mmio + S626_P_DEBIAD);
292 writel(val & 0xffff, devpriv->mmio + S626_P_DEBIAD);
293 s626_debi_transfer(dev);
296 /* ************** EEPROM ACCESS FUNCTIONS ************** */
298 static uint32_t s626_i2c_handshake(struct comedi_device *dev, uint32_t val)
300 struct s626_private *devpriv = dev->private;
303 /* Write I2C command to I2C Transfer Control shadow register */
304 writel(val, devpriv->mmio + S626_P_I2CCTRL);
307 * Upload I2C shadow registers into working registers and
308 * wait for upload confirmation.
310 s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
311 while (!s626_mc_test(dev, S626_MC2_UPLD_IIC, S626_P_MC2))
314 /* Wait until I2C bus transfer is finished or an error occurs */
316 ctrl = readl(devpriv->mmio + S626_P_I2CCTRL);
317 } while ((ctrl & (S626_I2C_BUSY | S626_I2C_ERR)) == S626_I2C_BUSY);
319 /* Return non-zero if I2C error occurred */
320 return ctrl & S626_I2C_ERR;
323 /* Read uint8_t from EEPROM. */
324 static uint8_t s626_i2c_read(struct comedi_device *dev, uint8_t addr)
326 struct s626_private *devpriv = dev->private;
329 * Send EEPROM target address:
330 * Byte2 = I2C command: write to I2C EEPROM device.
331 * Byte1 = EEPROM internal target address.
334 if (s626_i2c_handshake(dev, S626_I2C_B2(S626_I2C_ATTRSTART,
336 S626_I2C_B1(S626_I2C_ATTRSTOP, addr) |
337 S626_I2C_B0(S626_I2C_ATTRNOP, 0)))
338 /* Abort function and declare error if handshake failed. */
342 * Execute EEPROM read:
343 * Byte2 = I2C command: read from I2C EEPROM device.
344 * Byte1 receives uint8_t from EEPROM.
347 if (s626_i2c_handshake(dev, S626_I2C_B2(S626_I2C_ATTRSTART,
348 (devpriv->i2c_adrs | 1)) |
349 S626_I2C_B1(S626_I2C_ATTRSTOP, 0) |
350 S626_I2C_B0(S626_I2C_ATTRNOP, 0)))
351 /* Abort function and declare error if handshake failed. */
354 return (readl(devpriv->mmio + S626_P_I2CCTRL) >> 16) & 0xff;
357 /* *********** DAC FUNCTIONS *********** */
359 /* TrimDac LogicalChan-to-PhysicalChan mapping table. */
360 static const uint8_t s626_trimchan[] = { 10, 9, 8, 3, 2, 7, 6, 1, 0, 5, 4 };
362 /* TrimDac LogicalChan-to-EepromAdrs mapping table. */
363 static const uint8_t s626_trimadrs[] = {
364 0x40, 0x41, 0x42, 0x50, 0x51, 0x52, 0x53, 0x60, 0x61, 0x62, 0x63
368 s626_send_dac_wait_not_mc1_a2out,
369 s626_send_dac_wait_ssr_af2_out,
370 s626_send_dac_wait_fb_buffer2_msb_00,
371 s626_send_dac_wait_fb_buffer2_msb_ff
374 static int s626_send_dac_eoc(struct comedi_device *dev,
375 struct comedi_subdevice *s,
376 struct comedi_insn *insn,
377 unsigned long context)
379 struct s626_private *devpriv = dev->private;
383 case s626_send_dac_wait_not_mc1_a2out:
384 status = readl(devpriv->mmio + S626_P_MC1);
385 if (!(status & S626_MC1_A2OUT))
388 case s626_send_dac_wait_ssr_af2_out:
389 status = readl(devpriv->mmio + S626_P_SSR);
390 if (status & S626_SSR_AF2_OUT)
393 case s626_send_dac_wait_fb_buffer2_msb_00:
394 status = readl(devpriv->mmio + S626_P_FB_BUFFER2);
395 if (!(status & 0xff000000))
398 case s626_send_dac_wait_fb_buffer2_msb_ff:
399 status = readl(devpriv->mmio + S626_P_FB_BUFFER2);
400 if (status & 0xff000000)
410 * Private helper function: Transmit serial data to DAC via Audio
411 * channel 2. Assumes: (1) TSL2 slot records initialized, and (2)
412 * dacpol contains valid target image.
414 static int s626_send_dac(struct comedi_device *dev, uint32_t val)
416 struct s626_private *devpriv = dev->private;
419 /* START THE SERIAL CLOCK RUNNING ------------- */
422 * Assert DAC polarity control and enable gating of DAC serial clock
423 * and audio bit stream signals. At this point in time we must be
424 * assured of being in time slot 0. If we are not in slot 0, the
425 * serial clock and audio stream signals will be disabled; this is
426 * because the following s626_debi_write statement (which enables
427 * signals to be passed through the gate array) would execute before
428 * the trailing edge of WS1/WS3 (which turns off the signals), thus
429 * causing the signals to be inactive during the DAC write.
431 s626_debi_write(dev, S626_LP_DACPOL, devpriv->dacpol);
433 /* TRANSFER OUTPUT DWORD VALUE INTO A2'S OUTPUT FIFO ---------------- */
435 /* Copy DAC setpoint value to DAC's output DMA buffer. */
436 /* writel(val, devpriv->mmio + (uint32_t)devpriv->dac_wbuf); */
437 *devpriv->dac_wbuf = val;
440 * Enable the output DMA transfer. This will cause the DMAC to copy
441 * the DAC's data value to A2's output FIFO. The DMA transfer will
442 * then immediately terminate because the protection address is
443 * reached upon transfer of the first DWORD value.
445 s626_mc_enable(dev, S626_MC1_A2OUT, S626_P_MC1);
447 /* While the DMA transfer is executing ... */
450 * Reset Audio2 output FIFO's underflow flag (along with any
451 * other FIFO underflow/overflow flags). When set, this flag
452 * will indicate that we have emerged from slot 0.
454 writel(S626_ISR_AFOU, devpriv->mmio + S626_P_ISR);
457 * Wait for the DMA transfer to finish so that there will be data
458 * available in the FIFO when time slot 1 tries to transfer a DWORD
459 * from the FIFO to the output buffer register. We test for DMA
460 * Done by polling the DMAC enable flag; this flag is automatically
461 * cleared when the transfer has finished.
463 ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc,
464 s626_send_dac_wait_not_mc1_a2out);
466 comedi_error(dev, "DMA transfer timeout.");
470 /* START THE OUTPUT STREAM TO THE TARGET DAC -------------------- */
473 * FIFO data is now available, so we enable execution of time slots
474 * 1 and higher by clearing the EOS flag in slot 0. Note that SD3
475 * will be shifted in and stored in FB_BUFFER2 for end-of-slot-list
478 writel(S626_XSD2 | S626_RSD3 | S626_SIB_A2,
479 devpriv->mmio + S626_VECTPORT(0));
482 * Wait for slot 1 to execute to ensure that the Packet will be
483 * transmitted. This is detected by polling the Audio2 output FIFO
484 * underflow flag, which will be set when slot 1 execution has
485 * finished transferring the DAC's data DWORD from the output FIFO
486 * to the output buffer register.
488 ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc,
489 s626_send_dac_wait_ssr_af2_out);
491 comedi_error(dev, "TSL timeout waiting for slot 1 to execute.");
496 * Set up to trap execution at slot 0 when the TSL sequencer cycles
497 * back to slot 0 after executing the EOS in slot 5. Also,
498 * simultaneously shift out and in the 0x00 that is ALWAYS the value
499 * stored in the last byte to be shifted out of the FIFO's DWORD
502 writel(S626_XSD2 | S626_XFIFO_2 | S626_RSD2 | S626_SIB_A2 | S626_EOS,
503 devpriv->mmio + S626_VECTPORT(0));
505 /* WAIT FOR THE TRANSACTION TO FINISH ----------------------- */
508 * Wait for the TSL to finish executing all time slots before
509 * exiting this function. We must do this so that the next DAC
510 * write doesn't start, thereby enabling clock/chip select signals:
512 * 1. Before the TSL sequence cycles back to slot 0, which disables
513 * the clock/cs signal gating and traps slot // list execution.
514 * we have not yet finished slot 5 then the clock/cs signals are
515 * still gated and we have not finished transmitting the stream.
517 * 2. While slots 2-5 are executing due to a late slot 0 trap. In
518 * this case, the slot sequence is currently repeating, but with
519 * clock/cs signals disabled. We must wait for slot 0 to trap
520 * execution before setting up the next DAC setpoint DMA transfer
521 * and enabling the clock/cs signals. To detect the end of slot 5,
522 * we test for the FB_BUFFER2 MSB contents to be equal to 0xFF. If
523 * the TSL has not yet finished executing slot 5 ...
525 if (readl(devpriv->mmio + S626_P_FB_BUFFER2) & 0xff000000) {
527 * The trap was set on time and we are still executing somewhere
528 * in slots 2-5, so we now wait for slot 0 to execute and trap
529 * TSL execution. This is detected when FB_BUFFER2 MSB changes
530 * from 0xFF to 0x00, which slot 0 causes to happen by shifting
531 * out/in on SD2 the 0x00 that is always referenced by slot 5.
533 ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc,
534 s626_send_dac_wait_fb_buffer2_msb_00);
537 "TSL timeout waiting for slot 0 to execute.");
542 * Either (1) we were too late setting the slot 0 trap; the TSL
543 * sequencer restarted slot 0 before we could set the EOS trap flag,
544 * or (2) we were not late and execution is now trapped at slot 0.
545 * In either case, we must now change slot 0 so that it will store
546 * value 0xFF (instead of 0x00) to FB_BUFFER2 next time it executes.
547 * In order to do this, we reprogram slot 0 so that it will shift in
548 * SD3, which is driven only by a pull-up resistor.
550 writel(S626_RSD3 | S626_SIB_A2 | S626_EOS,
551 devpriv->mmio + S626_VECTPORT(0));
554 * Wait for slot 0 to execute, at which time the TSL is setup for
555 * the next DAC write. This is detected when FB_BUFFER2 MSB changes
558 ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc,
559 s626_send_dac_wait_fb_buffer2_msb_ff);
561 comedi_error(dev, "TSL timeout waiting for slot 0 to execute.");
568 * Private helper function: Write setpoint to an application DAC channel.
570 static int s626_set_dac(struct comedi_device *dev, uint16_t chan,
573 struct s626_private *devpriv = dev->private;
579 * Adjust DAC data polarity and set up Polarity Control Register image.
581 signmask = 1 << chan;
584 devpriv->dacpol |= signmask;
586 devpriv->dacpol &= ~signmask;
589 /* Limit DAC setpoint value to valid range. */
590 if ((uint16_t)dacdata > 0x1FFF)
594 * Set up TSL2 records (aka "vectors") for DAC update. Vectors V2
595 * and V3 transmit the setpoint to the target DAC. V4 and V5 send
596 * data to a non-existent TrimDac channel just to keep the clock
597 * running after sending data to the target DAC. This is necessary
598 * to eliminate the clock glitch that would otherwise occur at the
599 * end of the target DAC's serial data stream. When the sequence
600 * restarts at V0 (after executing V5), the gate array automatically
601 * disables gating for the DAC clock and all DAC chip selects.
604 /* Choose DAC chip select to be asserted */
605 ws_image = (chan & 2) ? S626_WS1 : S626_WS2;
606 /* Slot 2: Transmit high data byte to target DAC */
607 writel(S626_XSD2 | S626_XFIFO_1 | ws_image,
608 devpriv->mmio + S626_VECTPORT(2));
609 /* Slot 3: Transmit low data byte to target DAC */
610 writel(S626_XSD2 | S626_XFIFO_0 | ws_image,
611 devpriv->mmio + S626_VECTPORT(3));
612 /* Slot 4: Transmit to non-existent TrimDac channel to keep clock */
613 writel(S626_XSD2 | S626_XFIFO_3 | S626_WS3,
614 devpriv->mmio + S626_VECTPORT(4));
615 /* Slot 5: running after writing target DAC's low data byte */
616 writel(S626_XSD2 | S626_XFIFO_2 | S626_WS3 | S626_EOS,
617 devpriv->mmio + S626_VECTPORT(5));
620 * Construct and transmit target DAC's serial packet:
621 * (A10D DDDD), (DDDD DDDD), (0x0F), (0x00) where A is chan<0>,
622 * and D<12:0> is the DAC setpoint. Append a WORD value (that writes
623 * to a non-existent TrimDac channel) that serves to keep the clock
624 * running after the packet has been sent to the target DAC.
626 val = 0x0F000000; /* Continue clock after target DAC data
627 * (write to non-existent trimdac). */
628 val |= 0x00004000; /* Address the two main dual-DAC devices
629 * (TSL's chip select enables target device). */
630 val |= ((uint32_t)(chan & 1) << 15); /* Address the DAC channel
631 * within the device. */
632 val |= (uint32_t)dacdata; /* Include DAC setpoint data. */
633 return s626_send_dac(dev, val);
636 static int s626_write_trim_dac(struct comedi_device *dev, uint8_t logical_chan,
639 struct s626_private *devpriv = dev->private;
643 * Save the new setpoint in case the application needs to read it back
646 devpriv->trim_setpoint[logical_chan] = (uint8_t)dac_data;
648 /* Map logical channel number to physical channel number. */
649 chan = s626_trimchan[logical_chan];
652 * Set up TSL2 records for TrimDac write operation. All slots shift
653 * 0xFF in from pulled-up SD3 so that the end of the slot sequence
657 /* Slot 2: Send high uint8_t to target TrimDac */
658 writel(S626_XSD2 | S626_XFIFO_1 | S626_WS3,
659 devpriv->mmio + S626_VECTPORT(2));
660 /* Slot 3: Send low uint8_t to target TrimDac */
661 writel(S626_XSD2 | S626_XFIFO_0 | S626_WS3,
662 devpriv->mmio + S626_VECTPORT(3));
663 /* Slot 4: Send NOP high uint8_t to DAC0 to keep clock running */
664 writel(S626_XSD2 | S626_XFIFO_3 | S626_WS1,
665 devpriv->mmio + S626_VECTPORT(4));
666 /* Slot 5: Send NOP low uint8_t to DAC0 */
667 writel(S626_XSD2 | S626_XFIFO_2 | S626_WS1 | S626_EOS,
668 devpriv->mmio + S626_VECTPORT(5));
671 * Construct and transmit target DAC's serial packet:
672 * (0000 AAAA), (DDDD DDDD), (0x00), (0x00) where A<3:0> is the
673 * DAC channel's address, and D<7:0> is the DAC setpoint. Append a
674 * WORD value (that writes a channel 0 NOP command to a non-existent
675 * main DAC channel) that serves to keep the clock running after the
676 * packet has been sent to the target DAC.
680 * Address the DAC channel within the trimdac device.
681 * Include DAC setpoint data.
683 return s626_send_dac(dev, (chan << 8) | dac_data);
686 static int s626_load_trim_dacs(struct comedi_device *dev)
691 /* Copy TrimDac setpoint values from EEPROM to TrimDacs. */
692 for (i = 0; i < ARRAY_SIZE(s626_trimchan); i++) {
693 ret = s626_write_trim_dac(dev, i,
694 s626_i2c_read(dev, s626_trimadrs[i]));
701 /* ****** COUNTER FUNCTIONS ******* */
704 * All counter functions address a specific counter by means of the
705 * "Counter" argument, which is a logical counter number. The Counter
706 * argument may have any of the following legal values: 0=0A, 1=1A,
707 * 2=2A, 3=0B, 4=1B, 5=2B.
711 * Read a counter's output latch.
713 static uint32_t s626_read_latch(struct comedi_device *dev,
714 const struct s626_enc_info *k)
718 /* Latch counts and fetch LSW of latched counts value. */
719 value = s626_debi_read(dev, k->my_latch_lsw);
721 /* Fetch MSW of latched counts and combine with LSW. */
722 value |= ((uint32_t)s626_debi_read(dev, k->my_latch_lsw + 2) << 16);
724 /* Return latched counts. */
729 * Return/set a counter pair's latch trigger source. 0: On read
730 * access, 1: A index latches A, 2: B index latches B, 3: A overflow
733 static void s626_set_latch_source(struct comedi_device *dev,
734 const struct s626_enc_info *k, uint16_t value)
736 s626_debi_replace(dev, k->my_crb,
737 ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_LATCHSRC),
738 S626_SET_CRB_LATCHSRC(value));
742 * Write value into counter preload register.
744 static void s626_preload(struct comedi_device *dev,
745 const struct s626_enc_info *k, uint32_t value)
747 s626_debi_write(dev, k->my_latch_lsw, value);
748 s626_debi_write(dev, k->my_latch_lsw + 2, value >> 16);
751 /* ****** PRIVATE COUNTER FUNCTIONS ****** */
754 * Reset a counter's index and overflow event capture flags.
756 static void s626_reset_cap_flags_a(struct comedi_device *dev,
757 const struct s626_enc_info *k)
759 s626_debi_replace(dev, k->my_crb, ~S626_CRBMSK_INTCTRL,
760 (S626_SET_CRB_INTRESETCMD(1) |
761 S626_SET_CRB_INTRESET_A(1)));
764 static void s626_reset_cap_flags_b(struct comedi_device *dev,
765 const struct s626_enc_info *k)
767 s626_debi_replace(dev, k->my_crb, ~S626_CRBMSK_INTCTRL,
768 (S626_SET_CRB_INTRESETCMD(1) |
769 S626_SET_CRB_INTRESET_B(1)));
773 * Return counter setup in a format (COUNTER_SETUP) that is consistent
774 * for both A and B counters.
776 static uint16_t s626_get_mode_a(struct comedi_device *dev,
777 const struct s626_enc_info *k)
782 unsigned cntsrc, clkmult, clkpol, encmode;
784 /* Fetch CRA and CRB register images. */
785 cra = s626_debi_read(dev, k->my_cra);
786 crb = s626_debi_read(dev, k->my_crb);
789 * Populate the standardized counter setup bit fields.
792 /* LoadSrc = LoadSrcA. */
793 S626_SET_STD_LOADSRC(S626_GET_CRA_LOADSRC_A(cra)) |
794 /* LatchSrc = LatchSrcA. */
795 S626_SET_STD_LATCHSRC(S626_GET_CRB_LATCHSRC(crb)) |
796 /* IntSrc = IntSrcA. */
797 S626_SET_STD_INTSRC(S626_GET_CRA_INTSRC_A(cra)) |
798 /* IndxSrc = IndxSrcA. */
799 S626_SET_STD_INDXSRC(S626_GET_CRA_INDXSRC_A(cra)) |
800 /* IndxPol = IndxPolA. */
801 S626_SET_STD_INDXPOL(S626_GET_CRA_INDXPOL_A(cra)) |
802 /* ClkEnab = ClkEnabA. */
803 S626_SET_STD_CLKENAB(S626_GET_CRB_CLKENAB_A(crb));
805 /* Adjust mode-dependent parameters. */
806 cntsrc = S626_GET_CRA_CNTSRC_A(cra);
807 if (cntsrc & S626_CNTSRC_SYSCLK) {
808 /* Timer mode (CntSrcA<1> == 1): */
809 encmode = S626_ENCMODE_TIMER;
810 /* Set ClkPol to indicate count direction (CntSrcA<0>). */
812 /* ClkMult must be 1x in Timer mode. */
813 clkmult = S626_CLKMULT_1X;
815 /* Counter mode (CntSrcA<1> == 0): */
816 encmode = S626_ENCMODE_COUNTER;
817 /* Pass through ClkPol. */
818 clkpol = S626_GET_CRA_CLKPOL_A(cra);
819 /* Force ClkMult to 1x if not legal, else pass through. */
820 clkmult = S626_GET_CRA_CLKMULT_A(cra);
821 if (clkmult == S626_CLKMULT_SPECIAL)
822 clkmult = S626_CLKMULT_1X;
824 setup |= S626_SET_STD_ENCMODE(encmode) | S626_SET_STD_CLKMULT(clkmult) |
825 S626_SET_STD_CLKPOL(clkpol);
827 /* Return adjusted counter setup. */
831 static uint16_t s626_get_mode_b(struct comedi_device *dev,
832 const struct s626_enc_info *k)
837 unsigned cntsrc, clkmult, clkpol, encmode;
839 /* Fetch CRA and CRB register images. */
840 cra = s626_debi_read(dev, k->my_cra);
841 crb = s626_debi_read(dev, k->my_crb);
844 * Populate the standardized counter setup bit fields.
847 /* IntSrc = IntSrcB. */
848 S626_SET_STD_INTSRC(S626_GET_CRB_INTSRC_B(crb)) |
849 /* LatchSrc = LatchSrcB. */
850 S626_SET_STD_LATCHSRC(S626_GET_CRB_LATCHSRC(crb)) |
851 /* LoadSrc = LoadSrcB. */
852 S626_SET_STD_LOADSRC(S626_GET_CRB_LOADSRC_B(crb)) |
853 /* IndxPol = IndxPolB. */
854 S626_SET_STD_INDXPOL(S626_GET_CRB_INDXPOL_B(crb)) |
855 /* ClkEnab = ClkEnabB. */
856 S626_SET_STD_CLKENAB(S626_GET_CRB_CLKENAB_B(crb)) |
857 /* IndxSrc = IndxSrcB. */
858 S626_SET_STD_INDXSRC(S626_GET_CRA_INDXSRC_B(cra));
860 /* Adjust mode-dependent parameters. */
861 cntsrc = S626_GET_CRA_CNTSRC_B(cra);
862 clkmult = S626_GET_CRB_CLKMULT_B(crb);
863 if (clkmult == S626_CLKMULT_SPECIAL) {
864 /* Extender mode (ClkMultB == S626_CLKMULT_SPECIAL): */
865 encmode = S626_ENCMODE_EXTENDER;
866 /* Indicate multiplier is 1x. */
867 clkmult = S626_CLKMULT_1X;
868 /* Set ClkPol equal to Timer count direction (CntSrcB<0>). */
870 } else if (cntsrc & S626_CNTSRC_SYSCLK) {
871 /* Timer mode (CntSrcB<1> == 1): */
872 encmode = S626_ENCMODE_TIMER;
873 /* Indicate multiplier is 1x. */
874 clkmult = S626_CLKMULT_1X;
875 /* Set ClkPol equal to Timer count direction (CntSrcB<0>). */
878 /* If Counter mode (CntSrcB<1> == 0): */
879 encmode = S626_ENCMODE_COUNTER;
880 /* Clock multiplier is passed through. */
881 /* Clock polarity is passed through. */
882 clkpol = S626_GET_CRB_CLKPOL_B(crb);
884 setup |= S626_SET_STD_ENCMODE(encmode) | S626_SET_STD_CLKMULT(clkmult) |
885 S626_SET_STD_CLKPOL(clkpol);
887 /* Return adjusted counter setup. */
892 * Set the operating mode for the specified counter. The setup
893 * parameter is treated as a COUNTER_SETUP data type. The following
894 * parameters are programmable (all other parms are ignored): ClkMult,
895 * ClkPol, ClkEnab, IndexSrc, IndexPol, LoadSrc.
897 static void s626_set_mode_a(struct comedi_device *dev,
898 const struct s626_enc_info *k, uint16_t setup,
899 uint16_t disable_int_src)
901 struct s626_private *devpriv = dev->private;
904 unsigned cntsrc, clkmult, clkpol;
906 /* Initialize CRA and CRB images. */
907 /* Preload trigger is passed through. */
908 cra = S626_SET_CRA_LOADSRC_A(S626_GET_STD_LOADSRC(setup));
909 /* IndexSrc is passed through. */
910 cra |= S626_SET_CRA_INDXSRC_A(S626_GET_STD_INDXSRC(setup));
912 /* Reset any pending CounterA event captures. */
913 crb = S626_SET_CRB_INTRESETCMD(1) | S626_SET_CRB_INTRESET_A(1);
914 /* Clock enable is passed through. */
915 crb |= S626_SET_CRB_CLKENAB_A(S626_GET_STD_CLKENAB(setup));
917 /* Force IntSrc to Disabled if disable_int_src is asserted. */
918 if (!disable_int_src)
919 cra |= S626_SET_CRA_INTSRC_A(S626_GET_STD_INTSRC(setup));
921 /* Populate all mode-dependent attributes of CRA & CRB images. */
922 clkpol = S626_GET_STD_CLKPOL(setup);
923 switch (S626_GET_STD_ENCMODE(setup)) {
924 case S626_ENCMODE_EXTENDER: /* Extender Mode: */
925 /* Force to Timer mode (Extender valid only for B counters). */
926 /* Fall through to case S626_ENCMODE_TIMER: */
927 case S626_ENCMODE_TIMER: /* Timer Mode: */
928 /* CntSrcA<1> selects system clock */
929 cntsrc = S626_CNTSRC_SYSCLK;
930 /* Count direction (CntSrcA<0>) obtained from ClkPol. */
932 /* ClkPolA behaves as always-on clock enable. */
934 /* ClkMult must be 1x. */
935 clkmult = S626_CLKMULT_1X;
937 default: /* Counter Mode: */
938 /* Select ENC_C and ENC_D as clock/direction inputs. */
939 cntsrc = S626_CNTSRC_ENCODER;
940 /* Clock polarity is passed through. */
941 /* Force multiplier to x1 if not legal, else pass through. */
942 clkmult = S626_GET_STD_CLKMULT(setup);
943 if (clkmult == S626_CLKMULT_SPECIAL)
944 clkmult = S626_CLKMULT_1X;
947 cra |= S626_SET_CRA_CNTSRC_A(cntsrc) | S626_SET_CRA_CLKPOL_A(clkpol) |
948 S626_SET_CRA_CLKMULT_A(clkmult);
951 * Force positive index polarity if IndxSrc is software-driven only,
952 * otherwise pass it through.
954 if (S626_GET_STD_INDXSRC(setup) != S626_INDXSRC_SOFT)
955 cra |= S626_SET_CRA_INDXPOL_A(S626_GET_STD_INDXPOL(setup));
958 * If IntSrc has been forced to Disabled, update the MISC2 interrupt
959 * enable mask to indicate the counter interrupt is disabled.
962 devpriv->counter_int_enabs &= ~k->my_event_bits[3];
965 * While retaining CounterB and LatchSrc configurations, program the
966 * new counter operating mode.
968 s626_debi_replace(dev, k->my_cra,
969 S626_CRAMSK_INDXSRC_B | S626_CRAMSK_CNTSRC_B, cra);
970 s626_debi_replace(dev, k->my_crb,
971 ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_CLKENAB_A), crb);
974 static void s626_set_mode_b(struct comedi_device *dev,
975 const struct s626_enc_info *k, uint16_t setup,
976 uint16_t disable_int_src)
978 struct s626_private *devpriv = dev->private;
981 unsigned cntsrc, clkmult, clkpol;
983 /* Initialize CRA and CRB images. */
984 /* IndexSrc is passed through. */
985 cra = S626_SET_CRA_INDXSRC_B(S626_GET_STD_INDXSRC(setup));
987 /* Reset event captures and disable interrupts. */
988 crb = S626_SET_CRB_INTRESETCMD(1) | S626_SET_CRB_INTRESET_B(1);
989 /* Clock enable is passed through. */
990 crb |= S626_SET_CRB_CLKENAB_B(S626_GET_STD_CLKENAB(setup));
991 /* Preload trigger source is passed through. */
992 crb |= S626_SET_CRB_LOADSRC_B(S626_GET_STD_LOADSRC(setup));
994 /* Force IntSrc to Disabled if disable_int_src is asserted. */
995 if (!disable_int_src)
996 crb |= S626_SET_CRB_INTSRC_B(S626_GET_STD_INTSRC(setup));
998 /* Populate all mode-dependent attributes of CRA & CRB images. */
999 clkpol = S626_GET_STD_CLKPOL(setup);
1000 switch (S626_GET_STD_ENCMODE(setup)) {
1001 case S626_ENCMODE_TIMER: /* Timer Mode: */
1002 /* CntSrcB<1> selects system clock */
1003 cntsrc = S626_CNTSRC_SYSCLK;
1004 /* with direction (CntSrcB<0>) obtained from ClkPol. */
1006 /* ClkPolB behaves as always-on clock enable. */
1008 /* ClkMultB must be 1x. */
1009 clkmult = S626_CLKMULT_1X;
1011 case S626_ENCMODE_EXTENDER: /* Extender Mode: */
1012 /* CntSrcB source is OverflowA (same as "timer") */
1013 cntsrc = S626_CNTSRC_SYSCLK;
1014 /* with direction obtained from ClkPol. */
1016 /* ClkPolB controls IndexB -- always set to active. */
1018 /* ClkMultB selects OverflowA as the clock source. */
1019 clkmult = S626_CLKMULT_SPECIAL;
1021 default: /* Counter Mode: */
1022 /* Select ENC_C and ENC_D as clock/direction inputs. */
1023 cntsrc = S626_CNTSRC_ENCODER;
1024 /* ClkPol is passed through. */
1025 /* Force ClkMult to x1 if not legal, otherwise pass through. */
1026 clkmult = S626_GET_STD_CLKMULT(setup);
1027 if (clkmult == S626_CLKMULT_SPECIAL)
1028 clkmult = S626_CLKMULT_1X;
1031 cra |= S626_SET_CRA_CNTSRC_B(cntsrc);
1032 crb |= S626_SET_CRB_CLKPOL_B(clkpol) | S626_SET_CRB_CLKMULT_B(clkmult);
1035 * Force positive index polarity if IndxSrc is software-driven only,
1036 * otherwise pass it through.
1038 if (S626_GET_STD_INDXSRC(setup) != S626_INDXSRC_SOFT)
1039 crb |= S626_SET_CRB_INDXPOL_B(S626_GET_STD_INDXPOL(setup));
1042 * If IntSrc has been forced to Disabled, update the MISC2 interrupt
1043 * enable mask to indicate the counter interrupt is disabled.
1045 if (disable_int_src)
1046 devpriv->counter_int_enabs &= ~k->my_event_bits[3];
1049 * While retaining CounterA and LatchSrc configurations, program the
1050 * new counter operating mode.
1052 s626_debi_replace(dev, k->my_cra,
1053 ~(S626_CRAMSK_INDXSRC_B | S626_CRAMSK_CNTSRC_B), cra);
1054 s626_debi_replace(dev, k->my_crb,
1055 S626_CRBMSK_CLKENAB_A | S626_CRBMSK_LATCHSRC, crb);
1059 * Return/set a counter's enable. enab: 0=always enabled, 1=enabled by index.
1061 static void s626_set_enable_a(struct comedi_device *dev,
1062 const struct s626_enc_info *k, uint16_t enab)
1064 s626_debi_replace(dev, k->my_crb,
1065 ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_CLKENAB_A),
1066 S626_SET_CRB_CLKENAB_A(enab));
1069 static void s626_set_enable_b(struct comedi_device *dev,
1070 const struct s626_enc_info *k, uint16_t enab)
1072 s626_debi_replace(dev, k->my_crb,
1073 ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_CLKENAB_B),
1074 S626_SET_CRB_CLKENAB_B(enab));
1077 static uint16_t s626_get_enable_a(struct comedi_device *dev,
1078 const struct s626_enc_info *k)
1080 return S626_GET_CRB_CLKENAB_A(s626_debi_read(dev, k->my_crb));
1083 static uint16_t s626_get_enable_b(struct comedi_device *dev,
1084 const struct s626_enc_info *k)
1086 return S626_GET_CRB_CLKENAB_B(s626_debi_read(dev, k->my_crb));
1090 static uint16_t s626_get_latch_source(struct comedi_device *dev,
1091 const struct s626_enc_info *k)
1093 return S626_GET_CRB_LATCHSRC(s626_debi_read(dev, k->my_crb));
1098 * Return/set the event that will trigger transfer of the preload
1099 * register into the counter. 0=ThisCntr_Index, 1=ThisCntr_Overflow,
1100 * 2=OverflowA (B counters only), 3=disabled.
1102 static void s626_set_load_trig_a(struct comedi_device *dev,
1103 const struct s626_enc_info *k, uint16_t trig)
1105 s626_debi_replace(dev, k->my_cra, ~S626_CRAMSK_LOADSRC_A,
1106 S626_SET_CRA_LOADSRC_A(trig));
1109 static void s626_set_load_trig_b(struct comedi_device *dev,
1110 const struct s626_enc_info *k, uint16_t trig)
1112 s626_debi_replace(dev, k->my_crb,
1113 ~(S626_CRBMSK_LOADSRC_B | S626_CRBMSK_INTCTRL),
1114 S626_SET_CRB_LOADSRC_B(trig));
1117 static uint16_t s626_get_load_trig_a(struct comedi_device *dev,
1118 const struct s626_enc_info *k)
1120 return S626_GET_CRA_LOADSRC_A(s626_debi_read(dev, k->my_cra));
1123 static uint16_t s626_get_load_trig_b(struct comedi_device *dev,
1124 const struct s626_enc_info *k)
1126 return S626_GET_CRB_LOADSRC_B(s626_debi_read(dev, k->my_crb));
1130 * Return/set counter interrupt source and clear any captured
1131 * index/overflow events. int_source: 0=Disabled, 1=OverflowOnly,
1132 * 2=IndexOnly, 3=IndexAndOverflow.
1134 static void s626_set_int_src_a(struct comedi_device *dev,
1135 const struct s626_enc_info *k,
1136 uint16_t int_source)
1138 struct s626_private *devpriv = dev->private;
1140 /* Reset any pending counter overflow or index captures. */
1141 s626_debi_replace(dev, k->my_crb, ~S626_CRBMSK_INTCTRL,
1142 (S626_SET_CRB_INTRESETCMD(1) |
1143 S626_SET_CRB_INTRESET_A(1)));
1145 /* Program counter interrupt source. */
1146 s626_debi_replace(dev, k->my_cra, ~S626_CRAMSK_INTSRC_A,
1147 S626_SET_CRA_INTSRC_A(int_source));
1149 /* Update MISC2 interrupt enable mask. */
1150 devpriv->counter_int_enabs =
1151 (devpriv->counter_int_enabs & ~k->my_event_bits[3]) |
1152 k->my_event_bits[int_source];
1155 static void s626_set_int_src_b(struct comedi_device *dev,
1156 const struct s626_enc_info *k,
1157 uint16_t int_source)
1159 struct s626_private *devpriv = dev->private;
1162 /* Cache writeable CRB register image. */
1163 crb = s626_debi_read(dev, k->my_crb) & ~S626_CRBMSK_INTCTRL;
1165 /* Reset any pending counter overflow or index captures. */
1166 s626_debi_write(dev, k->my_crb, (crb | S626_SET_CRB_INTRESETCMD(1) |
1167 S626_SET_CRB_INTRESET_B(1)));
1169 /* Program counter interrupt source. */
1170 s626_debi_write(dev, k->my_crb, ((crb & ~S626_CRBMSK_INTSRC_B) |
1171 S626_SET_CRB_INTSRC_B(int_source)));
1173 /* Update MISC2 interrupt enable mask. */
1174 devpriv->counter_int_enabs =
1175 (devpriv->counter_int_enabs & ~k->my_event_bits[3]) |
1176 k->my_event_bits[int_source];
1179 static uint16_t s626_get_int_src_a(struct comedi_device *dev,
1180 const struct s626_enc_info *k)
1182 return S626_GET_CRA_INTSRC_A(s626_debi_read(dev, k->my_cra));
1185 static uint16_t s626_get_int_src_b(struct comedi_device *dev,
1186 const struct s626_enc_info *k)
1188 return S626_GET_CRB_INTSRC_B(s626_debi_read(dev, k->my_crb));
1193 * Return/set the clock multiplier.
1195 static void s626_set_clk_mult(struct comedi_device *dev,
1196 const struct s626_enc_info *k, uint16_t value)
1198 k->set_mode(dev, k, ((k->get_mode(dev, k) & ~S626_STDMSK_CLKMULT) |
1199 S626_SET_STD_CLKMULT(value)), false);
1202 static uint16_t s626_get_clk_mult(struct comedi_device *dev,
1203 const struct s626_enc_info *k)
1205 return S626_GET_STD_CLKMULT(k->get_mode(dev, k));
1209 * Return/set the clock polarity.
1211 static void s626_set_clk_pol(struct comedi_device *dev,
1212 const struct s626_enc_info *k, uint16_t value)
1214 k->set_mode(dev, k, ((k->get_mode(dev, k) & ~S626_STDMSK_CLKPOL) |
1215 S626_SET_STD_CLKPOL(value)), false);
1218 static uint16_t s626_get_clk_pol(struct comedi_device *dev,
1219 const struct s626_enc_info *k)
1221 return S626_GET_STD_CLKPOL(k->get_mode(dev, k));
1225 * Return/set the encoder mode.
1227 static void s626_set_enc_mode(struct comedi_device *dev,
1228 const struct s626_enc_info *k, uint16_t value)
1230 k->set_mode(dev, k, ((k->get_mode(dev, k) & ~S626_STDMSK_ENCMODE) |
1231 S626_SET_STD_ENCMODE(value)), false);
1234 static uint16_t s626_get_enc_mode(struct comedi_device *dev,
1235 const struct s626_enc_info *k)
1237 return S626_GET_STD_ENCMODE(k->get_mode(dev, k));
1241 * Return/set the index polarity.
1243 static void s626_set_index_pol(struct comedi_device *dev,
1244 const struct s626_enc_info *k, uint16_t value)
1246 k->set_mode(dev, k, ((k->get_mode(dev, k) & ~S626_STDMSK_INDXPOL) |
1247 S626_SET_STD_INDXPOL(value != 0)), false);
1250 static uint16_t s626_get_index_pol(struct comedi_device *dev,
1251 const struct s626_enc_info *k)
1253 return S626_GET_STD_INDXPOL(k->get_mode(dev, k));
1257 * Return/set the index source.
1259 static void s626_set_index_src(struct comedi_device *dev,
1260 const struct s626_enc_info *k, uint16_t value)
1262 k->set_mode(dev, k, ((k->get_mode(dev, k) & ~S626_STDMSK_INDXSRC) |
1263 S626_SET_STD_INDXSRC(value != 0)), false);
1266 static uint16_t s626_get_index_src(struct comedi_device *dev,
1267 const struct s626_enc_info *k)
1269 return S626_GET_STD_INDXSRC(k->get_mode(dev, k));
1274 * Generate an index pulse.
1276 static void s626_pulse_index_a(struct comedi_device *dev,
1277 const struct s626_enc_info *k)
1281 cra = s626_debi_read(dev, k->my_cra);
1283 s626_debi_write(dev, k->my_cra, (cra ^ S626_CRAMSK_INDXPOL_A));
1284 s626_debi_write(dev, k->my_cra, cra);
1287 static void s626_pulse_index_b(struct comedi_device *dev,
1288 const struct s626_enc_info *k)
1292 crb = s626_debi_read(dev, k->my_crb) & ~S626_CRBMSK_INTCTRL;
1294 s626_debi_write(dev, k->my_crb, (crb ^ S626_CRBMSK_INDXPOL_B));
1295 s626_debi_write(dev, k->my_crb, crb);
1298 static const struct s626_enc_info s626_enc_chan_info[] = {
1300 .get_enable = s626_get_enable_a,
1301 .get_int_src = s626_get_int_src_a,
1302 .get_load_trig = s626_get_load_trig_a,
1303 .get_mode = s626_get_mode_a,
1304 .pulse_index = s626_pulse_index_a,
1305 .set_enable = s626_set_enable_a,
1306 .set_int_src = s626_set_int_src_a,
1307 .set_load_trig = s626_set_load_trig_a,
1308 .set_mode = s626_set_mode_a,
1309 .reset_cap_flags = s626_reset_cap_flags_a,
1310 .my_cra = S626_LP_CR0A,
1311 .my_crb = S626_LP_CR0B,
1312 .my_latch_lsw = S626_LP_CNTR0ALSW,
1313 .my_event_bits = S626_EVBITS(0),
1315 .get_enable = s626_get_enable_a,
1316 .get_int_src = s626_get_int_src_a,
1317 .get_load_trig = s626_get_load_trig_a,
1318 .get_mode = s626_get_mode_a,
1319 .pulse_index = s626_pulse_index_a,
1320 .set_enable = s626_set_enable_a,
1321 .set_int_src = s626_set_int_src_a,
1322 .set_load_trig = s626_set_load_trig_a,
1323 .set_mode = s626_set_mode_a,
1324 .reset_cap_flags = s626_reset_cap_flags_a,
1325 .my_cra = S626_LP_CR1A,
1326 .my_crb = S626_LP_CR1B,
1327 .my_latch_lsw = S626_LP_CNTR1ALSW,
1328 .my_event_bits = S626_EVBITS(1),
1330 .get_enable = s626_get_enable_a,
1331 .get_int_src = s626_get_int_src_a,
1332 .get_load_trig = s626_get_load_trig_a,
1333 .get_mode = s626_get_mode_a,
1334 .pulse_index = s626_pulse_index_a,
1335 .set_enable = s626_set_enable_a,
1336 .set_int_src = s626_set_int_src_a,
1337 .set_load_trig = s626_set_load_trig_a,
1338 .set_mode = s626_set_mode_a,
1339 .reset_cap_flags = s626_reset_cap_flags_a,
1340 .my_cra = S626_LP_CR2A,
1341 .my_crb = S626_LP_CR2B,
1342 .my_latch_lsw = S626_LP_CNTR2ALSW,
1343 .my_event_bits = S626_EVBITS(2),
1345 .get_enable = s626_get_enable_b,
1346 .get_int_src = s626_get_int_src_b,
1347 .get_load_trig = s626_get_load_trig_b,
1348 .get_mode = s626_get_mode_b,
1349 .pulse_index = s626_pulse_index_b,
1350 .set_enable = s626_set_enable_b,
1351 .set_int_src = s626_set_int_src_b,
1352 .set_load_trig = s626_set_load_trig_b,
1353 .set_mode = s626_set_mode_b,
1354 .reset_cap_flags = s626_reset_cap_flags_b,
1355 .my_cra = S626_LP_CR0A,
1356 .my_crb = S626_LP_CR0B,
1357 .my_latch_lsw = S626_LP_CNTR0BLSW,
1358 .my_event_bits = S626_EVBITS(3),
1360 .get_enable = s626_get_enable_b,
1361 .get_int_src = s626_get_int_src_b,
1362 .get_load_trig = s626_get_load_trig_b,
1363 .get_mode = s626_get_mode_b,
1364 .pulse_index = s626_pulse_index_b,
1365 .set_enable = s626_set_enable_b,
1366 .set_int_src = s626_set_int_src_b,
1367 .set_load_trig = s626_set_load_trig_b,
1368 .set_mode = s626_set_mode_b,
1369 .reset_cap_flags = s626_reset_cap_flags_b,
1370 .my_cra = S626_LP_CR1A,
1371 .my_crb = S626_LP_CR1B,
1372 .my_latch_lsw = S626_LP_CNTR1BLSW,
1373 .my_event_bits = S626_EVBITS(4),
1375 .get_enable = s626_get_enable_b,
1376 .get_int_src = s626_get_int_src_b,
1377 .get_load_trig = s626_get_load_trig_b,
1378 .get_mode = s626_get_mode_b,
1379 .pulse_index = s626_pulse_index_b,
1380 .set_enable = s626_set_enable_b,
1381 .set_int_src = s626_set_int_src_b,
1382 .set_load_trig = s626_set_load_trig_b,
1383 .set_mode = s626_set_mode_b,
1384 .reset_cap_flags = s626_reset_cap_flags_b,
1385 .my_cra = S626_LP_CR2A,
1386 .my_crb = S626_LP_CR2B,
1387 .my_latch_lsw = S626_LP_CNTR2BLSW,
1388 .my_event_bits = S626_EVBITS(5),
1392 static unsigned int s626_ai_reg_to_uint(unsigned int data)
1394 return ((data >> 18) & 0x3fff) ^ 0x2000;
1397 static int s626_dio_set_irq(struct comedi_device *dev, unsigned int chan)
1399 unsigned int group = chan / 16;
1400 unsigned int mask = 1 << (chan - (16 * group));
1401 unsigned int status;
1403 /* set channel to capture positive edge */
1404 status = s626_debi_read(dev, S626_LP_RDEDGSEL(group));
1405 s626_debi_write(dev, S626_LP_WREDGSEL(group), mask | status);
1407 /* enable interrupt on selected channel */
1408 status = s626_debi_read(dev, S626_LP_RDINTSEL(group));
1409 s626_debi_write(dev, S626_LP_WRINTSEL(group), mask | status);
1411 /* enable edge capture write command */
1412 s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_EDCAP);
1414 /* enable edge capture on selected channel */
1415 status = s626_debi_read(dev, S626_LP_RDCAPSEL(group));
1416 s626_debi_write(dev, S626_LP_WRCAPSEL(group), mask | status);
1421 static int s626_dio_reset_irq(struct comedi_device *dev, unsigned int group,
1424 /* disable edge capture write command */
1425 s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP);
1427 /* enable edge capture on selected channel */
1428 s626_debi_write(dev, S626_LP_WRCAPSEL(group), mask);
1433 static int s626_dio_clear_irq(struct comedi_device *dev)
1437 /* disable edge capture write command */
1438 s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP);
1440 /* clear all dio pending events and interrupt */
1441 for (group = 0; group < S626_DIO_BANKS; group++)
1442 s626_debi_write(dev, S626_LP_WRCAPSEL(group), 0xffff);
1447 static void s626_handle_dio_interrupt(struct comedi_device *dev,
1448 uint16_t irqbit, uint8_t group)
1450 struct s626_private *devpriv = dev->private;
1451 struct comedi_subdevice *s = dev->read_subdev;
1452 struct comedi_cmd *cmd = &s->async->cmd;
1454 s626_dio_reset_irq(dev, group, irqbit);
1456 if (devpriv->ai_cmd_running) {
1457 /* check if interrupt is an ai acquisition start trigger */
1458 if ((irqbit >> (cmd->start_arg - (16 * group))) == 1 &&
1459 cmd->start_src == TRIG_EXT) {
1460 /* Start executing the RPS program */
1461 s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1);
1463 if (cmd->scan_begin_src == TRIG_EXT)
1464 s626_dio_set_irq(dev, cmd->scan_begin_arg);
1466 if ((irqbit >> (cmd->scan_begin_arg - (16 * group))) == 1 &&
1467 cmd->scan_begin_src == TRIG_EXT) {
1468 /* Trigger ADC scan loop start */
1469 s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1471 if (cmd->convert_src == TRIG_EXT) {
1472 devpriv->ai_convert_count = cmd->chanlist_len;
1474 s626_dio_set_irq(dev, cmd->convert_arg);
1477 if (cmd->convert_src == TRIG_TIMER) {
1478 const struct s626_enc_info *k =
1479 &s626_enc_chan_info[5];
1481 devpriv->ai_convert_count = cmd->chanlist_len;
1482 k->set_enable(dev, k, S626_CLKENAB_ALWAYS);
1485 if ((irqbit >> (cmd->convert_arg - (16 * group))) == 1 &&
1486 cmd->convert_src == TRIG_EXT) {
1487 /* Trigger ADC scan loop start */
1488 s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1490 devpriv->ai_convert_count--;
1491 if (devpriv->ai_convert_count > 0)
1492 s626_dio_set_irq(dev, cmd->convert_arg);
1497 static void s626_check_dio_interrupts(struct comedi_device *dev)
1502 for (group = 0; group < S626_DIO_BANKS; group++) {
1504 /* read interrupt type */
1505 irqbit = s626_debi_read(dev, S626_LP_RDCAPFLG(group));
1507 /* check if interrupt is generated from dio channels */
1509 s626_handle_dio_interrupt(dev, irqbit, group);
1515 static void s626_check_counter_interrupts(struct comedi_device *dev)
1517 struct s626_private *devpriv = dev->private;
1518 struct comedi_subdevice *s = dev->read_subdev;
1519 struct comedi_async *async = s->async;
1520 struct comedi_cmd *cmd = &async->cmd;
1521 const struct s626_enc_info *k;
1524 /* read interrupt type */
1525 irqbit = s626_debi_read(dev, S626_LP_RDMISC2);
1527 /* check interrupt on counters */
1528 if (irqbit & S626_IRQ_COINT1A) {
1529 k = &s626_enc_chan_info[0];
1531 /* clear interrupt capture flag */
1532 k->reset_cap_flags(dev, k);
1534 if (irqbit & S626_IRQ_COINT2A) {
1535 k = &s626_enc_chan_info[1];
1537 /* clear interrupt capture flag */
1538 k->reset_cap_flags(dev, k);
1540 if (irqbit & S626_IRQ_COINT3A) {
1541 k = &s626_enc_chan_info[2];
1543 /* clear interrupt capture flag */
1544 k->reset_cap_flags(dev, k);
1546 if (irqbit & S626_IRQ_COINT1B) {
1547 k = &s626_enc_chan_info[3];
1549 /* clear interrupt capture flag */
1550 k->reset_cap_flags(dev, k);
1552 if (irqbit & S626_IRQ_COINT2B) {
1553 k = &s626_enc_chan_info[4];
1555 /* clear interrupt capture flag */
1556 k->reset_cap_flags(dev, k);
1558 if (devpriv->ai_convert_count > 0) {
1559 devpriv->ai_convert_count--;
1560 if (devpriv->ai_convert_count == 0)
1561 k->set_enable(dev, k, S626_CLKENAB_INDEX);
1563 if (cmd->convert_src == TRIG_TIMER) {
1564 /* Trigger ADC scan loop start */
1565 s626_mc_enable(dev, S626_MC2_ADC_RPS,
1570 if (irqbit & S626_IRQ_COINT3B) {
1571 k = &s626_enc_chan_info[5];
1573 /* clear interrupt capture flag */
1574 k->reset_cap_flags(dev, k);
1576 if (cmd->scan_begin_src == TRIG_TIMER) {
1577 /* Trigger ADC scan loop start */
1578 s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1581 if (cmd->convert_src == TRIG_TIMER) {
1582 k = &s626_enc_chan_info[4];
1583 devpriv->ai_convert_count = cmd->chanlist_len;
1584 k->set_enable(dev, k, S626_CLKENAB_ALWAYS);
1589 static bool s626_handle_eos_interrupt(struct comedi_device *dev)
1591 struct s626_private *devpriv = dev->private;
1592 struct comedi_subdevice *s = dev->read_subdev;
1593 struct comedi_async *async = s->async;
1594 struct comedi_cmd *cmd = &async->cmd;
1596 * Init ptr to DMA buffer that holds new ADC data. We skip the
1597 * first uint16_t in the buffer because it contains junk data
1598 * from the final ADC of the previous poll list scan.
1600 uint32_t *readaddr = (uint32_t *)devpriv->ana_buf.logical_base + 1;
1601 bool finished = false;
1604 /* get the data and hand it over to comedi */
1605 for (i = 0; i < cmd->chanlist_len; i++) {
1606 unsigned short tempdata;
1609 * Convert ADC data to 16-bit integer values and copy
1610 * to application buffer.
1612 tempdata = s626_ai_reg_to_uint(*readaddr);
1615 /* put data into read buffer */
1616 /* comedi_buf_put(async, tempdata); */
1617 cfc_write_to_buffer(s, tempdata);
1620 /* end of scan occurs */
1621 async->events |= COMEDI_CB_EOS;
1623 if (!devpriv->ai_continuous)
1624 devpriv->ai_sample_count--;
1625 if (devpriv->ai_sample_count <= 0) {
1626 devpriv->ai_cmd_running = 0;
1628 /* Stop RPS program */
1629 s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1);
1631 /* send end of acquisition */
1632 async->events |= COMEDI_CB_EOA;
1634 /* disable master interrupt */
1638 if (devpriv->ai_cmd_running && cmd->scan_begin_src == TRIG_EXT)
1639 s626_dio_set_irq(dev, cmd->scan_begin_arg);
1641 /* tell comedi that data is there */
1642 comedi_event(dev, s);
1647 static irqreturn_t s626_irq_handler(int irq, void *d)
1649 struct comedi_device *dev = d;
1650 struct s626_private *devpriv = dev->private;
1651 unsigned long flags;
1652 uint32_t irqtype, irqstatus;
1656 /* lock to avoid race with comedi_poll */
1657 spin_lock_irqsave(&dev->spinlock, flags);
1659 /* save interrupt enable register state */
1660 irqstatus = readl(devpriv->mmio + S626_P_IER);
1662 /* read interrupt type */
1663 irqtype = readl(devpriv->mmio + S626_P_ISR);
1665 /* disable master interrupt */
1666 writel(0, devpriv->mmio + S626_P_IER);
1668 /* clear interrupt */
1669 writel(irqtype, devpriv->mmio + S626_P_ISR);
1672 case S626_IRQ_RPS1: /* end_of_scan occurs */
1673 if (s626_handle_eos_interrupt(dev))
1676 case S626_IRQ_GPIO3: /* check dio and counter interrupt */
1677 /* s626_dio_clear_irq(dev); */
1678 s626_check_dio_interrupts(dev);
1679 s626_check_counter_interrupts(dev);
1683 /* enable interrupt */
1684 writel(irqstatus, devpriv->mmio + S626_P_IER);
1686 spin_unlock_irqrestore(&dev->spinlock, flags);
1691 * This function builds the RPS program for hardware driven acquisition.
1693 static void s626_reset_adc(struct comedi_device *dev, uint8_t *ppl)
1695 struct s626_private *devpriv = dev->private;
1696 struct comedi_subdevice *s = dev->read_subdev;
1697 struct comedi_cmd *cmd = &s->async->cmd;
1704 /* Stop RPS program in case it is currently running */
1705 s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1);
1707 /* Set starting logical address to write RPS commands. */
1708 rps = (uint32_t *)devpriv->rps_buf.logical_base;
1710 /* Initialize RPS instruction pointer */
1711 writel((uint32_t)devpriv->rps_buf.physical_base,
1712 devpriv->mmio + S626_P_RPSADDR1);
1714 /* Construct RPS program in rps_buf DMA buffer */
1715 if (cmd != NULL && cmd->scan_begin_src != TRIG_FOLLOW) {
1716 /* Wait for Start trigger. */
1717 *rps++ = S626_RPS_PAUSE | S626_RPS_SIGADC;
1718 *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_SIGADC;
1722 * SAA7146 BUG WORKAROUND Do a dummy DEBI Write. This is necessary
1723 * because the first RPS DEBI Write following a non-RPS DEBI write
1724 * seems to always fail. If we don't do this dummy write, the ADC
1725 * gain might not be set to the value required for the first slot in
1726 * the poll list; the ADC gain would instead remain unchanged from
1727 * the previously programmed value.
1729 /* Write DEBI Write command and address to shadow RAM. */
1730 *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2);
1731 *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_GSEL;
1732 *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2);
1733 /* Write DEBI immediate data to shadow RAM: */
1734 *rps++ = S626_GSEL_BIPOLAR5V; /* arbitrary immediate data value. */
1735 *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI;
1736 /* Reset "shadow RAM uploaded" flag. */
1737 /* Invoke shadow RAM upload. */
1738 *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI;
1739 /* Wait for shadow upload to finish. */
1740 *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI;
1743 * Digitize all slots in the poll list. This is implemented as a
1744 * for loop to limit the slot count to 16 in case the application
1745 * forgot to set the S626_EOPL flag in the final slot.
1747 for (devpriv->adc_items = 0; devpriv->adc_items < 16;
1748 devpriv->adc_items++) {
1750 * Convert application's poll list item to private board class
1751 * format. Each app poll list item is an uint8_t with form
1752 * (EOPL,x,x,RANGE,CHAN<3:0>), where RANGE code indicates 0 =
1753 * +-10V, 1 = +-5V, and EOPL = End of Poll List marker.
1755 local_ppl = (*ppl << 8) | (*ppl & 0x10 ? S626_GSEL_BIPOLAR5V :
1756 S626_GSEL_BIPOLAR10V);
1758 /* Switch ADC analog gain. */
1759 /* Write DEBI command and address to shadow RAM. */
1760 *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2);
1761 *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_GSEL;
1762 /* Write DEBI immediate data to shadow RAM. */
1763 *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2);
1765 /* Reset "shadow RAM uploaded" flag. */
1766 *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI;
1767 /* Invoke shadow RAM upload. */
1768 *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI;
1769 /* Wait for shadow upload to finish. */
1770 *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI;
1771 /* Select ADC analog input channel. */
1772 *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2);
1773 /* Write DEBI command and address to shadow RAM. */
1774 *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_ISEL;
1775 *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2);
1776 /* Write DEBI immediate data to shadow RAM. */
1778 /* Reset "shadow RAM uploaded" flag. */
1779 *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI;
1780 /* Invoke shadow RAM upload. */
1781 *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI;
1782 /* Wait for shadow upload to finish. */
1783 *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI;
1786 * Delay at least 10 microseconds for analog input settling.
1787 * Instead of padding with NOPs, we use S626_RPS_JUMP
1788 * instructions here; this allows us to produce a longer delay
1789 * than is possible with NOPs because each S626_RPS_JUMP
1790 * flushes the RPS' instruction prefetch pipeline.
1793 (uint32_t)devpriv->rps_buf.physical_base +
1794 (uint32_t)((unsigned long)rps -
1795 (unsigned long)devpriv->
1796 rps_buf.logical_base);
1797 for (i = 0; i < (10 * S626_RPSCLK_PER_US / 2); i++) {
1798 jmp_adrs += 8; /* Repeat to implement time delay: */
1799 /* Jump to next RPS instruction. */
1800 *rps++ = S626_RPS_JUMP;
1804 if (cmd != NULL && cmd->convert_src != TRIG_NOW) {
1805 /* Wait for Start trigger. */
1806 *rps++ = S626_RPS_PAUSE | S626_RPS_SIGADC;
1807 *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_SIGADC;
1809 /* Start ADC by pulsing GPIO1. */
1810 /* Begin ADC Start pulse. */
1811 *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2);
1812 *rps++ = S626_GPIO_BASE | S626_GPIO1_LO;
1813 *rps++ = S626_RPS_NOP;
1814 /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */
1815 /* End ADC Start pulse. */
1816 *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2);
1817 *rps++ = S626_GPIO_BASE | S626_GPIO1_HI;
1819 * Wait for ADC to complete (GPIO2 is asserted high when ADC not
1820 * busy) and for data from previous conversion to shift into FB
1821 * BUFFER 1 register.
1823 /* Wait for ADC done. */
1824 *rps++ = S626_RPS_PAUSE | S626_RPS_GPIO2;
1826 /* Transfer ADC data from FB BUFFER 1 register to DMA buffer. */
1827 *rps++ = S626_RPS_STREG |
1828 (S626_BUGFIX_STREG(S626_P_FB_BUFFER1) >> 2);
1829 *rps++ = (uint32_t)devpriv->ana_buf.physical_base +
1830 (devpriv->adc_items << 2);
1833 * If this slot's EndOfPollList flag is set, all channels have
1834 * now been processed.
1836 if (*ppl++ & S626_EOPL) {
1837 devpriv->adc_items++; /* Adjust poll list item count. */
1838 break; /* Exit poll list processing loop. */
1843 * VERSION 2.01 CHANGE: DELAY CHANGED FROM 250NS to 2US. Allow the
1844 * ADC to stabilize for 2 microseconds before starting the final
1845 * (dummy) conversion. This delay is necessary to allow sufficient
1846 * time between last conversion finished and the start of the dummy
1847 * conversion. Without this delay, the last conversion's data value
1848 * is sometimes set to the previous conversion's data value.
1850 for (n = 0; n < (2 * S626_RPSCLK_PER_US); n++)
1851 *rps++ = S626_RPS_NOP;
1854 * Start a dummy conversion to cause the data from the last
1855 * conversion of interest to be shifted in.
1857 /* Begin ADC Start pulse. */
1858 *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2);
1859 *rps++ = S626_GPIO_BASE | S626_GPIO1_LO;
1860 *rps++ = S626_RPS_NOP;
1861 /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */
1862 *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2); /* End ADC Start pulse. */
1863 *rps++ = S626_GPIO_BASE | S626_GPIO1_HI;
1866 * Wait for the data from the last conversion of interest to arrive
1867 * in FB BUFFER 1 register.
1869 *rps++ = S626_RPS_PAUSE | S626_RPS_GPIO2; /* Wait for ADC done. */
1871 /* Transfer final ADC data from FB BUFFER 1 register to DMA buffer. */
1872 *rps++ = S626_RPS_STREG | (S626_BUGFIX_STREG(S626_P_FB_BUFFER1) >> 2);
1873 *rps++ = (uint32_t)devpriv->ana_buf.physical_base +
1874 (devpriv->adc_items << 2);
1876 /* Indicate ADC scan loop is finished. */
1877 /* Signal ReadADC() that scan is done. */
1878 /* *rps++= S626_RPS_CLRSIGNAL | S626_RPS_SIGADC; */
1880 /* invoke interrupt */
1881 if (devpriv->ai_cmd_running == 1)
1882 *rps++ = S626_RPS_IRQ;
1884 /* Restart RPS program at its beginning. */
1885 *rps++ = S626_RPS_JUMP; /* Branch to start of RPS program. */
1886 *rps++ = (uint32_t)devpriv->rps_buf.physical_base;
1888 /* End of RPS program build */
1892 static int s626_ai_rinsn(struct comedi_device *dev,
1893 struct comedi_subdevice *s,
1894 struct comedi_insn *insn,
1897 struct s626_private *devpriv = dev->private;
1901 /* Trigger ADC scan loop start */
1902 s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1904 /* Wait until ADC scan loop is finished (RPS Signal 0 reset) */
1905 while (s626_mc_test(dev, S626_MC2_ADC_RPS, S626_P_MC2))
1909 * Init ptr to DMA buffer that holds new ADC data. We skip the
1910 * first uint16_t in the buffer because it contains junk data from
1911 * the final ADC of the previous poll list scan.
1913 readaddr = (uint32_t *)devpriv->ana_buf.logical_base + 1;
1916 * Convert ADC data to 16-bit integer values and
1917 * copy to application buffer.
1919 for (i = 0; i < devpriv->adc_items; i++) {
1920 *data = s626_ai_reg_to_uint(*readaddr++);
1928 static int s626_ai_eoc(struct comedi_device *dev,
1929 struct comedi_subdevice *s,
1930 struct comedi_insn *insn,
1931 unsigned long context)
1933 struct s626_private *devpriv = dev->private;
1934 unsigned int status;
1936 status = readl(devpriv->mmio + S626_P_PSR);
1937 if (status & S626_PSR_GPIO2)
1942 static int s626_ai_insn_read(struct comedi_device *dev,
1943 struct comedi_subdevice *s,
1944 struct comedi_insn *insn, unsigned int *data)
1946 struct s626_private *devpriv = dev->private;
1947 uint16_t chan = CR_CHAN(insn->chanspec);
1948 uint16_t range = CR_RANGE(insn->chanspec);
1949 uint16_t adc_spec = 0;
1950 uint32_t gpio_image;
1956 * Convert application's ADC specification into form
1957 * appropriate for register programming.
1960 adc_spec = (chan << 8) | (S626_GSEL_BIPOLAR5V);
1962 adc_spec = (chan << 8) | (S626_GSEL_BIPOLAR10V);
1964 /* Switch ADC analog gain. */
1965 s626_debi_write(dev, S626_LP_GSEL, adc_spec); /* Set gain. */
1967 /* Select ADC analog input channel. */
1968 s626_debi_write(dev, S626_LP_ISEL, adc_spec); /* Select channel. */
1970 for (n = 0; n < insn->n; n++) {
1971 /* Delay 10 microseconds for analog input settling. */
1974 /* Start ADC by pulsing GPIO1 low */
1975 gpio_image = readl(devpriv->mmio + S626_P_GPIO);
1976 /* Assert ADC Start command */
1977 writel(gpio_image & ~S626_GPIO1_HI,
1978 devpriv->mmio + S626_P_GPIO);
1979 /* and stretch it out */
1980 writel(gpio_image & ~S626_GPIO1_HI,
1981 devpriv->mmio + S626_P_GPIO);
1982 writel(gpio_image & ~S626_GPIO1_HI,
1983 devpriv->mmio + S626_P_GPIO);
1984 /* Negate ADC Start command */
1985 writel(gpio_image | S626_GPIO1_HI, devpriv->mmio + S626_P_GPIO);
1988 * Wait for ADC to complete (GPIO2 is asserted high when
1989 * ADC not busy) and for data from previous conversion to
1990 * shift into FB BUFFER 1 register.
1993 /* Wait for ADC done */
1994 ret = comedi_timeout(dev, s, insn, s626_ai_eoc, 0);
1998 /* Fetch ADC data */
2000 tmp = readl(devpriv->mmio + S626_P_FB_BUFFER1);
2001 data[n - 1] = s626_ai_reg_to_uint(tmp);
2005 * Allow the ADC to stabilize for 4 microseconds before
2006 * starting the next (final) conversion. This delay is
2007 * necessary to allow sufficient time between last
2008 * conversion finished and the start of the next
2009 * conversion. Without this delay, the last conversion's
2010 * data value is sometimes set to the previous
2011 * conversion's data value.
2017 * Start a dummy conversion to cause the data from the
2018 * previous conversion to be shifted in.
2020 gpio_image = readl(devpriv->mmio + S626_P_GPIO);
2021 /* Assert ADC Start command */
2022 writel(gpio_image & ~S626_GPIO1_HI, devpriv->mmio + S626_P_GPIO);
2023 /* and stretch it out */
2024 writel(gpio_image & ~S626_GPIO1_HI, devpriv->mmio + S626_P_GPIO);
2025 writel(gpio_image & ~S626_GPIO1_HI, devpriv->mmio + S626_P_GPIO);
2026 /* Negate ADC Start command */
2027 writel(gpio_image | S626_GPIO1_HI, devpriv->mmio + S626_P_GPIO);
2029 /* Wait for the data to arrive in FB BUFFER 1 register. */
2031 /* Wait for ADC done */
2032 while (!(readl(devpriv->mmio + S626_P_PSR) & S626_PSR_GPIO2))
2035 /* Fetch ADC data from audio interface's input shift register. */
2037 /* Fetch ADC data */
2039 tmp = readl(devpriv->mmio + S626_P_FB_BUFFER1);
2040 data[n - 1] = s626_ai_reg_to_uint(tmp);
2046 static int s626_ai_load_polllist(uint8_t *ppl, struct comedi_cmd *cmd)
2050 for (n = 0; n < cmd->chanlist_len; n++) {
2051 if (CR_RANGE(cmd->chanlist[n]) == 0)
2052 ppl[n] = CR_CHAN(cmd->chanlist[n]) | S626_RANGE_5V;
2054 ppl[n] = CR_CHAN(cmd->chanlist[n]) | S626_RANGE_10V;
2057 ppl[n - 1] |= S626_EOPL;
2062 static int s626_ai_inttrig(struct comedi_device *dev,
2063 struct comedi_subdevice *s, unsigned int trignum)
2068 /* Start executing the RPS program */
2069 s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1);
2071 s->async->inttrig = NULL;
2077 * This function doesn't require a particular form, this is just what
2078 * happens to be used in some of the drivers. It should convert ns
2079 * nanoseconds to a counter value suitable for programming the device.
2080 * Also, it should adjust ns so that it cooresponds to the actual time
2081 * that the device will use.
2083 static int s626_ns_to_timer(int *nanosec, int round_mode)
2087 base = 500; /* 2MHz internal clock */
2089 switch (round_mode) {
2090 case TRIG_ROUND_NEAREST:
2092 divider = (*nanosec + base / 2) / base;
2094 case TRIG_ROUND_DOWN:
2095 divider = (*nanosec) / base;
2098 divider = (*nanosec + base - 1) / base;
2102 *nanosec = base * divider;
2106 static void s626_timer_load(struct comedi_device *dev,
2107 const struct s626_enc_info *k, int tick)
2110 /* Preload upon index. */
2111 S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) |
2112 /* Disable hardware index. */
2113 S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) |
2114 /* Operating mode is Timer. */
2115 S626_SET_STD_ENCMODE(S626_ENCMODE_TIMER) |
2116 /* Count direction is Down. */
2117 S626_SET_STD_CLKPOL(S626_CNTDIR_DOWN) |
2118 /* Clock multiplier is 1x. */
2119 S626_SET_STD_CLKMULT(S626_CLKMULT_1X) |
2120 /* Enabled by index */
2121 S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX);
2122 uint16_t value_latchsrc = S626_LATCHSRC_A_INDXA;
2123 /* uint16_t enab = S626_CLKENAB_ALWAYS; */
2125 k->set_mode(dev, k, setup, false);
2127 /* Set the preload register */
2128 s626_preload(dev, k, tick);
2131 * Software index pulse forces the preload register to load
2134 k->set_load_trig(dev, k, 0);
2135 k->pulse_index(dev, k);
2137 /* set reload on counter overflow */
2138 k->set_load_trig(dev, k, 1);
2140 /* set interrupt on overflow */
2141 k->set_int_src(dev, k, S626_INTSRC_OVER);
2143 s626_set_latch_source(dev, k, value_latchsrc);
2144 /* k->set_enable(dev, k, (uint16_t)(enab != 0)); */
2148 static int s626_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2150 struct s626_private *devpriv = dev->private;
2152 struct comedi_cmd *cmd = &s->async->cmd;
2153 const struct s626_enc_info *k;
2156 if (devpriv->ai_cmd_running) {
2157 dev_err(dev->class_dev,
2158 "s626_ai_cmd: Another ai_cmd is running\n");
2161 /* disable interrupt */
2162 writel(0, devpriv->mmio + S626_P_IER);
2164 /* clear interrupt request */
2165 writel(S626_IRQ_RPS1 | S626_IRQ_GPIO3, devpriv->mmio + S626_P_ISR);
2167 /* clear any pending interrupt */
2168 s626_dio_clear_irq(dev);
2169 /* s626_enc_clear_irq(dev); */
2171 /* reset ai_cmd_running flag */
2172 devpriv->ai_cmd_running = 0;
2174 /* test if cmd is valid */
2178 s626_ai_load_polllist(ppl, cmd);
2179 devpriv->ai_cmd_running = 1;
2180 devpriv->ai_convert_count = 0;
2182 switch (cmd->scan_begin_src) {
2187 * set a counter to generate adc trigger at scan_begin_arg
2190 k = &s626_enc_chan_info[5];
2191 tick = s626_ns_to_timer((int *)&cmd->scan_begin_arg,
2192 cmd->flags & TRIG_ROUND_MASK);
2194 /* load timer value and enable interrupt */
2195 s626_timer_load(dev, k, tick);
2196 k->set_enable(dev, k, S626_CLKENAB_ALWAYS);
2199 /* set the digital line and interrupt for scan trigger */
2200 if (cmd->start_src != TRIG_EXT)
2201 s626_dio_set_irq(dev, cmd->scan_begin_arg);
2205 switch (cmd->convert_src) {
2210 * set a counter to generate adc trigger at convert_arg
2213 k = &s626_enc_chan_info[4];
2214 tick = s626_ns_to_timer((int *)&cmd->convert_arg,
2215 cmd->flags & TRIG_ROUND_MASK);
2217 /* load timer value and enable interrupt */
2218 s626_timer_load(dev, k, tick);
2219 k->set_enable(dev, k, S626_CLKENAB_INDEX);
2222 /* set the digital line and interrupt for convert trigger */
2223 if (cmd->scan_begin_src != TRIG_EXT &&
2224 cmd->start_src == TRIG_EXT)
2225 s626_dio_set_irq(dev, cmd->convert_arg);
2229 switch (cmd->stop_src) {
2231 /* data arrives as one packet */
2232 devpriv->ai_sample_count = cmd->stop_arg;
2233 devpriv->ai_continuous = 0;
2236 /* continuous acquisition */
2237 devpriv->ai_continuous = 1;
2238 devpriv->ai_sample_count = 1;
2242 s626_reset_adc(dev, ppl);
2244 switch (cmd->start_src) {
2246 /* Trigger ADC scan loop start */
2247 /* s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2); */
2249 /* Start executing the RPS program */
2250 s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1);
2251 s->async->inttrig = NULL;
2254 /* configure DIO channel for acquisition trigger */
2255 s626_dio_set_irq(dev, cmd->start_arg);
2256 s->async->inttrig = NULL;
2259 s->async->inttrig = s626_ai_inttrig;
2263 /* enable interrupt */
2264 writel(S626_IRQ_GPIO3 | S626_IRQ_RPS1, devpriv->mmio + S626_P_IER);
2269 static int s626_ai_cmdtest(struct comedi_device *dev,
2270 struct comedi_subdevice *s, struct comedi_cmd *cmd)
2275 /* Step 1 : check if triggers are trivially valid */
2277 err |= cfc_check_trigger_src(&cmd->start_src,
2278 TRIG_NOW | TRIG_INT | TRIG_EXT);
2279 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
2280 TRIG_TIMER | TRIG_EXT | TRIG_FOLLOW);
2281 err |= cfc_check_trigger_src(&cmd->convert_src,
2282 TRIG_TIMER | TRIG_EXT | TRIG_NOW);
2283 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2284 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2289 /* Step 2a : make sure trigger sources are unique */
2291 err |= cfc_check_trigger_is_unique(cmd->start_src);
2292 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2293 err |= cfc_check_trigger_is_unique(cmd->convert_src);
2294 err |= cfc_check_trigger_is_unique(cmd->stop_src);
2296 /* Step 2b : and mutually compatible */
2301 /* step 3: make sure arguments are trivially compatible */
2303 if (cmd->start_src != TRIG_EXT)
2304 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
2305 if (cmd->start_src == TRIG_EXT)
2306 err |= cfc_check_trigger_arg_max(&cmd->start_arg, 39);
2307 if (cmd->scan_begin_src == TRIG_EXT)
2308 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 39);
2309 if (cmd->convert_src == TRIG_EXT)
2310 err |= cfc_check_trigger_arg_max(&cmd->convert_arg, 39);
2312 #define S626_MAX_SPEED 200000 /* in nanoseconds */
2313 #define S626_MIN_SPEED 2000000000 /* in nanoseconds */
2315 if (cmd->scan_begin_src == TRIG_TIMER) {
2316 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
2318 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
2321 /* external trigger */
2322 /* should be level/edge, hi/lo specification here */
2323 /* should specify multiple external triggers */
2324 /* err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 9); */
2326 if (cmd->convert_src == TRIG_TIMER) {
2327 err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
2329 err |= cfc_check_trigger_arg_max(&cmd->convert_arg,
2332 /* external trigger */
2334 /* err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 9); */
2337 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
2339 if (cmd->stop_src == TRIG_COUNT)
2340 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
2341 else /* TRIG_NONE */
2342 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
2347 /* step 4: fix up any arguments */
2349 if (cmd->scan_begin_src == TRIG_TIMER) {
2350 tmp = cmd->scan_begin_arg;
2351 s626_ns_to_timer((int *)&cmd->scan_begin_arg,
2352 cmd->flags & TRIG_ROUND_MASK);
2353 if (tmp != cmd->scan_begin_arg)
2356 if (cmd->convert_src == TRIG_TIMER) {
2357 tmp = cmd->convert_arg;
2358 s626_ns_to_timer((int *)&cmd->convert_arg,
2359 cmd->flags & TRIG_ROUND_MASK);
2360 if (tmp != cmd->convert_arg)
2362 if (cmd->scan_begin_src == TRIG_TIMER &&
2363 cmd->scan_begin_arg < cmd->convert_arg *
2364 cmd->scan_end_arg) {
2365 cmd->scan_begin_arg = cmd->convert_arg *
2377 static int s626_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
2379 struct s626_private *devpriv = dev->private;
2381 /* Stop RPS program in case it is currently running */
2382 s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1);
2384 /* disable master interrupt */
2385 writel(0, devpriv->mmio + S626_P_IER);
2387 devpriv->ai_cmd_running = 0;
2392 static int s626_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
2393 struct comedi_insn *insn, unsigned int *data)
2395 struct s626_private *devpriv = dev->private;
2398 uint16_t chan = CR_CHAN(insn->chanspec);
2401 for (i = 0; i < insn->n; i++) {
2402 dacdata = (int16_t) data[i];
2403 devpriv->ao_readback[CR_CHAN(insn->chanspec)] = data[i];
2404 dacdata -= (0x1fff);
2406 ret = s626_set_dac(dev, chan, dacdata);
2414 static int s626_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
2415 struct comedi_insn *insn, unsigned int *data)
2417 struct s626_private *devpriv = dev->private;
2420 for (i = 0; i < insn->n; i++)
2421 data[i] = devpriv->ao_readback[CR_CHAN(insn->chanspec)];
2426 /* *************** DIGITAL I/O FUNCTIONS *************** */
2429 * All DIO functions address a group of DIO channels by means of
2430 * "group" argument. group may be 0, 1 or 2, which correspond to DIO
2431 * ports A, B and C, respectively.
2434 static void s626_dio_init(struct comedi_device *dev)
2438 /* Prepare to treat writes to WRCapSel as capture disables. */
2439 s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP);
2441 /* For each group of sixteen channels ... */
2442 for (group = 0; group < S626_DIO_BANKS; group++) {
2443 /* Disable all interrupts */
2444 s626_debi_write(dev, S626_LP_WRINTSEL(group), 0);
2445 /* Disable all event captures */
2446 s626_debi_write(dev, S626_LP_WRCAPSEL(group), 0xffff);
2447 /* Init all DIOs to default edge polarity */
2448 s626_debi_write(dev, S626_LP_WREDGSEL(group), 0);
2449 /* Program all outputs to inactive state */
2450 s626_debi_write(dev, S626_LP_WRDOUT(group), 0);
2454 static int s626_dio_insn_bits(struct comedi_device *dev,
2455 struct comedi_subdevice *s,
2456 struct comedi_insn *insn,
2459 unsigned long group = (unsigned long)s->private;
2461 if (comedi_dio_update_state(s, data))
2462 s626_debi_write(dev, S626_LP_WRDOUT(group), s->state);
2464 data[1] = s626_debi_read(dev, S626_LP_RDDIN(group));
2469 static int s626_dio_insn_config(struct comedi_device *dev,
2470 struct comedi_subdevice *s,
2471 struct comedi_insn *insn,
2474 unsigned long group = (unsigned long)s->private;
2477 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
2481 s626_debi_write(dev, S626_LP_WRDOUT(group), s->io_bits);
2487 * Now this function initializes the value of the counter (data[0])
2488 * and set the subdevice. To complete with trigger and interrupt
2491 * FIXME: data[0] is supposed to be an INSN_CONFIG_xxx constant indicating
2492 * what is being configured, but this function appears to be using data[0]
2495 static int s626_enc_insn_config(struct comedi_device *dev,
2496 struct comedi_subdevice *s,
2497 struct comedi_insn *insn, unsigned int *data)
2500 /* Preload upon index. */
2501 S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) |
2502 /* Disable hardware index. */
2503 S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) |
2504 /* Operating mode is Counter. */
2505 S626_SET_STD_ENCMODE(S626_ENCMODE_COUNTER) |
2506 /* Active high clock. */
2507 S626_SET_STD_CLKPOL(S626_CLKPOL_POS) |
2508 /* Clock multiplier is 1x. */
2509 S626_SET_STD_CLKMULT(S626_CLKMULT_1X) |
2510 /* Enabled by index */
2511 S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX);
2512 /* uint16_t disable_int_src = true; */
2513 /* uint32_t Preloadvalue; //Counter initial value */
2514 uint16_t value_latchsrc = S626_LATCHSRC_AB_READ;
2515 uint16_t enab = S626_CLKENAB_ALWAYS;
2516 const struct s626_enc_info *k =
2517 &s626_enc_chan_info[CR_CHAN(insn->chanspec)];
2519 /* (data==NULL) ? (Preloadvalue=0) : (Preloadvalue=data[0]); */
2521 k->set_mode(dev, k, setup, true);
2522 s626_preload(dev, k, data[0]);
2523 k->pulse_index(dev, k);
2524 s626_set_latch_source(dev, k, value_latchsrc);
2525 k->set_enable(dev, k, (enab != 0));
2530 static int s626_enc_insn_read(struct comedi_device *dev,
2531 struct comedi_subdevice *s,
2532 struct comedi_insn *insn, unsigned int *data)
2535 const struct s626_enc_info *k =
2536 &s626_enc_chan_info[CR_CHAN(insn->chanspec)];
2538 for (n = 0; n < insn->n; n++)
2539 data[n] = s626_read_latch(dev, k);
2544 static int s626_enc_insn_write(struct comedi_device *dev,
2545 struct comedi_subdevice *s,
2546 struct comedi_insn *insn, unsigned int *data)
2548 const struct s626_enc_info *k =
2549 &s626_enc_chan_info[CR_CHAN(insn->chanspec)];
2551 /* Set the preload register */
2552 s626_preload(dev, k, data[0]);
2555 * Software index pulse forces the preload register to load
2558 k->set_load_trig(dev, k, 0);
2559 k->pulse_index(dev, k);
2560 k->set_load_trig(dev, k, 2);
2565 static void s626_write_misc2(struct comedi_device *dev, uint16_t new_image)
2567 s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_WENABLE);
2568 s626_debi_write(dev, S626_LP_WRMISC2, new_image);
2569 s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_WDISABLE);
2572 static void s626_close_dma_b(struct comedi_device *dev,
2573 struct s626_buffer_dma *pdma, size_t bsize)
2575 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2582 /* find the matching allocation from the board struct */
2583 vbptr = pdma->logical_base;
2584 vpptr = pdma->physical_base;
2586 pci_free_consistent(pcidev, bsize, vbptr, vpptr);
2587 pdma->logical_base = NULL;
2588 pdma->physical_base = 0;
2592 static void s626_counters_init(struct comedi_device *dev)
2595 const struct s626_enc_info *k;
2597 /* Preload upon index. */
2598 S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) |
2599 /* Disable hardware index. */
2600 S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) |
2601 /* Operating mode is counter. */
2602 S626_SET_STD_ENCMODE(S626_ENCMODE_COUNTER) |
2603 /* Active high clock. */
2604 S626_SET_STD_CLKPOL(S626_CLKPOL_POS) |
2605 /* Clock multiplier is 1x. */
2606 S626_SET_STD_CLKMULT(S626_CLKMULT_1X) |
2607 /* Enabled by index */
2608 S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX);
2611 * Disable all counter interrupts and clear any captured counter events.
2613 for (chan = 0; chan < S626_ENCODER_CHANNELS; chan++) {
2614 k = &s626_enc_chan_info[chan];
2615 k->set_mode(dev, k, setup, true);
2616 k->set_int_src(dev, k, 0);
2617 k->reset_cap_flags(dev, k);
2618 k->set_enable(dev, k, S626_CLKENAB_ALWAYS);
2622 static int s626_allocate_dma_buffers(struct comedi_device *dev)
2624 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2625 struct s626_private *devpriv = dev->private;
2629 addr = pci_alloc_consistent(pcidev, S626_DMABUF_SIZE, &appdma);
2632 devpriv->ana_buf.logical_base = addr;
2633 devpriv->ana_buf.physical_base = appdma;
2635 addr = pci_alloc_consistent(pcidev, S626_DMABUF_SIZE, &appdma);
2638 devpriv->rps_buf.logical_base = addr;
2639 devpriv->rps_buf.physical_base = appdma;
2644 static int s626_initialize(struct comedi_device *dev)
2646 struct s626_private *devpriv = dev->private;
2647 dma_addr_t phys_buf;
2652 /* Enable DEBI and audio pins, enable I2C interface */
2653 s626_mc_enable(dev, S626_MC1_DEBI | S626_MC1_AUDIO | S626_MC1_I2C,
2657 * Configure DEBI operating mode
2659 * Local bus is 16 bits wide
2660 * Declare DEBI transfer timeout interval
2661 * Set up byte lane steering
2662 * Intel-compatible local bus (DEBI never times out)
2664 writel(S626_DEBI_CFG_SLAVE16 |
2665 (S626_DEBI_TOUT << S626_DEBI_CFG_TOUT_BIT) | S626_DEBI_SWAP |
2666 S626_DEBI_CFG_INTEL, devpriv->mmio + S626_P_DEBICFG);
2668 /* Disable MMU paging */
2669 writel(S626_DEBI_PAGE_DISABLE, devpriv->mmio + S626_P_DEBIPAGE);
2671 /* Init GPIO so that ADC Start* is negated */
2672 writel(S626_GPIO_BASE | S626_GPIO1_HI, devpriv->mmio + S626_P_GPIO);
2674 /* I2C device address for onboard eeprom (revb) */
2675 devpriv->i2c_adrs = 0xA0;
2678 * Issue an I2C ABORT command to halt any I2C
2679 * operation in progress and reset BUSY flag.
2681 writel(S626_I2C_CLKSEL | S626_I2C_ABORT,
2682 devpriv->mmio + S626_P_I2CSTAT);
2683 s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
2684 while (!(readl(devpriv->mmio + S626_P_MC2) & S626_MC2_UPLD_IIC))
2688 * Per SAA7146 data sheet, write to STATUS
2689 * reg twice to reset all I2C error flags.
2691 for (i = 0; i < 2; i++) {
2692 writel(S626_I2C_CLKSEL, devpriv->mmio + S626_P_I2CSTAT);
2693 s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
2694 while (!s626_mc_test(dev, S626_MC2_UPLD_IIC, S626_P_MC2))
2699 * Init audio interface functional attributes: set DAC/ADC
2700 * serial clock rates, invert DAC serial clock so that
2701 * DAC data setup times are satisfied, enable DAC serial
2704 writel(S626_ACON2_INIT, devpriv->mmio + S626_P_ACON2);
2707 * Set up TSL1 slot list, which is used to control the
2708 * accumulation of ADC data: S626_RSD1 = shift data in on SD1.
2709 * S626_SIB_A1 = store data uint8_t at next available location
2710 * in FB BUFFER1 register.
2712 writel(S626_RSD1 | S626_SIB_A1, devpriv->mmio + S626_P_TSL1);
2713 writel(S626_RSD1 | S626_SIB_A1 | S626_EOS,
2714 devpriv->mmio + S626_P_TSL1 + 4);
2716 /* Enable TSL1 slot list so that it executes all the time */
2717 writel(S626_ACON1_ADCSTART, devpriv->mmio + S626_P_ACON1);
2720 * Initialize RPS registers used for ADC
2723 /* Physical start of RPS program */
2724 writel((uint32_t)devpriv->rps_buf.physical_base,
2725 devpriv->mmio + S626_P_RPSADDR1);
2726 /* RPS program performs no explicit mem writes */
2727 writel(0, devpriv->mmio + S626_P_RPSPAGE1);
2728 /* Disable RPS timeouts */
2729 writel(0, devpriv->mmio + S626_P_RPS1_TOUT);
2733 * SAA7146 BUG WORKAROUND
2735 * Initialize SAA7146 ADC interface to a known state by
2736 * invoking ADCs until FB BUFFER 1 register shows that it
2737 * is correctly receiving ADC data. This is necessary
2738 * because the SAA7146 ADC interface does not start up in
2739 * a defined state after a PCI reset.
2742 struct comedi_subdevice *s = dev->read_subdev;
2747 unsigned int data[16];
2749 /* Create a simple polling list for analog input channel 0 */
2750 poll_list = S626_EOPL;
2751 s626_reset_adc(dev, &poll_list);
2753 /* Get initial ADC value */
2754 s626_ai_rinsn(dev, s, NULL, data);
2755 start_val = data[0];
2758 * VERSION 2.01 CHANGE: TIMEOUT ADDED TO PREVENT HANGED
2761 * Invoke ADCs until the new ADC value differs from the initial
2762 * value or a timeout occurs. The timeout protects against the
2763 * possibility that the driver is restarting and the ADC data is
2764 * a fixed value resulting from the applied ADC analog input
2765 * being unusually quiet or at the rail.
2767 for (index = 0; index < 500; index++) {
2768 s626_ai_rinsn(dev, s, NULL, data);
2770 if (adc_data != start_val)
2774 #endif /* SAA7146 BUG WORKAROUND */
2777 * Initialize the DAC interface
2781 * Init Audio2's output DMAC attributes:
2782 * burst length = 1 DWORD
2783 * threshold = 1 DWORD.
2785 writel(0, devpriv->mmio + S626_P_PCI_BT_A);
2788 * Init Audio2's output DMA physical addresses. The protection
2789 * address is set to 1 DWORD past the base address so that a
2790 * single DWORD will be transferred each time a DMA transfer is
2793 phys_buf = devpriv->ana_buf.physical_base +
2794 (S626_DAC_WDMABUF_OS * sizeof(uint32_t));
2795 writel((uint32_t)phys_buf, devpriv->mmio + S626_P_BASEA2_OUT);
2796 writel((uint32_t)(phys_buf + sizeof(uint32_t)),
2797 devpriv->mmio + S626_P_PROTA2_OUT);
2800 * Cache Audio2's output DMA buffer logical address. This is
2801 * where DAC data is buffered for A2 output DMA transfers.
2803 devpriv->dac_wbuf = (uint32_t *)devpriv->ana_buf.logical_base +
2804 S626_DAC_WDMABUF_OS;
2807 * Audio2's output channels does not use paging. The
2808 * protection violation handling bit is set so that the
2809 * DMAC will automatically halt and its PCI address pointer
2810 * will be reset when the protection address is reached.
2812 writel(8, devpriv->mmio + S626_P_PAGEA2_OUT);
2815 * Initialize time slot list 2 (TSL2), which is used to control
2816 * the clock generation for and serialization of data to be sent
2817 * to the DAC devices. Slot 0 is a NOP that is used to trap TSL
2818 * execution; this permits other slots to be safely modified
2819 * without first turning off the TSL sequencer (which is
2820 * apparently impossible to do). Also, SD3 (which is driven by a
2821 * pull-up resistor) is shifted in and stored to the MSB of
2822 * FB_BUFFER2 to be used as evidence that the slot sequence has
2823 * not yet finished executing.
2826 /* Slot 0: Trap TSL execution, shift 0xFF into FB_BUFFER2 */
2827 writel(S626_XSD2 | S626_RSD3 | S626_SIB_A2 | S626_EOS,
2828 devpriv->mmio + S626_VECTPORT(0));
2831 * Initialize slot 1, which is constant. Slot 1 causes a
2832 * DWORD to be transferred from audio channel 2's output FIFO
2833 * to the FIFO's output buffer so that it can be serialized
2834 * and sent to the DAC during subsequent slots. All remaining
2835 * slots are dynamically populated as required by the target
2839 /* Slot 1: Fetch DWORD from Audio2's output FIFO */
2840 writel(S626_LF_A2, devpriv->mmio + S626_VECTPORT(1));
2842 /* Start DAC's audio interface (TSL2) running */
2843 writel(S626_ACON1_DACSTART, devpriv->mmio + S626_P_ACON1);
2846 * Init Trim DACs to calibrated values. Do it twice because the
2847 * SAA7146 audio channel does not always reset properly and
2848 * sometimes causes the first few TrimDAC writes to malfunction.
2850 s626_load_trim_dacs(dev);
2851 ret = s626_load_trim_dacs(dev);
2856 * Manually init all gate array hardware in case this is a soft
2857 * reset (we have no way of determining whether this is a warm
2858 * or cold start). This is necessary because the gate array will
2859 * reset only in response to a PCI hard reset; there is no soft
2864 * Init all DAC outputs to 0V and init all DAC setpoint and
2867 for (chan = 0; chan < S626_DAC_CHANNELS; chan++) {
2868 ret = s626_set_dac(dev, chan, 0);
2874 s626_counters_init(dev);
2877 * Without modifying the state of the Battery Backup enab, disable
2878 * the watchdog timer, set DIO channels 0-5 to operate in the
2879 * standard DIO (vs. counter overflow) mode, disable the battery
2880 * charger, and reset the watchdog interval selector to zero.
2882 s626_write_misc2(dev, (s626_debi_read(dev, S626_LP_RDMISC2) &
2883 S626_MISC2_BATT_ENABLE));
2885 /* Initialize the digital I/O subsystem */
2891 static int s626_auto_attach(struct comedi_device *dev,
2892 unsigned long context_unused)
2894 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2895 struct s626_private *devpriv;
2896 struct comedi_subdevice *s;
2899 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
2903 ret = comedi_pci_enable(dev);
2907 devpriv->mmio = pci_ioremap_bar(pcidev, 0);
2911 /* disable master interrupt */
2912 writel(0, devpriv->mmio + S626_P_IER);
2915 writel(S626_MC1_SOFT_RESET, devpriv->mmio + S626_P_MC1);
2917 /* DMA FIXME DMA// */
2919 ret = s626_allocate_dma_buffers(dev);
2924 ret = request_irq(pcidev->irq, s626_irq_handler, IRQF_SHARED,
2925 dev->board_name, dev);
2928 dev->irq = pcidev->irq;
2931 ret = comedi_alloc_subdevices(dev, 6);
2935 s = &dev->subdevices[0];
2936 /* analog input subdevice */
2937 s->type = COMEDI_SUBD_AI;
2938 s->subdev_flags = SDF_READABLE | SDF_DIFF;
2939 s->n_chan = S626_ADC_CHANNELS;
2940 s->maxdata = 0x3fff;
2941 s->range_table = &s626_range_table;
2942 s->len_chanlist = S626_ADC_CHANNELS;
2943 s->insn_read = s626_ai_insn_read;
2945 dev->read_subdev = s;
2946 s->subdev_flags |= SDF_CMD_READ;
2947 s->do_cmd = s626_ai_cmd;
2948 s->do_cmdtest = s626_ai_cmdtest;
2949 s->cancel = s626_ai_cancel;
2952 s = &dev->subdevices[1];
2953 /* analog output subdevice */
2954 s->type = COMEDI_SUBD_AO;
2955 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2956 s->n_chan = S626_DAC_CHANNELS;
2957 s->maxdata = 0x3fff;
2958 s->range_table = &range_bipolar10;
2959 s->insn_write = s626_ao_winsn;
2960 s->insn_read = s626_ao_rinsn;
2962 s = &dev->subdevices[2];
2963 /* digital I/O subdevice */
2964 s->type = COMEDI_SUBD_DIO;
2965 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2968 s->io_bits = 0xffff;
2969 s->private = (void *)0; /* DIO group 0 */
2970 s->range_table = &range_digital;
2971 s->insn_config = s626_dio_insn_config;
2972 s->insn_bits = s626_dio_insn_bits;
2974 s = &dev->subdevices[3];
2975 /* digital I/O subdevice */
2976 s->type = COMEDI_SUBD_DIO;
2977 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2980 s->io_bits = 0xffff;
2981 s->private = (void *)1; /* DIO group 1 */
2982 s->range_table = &range_digital;
2983 s->insn_config = s626_dio_insn_config;
2984 s->insn_bits = s626_dio_insn_bits;
2986 s = &dev->subdevices[4];
2987 /* digital I/O subdevice */
2988 s->type = COMEDI_SUBD_DIO;
2989 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2992 s->io_bits = 0xffff;
2993 s->private = (void *)2; /* DIO group 2 */
2994 s->range_table = &range_digital;
2995 s->insn_config = s626_dio_insn_config;
2996 s->insn_bits = s626_dio_insn_bits;
2998 s = &dev->subdevices[5];
2999 /* encoder (counter) subdevice */
3000 s->type = COMEDI_SUBD_COUNTER;
3001 s->subdev_flags = SDF_WRITABLE | SDF_READABLE | SDF_LSAMPL;
3002 s->n_chan = S626_ENCODER_CHANNELS;
3003 s->maxdata = 0xffffff;
3004 s->range_table = &range_unknown;
3005 s->insn_config = s626_enc_insn_config;
3006 s->insn_read = s626_enc_insn_read;
3007 s->insn_write = s626_enc_insn_write;
3009 ret = s626_initialize(dev);
3016 static void s626_detach(struct comedi_device *dev)
3018 struct s626_private *devpriv = dev->private;
3021 /* stop ai_command */
3022 devpriv->ai_cmd_running = 0;
3024 if (devpriv->mmio) {
3025 /* interrupt mask */
3026 /* Disable master interrupt */
3027 writel(0, devpriv->mmio + S626_P_IER);
3028 /* Clear board's IRQ status flag */
3029 writel(S626_IRQ_GPIO3 | S626_IRQ_RPS1,
3030 devpriv->mmio + S626_P_ISR);
3032 /* Disable the watchdog timer and battery charger. */
3033 s626_write_misc2(dev, 0);
3035 /* Close all interfaces on 7146 device */
3036 writel(S626_MC1_SHUTDOWN, devpriv->mmio + S626_P_MC1);
3037 writel(S626_ACON1_BASE, devpriv->mmio + S626_P_ACON1);
3039 s626_close_dma_b(dev, &devpriv->rps_buf,
3041 s626_close_dma_b(dev, &devpriv->ana_buf,
3046 free_irq(dev->irq, dev);
3048 iounmap(devpriv->mmio);
3050 comedi_pci_disable(dev);
3053 static struct comedi_driver s626_driver = {
3054 .driver_name = "s626",
3055 .module = THIS_MODULE,
3056 .auto_attach = s626_auto_attach,
3057 .detach = s626_detach,
3060 static int s626_pci_probe(struct pci_dev *dev,
3061 const struct pci_device_id *id)
3063 return comedi_pci_auto_config(dev, &s626_driver, id->driver_data);
3067 * For devices with vendor:device id == 0x1131:0x7146 you must specify
3068 * also subvendor:subdevice ids, because otherwise it will conflict with
3069 * Philips SAA7146 media/dvb based cards.
3071 static const struct pci_device_id s626_pci_table[] = {
3072 { PCI_DEVICE_SUB(PCI_VENDOR_ID_PHILIPS, PCI_DEVICE_ID_PHILIPS_SAA7146,
3076 MODULE_DEVICE_TABLE(pci, s626_pci_table);
3078 static struct pci_driver s626_pci_driver = {
3080 .id_table = s626_pci_table,
3081 .probe = s626_pci_probe,
3082 .remove = comedi_pci_auto_unconfig,
3084 module_comedi_pci_driver(s626_driver, s626_pci_driver);
3086 MODULE_AUTHOR("Gianluca Palli <gpalli@deis.unibo.it>");
3087 MODULE_DESCRIPTION("Sensoray 626 Comedi driver module");
3088 MODULE_LICENSE("GPL");