3 Sensoray s626 Comedi driver
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 2000 David A. Schleef <ds@schleef.org>
8 Based on Sensoray Model 626 Linux driver Version 0.2
9 Copyright (C) 2002-2004 Sensoray Co., Inc.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 Description: Sensoray 626 driver
30 Devices: [Sensoray] 626 (s626)
31 Authors: Gianluca Palli <gpalli@deis.unibo.it>,
32 Updated: Fri, 15 Feb 2008 10:28:42 +0000
35 Configuration options: not applicable, uses PCI auto config
37 INSN_CONFIG instructions:
45 s626 has 3 dio subdevices (2,3 and 4) each with 16 i/o channels
46 supported configuration options:
52 Every channel must be configured before reading.
56 insn.insn=INSN_CONFIG; //configuration instruction
57 insn.n=1; //number of operation (must be 1)
58 insn.data=&initialvalue; //initial value loaded into encoder
59 //during configuration
60 insn.subdev=5; //encoder subdevice
61 insn.chanspec=CR_PACK(encoder_channel,0,AREF_OTHER); //encoder_channel
64 comedi_do_insn(cf,&insn); //executing configuration
67 #include <linux/pci.h>
68 #include <linux/interrupt.h>
69 #include <linux/kernel.h>
70 #include <linux/types.h>
72 #include "../comedidev.h"
74 #include "comedi_fc.h"
77 #define PCI_VENDOR_ID_S626 0x1131
78 #define PCI_DEVICE_ID_S626 0x7146
79 #define PCI_SUBVENDOR_ID_S626 0x6000
80 #define PCI_SUBDEVICE_ID_S626 0x0272
83 void __iomem *base_addr;
84 uint8_t ai_cmd_running; /* ai_cmd is running */
85 uint8_t ai_continous; /* continous acquisition */
86 int ai_sample_count; /* number of samples to acquire */
87 unsigned int ai_sample_timer;
88 /* time between samples in units of the timer */
89 int ai_convert_count; /* conversion counter */
90 unsigned int ai_convert_timer;
91 /* time between conversion in units of the timer */
92 uint16_t CounterIntEnabs;
93 /* Counter interrupt enable mask for MISC2 register. */
94 uint8_t AdcItems; /* Number of items in ADC poll list. */
95 struct bufferDMA RPSBuf; /* DMA buffer used to hold ADC (RPS1) program. */
96 struct bufferDMA ANABuf;
97 /* DMA buffer used to receive ADC data and hold DAC data. */
99 /* Pointer to logical adrs of DMA buffer used to hold DAC data. */
100 uint16_t Dacpol; /* Image of DAC polarity register. */
101 uint8_t TrimSetpoint[12]; /* Images of TrimDAC setpoints */
102 /* Charge Enabled (0 or WRMISC2_CHARGE_ENABLE). */
104 /* I2C device address for onboard EEPROM (board rev dependent). */
106 unsigned int ao_readback[S626_DAC_CHANNELS];
109 /* COUNTER OBJECT ------------------------------------------------ */
111 /* Pointers to functions that differ for A and B counters: */
112 uint16_t(*GetEnable) (struct comedi_device *dev, struct enc_private *); /* Return clock enable. */
113 uint16_t(*GetIntSrc) (struct comedi_device *dev, struct enc_private *); /* Return interrupt source. */
114 uint16_t(*GetLoadTrig) (struct comedi_device *dev, struct enc_private *); /* Return preload trigger source. */
115 uint16_t(*GetMode) (struct comedi_device *dev, struct enc_private *); /* Return standardized operating mode. */
116 void (*PulseIndex) (struct comedi_device *dev, struct enc_private *); /* Generate soft index strobe. */
117 void (*SetEnable) (struct comedi_device *dev, struct enc_private *, uint16_t enab); /* Program clock enable. */
118 void (*SetIntSrc) (struct comedi_device *dev, struct enc_private *, uint16_t IntSource); /* Program interrupt source. */
119 void (*SetLoadTrig) (struct comedi_device *dev, struct enc_private *, uint16_t Trig); /* Program preload trigger source. */
120 void (*SetMode) (struct comedi_device *dev, struct enc_private *, uint16_t Setup, uint16_t DisableIntSrc); /* Program standardized operating mode. */
121 void (*ResetCapFlags) (struct comedi_device *dev, struct enc_private *); /* Reset event capture flags. */
123 uint16_t MyCRA; /* Address of CRA register. */
124 uint16_t MyCRB; /* Address of CRB register. */
125 uint16_t MyLatchLsw; /* Address of Latch least-significant-word */
127 uint16_t MyEventBits[4]; /* Bit translations for IntSrc -->RDMISC2. */
130 #define encpriv ((struct enc_private *)(dev->subdevices+5)->private)
132 /* Counter overflow/index event flag masks for RDMISC2. */
133 #define INDXMASK(C) (1 << (((C) > 2) ? ((C) * 2 - 1) : ((C) * 2 + 4)))
134 #define OVERMASK(C) (1 << (((C) > 2) ? ((C) * 2 + 5) : ((C) * 2 + 10)))
135 #define EVBITS(C) { 0, OVERMASK(C), INDXMASK(C), OVERMASK(C) | INDXMASK(C) }
137 /* Translation table to map IntSrc into equivalent RDMISC2 event flag bits. */
138 /* static const uint16_t EventBits[][4] = { EVBITS(0), EVBITS(1), EVBITS(2), EVBITS(3), EVBITS(4), EVBITS(5) }; */
141 * Enable/disable a function or test status bit(s) that are accessed
142 * through Main Control Registers 1 or 2.
144 static void s626_mc_enable(struct comedi_device *dev,
145 unsigned int cmd, unsigned int reg)
147 struct s626_private *devpriv = dev->private;
148 unsigned int val = (cmd << 16) | cmd;
150 writel(val, devpriv->base_addr + reg);
153 #define MC_DISABLE(REGADRS, CTRLWORD) writel((uint32_t)(CTRLWORD) << 16 , devpriv->base_addr+(REGADRS))
155 #define MC_TEST(REGADRS, CTRLWORD) ((readl(devpriv->base_addr+(REGADRS)) & CTRLWORD) != 0)
157 /* #define WR7146(REGARDS,CTRLWORD)
158 writel(CTRLWORD,(uint32_t)(devpriv->base_addr+(REGARDS))) */
159 #define WR7146(REGARDS, CTRLWORD) writel(CTRLWORD, devpriv->base_addr+(REGARDS))
161 /* #define RR7146(REGARDS)
162 readl((uint32_t)(devpriv->base_addr+(REGARDS))) */
163 #define RR7146(REGARDS) readl(devpriv->base_addr+(REGARDS))
165 #define BUGFIX_STREG(REGADRS) (REGADRS - 4)
167 /* Write a time slot control record to TSL2. */
168 #define VECTPORT(VECTNUM) (P_TSL2 + ((VECTNUM) << 2))
169 #define SETVECT(VECTNUM, VECTVAL) WR7146(VECTPORT(VECTNUM), (VECTVAL))
171 /* Code macros used for constructing I2C command bytes. */
172 #define I2C_B2(ATTR, VAL) (((ATTR) << 6) | ((VAL) << 24))
173 #define I2C_B1(ATTR, VAL) (((ATTR) << 4) | ((VAL) << 16))
174 #define I2C_B0(ATTR, VAL) (((ATTR) << 2) | ((VAL) << 8))
176 static const struct comedi_lrange s626_range_table = {
183 /* Execute a DEBI transfer. This must be called from within a */
184 /* critical section. */
185 static void DEBItransfer(struct comedi_device *dev)
187 struct s626_private *devpriv = dev->private;
189 /* Initiate upload of shadow RAM to DEBI control register */
190 s626_mc_enable(dev, MC2_UPLD_DEBI, P_MC2);
192 /* Wait for completion of upload from shadow RAM to DEBI control */
194 while (!MC_TEST(P_MC2, MC2_UPLD_DEBI))
197 /* Wait until DEBI transfer is done. */
198 while (RR7146(P_PSR) & PSR_DEBI_S)
202 /* Initialize the DEBI interface for all transfers. */
204 static uint16_t DEBIread(struct comedi_device *dev, uint16_t addr)
206 struct s626_private *devpriv = dev->private;
209 /* Set up DEBI control register value in shadow RAM. */
210 WR7146(P_DEBICMD, DEBI_CMD_RDWORD | addr);
212 /* Execute the DEBI transfer. */
215 /* Fetch target register value. */
216 retval = (uint16_t) RR7146(P_DEBIAD);
218 /* Return register value. */
222 /* Write a value to a gate array register. */
223 static void DEBIwrite(struct comedi_device *dev, uint16_t addr, uint16_t wdata)
225 struct s626_private *devpriv = dev->private;
227 /* Set up DEBI control register value in shadow RAM. */
228 WR7146(P_DEBICMD, DEBI_CMD_WRWORD | addr);
229 WR7146(P_DEBIAD, wdata);
231 /* Execute the DEBI transfer. */
235 /* Replace the specified bits in a gate array register. Imports: mask
236 * specifies bits that are to be preserved, wdata is new value to be
237 * or'd with the masked original.
239 static void DEBIreplace(struct comedi_device *dev, uint16_t addr, uint16_t mask,
242 struct s626_private *devpriv = dev->private;
244 /* Copy target gate array register into P_DEBIAD register. */
245 WR7146(P_DEBICMD, DEBI_CMD_RDWORD | addr);
246 /* Set up DEBI control reg value in shadow RAM. */
247 DEBItransfer(dev); /* Execute the DEBI Read transfer. */
249 /* Write back the modified image. */
250 WR7146(P_DEBICMD, DEBI_CMD_WRWORD | addr);
251 /* Set up DEBI control reg value in shadow RAM. */
253 WR7146(P_DEBIAD, wdata | ((uint16_t) RR7146(P_DEBIAD) & mask));
254 /* Modify the register image. */
255 DEBItransfer(dev); /* Execute the DEBI Write transfer. */
258 /* ************** EEPROM ACCESS FUNCTIONS ************** */
260 static uint32_t I2Chandshake(struct comedi_device *dev, uint32_t val)
262 struct s626_private *devpriv = dev->private;
264 /* Write I2C command to I2C Transfer Control shadow register. */
265 WR7146(P_I2CCTRL, val);
268 * Upload I2C shadow registers into working registers and
269 * wait for upload confirmation.
271 s626_mc_enable(dev, MC2_UPLD_IIC, P_MC2);
272 while (!MC_TEST(P_MC2, MC2_UPLD_IIC))
275 /* Wait until I2C bus transfer is finished or an error occurs. */
276 while ((RR7146(P_I2CCTRL) & (I2C_BUSY | I2C_ERR)) == I2C_BUSY)
279 /* Return non-zero if I2C error occurred. */
280 return RR7146(P_I2CCTRL) & I2C_ERR;
284 /* Read uint8_t from EEPROM. */
285 static uint8_t I2Cread(struct comedi_device *dev, uint8_t addr)
287 struct s626_private *devpriv = dev->private;
290 /* Send EEPROM target address. */
291 if (I2Chandshake(dev, I2C_B2(I2C_ATTRSTART, I2CW)
292 /* Byte2 = I2C command: write to I2C EEPROM device. */
293 | I2C_B1(I2C_ATTRSTOP, addr)
294 /* Byte1 = EEPROM internal target address. */
295 | I2C_B0(I2C_ATTRNOP, 0))) { /* Byte0 = Not sent. */
296 /* Abort function and declare error if handshake failed. */
299 /* Execute EEPROM read. */
300 if (I2Chandshake(dev, I2C_B2(I2C_ATTRSTART, I2CR)
304 /* from I2C EEPROM */
306 |I2C_B1(I2C_ATTRSTOP, 0)
311 |I2C_B0(I2C_ATTRNOP, 0))) { /* Byte0 = Not sent. */
313 /* Abort function and declare error if handshake failed. */
316 /* Return copy of EEPROM value. */
317 rtnval = (uint8_t) (RR7146(P_I2CCTRL) >> 16);
321 /* *********** DAC FUNCTIONS *********** */
323 /* Slot 0 base settings. */
324 #define VECT0 (XSD2 | RSD3 | SIB_A2)
325 /* Slot 0 always shifts in 0xFF and store it to FB_BUFFER2. */
327 /* TrimDac LogicalChan-to-PhysicalChan mapping table. */
328 static uint8_t trimchan[] = { 10, 9, 8, 3, 2, 7, 6, 1, 0, 5, 4 };
330 /* TrimDac LogicalChan-to-EepromAdrs mapping table. */
331 static uint8_t trimadrs[] = { 0x40, 0x41, 0x42, 0x50, 0x51, 0x52, 0x53, 0x60, 0x61, 0x62, 0x63 };
333 /* Private helper function: Transmit serial data to DAC via Audio
334 * channel 2. Assumes: (1) TSL2 slot records initialized, and (2)
335 * Dacpol contains valid target image.
337 static void SendDAC(struct comedi_device *dev, uint32_t val)
339 struct s626_private *devpriv = dev->private;
341 /* START THE SERIAL CLOCK RUNNING ------------- */
343 /* Assert DAC polarity control and enable gating of DAC serial clock
344 * and audio bit stream signals. At this point in time we must be
345 * assured of being in time slot 0. If we are not in slot 0, the
346 * serial clock and audio stream signals will be disabled; this is
347 * because the following DEBIwrite statement (which enables signals
348 * to be passed through the gate array) would execute before the
349 * trailing edge of WS1/WS3 (which turns off the signals), thus
350 * causing the signals to be inactive during the DAC write.
352 DEBIwrite(dev, LP_DACPOL, devpriv->Dacpol);
354 /* TRANSFER OUTPUT DWORD VALUE INTO A2'S OUTPUT FIFO ---------------- */
356 /* Copy DAC setpoint value to DAC's output DMA buffer. */
358 /* WR7146( (uint32_t)devpriv->pDacWBuf, val ); */
359 *devpriv->pDacWBuf = val;
362 * Enable the output DMA transfer. This will cause the DMAC to copy
363 * the DAC's data value to A2's output FIFO. The DMA transfer will
364 * then immediately terminate because the protection address is
365 * reached upon transfer of the first DWORD value.
367 s626_mc_enable(dev, MC1_A2OUT, P_MC1);
369 /* While the DMA transfer is executing ... */
371 /* Reset Audio2 output FIFO's underflow flag (along with any other
372 * FIFO underflow/overflow flags). When set, this flag will
373 * indicate that we have emerged from slot 0.
375 WR7146(P_ISR, ISR_AFOU);
377 /* Wait for the DMA transfer to finish so that there will be data
378 * available in the FIFO when time slot 1 tries to transfer a DWORD
379 * from the FIFO to the output buffer register. We test for DMA
380 * Done by polling the DMAC enable flag; this flag is automatically
381 * cleared when the transfer has finished.
383 while ((RR7146(P_MC1) & MC1_A2OUT) != 0)
386 /* START THE OUTPUT STREAM TO THE TARGET DAC -------------------- */
388 /* FIFO data is now available, so we enable execution of time slots
389 * 1 and higher by clearing the EOS flag in slot 0. Note that SD3
390 * will be shifted in and stored in FB_BUFFER2 for end-of-slot-list
393 SETVECT(0, XSD2 | RSD3 | SIB_A2);
395 /* Wait for slot 1 to execute to ensure that the Packet will be
396 * transmitted. This is detected by polling the Audio2 output FIFO
397 * underflow flag, which will be set when slot 1 execution has
398 * finished transferring the DAC's data DWORD from the output FIFO
399 * to the output buffer register.
401 while ((RR7146(P_SSR) & SSR_AF2_OUT) == 0)
404 /* Set up to trap execution at slot 0 when the TSL sequencer cycles
405 * back to slot 0 after executing the EOS in slot 5. Also,
406 * simultaneously shift out and in the 0x00 that is ALWAYS the value
407 * stored in the last byte to be shifted out of the FIFO's DWORD
410 SETVECT(0, XSD2 | XFIFO_2 | RSD2 | SIB_A2 | EOS);
412 /* WAIT FOR THE TRANSACTION TO FINISH ----------------------- */
414 /* Wait for the TSL to finish executing all time slots before
415 * exiting this function. We must do this so that the next DAC
416 * write doesn't start, thereby enabling clock/chip select signals:
418 * 1. Before the TSL sequence cycles back to slot 0, which disables
419 * the clock/cs signal gating and traps slot // list execution.
420 * we have not yet finished slot 5 then the clock/cs signals are
421 * still gated and we have not finished transmitting the stream.
423 * 2. While slots 2-5 are executing due to a late slot 0 trap. In
424 * this case, the slot sequence is currently repeating, but with
425 * clock/cs signals disabled. We must wait for slot 0 to trap
426 * execution before setting up the next DAC setpoint DMA transfer
427 * and enabling the clock/cs signals. To detect the end of slot 5,
428 * we test for the FB_BUFFER2 MSB contents to be equal to 0xFF. If
429 * the TSL has not yet finished executing slot 5 ...
431 if ((RR7146(P_FB_BUFFER2) & 0xFF000000) != 0) {
432 /* The trap was set on time and we are still executing somewhere
433 * in slots 2-5, so we now wait for slot 0 to execute and trap
434 * TSL execution. This is detected when FB_BUFFER2 MSB changes
435 * from 0xFF to 0x00, which slot 0 causes to happen by shifting
436 * out/in on SD2 the 0x00 that is always referenced by slot 5.
438 while ((RR7146(P_FB_BUFFER2) & 0xFF000000) != 0)
441 /* Either (1) we were too late setting the slot 0 trap; the TSL
442 * sequencer restarted slot 0 before we could set the EOS trap flag,
443 * or (2) we were not late and execution is now trapped at slot 0.
444 * In either case, we must now change slot 0 so that it will store
445 * value 0xFF (instead of 0x00) to FB_BUFFER2 next time it executes.
446 * In order to do this, we reprogram slot 0 so that it will shift in
447 * SD3, which is driven only by a pull-up resistor.
449 SETVECT(0, RSD3 | SIB_A2 | EOS);
451 /* Wait for slot 0 to execute, at which time the TSL is setup for
452 * the next DAC write. This is detected when FB_BUFFER2 MSB changes
455 while ((RR7146(P_FB_BUFFER2) & 0xFF000000) == 0)
459 /* Private helper function: Write setpoint to an application DAC channel. */
460 static void SetDAC(struct comedi_device *dev, uint16_t chan, short dacdata)
462 struct s626_private *devpriv = dev->private;
463 register uint16_t signmask;
464 register uint32_t WSImage;
466 /* Adjust DAC data polarity and set up Polarity Control Register */
468 signmask = 1 << chan;
471 devpriv->Dacpol |= signmask;
473 devpriv->Dacpol &= ~signmask;
475 /* Limit DAC setpoint value to valid range. */
476 if ((uint16_t) dacdata > 0x1FFF)
479 /* Set up TSL2 records (aka "vectors") for DAC update. Vectors V2
480 * and V3 transmit the setpoint to the target DAC. V4 and V5 send
481 * data to a non-existent TrimDac channel just to keep the clock
482 * running after sending data to the target DAC. This is necessary
483 * to eliminate the clock glitch that would otherwise occur at the
484 * end of the target DAC's serial data stream. When the sequence
485 * restarts at V0 (after executing V5), the gate array automatically
486 * disables gating for the DAC clock and all DAC chip selects.
489 WSImage = (chan & 2) ? WS1 : WS2;
490 /* Choose DAC chip select to be asserted. */
491 SETVECT(2, XSD2 | XFIFO_1 | WSImage);
492 /* Slot 2: Transmit high data byte to target DAC. */
493 SETVECT(3, XSD2 | XFIFO_0 | WSImage);
494 /* Slot 3: Transmit low data byte to target DAC. */
495 SETVECT(4, XSD2 | XFIFO_3 | WS3);
496 /* Slot 4: Transmit to non-existent TrimDac channel to keep clock */
497 SETVECT(5, XSD2 | XFIFO_2 | WS3 | EOS);
498 /* Slot 5: running after writing target DAC's low data byte. */
500 /* Construct and transmit target DAC's serial packet:
501 * ( A10D DDDD ),( DDDD DDDD ),( 0x0F ),( 0x00 ) where A is chan<0>,
502 * and D<12:0> is the DAC setpoint. Append a WORD value (that writes
503 * to a non-existent TrimDac channel) that serves to keep the clock
504 * running after the packet has been sent to the target DAC.
506 SendDAC(dev, 0x0F000000
507 /* Continue clock after target DAC data (write to non-existent trimdac). */
509 /* Address the two main dual-DAC devices (TSL's chip select enables
511 | ((uint32_t) (chan & 1) << 15)
512 /* Address the DAC channel within the device. */
513 | (uint32_t) dacdata); /* Include DAC setpoint data. */
517 static void WriteTrimDAC(struct comedi_device *dev, uint8_t LogicalChan,
520 struct s626_private *devpriv = dev->private;
523 /* Save the new setpoint in case the application needs to read it back later. */
524 devpriv->TrimSetpoint[LogicalChan] = (uint8_t) DacData;
526 /* Map logical channel number to physical channel number. */
527 chan = (uint32_t) trimchan[LogicalChan];
529 /* Set up TSL2 records for TrimDac write operation. All slots shift
530 * 0xFF in from pulled-up SD3 so that the end of the slot sequence
534 SETVECT(2, XSD2 | XFIFO_1 | WS3);
535 /* Slot 2: Send high uint8_t to target TrimDac. */
536 SETVECT(3, XSD2 | XFIFO_0 | WS3);
537 /* Slot 3: Send low uint8_t to target TrimDac. */
538 SETVECT(4, XSD2 | XFIFO_3 | WS1);
539 /* Slot 4: Send NOP high uint8_t to DAC0 to keep clock running. */
540 SETVECT(5, XSD2 | XFIFO_2 | WS1 | EOS);
541 /* Slot 5: Send NOP low uint8_t to DAC0. */
543 /* Construct and transmit target DAC's serial packet:
544 * ( 0000 AAAA ), ( DDDD DDDD ),( 0x00 ),( 0x00 ) where A<3:0> is the
545 * DAC channel's address, and D<7:0> is the DAC setpoint. Append a
546 * WORD value (that writes a channel 0 NOP command to a non-existent
547 * main DAC channel) that serves to keep the clock running after the
548 * packet has been sent to the target DAC.
551 /* Address the DAC channel within the trimdac device. */
552 SendDAC(dev, ((uint32_t) chan << 8)
553 | (uint32_t) DacData); /* Include DAC setpoint data. */
556 static void LoadTrimDACs(struct comedi_device *dev)
560 /* Copy TrimDac setpoint values from EEPROM to TrimDacs. */
561 for (i = 0; i < ARRAY_SIZE(trimchan); i++)
562 WriteTrimDAC(dev, i, I2Cread(dev, trimadrs[i]));
565 /* ****** COUNTER FUNCTIONS ******* */
566 /* All counter functions address a specific counter by means of the
567 * "Counter" argument, which is a logical counter number. The Counter
568 * argument may have any of the following legal values: 0=0A, 1=1A,
569 * 2=2A, 3=0B, 4=1B, 5=2B.
572 /* Read a counter's output latch. */
573 static uint32_t ReadLatch(struct comedi_device *dev, struct enc_private *k)
575 register uint32_t value;
577 /* Latch counts and fetch LSW of latched counts value. */
578 value = (uint32_t) DEBIread(dev, k->MyLatchLsw);
580 /* Fetch MSW of latched counts and combine with LSW. */
581 value |= ((uint32_t) DEBIread(dev, k->MyLatchLsw + 2) << 16);
583 /* Return latched counts. */
587 /* Return/set a counter pair's latch trigger source. 0: On read
588 * access, 1: A index latches A, 2: B index latches B, 3: A overflow
591 static void SetLatchSource(struct comedi_device *dev, struct enc_private *k,
594 DEBIreplace(dev, k->MyCRB,
595 (uint16_t) (~(CRBMSK_INTCTRL | CRBMSK_LATCHSRC)),
596 (uint16_t) (value << CRBBIT_LATCHSRC));
599 /* Write value into counter preload register. */
600 static void Preload(struct comedi_device *dev, struct enc_private *k,
603 DEBIwrite(dev, (uint16_t) (k->MyLatchLsw), (uint16_t) value);
604 DEBIwrite(dev, (uint16_t) (k->MyLatchLsw + 2),
605 (uint16_t) (value >> 16));
608 static unsigned int s626_ai_reg_to_uint(int data)
610 unsigned int tempdata;
612 tempdata = (data >> 18);
613 if (tempdata & 0x2000)
616 tempdata += (1 << 13);
621 /* static unsigned int s626_uint_to_reg(struct comedi_subdevice *s, int data){ */
625 static int s626_dio_set_irq(struct comedi_device *dev, unsigned int chan)
627 unsigned int group = chan / 16;
628 unsigned int mask = 1 << (chan - (16 * group));
631 /* set channel to capture positive edge */
632 status = DEBIread(dev, LP_RDEDGSEL(group));
633 DEBIwrite(dev, LP_WREDGSEL(group), mask | status);
635 /* enable interrupt on selected channel */
636 status = DEBIread(dev, LP_RDINTSEL(group));
637 DEBIwrite(dev, LP_WRINTSEL(group), mask | status);
639 /* enable edge capture write command */
640 DEBIwrite(dev, LP_MISC1, MISC1_EDCAP);
642 /* enable edge capture on selected channel */
643 status = DEBIread(dev, LP_RDCAPSEL(group));
644 DEBIwrite(dev, LP_WRCAPSEL(group), mask | status);
649 static int s626_dio_reset_irq(struct comedi_device *dev, unsigned int group,
652 /* disable edge capture write command */
653 DEBIwrite(dev, LP_MISC1, MISC1_NOEDCAP);
655 /* enable edge capture on selected channel */
656 DEBIwrite(dev, LP_WRCAPSEL(group), mask);
661 static int s626_dio_clear_irq(struct comedi_device *dev)
665 /* disable edge capture write command */
666 DEBIwrite(dev, LP_MISC1, MISC1_NOEDCAP);
668 /* clear all dio pending events and interrupt */
669 for (group = 0; group < S626_DIO_BANKS; group++)
670 DEBIwrite(dev, LP_WRCAPSEL(group), 0xffff);
675 static void handle_dio_interrupt(struct comedi_device *dev,
676 uint16_t irqbit, uint8_t group)
678 struct s626_private *devpriv = dev->private;
679 struct comedi_subdevice *s = dev->read_subdev;
680 struct comedi_cmd *cmd = &s->async->cmd;
682 s626_dio_reset_irq(dev, group, irqbit);
684 if (devpriv->ai_cmd_running) {
685 /* check if interrupt is an ai acquisition start trigger */
686 if ((irqbit >> (cmd->start_arg - (16 * group))) == 1 &&
687 cmd->start_src == TRIG_EXT) {
688 /* Start executing the RPS program */
689 s626_mc_enable(dev, MC1_ERPS1, P_MC1);
691 if (cmd->scan_begin_src == TRIG_EXT)
692 s626_dio_set_irq(dev, cmd->scan_begin_arg);
694 if ((irqbit >> (cmd->scan_begin_arg - (16 * group))) == 1 &&
695 cmd->scan_begin_src == TRIG_EXT) {
696 /* Trigger ADC scan loop start */
697 s626_mc_enable(dev, MC2_ADC_RPS, P_MC2);
699 if (cmd->convert_src == TRIG_EXT) {
700 devpriv->ai_convert_count = cmd->chanlist_len;
702 s626_dio_set_irq(dev, cmd->convert_arg);
705 if (cmd->convert_src == TRIG_TIMER) {
706 struct enc_private *k = &encpriv[5];
708 devpriv->ai_convert_count = cmd->chanlist_len;
709 k->SetEnable(dev, k, CLKENAB_ALWAYS);
712 if ((irqbit >> (cmd->convert_arg - (16 * group))) == 1 &&
713 cmd->convert_src == TRIG_EXT) {
714 /* Trigger ADC scan loop start */
715 s626_mc_enable(dev, MC2_ADC_RPS, P_MC2);
717 devpriv->ai_convert_count--;
718 if (devpriv->ai_convert_count > 0)
719 s626_dio_set_irq(dev, cmd->convert_arg);
724 static void check_dio_interrupts(struct comedi_device *dev)
729 for (group = 0; group < S626_DIO_BANKS; group++) {
731 /* read interrupt type */
732 irqbit = DEBIread(dev, LP_RDCAPFLG(group));
734 /* check if interrupt is generated from dio channels */
736 handle_dio_interrupt(dev, irqbit, group);
742 static void check_counter_interrupts(struct comedi_device *dev)
744 struct s626_private *devpriv = dev->private;
745 struct comedi_subdevice *s = dev->read_subdev;
746 struct comedi_async *async = s->async;
747 struct comedi_cmd *cmd = &async->cmd;
748 struct enc_private *k;
751 /* read interrupt type */
752 irqbit = DEBIread(dev, LP_RDMISC2);
754 /* check interrupt on counters */
755 if (irqbit & IRQ_COINT1A) {
758 /* clear interrupt capture flag */
759 k->ResetCapFlags(dev, k);
761 if (irqbit & IRQ_COINT2A) {
764 /* clear interrupt capture flag */
765 k->ResetCapFlags(dev, k);
767 if (irqbit & IRQ_COINT3A) {
770 /* clear interrupt capture flag */
771 k->ResetCapFlags(dev, k);
773 if (irqbit & IRQ_COINT1B) {
776 /* clear interrupt capture flag */
777 k->ResetCapFlags(dev, k);
779 if (irqbit & IRQ_COINT2B) {
782 /* clear interrupt capture flag */
783 k->ResetCapFlags(dev, k);
785 if (devpriv->ai_convert_count > 0) {
786 devpriv->ai_convert_count--;
787 if (devpriv->ai_convert_count == 0)
788 k->SetEnable(dev, k, CLKENAB_INDEX);
790 if (cmd->convert_src == TRIG_TIMER) {
791 /* Trigger ADC scan loop start */
792 s626_mc_enable(dev, MC2_ADC_RPS, P_MC2);
796 if (irqbit & IRQ_COINT3B) {
799 /* clear interrupt capture flag */
800 k->ResetCapFlags(dev, k);
802 if (cmd->scan_begin_src == TRIG_TIMER) {
803 /* Trigger ADC scan loop start */
804 s626_mc_enable(dev, MC2_ADC_RPS, P_MC2);
807 if (cmd->convert_src == TRIG_TIMER) {
809 devpriv->ai_convert_count = cmd->chanlist_len;
810 k->SetEnable(dev, k, CLKENAB_ALWAYS);
815 static bool handle_eos_interrupt(struct comedi_device *dev)
817 struct s626_private *devpriv = dev->private;
818 struct comedi_subdevice *s = dev->read_subdev;
819 struct comedi_async *async = s->async;
820 struct comedi_cmd *cmd = &async->cmd;
822 * Init ptr to DMA buffer that holds new ADC data. We skip the
823 * first uint16_t in the buffer because it contains junk data
824 * from the final ADC of the previous poll list scan.
826 int32_t *readaddr = (int32_t *)devpriv->ANABuf.LogicalBase + 1;
827 bool finished = false;
830 /* get the data and hand it over to comedi */
831 for (i = 0; i < cmd->chanlist_len; i++) {
835 * Convert ADC data to 16-bit integer values and copy
836 * to application buffer.
838 tempdata = s626_ai_reg_to_uint((int)*readaddr);
841 /* put data into read buffer */
842 /* comedi_buf_put(async, tempdata); */
843 cfc_write_to_buffer(s, tempdata);
846 /* end of scan occurs */
847 async->events |= COMEDI_CB_EOS;
849 if (!devpriv->ai_continous)
850 devpriv->ai_sample_count--;
851 if (devpriv->ai_sample_count <= 0) {
852 devpriv->ai_cmd_running = 0;
854 /* Stop RPS program. */
855 MC_DISABLE(P_MC1, MC1_ERPS1);
857 /* send end of acquisition */
858 async->events |= COMEDI_CB_EOA;
860 /* disable master interrupt */
864 if (devpriv->ai_cmd_running && cmd->scan_begin_src == TRIG_EXT)
865 s626_dio_set_irq(dev, cmd->scan_begin_arg);
867 /* tell comedi that data is there */
868 comedi_event(dev, s);
873 static irqreturn_t s626_irq_handler(int irq, void *d)
875 struct comedi_device *dev = d;
876 struct s626_private *devpriv = dev->private;
878 uint32_t irqtype, irqstatus;
882 /* lock to avoid race with comedi_poll */
883 spin_lock_irqsave(&dev->spinlock, flags);
885 /* save interrupt enable register state */
886 irqstatus = readl(devpriv->base_addr + P_IER);
888 /* read interrupt type */
889 irqtype = readl(devpriv->base_addr + P_ISR);
891 /* disable master interrupt */
892 writel(0, devpriv->base_addr + P_IER);
894 /* clear interrupt */
895 writel(irqtype, devpriv->base_addr + P_ISR);
898 case IRQ_RPS1: /* end_of_scan occurs */
899 if (handle_eos_interrupt(dev))
902 case IRQ_GPIO3: /* check dio and conter interrupt */
903 /* s626_dio_clear_irq(dev); */
904 check_dio_interrupts(dev);
905 check_counter_interrupts(dev);
909 /* enable interrupt */
910 writel(irqstatus, devpriv->base_addr + P_IER);
912 spin_unlock_irqrestore(&dev->spinlock, flags);
917 * this functions build the RPS program for hardware driven acquistion
919 static void ResetADC(struct comedi_device *dev, uint8_t *ppl)
921 struct s626_private *devpriv = dev->private;
922 register uint32_t *pRPS;
927 struct comedi_cmd *cmd = &(dev->subdevices->async->cmd);
929 /* Stop RPS program in case it is currently running. */
930 MC_DISABLE(P_MC1, MC1_ERPS1);
932 /* Set starting logical address to write RPS commands. */
933 pRPS = (uint32_t *) devpriv->RPSBuf.LogicalBase;
935 /* Initialize RPS instruction pointer. */
936 WR7146(P_RPSADDR1, (uint32_t) devpriv->RPSBuf.PhysicalBase);
938 /* Construct RPS program in RPSBuf DMA buffer */
940 if (cmd != NULL && cmd->scan_begin_src != TRIG_FOLLOW) {
941 /* Wait for Start trigger. */
942 *pRPS++ = RPS_PAUSE | RPS_SIGADC;
943 *pRPS++ = RPS_CLRSIGNAL | RPS_SIGADC;
946 /* SAA7146 BUG WORKAROUND Do a dummy DEBI Write. This is necessary
947 * because the first RPS DEBI Write following a non-RPS DEBI write
948 * seems to always fail. If we don't do this dummy write, the ADC
949 * gain might not be set to the value required for the first slot in
950 * the poll list; the ADC gain would instead remain unchanged from
951 * the previously programmed value.
953 *pRPS++ = RPS_LDREG | (P_DEBICMD >> 2);
954 /* Write DEBI Write command and address to shadow RAM. */
956 *pRPS++ = DEBI_CMD_WRWORD | LP_GSEL;
957 *pRPS++ = RPS_LDREG | (P_DEBIAD >> 2);
958 /* Write DEBI immediate data to shadow RAM: */
960 *pRPS++ = GSEL_BIPOLAR5V;
961 /* arbitrary immediate data value. */
963 *pRPS++ = RPS_CLRSIGNAL | RPS_DEBI;
964 /* Reset "shadow RAM uploaded" flag. */
965 *pRPS++ = RPS_UPLOAD | RPS_DEBI; /* Invoke shadow RAM upload. */
966 *pRPS++ = RPS_PAUSE | RPS_DEBI; /* Wait for shadow upload to finish. */
968 /* Digitize all slots in the poll list. This is implemented as a
969 * for loop to limit the slot count to 16 in case the application
970 * forgot to set the EOPL flag in the final slot.
972 for (devpriv->AdcItems = 0; devpriv->AdcItems < 16; devpriv->AdcItems++) {
973 /* Convert application's poll list item to private board class
974 * format. Each app poll list item is an uint8_t with form
975 * (EOPL,x,x,RANGE,CHAN<3:0>), where RANGE code indicates 0 =
976 * +-10V, 1 = +-5V, and EOPL = End of Poll List marker.
979 (*ppl << 8) | (*ppl & 0x10 ? GSEL_BIPOLAR5V :
982 /* Switch ADC analog gain. */
983 *pRPS++ = RPS_LDREG | (P_DEBICMD >> 2); /* Write DEBI command */
986 *pRPS++ = DEBI_CMD_WRWORD | LP_GSEL;
987 *pRPS++ = RPS_LDREG | (P_DEBIAD >> 2); /* Write DEBI */
988 /* immediate data to */
991 *pRPS++ = RPS_CLRSIGNAL | RPS_DEBI; /* Reset "shadow RAM uploaded" */
993 *pRPS++ = RPS_UPLOAD | RPS_DEBI; /* Invoke shadow RAM upload. */
994 *pRPS++ = RPS_PAUSE | RPS_DEBI; /* Wait for shadow upload to */
997 /* Select ADC analog input channel. */
998 *pRPS++ = RPS_LDREG | (P_DEBICMD >> 2);
999 /* Write DEBI command and address to shadow RAM. */
1000 *pRPS++ = DEBI_CMD_WRWORD | LP_ISEL;
1001 *pRPS++ = RPS_LDREG | (P_DEBIAD >> 2);
1002 /* Write DEBI immediate data to shadow RAM. */
1004 *pRPS++ = RPS_CLRSIGNAL | RPS_DEBI;
1005 /* Reset "shadow RAM uploaded" flag. */
1007 *pRPS++ = RPS_UPLOAD | RPS_DEBI;
1008 /* Invoke shadow RAM upload. */
1010 *pRPS++ = RPS_PAUSE | RPS_DEBI;
1011 /* Wait for shadow upload to finish. */
1013 /* Delay at least 10 microseconds for analog input settling.
1014 * Instead of padding with NOPs, we use RPS_JUMP instructions
1015 * here; this allows us to produce a longer delay than is
1016 * possible with NOPs because each RPS_JUMP flushes the RPS'
1017 * instruction prefetch pipeline.
1020 (uint32_t) devpriv->RPSBuf.PhysicalBase +
1021 (uint32_t) ((unsigned long)pRPS -
1022 (unsigned long)devpriv->RPSBuf.LogicalBase);
1023 for (i = 0; i < (10 * RPSCLK_PER_US / 2); i++) {
1024 JmpAdrs += 8; /* Repeat to implement time delay: */
1025 *pRPS++ = RPS_JUMP; /* Jump to next RPS instruction. */
1029 if (cmd != NULL && cmd->convert_src != TRIG_NOW) {
1030 /* Wait for Start trigger. */
1031 *pRPS++ = RPS_PAUSE | RPS_SIGADC;
1032 *pRPS++ = RPS_CLRSIGNAL | RPS_SIGADC;
1034 /* Start ADC by pulsing GPIO1. */
1035 *pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* Begin ADC Start pulse. */
1036 *pRPS++ = GPIO_BASE | GPIO1_LO;
1038 /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */
1039 *pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* End ADC Start pulse. */
1040 *pRPS++ = GPIO_BASE | GPIO1_HI;
1042 /* Wait for ADC to complete (GPIO2 is asserted high when ADC not
1043 * busy) and for data from previous conversion to shift into FB
1044 * BUFFER 1 register.
1046 *pRPS++ = RPS_PAUSE | RPS_GPIO2; /* Wait for ADC done. */
1048 /* Transfer ADC data from FB BUFFER 1 register to DMA buffer. */
1049 *pRPS++ = RPS_STREG | (BUGFIX_STREG(P_FB_BUFFER1) >> 2);
1051 (uint32_t) devpriv->ANABuf.PhysicalBase +
1052 (devpriv->AdcItems << 2);
1054 /* If this slot's EndOfPollList flag is set, all channels have */
1055 /* now been processed. */
1056 if (*ppl++ & EOPL) {
1057 devpriv->AdcItems++; /* Adjust poll list item count. */
1058 break; /* Exit poll list processing loop. */
1062 /* VERSION 2.01 CHANGE: DELAY CHANGED FROM 250NS to 2US. Allow the
1063 * ADC to stabilize for 2 microseconds before starting the final
1064 * (dummy) conversion. This delay is necessary to allow sufficient
1065 * time between last conversion finished and the start of the dummy
1066 * conversion. Without this delay, the last conversion's data value
1067 * is sometimes set to the previous conversion's data value.
1069 for (n = 0; n < (2 * RPSCLK_PER_US); n++)
1072 /* Start a dummy conversion to cause the data from the last
1073 * conversion of interest to be shifted in.
1075 *pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* Begin ADC Start pulse. */
1076 *pRPS++ = GPIO_BASE | GPIO1_LO;
1078 /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */
1079 *pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* End ADC Start pulse. */
1080 *pRPS++ = GPIO_BASE | GPIO1_HI;
1082 /* Wait for the data from the last conversion of interest to arrive
1083 * in FB BUFFER 1 register.
1085 *pRPS++ = RPS_PAUSE | RPS_GPIO2; /* Wait for ADC done. */
1087 /* Transfer final ADC data from FB BUFFER 1 register to DMA buffer. */
1088 *pRPS++ = RPS_STREG | (BUGFIX_STREG(P_FB_BUFFER1) >> 2); /* */
1090 (uint32_t) devpriv->ANABuf.PhysicalBase + (devpriv->AdcItems << 2);
1092 /* Indicate ADC scan loop is finished. */
1093 /* *pRPS++= RPS_CLRSIGNAL | RPS_SIGADC ; // Signal ReadADC() that scan is done. */
1095 /* invoke interrupt */
1096 if (devpriv->ai_cmd_running == 1) {
1099 /* Restart RPS program at its beginning. */
1100 *pRPS++ = RPS_JUMP; /* Branch to start of RPS program. */
1101 *pRPS++ = (uint32_t) devpriv->RPSBuf.PhysicalBase;
1103 /* End of RPS program build */
1106 /* TO COMPLETE, IF NECESSARY */
1107 static int s626_ai_insn_config(struct comedi_device *dev,
1108 struct comedi_subdevice *s,
1109 struct comedi_insn *insn, unsigned int *data)
1116 static int s626_ai_rinsn(struct comedi_device *dev,
1117 struct comedi_subdevice *s,
1118 struct comedi_insn *insn,
1121 struct s626_private *devpriv = dev->private;
1123 register int32_t *readaddr;
1125 /* Trigger ADC scan loop start */
1126 s626_mc_enable(dev, MC2_ADC_RPS, P_MC2);
1128 /* Wait until ADC scan loop is finished (RPS Signal 0 reset) */
1129 while (MC_TEST(P_MC2, MC2_ADC_RPS))
1133 * Init ptr to DMA buffer that holds new ADC data. We skip the
1134 * first uint16_t in the buffer because it contains junk data from
1135 * the final ADC of the previous poll list scan.
1137 readaddr = (uint32_t *)devpriv->ANABuf.LogicalBase + 1;
1140 * Convert ADC data to 16-bit integer values and
1141 * copy to application buffer.
1143 for (i = 0; i < devpriv->AdcItems; i++) {
1144 *data = s626_ai_reg_to_uint(*readaddr++);
1152 static int s626_ai_insn_read(struct comedi_device *dev,
1153 struct comedi_subdevice *s,
1154 struct comedi_insn *insn, unsigned int *data)
1156 struct s626_private *devpriv = dev->private;
1157 uint16_t chan = CR_CHAN(insn->chanspec);
1158 uint16_t range = CR_RANGE(insn->chanspec);
1159 uint16_t AdcSpec = 0;
1163 /* interrupt call test */
1164 /* writel(IRQ_GPIO3,devpriv->base_addr+P_PSR); */
1165 /* Writing a logical 1 into any of the RPS_PSR bits causes the
1166 * corresponding interrupt to be generated if enabled
1169 /* Convert application's ADC specification into form
1170 * appropriate for register programming.
1173 AdcSpec = (chan << 8) | (GSEL_BIPOLAR5V);
1175 AdcSpec = (chan << 8) | (GSEL_BIPOLAR10V);
1177 /* Switch ADC analog gain. */
1178 DEBIwrite(dev, LP_GSEL, AdcSpec); /* Set gain. */
1180 /* Select ADC analog input channel. */
1181 DEBIwrite(dev, LP_ISEL, AdcSpec); /* Select channel. */
1183 for (n = 0; n < insn->n; n++) {
1185 /* Delay 10 microseconds for analog input settling. */
1188 /* Start ADC by pulsing GPIO1 low. */
1189 GpioImage = RR7146(P_GPIO);
1190 /* Assert ADC Start command */
1191 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
1192 /* and stretch it out. */
1193 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
1194 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
1195 /* Negate ADC Start command. */
1196 WR7146(P_GPIO, GpioImage | GPIO1_HI);
1198 /* Wait for ADC to complete (GPIO2 is asserted high when */
1199 /* ADC not busy) and for data from previous conversion to */
1200 /* shift into FB BUFFER 1 register. */
1202 /* Wait for ADC done. */
1203 while (!(RR7146(P_PSR) & PSR_GPIO2))
1206 /* Fetch ADC data. */
1208 data[n - 1] = s626_ai_reg_to_uint(RR7146(P_FB_BUFFER1));
1210 /* Allow the ADC to stabilize for 4 microseconds before
1211 * starting the next (final) conversion. This delay is
1212 * necessary to allow sufficient time between last
1213 * conversion finished and the start of the next
1214 * conversion. Without this delay, the last conversion's
1215 * data value is sometimes set to the previous
1216 * conversion's data value.
1221 /* Start a dummy conversion to cause the data from the
1222 * previous conversion to be shifted in. */
1223 GpioImage = RR7146(P_GPIO);
1225 /* Assert ADC Start command */
1226 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
1227 /* and stretch it out. */
1228 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
1229 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
1230 /* Negate ADC Start command. */
1231 WR7146(P_GPIO, GpioImage | GPIO1_HI);
1233 /* Wait for the data to arrive in FB BUFFER 1 register. */
1235 /* Wait for ADC done. */
1236 while (!(RR7146(P_PSR) & PSR_GPIO2))
1239 /* Fetch ADC data from audio interface's input shift register. */
1241 /* Fetch ADC data. */
1243 data[n - 1] = s626_ai_reg_to_uint(RR7146(P_FB_BUFFER1));
1248 static int s626_ai_load_polllist(uint8_t *ppl, struct comedi_cmd *cmd)
1253 for (n = 0; n < cmd->chanlist_len; n++) {
1254 if (CR_RANGE((cmd->chanlist)[n]) == 0)
1255 ppl[n] = (CR_CHAN((cmd->chanlist)[n])) | (RANGE_5V);
1257 ppl[n] = (CR_CHAN((cmd->chanlist)[n])) | (RANGE_10V);
1265 static int s626_ai_inttrig(struct comedi_device *dev,
1266 struct comedi_subdevice *s, unsigned int trignum)
1271 /* Start executing the RPS program */
1272 s626_mc_enable(dev, MC1_ERPS1, P_MC1);
1274 s->async->inttrig = NULL;
1279 /* This function doesn't require a particular form, this is just what
1280 * happens to be used in some of the drivers. It should convert ns
1281 * nanoseconds to a counter value suitable for programming the device.
1282 * Also, it should adjust ns so that it cooresponds to the actual time
1283 * that the device will use. */
1284 static int s626_ns_to_timer(int *nanosec, int round_mode)
1288 base = 500; /* 2MHz internal clock */
1290 switch (round_mode) {
1291 case TRIG_ROUND_NEAREST:
1293 divider = (*nanosec + base / 2) / base;
1295 case TRIG_ROUND_DOWN:
1296 divider = (*nanosec) / base;
1299 divider = (*nanosec + base - 1) / base;
1303 *nanosec = base * divider;
1307 static void s626_timer_load(struct comedi_device *dev, struct enc_private *k,
1310 uint16_t Setup = (LOADSRC_INDX << BF_LOADSRC) | /* Preload upon */
1312 (INDXSRC_SOFT << BF_INDXSRC) | /* Disable hardware index. */
1313 (CLKSRC_TIMER << BF_CLKSRC) | /* Operating mode is Timer. */
1314 (CLKPOL_POS << BF_CLKPOL) | /* Active high clock. */
1315 (CNTDIR_DOWN << BF_CLKPOL) | /* Count direction is Down. */
1316 (CLKMULT_1X << BF_CLKMULT) | /* Clock multiplier is 1x. */
1317 (CLKENAB_INDEX << BF_CLKENAB);
1318 uint16_t valueSrclatch = LATCHSRC_A_INDXA;
1319 /* uint16_t enab=CLKENAB_ALWAYS; */
1321 k->SetMode(dev, k, Setup, FALSE);
1323 /* Set the preload register */
1324 Preload(dev, k, tick);
1326 /* Software index pulse forces the preload register to load */
1327 /* into the counter */
1328 k->SetLoadTrig(dev, k, 0);
1329 k->PulseIndex(dev, k);
1331 /* set reload on counter overflow */
1332 k->SetLoadTrig(dev, k, 1);
1334 /* set interrupt on overflow */
1335 k->SetIntSrc(dev, k, INTSRC_OVER);
1337 SetLatchSource(dev, k, valueSrclatch);
1338 /* k->SetEnable(dev,k,(uint16_t)(enab != 0)); */
1342 static int s626_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
1344 struct s626_private *devpriv = dev->private;
1346 struct comedi_cmd *cmd = &s->async->cmd;
1347 struct enc_private *k;
1350 if (devpriv->ai_cmd_running) {
1351 printk(KERN_ERR "s626_ai_cmd: Another ai_cmd is running %d\n",
1355 /* disable interrupt */
1356 writel(0, devpriv->base_addr + P_IER);
1358 /* clear interrupt request */
1359 writel(IRQ_RPS1 | IRQ_GPIO3, devpriv->base_addr + P_ISR);
1361 /* clear any pending interrupt */
1362 s626_dio_clear_irq(dev);
1363 /* s626_enc_clear_irq(dev); */
1365 /* reset ai_cmd_running flag */
1366 devpriv->ai_cmd_running = 0;
1368 /* test if cmd is valid */
1372 if (dev->irq == 0) {
1374 "s626_ai_cmd: cannot run command without an irq");
1378 s626_ai_load_polllist(ppl, cmd);
1379 devpriv->ai_cmd_running = 1;
1380 devpriv->ai_convert_count = 0;
1382 switch (cmd->scan_begin_src) {
1386 /* set a conter to generate adc trigger at scan_begin_arg interval */
1388 tick = s626_ns_to_timer((int *)&cmd->scan_begin_arg,
1389 cmd->flags & TRIG_ROUND_MASK);
1391 /* load timer value and enable interrupt */
1392 s626_timer_load(dev, k, tick);
1393 k->SetEnable(dev, k, CLKENAB_ALWAYS);
1396 /* set the digital line and interrupt for scan trigger */
1397 if (cmd->start_src != TRIG_EXT)
1398 s626_dio_set_irq(dev, cmd->scan_begin_arg);
1402 switch (cmd->convert_src) {
1406 /* set a conter to generate adc trigger at convert_arg interval */
1408 tick = s626_ns_to_timer((int *)&cmd->convert_arg,
1409 cmd->flags & TRIG_ROUND_MASK);
1411 /* load timer value and enable interrupt */
1412 s626_timer_load(dev, k, tick);
1413 k->SetEnable(dev, k, CLKENAB_INDEX);
1416 /* set the digital line and interrupt for convert trigger */
1417 if (cmd->scan_begin_src != TRIG_EXT
1418 && cmd->start_src == TRIG_EXT)
1419 s626_dio_set_irq(dev, cmd->convert_arg);
1423 switch (cmd->stop_src) {
1425 /* data arrives as one packet */
1426 devpriv->ai_sample_count = cmd->stop_arg;
1427 devpriv->ai_continous = 0;
1430 /* continous acquisition */
1431 devpriv->ai_continous = 1;
1432 devpriv->ai_sample_count = 0;
1438 switch (cmd->start_src) {
1440 /* Trigger ADC scan loop start */
1441 /* s626_mc_enable(dev, MC2_ADC_RPS, P_MC2); */
1443 /* Start executing the RPS program */
1444 s626_mc_enable(dev, MC1_ERPS1, P_MC1);
1446 s->async->inttrig = NULL;
1449 /* configure DIO channel for acquisition trigger */
1450 s626_dio_set_irq(dev, cmd->start_arg);
1452 s->async->inttrig = NULL;
1455 s->async->inttrig = s626_ai_inttrig;
1459 /* enable interrupt */
1460 writel(IRQ_GPIO3 | IRQ_RPS1, devpriv->base_addr + P_IER);
1465 static int s626_ai_cmdtest(struct comedi_device *dev,
1466 struct comedi_subdevice *s, struct comedi_cmd *cmd)
1471 /* Step 1 : check if triggers are trivially valid */
1473 err |= cfc_check_trigger_src(&cmd->start_src,
1474 TRIG_NOW | TRIG_INT | TRIG_EXT);
1475 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
1476 TRIG_TIMER | TRIG_EXT | TRIG_FOLLOW);
1477 err |= cfc_check_trigger_src(&cmd->convert_src,
1478 TRIG_TIMER | TRIG_EXT | TRIG_NOW);
1479 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
1480 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
1485 /* Step 2a : make sure trigger sources are unique */
1487 err |= cfc_check_trigger_is_unique(cmd->start_src);
1488 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
1489 err |= cfc_check_trigger_is_unique(cmd->convert_src);
1490 err |= cfc_check_trigger_is_unique(cmd->stop_src);
1492 /* Step 2b : and mutually compatible */
1497 /* step 3: make sure arguments are trivially compatible */
1499 if (cmd->start_src != TRIG_EXT)
1500 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
1501 if (cmd->start_src == TRIG_EXT)
1502 err |= cfc_check_trigger_arg_max(&cmd->start_arg, 39);
1504 if (cmd->scan_begin_src == TRIG_EXT)
1505 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 39);
1507 if (cmd->convert_src == TRIG_EXT)
1508 err |= cfc_check_trigger_arg_max(&cmd->convert_arg, 39);
1510 #define MAX_SPEED 200000 /* in nanoseconds */
1511 #define MIN_SPEED 2000000000 /* in nanoseconds */
1513 if (cmd->scan_begin_src == TRIG_TIMER) {
1514 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
1516 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
1519 /* external trigger */
1520 /* should be level/edge, hi/lo specification here */
1521 /* should specify multiple external triggers */
1522 /* err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 9); */
1524 if (cmd->convert_src == TRIG_TIMER) {
1525 err |= cfc_check_trigger_arg_min(&cmd->convert_arg, MAX_SPEED);
1526 err |= cfc_check_trigger_arg_max(&cmd->convert_arg, MIN_SPEED);
1528 /* external trigger */
1530 /* err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 9); */
1533 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
1535 if (cmd->stop_src == TRIG_COUNT)
1536 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
1537 else /* TRIG_NONE */
1538 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
1543 /* step 4: fix up any arguments */
1545 if (cmd->scan_begin_src == TRIG_TIMER) {
1546 tmp = cmd->scan_begin_arg;
1547 s626_ns_to_timer((int *)&cmd->scan_begin_arg,
1548 cmd->flags & TRIG_ROUND_MASK);
1549 if (tmp != cmd->scan_begin_arg)
1552 if (cmd->convert_src == TRIG_TIMER) {
1553 tmp = cmd->convert_arg;
1554 s626_ns_to_timer((int *)&cmd->convert_arg,
1555 cmd->flags & TRIG_ROUND_MASK);
1556 if (tmp != cmd->convert_arg)
1558 if (cmd->scan_begin_src == TRIG_TIMER &&
1559 cmd->scan_begin_arg <
1560 cmd->convert_arg * cmd->scan_end_arg) {
1561 cmd->scan_begin_arg =
1562 cmd->convert_arg * cmd->scan_end_arg;
1573 static int s626_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
1575 struct s626_private *devpriv = dev->private;
1577 /* Stop RPS program in case it is currently running. */
1578 MC_DISABLE(P_MC1, MC1_ERPS1);
1580 /* disable master interrupt */
1581 writel(0, devpriv->base_addr + P_IER);
1583 devpriv->ai_cmd_running = 0;
1588 static int s626_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
1589 struct comedi_insn *insn, unsigned int *data)
1591 struct s626_private *devpriv = dev->private;
1593 uint16_t chan = CR_CHAN(insn->chanspec);
1596 for (i = 0; i < insn->n; i++) {
1597 dacdata = (int16_t) data[i];
1598 devpriv->ao_readback[CR_CHAN(insn->chanspec)] = data[i];
1599 dacdata -= (0x1fff);
1601 SetDAC(dev, chan, dacdata);
1607 static int s626_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1608 struct comedi_insn *insn, unsigned int *data)
1610 struct s626_private *devpriv = dev->private;
1613 for (i = 0; i < insn->n; i++)
1614 data[i] = devpriv->ao_readback[CR_CHAN(insn->chanspec)];
1619 /* *************** DIGITAL I/O FUNCTIONS ***************
1620 * All DIO functions address a group of DIO channels by means of
1621 * "group" argument. group may be 0, 1 or 2, which correspond to DIO
1622 * ports A, B and C, respectively.
1625 static void s626_dio_init(struct comedi_device *dev)
1629 /* Prepare to treat writes to WRCapSel as capture disables. */
1630 DEBIwrite(dev, LP_MISC1, MISC1_NOEDCAP);
1632 /* For each group of sixteen channels ... */
1633 for (group = 0; group < S626_DIO_BANKS; group++) {
1634 /* Disable all interrupts */
1635 DEBIwrite(dev, LP_WRINTSEL(group), 0);
1636 /* Disable all event captures */
1637 DEBIwrite(dev, LP_WRCAPSEL(group), 0xffff);
1638 /* Init all DIOs to default edge polarity */
1639 DEBIwrite(dev, LP_WREDGSEL(group), 0);
1640 /* Program all outputs to inactive state */
1641 DEBIwrite(dev, LP_WRDOUT(group), 0);
1645 /* DIO devices are slightly special. Although it is possible to
1646 * implement the insn_read/insn_write interface, it is much more
1647 * useful to applications if you implement the insn_bits interface.
1648 * This allows packed reading/writing of the DIO channels. The comedi
1649 * core can convert between insn_bits and insn_read/write */
1651 static int s626_dio_insn_bits(struct comedi_device *dev,
1652 struct comedi_subdevice *s,
1653 struct comedi_insn *insn, unsigned int *data)
1655 unsigned long group = (unsigned long)s->private;
1658 * The insn data consists of a mask in data[0] and the new data in
1659 * data[1]. The mask defines which bits we are concerning about.
1660 * The new data must be anded with the mask. Each channel
1661 * corresponds to a bit.
1664 /* Check if requested ports are configured for output */
1665 if ((s->io_bits & data[0]) != data[0])
1668 s->state &= ~data[0];
1669 s->state |= data[0] & data[1];
1671 /* Write out the new digital output lines */
1673 DEBIwrite(dev, LP_WRDOUT(group), s->state);
1675 data[1] = DEBIread(dev, LP_RDDIN(group));
1680 static int s626_dio_insn_config(struct comedi_device *dev,
1681 struct comedi_subdevice *s,
1682 struct comedi_insn *insn, unsigned int *data)
1684 unsigned long group = (unsigned long)s->private;
1687 case INSN_CONFIG_DIO_QUERY:
1690 io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
1695 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
1698 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
1704 DEBIwrite(dev, LP_WRDOUT(group), s->io_bits);
1709 /* Now this function initializes the value of the counter (data[0])
1710 and set the subdevice. To complete with trigger and interrupt
1712 /* FIXME: data[0] is supposed to be an INSN_CONFIG_xxx constant indicating
1713 * what is being configured, but this function appears to be using data[0]
1715 static int s626_enc_insn_config(struct comedi_device *dev,
1716 struct comedi_subdevice *s,
1717 struct comedi_insn *insn, unsigned int *data)
1719 uint16_t Setup = (LOADSRC_INDX << BF_LOADSRC) | /* Preload upon */
1721 (INDXSRC_SOFT << BF_INDXSRC) | /* Disable hardware index. */
1722 (CLKSRC_COUNTER << BF_CLKSRC) | /* Operating mode is Counter. */
1723 (CLKPOL_POS << BF_CLKPOL) | /* Active high clock. */
1724 /* ( CNTDIR_UP << BF_CLKPOL ) | // Count direction is Down. */
1725 (CLKMULT_1X << BF_CLKMULT) | /* Clock multiplier is 1x. */
1726 (CLKENAB_INDEX << BF_CLKENAB);
1727 /* uint16_t DisableIntSrc=TRUE; */
1728 /* uint32_t Preloadvalue; //Counter initial value */
1729 uint16_t valueSrclatch = LATCHSRC_AB_READ;
1730 uint16_t enab = CLKENAB_ALWAYS;
1731 struct enc_private *k = &encpriv[CR_CHAN(insn->chanspec)];
1733 /* (data==NULL) ? (Preloadvalue=0) : (Preloadvalue=data[0]); */
1735 k->SetMode(dev, k, Setup, TRUE);
1736 Preload(dev, k, data[0]);
1737 k->PulseIndex(dev, k);
1738 SetLatchSource(dev, k, valueSrclatch);
1739 k->SetEnable(dev, k, (uint16_t) (enab != 0));
1744 static int s626_enc_insn_read(struct comedi_device *dev,
1745 struct comedi_subdevice *s,
1746 struct comedi_insn *insn, unsigned int *data)
1750 struct enc_private *k = &encpriv[CR_CHAN(insn->chanspec)];
1752 for (n = 0; n < insn->n; n++)
1753 data[n] = ReadLatch(dev, k);
1758 static int s626_enc_insn_write(struct comedi_device *dev,
1759 struct comedi_subdevice *s,
1760 struct comedi_insn *insn, unsigned int *data)
1763 struct enc_private *k = &encpriv[CR_CHAN(insn->chanspec)];
1765 /* Set the preload register */
1766 Preload(dev, k, data[0]);
1768 /* Software index pulse forces the preload register to load */
1769 /* into the counter */
1770 k->SetLoadTrig(dev, k, 0);
1771 k->PulseIndex(dev, k);
1772 k->SetLoadTrig(dev, k, 2);
1777 static void WriteMISC2(struct comedi_device *dev, uint16_t NewImage)
1779 DEBIwrite(dev, LP_MISC1, MISC1_WENABLE); /* enab writes to */
1780 /* MISC2 register. */
1781 DEBIwrite(dev, LP_WRMISC2, NewImage); /* Write new image to MISC2. */
1782 DEBIwrite(dev, LP_MISC1, MISC1_WDISABLE); /* Disable writes to MISC2. */
1785 static void CloseDMAB(struct comedi_device *dev, struct bufferDMA *pdma,
1788 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1794 /* find the matching allocation from the board struct */
1796 vbptr = pdma->LogicalBase;
1797 vpptr = pdma->PhysicalBase;
1799 pci_free_consistent(pcidev, bsize, vbptr, vpptr);
1800 pdma->LogicalBase = NULL;
1801 pdma->PhysicalBase = 0;
1805 /* ****** PRIVATE COUNTER FUNCTIONS ****** */
1807 /* Reset a counter's index and overflow event capture flags. */
1809 static void ResetCapFlags_A(struct comedi_device *dev, struct enc_private *k)
1811 DEBIreplace(dev, k->MyCRB, (uint16_t) (~CRBMSK_INTCTRL),
1812 CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A);
1815 static void ResetCapFlags_B(struct comedi_device *dev, struct enc_private *k)
1817 DEBIreplace(dev, k->MyCRB, (uint16_t) (~CRBMSK_INTCTRL),
1818 CRBMSK_INTRESETCMD | CRBMSK_INTRESET_B);
1821 /* Return counter setup in a format (COUNTER_SETUP) that is consistent */
1822 /* for both A and B counters. */
1824 static uint16_t GetMode_A(struct comedi_device *dev, struct enc_private *k)
1826 register uint16_t cra;
1827 register uint16_t crb;
1828 register uint16_t setup;
1830 /* Fetch CRA and CRB register images. */
1831 cra = DEBIread(dev, k->MyCRA);
1832 crb = DEBIread(dev, k->MyCRB);
1834 /* Populate the standardized counter setup bit fields. Note: */
1835 /* IndexSrc is restricted to ENC_X or IndxPol. */
1836 setup = ((cra & STDMSK_LOADSRC) /* LoadSrc = LoadSrcA. */
1837 |((crb << (STDBIT_LATCHSRC - CRBBIT_LATCHSRC)) & STDMSK_LATCHSRC) /* LatchSrc = LatchSrcA. */
1838 |((cra << (STDBIT_INTSRC - CRABIT_INTSRC_A)) & STDMSK_INTSRC) /* IntSrc = IntSrcA. */
1839 |((cra << (STDBIT_INDXSRC - (CRABIT_INDXSRC_A + 1))) & STDMSK_INDXSRC) /* IndxSrc = IndxSrcA<1>. */
1840 |((cra >> (CRABIT_INDXPOL_A - STDBIT_INDXPOL)) & STDMSK_INDXPOL) /* IndxPol = IndxPolA. */
1841 |((crb >> (CRBBIT_CLKENAB_A - STDBIT_CLKENAB)) & STDMSK_CLKENAB)); /* ClkEnab = ClkEnabA. */
1843 /* Adjust mode-dependent parameters. */
1844 if (cra & (2 << CRABIT_CLKSRC_A)) /* If Timer mode (ClkSrcA<1> == 1): */
1845 setup |= ((CLKSRC_TIMER << STDBIT_CLKSRC) /* Indicate Timer mode. */
1846 |((cra << (STDBIT_CLKPOL - CRABIT_CLKSRC_A)) & STDMSK_CLKPOL) /* Set ClkPol to indicate count direction (ClkSrcA<0>). */
1847 |(MULT_X1 << STDBIT_CLKMULT)); /* ClkMult must be 1x in Timer mode. */
1849 else /* If Counter mode (ClkSrcA<1> == 0): */
1850 setup |= ((CLKSRC_COUNTER << STDBIT_CLKSRC) /* Indicate Counter mode. */
1851 |((cra >> (CRABIT_CLKPOL_A - STDBIT_CLKPOL)) & STDMSK_CLKPOL) /* Pass through ClkPol. */
1852 |(((cra & CRAMSK_CLKMULT_A) == (MULT_X0 << CRABIT_CLKMULT_A)) ? /* Force ClkMult to 1x if not legal, else pass through. */
1853 (MULT_X1 << STDBIT_CLKMULT) :
1854 ((cra >> (CRABIT_CLKMULT_A -
1855 STDBIT_CLKMULT)) & STDMSK_CLKMULT)));
1857 /* Return adjusted counter setup. */
1861 static uint16_t GetMode_B(struct comedi_device *dev, struct enc_private *k)
1863 register uint16_t cra;
1864 register uint16_t crb;
1865 register uint16_t setup;
1867 /* Fetch CRA and CRB register images. */
1868 cra = DEBIread(dev, k->MyCRA);
1869 crb = DEBIread(dev, k->MyCRB);
1871 /* Populate the standardized counter setup bit fields. Note: */
1872 /* IndexSrc is restricted to ENC_X or IndxPol. */
1873 setup = (((crb << (STDBIT_INTSRC - CRBBIT_INTSRC_B)) & STDMSK_INTSRC) /* IntSrc = IntSrcB. */
1874 |((crb << (STDBIT_LATCHSRC - CRBBIT_LATCHSRC)) & STDMSK_LATCHSRC) /* LatchSrc = LatchSrcB. */
1875 |((crb << (STDBIT_LOADSRC - CRBBIT_LOADSRC_B)) & STDMSK_LOADSRC) /* LoadSrc = LoadSrcB. */
1876 |((crb << (STDBIT_INDXPOL - CRBBIT_INDXPOL_B)) & STDMSK_INDXPOL) /* IndxPol = IndxPolB. */
1877 |((crb >> (CRBBIT_CLKENAB_B - STDBIT_CLKENAB)) & STDMSK_CLKENAB) /* ClkEnab = ClkEnabB. */
1878 |((cra >> ((CRABIT_INDXSRC_B + 1) - STDBIT_INDXSRC)) & STDMSK_INDXSRC)); /* IndxSrc = IndxSrcB<1>. */
1880 /* Adjust mode-dependent parameters. */
1881 if ((crb & CRBMSK_CLKMULT_B) == (MULT_X0 << CRBBIT_CLKMULT_B)) /* If Extender mode (ClkMultB == MULT_X0): */
1882 setup |= ((CLKSRC_EXTENDER << STDBIT_CLKSRC) /* Indicate Extender mode. */
1883 |(MULT_X1 << STDBIT_CLKMULT) /* Indicate multiplier is 1x. */
1884 |((cra >> (CRABIT_CLKSRC_B - STDBIT_CLKPOL)) & STDMSK_CLKPOL)); /* Set ClkPol equal to Timer count direction (ClkSrcB<0>). */
1886 else if (cra & (2 << CRABIT_CLKSRC_B)) /* If Timer mode (ClkSrcB<1> == 1): */
1887 setup |= ((CLKSRC_TIMER << STDBIT_CLKSRC) /* Indicate Timer mode. */
1888 |(MULT_X1 << STDBIT_CLKMULT) /* Indicate multiplier is 1x. */
1889 |((cra >> (CRABIT_CLKSRC_B - STDBIT_CLKPOL)) & STDMSK_CLKPOL)); /* Set ClkPol equal to Timer count direction (ClkSrcB<0>). */
1891 else /* If Counter mode (ClkSrcB<1> == 0): */
1892 setup |= ((CLKSRC_COUNTER << STDBIT_CLKSRC) /* Indicate Timer mode. */
1893 |((crb >> (CRBBIT_CLKMULT_B - STDBIT_CLKMULT)) & STDMSK_CLKMULT) /* Clock multiplier is passed through. */
1894 |((crb << (STDBIT_CLKPOL - CRBBIT_CLKPOL_B)) & STDMSK_CLKPOL)); /* Clock polarity is passed through. */
1896 /* Return adjusted counter setup. */
1901 * Set the operating mode for the specified counter. The setup
1902 * parameter is treated as a COUNTER_SETUP data type. The following
1903 * parameters are programmable (all other parms are ignored): ClkMult,
1904 * ClkPol, ClkEnab, IndexSrc, IndexPol, LoadSrc.
1907 static void SetMode_A(struct comedi_device *dev, struct enc_private *k,
1908 uint16_t Setup, uint16_t DisableIntSrc)
1910 struct s626_private *devpriv = dev->private;
1911 register uint16_t cra;
1912 register uint16_t crb;
1913 register uint16_t setup = Setup; /* Cache the Standard Setup. */
1915 /* Initialize CRA and CRB images. */
1916 cra = ((setup & CRAMSK_LOADSRC_A) /* Preload trigger is passed through. */
1917 |((setup & STDMSK_INDXSRC) >> (STDBIT_INDXSRC - (CRABIT_INDXSRC_A + 1)))); /* IndexSrc is restricted to ENC_X or IndxPol. */
1919 crb = (CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A /* Reset any pending CounterA event captures. */
1920 | ((setup & STDMSK_CLKENAB) << (CRBBIT_CLKENAB_A - STDBIT_CLKENAB))); /* Clock enable is passed through. */
1922 /* Force IntSrc to Disabled if DisableIntSrc is asserted. */
1924 cra |= ((setup & STDMSK_INTSRC) >> (STDBIT_INTSRC -
1927 /* Populate all mode-dependent attributes of CRA & CRB images. */
1928 switch ((setup & STDMSK_CLKSRC) >> STDBIT_CLKSRC) {
1929 case CLKSRC_EXTENDER: /* Extender Mode: Force to Timer mode */
1930 /* (Extender valid only for B counters). */
1932 case CLKSRC_TIMER: /* Timer Mode: */
1933 cra |= ((2 << CRABIT_CLKSRC_A) /* ClkSrcA<1> selects system clock */
1934 |((setup & STDMSK_CLKPOL) >> (STDBIT_CLKPOL - CRABIT_CLKSRC_A)) /* with count direction (ClkSrcA<0>) obtained from ClkPol. */
1935 |(1 << CRABIT_CLKPOL_A) /* ClkPolA behaves as always-on clock enable. */
1936 |(MULT_X1 << CRABIT_CLKMULT_A)); /* ClkMult must be 1x. */
1939 default: /* Counter Mode: */
1940 cra |= (CLKSRC_COUNTER /* Select ENC_C and ENC_D as clock/direction inputs. */
1941 | ((setup & STDMSK_CLKPOL) << (CRABIT_CLKPOL_A - STDBIT_CLKPOL)) /* Clock polarity is passed through. */
1942 |(((setup & STDMSK_CLKMULT) == (MULT_X0 << STDBIT_CLKMULT)) ? /* Force multiplier to x1 if not legal, otherwise pass through. */
1943 (MULT_X1 << CRABIT_CLKMULT_A) :
1944 ((setup & STDMSK_CLKMULT) << (CRABIT_CLKMULT_A -
1948 /* Force positive index polarity if IndxSrc is software-driven only, */
1949 /* otherwise pass it through. */
1950 if (~setup & STDMSK_INDXSRC)
1951 cra |= ((setup & STDMSK_INDXPOL) << (CRABIT_INDXPOL_A -
1954 /* If IntSrc has been forced to Disabled, update the MISC2 interrupt */
1955 /* enable mask to indicate the counter interrupt is disabled. */
1957 devpriv->CounterIntEnabs &= ~k->MyEventBits[3];
1959 /* While retaining CounterB and LatchSrc configurations, program the */
1960 /* new counter operating mode. */
1961 DEBIreplace(dev, k->MyCRA, CRAMSK_INDXSRC_B | CRAMSK_CLKSRC_B, cra);
1962 DEBIreplace(dev, k->MyCRB,
1963 (uint16_t) (~(CRBMSK_INTCTRL | CRBMSK_CLKENAB_A)), crb);
1966 static void SetMode_B(struct comedi_device *dev, struct enc_private *k,
1967 uint16_t Setup, uint16_t DisableIntSrc)
1969 struct s626_private *devpriv = dev->private;
1970 register uint16_t cra;
1971 register uint16_t crb;
1972 register uint16_t setup = Setup; /* Cache the Standard Setup. */
1974 /* Initialize CRA and CRB images. */
1975 cra = ((setup & STDMSK_INDXSRC) << ((CRABIT_INDXSRC_B + 1) - STDBIT_INDXSRC)); /* IndexSrc field is restricted to ENC_X or IndxPol. */
1977 crb = (CRBMSK_INTRESETCMD | CRBMSK_INTRESET_B /* Reset event captures and disable interrupts. */
1978 | ((setup & STDMSK_CLKENAB) << (CRBBIT_CLKENAB_B - STDBIT_CLKENAB)) /* Clock enable is passed through. */
1979 |((setup & STDMSK_LOADSRC) >> (STDBIT_LOADSRC - CRBBIT_LOADSRC_B))); /* Preload trigger source is passed through. */
1981 /* Force IntSrc to Disabled if DisableIntSrc is asserted. */
1983 crb |= ((setup & STDMSK_INTSRC) >> (STDBIT_INTSRC -
1986 /* Populate all mode-dependent attributes of CRA & CRB images. */
1987 switch ((setup & STDMSK_CLKSRC) >> STDBIT_CLKSRC) {
1988 case CLKSRC_TIMER: /* Timer Mode: */
1989 cra |= ((2 << CRABIT_CLKSRC_B) /* ClkSrcB<1> selects system clock */
1990 |((setup & STDMSK_CLKPOL) << (CRABIT_CLKSRC_B - STDBIT_CLKPOL))); /* with direction (ClkSrcB<0>) obtained from ClkPol. */
1991 crb |= ((1 << CRBBIT_CLKPOL_B) /* ClkPolB behaves as always-on clock enable. */
1992 |(MULT_X1 << CRBBIT_CLKMULT_B)); /* ClkMultB must be 1x. */
1995 case CLKSRC_EXTENDER: /* Extender Mode: */
1996 cra |= ((2 << CRABIT_CLKSRC_B) /* ClkSrcB source is OverflowA (same as "timer") */
1997 |((setup & STDMSK_CLKPOL) << (CRABIT_CLKSRC_B - STDBIT_CLKPOL))); /* with direction obtained from ClkPol. */
1998 crb |= ((1 << CRBBIT_CLKPOL_B) /* ClkPolB controls IndexB -- always set to active. */
1999 |(MULT_X0 << CRBBIT_CLKMULT_B)); /* ClkMultB selects OverflowA as the clock source. */
2002 default: /* Counter Mode: */
2003 cra |= (CLKSRC_COUNTER << CRABIT_CLKSRC_B); /* Select ENC_C and ENC_D as clock/direction inputs. */
2004 crb |= (((setup & STDMSK_CLKPOL) >> (STDBIT_CLKPOL - CRBBIT_CLKPOL_B)) /* ClkPol is passed through. */
2005 |(((setup & STDMSK_CLKMULT) == (MULT_X0 << STDBIT_CLKMULT)) ? /* Force ClkMult to x1 if not legal, otherwise pass through. */
2006 (MULT_X1 << CRBBIT_CLKMULT_B) :
2007 ((setup & STDMSK_CLKMULT) << (CRBBIT_CLKMULT_B -
2011 /* Force positive index polarity if IndxSrc is software-driven only, */
2012 /* otherwise pass it through. */
2013 if (~setup & STDMSK_INDXSRC)
2014 crb |= ((setup & STDMSK_INDXPOL) >> (STDBIT_INDXPOL -
2017 /* If IntSrc has been forced to Disabled, update the MISC2 interrupt */
2018 /* enable mask to indicate the counter interrupt is disabled. */
2020 devpriv->CounterIntEnabs &= ~k->MyEventBits[3];
2022 /* While retaining CounterA and LatchSrc configurations, program the */
2023 /* new counter operating mode. */
2024 DEBIreplace(dev, k->MyCRA,
2025 (uint16_t) (~(CRAMSK_INDXSRC_B | CRAMSK_CLKSRC_B)), cra);
2026 DEBIreplace(dev, k->MyCRB, CRBMSK_CLKENAB_A | CRBMSK_LATCHSRC, crb);
2029 /* Return/set a counter's enable. enab: 0=always enabled, 1=enabled by index. */
2031 static void SetEnable_A(struct comedi_device *dev, struct enc_private *k,
2034 DEBIreplace(dev, k->MyCRB,
2035 (uint16_t) (~(CRBMSK_INTCTRL | CRBMSK_CLKENAB_A)),
2036 (uint16_t) (enab << CRBBIT_CLKENAB_A));
2039 static void SetEnable_B(struct comedi_device *dev, struct enc_private *k,
2042 DEBIreplace(dev, k->MyCRB,
2043 (uint16_t) (~(CRBMSK_INTCTRL | CRBMSK_CLKENAB_B)),
2044 (uint16_t) (enab << CRBBIT_CLKENAB_B));
2047 static uint16_t GetEnable_A(struct comedi_device *dev, struct enc_private *k)
2049 return (DEBIread(dev, k->MyCRB) >> CRBBIT_CLKENAB_A) & 1;
2052 static uint16_t GetEnable_B(struct comedi_device *dev, struct enc_private *k)
2054 return (DEBIread(dev, k->MyCRB) >> CRBBIT_CLKENAB_B) & 1;
2058 * static uint16_t GetLatchSource(struct comedi_device *dev, struct enc_private *k )
2060 * return ( DEBIread( dev, k->MyCRB) >> CRBBIT_LATCHSRC ) & 3;
2065 * Return/set the event that will trigger transfer of the preload
2066 * register into the counter. 0=ThisCntr_Index, 1=ThisCntr_Overflow,
2067 * 2=OverflowA (B counters only), 3=disabled.
2070 static void SetLoadTrig_A(struct comedi_device *dev, struct enc_private *k,
2073 DEBIreplace(dev, k->MyCRA, (uint16_t) (~CRAMSK_LOADSRC_A),
2074 (uint16_t) (Trig << CRABIT_LOADSRC_A));
2077 static void SetLoadTrig_B(struct comedi_device *dev, struct enc_private *k,
2080 DEBIreplace(dev, k->MyCRB,
2081 (uint16_t) (~(CRBMSK_LOADSRC_B | CRBMSK_INTCTRL)),
2082 (uint16_t) (Trig << CRBBIT_LOADSRC_B));
2085 static uint16_t GetLoadTrig_A(struct comedi_device *dev, struct enc_private *k)
2087 return (DEBIread(dev, k->MyCRA) >> CRABIT_LOADSRC_A) & 3;
2090 static uint16_t GetLoadTrig_B(struct comedi_device *dev, struct enc_private *k)
2092 return (DEBIread(dev, k->MyCRB) >> CRBBIT_LOADSRC_B) & 3;
2095 /* Return/set counter interrupt source and clear any captured
2096 * index/overflow events. IntSource: 0=Disabled, 1=OverflowOnly,
2097 * 2=IndexOnly, 3=IndexAndOverflow.
2100 static void SetIntSrc_A(struct comedi_device *dev, struct enc_private *k,
2103 struct s626_private *devpriv = dev->private;
2105 /* Reset any pending counter overflow or index captures. */
2106 DEBIreplace(dev, k->MyCRB, (uint16_t) (~CRBMSK_INTCTRL),
2107 CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A);
2109 /* Program counter interrupt source. */
2110 DEBIreplace(dev, k->MyCRA, ~CRAMSK_INTSRC_A,
2111 (uint16_t) (IntSource << CRABIT_INTSRC_A));
2113 /* Update MISC2 interrupt enable mask. */
2114 devpriv->CounterIntEnabs =
2115 (devpriv->CounterIntEnabs & ~k->
2116 MyEventBits[3]) | k->MyEventBits[IntSource];
2119 static void SetIntSrc_B(struct comedi_device *dev, struct enc_private *k,
2122 struct s626_private *devpriv = dev->private;
2125 /* Cache writeable CRB register image. */
2126 crb = DEBIread(dev, k->MyCRB) & ~CRBMSK_INTCTRL;
2128 /* Reset any pending counter overflow or index captures. */
2129 DEBIwrite(dev, k->MyCRB,
2130 (uint16_t) (crb | CRBMSK_INTRESETCMD | CRBMSK_INTRESET_B));
2132 /* Program counter interrupt source. */
2133 DEBIwrite(dev, k->MyCRB,
2134 (uint16_t) ((crb & ~CRBMSK_INTSRC_B) | (IntSource <<
2137 /* Update MISC2 interrupt enable mask. */
2138 devpriv->CounterIntEnabs =
2139 (devpriv->CounterIntEnabs & ~k->
2140 MyEventBits[3]) | k->MyEventBits[IntSource];
2143 static uint16_t GetIntSrc_A(struct comedi_device *dev, struct enc_private *k)
2145 return (DEBIread(dev, k->MyCRA) >> CRABIT_INTSRC_A) & 3;
2148 static uint16_t GetIntSrc_B(struct comedi_device *dev, struct enc_private *k)
2150 return (DEBIread(dev, k->MyCRB) >> CRBBIT_INTSRC_B) & 3;
2153 /* Return/set the clock multiplier. */
2155 /* static void SetClkMult(struct comedi_device *dev, struct enc_private *k, uint16_t value ) */
2157 /* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_CLKMULT ) | ( value << STDBIT_CLKMULT ) ), FALSE ); */
2160 /* static uint16_t GetClkMult(struct comedi_device *dev, struct enc_private *k ) */
2162 /* return ( k->GetMode(dev, k ) >> STDBIT_CLKMULT ) & 3; */
2165 /* Return/set the clock polarity. */
2167 /* static void SetClkPol( struct comedi_device *dev,struct enc_private *k, uint16_t value ) */
2169 /* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_CLKPOL ) | ( value << STDBIT_CLKPOL ) ), FALSE ); */
2172 /* static uint16_t GetClkPol(struct comedi_device *dev, struct enc_private *k ) */
2174 /* return ( k->GetMode(dev, k ) >> STDBIT_CLKPOL ) & 1; */
2177 /* Return/set the clock source. */
2179 /* static void SetClkSrc( struct comedi_device *dev,struct enc_private *k, uint16_t value ) */
2181 /* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_CLKSRC ) | ( value << STDBIT_CLKSRC ) ), FALSE ); */
2184 /* static uint16_t GetClkSrc( struct comedi_device *dev,struct enc_private *k ) */
2186 /* return ( k->GetMode(dev, k ) >> STDBIT_CLKSRC ) & 3; */
2189 /* Return/set the index polarity. */
2191 /* static void SetIndexPol(struct comedi_device *dev, struct enc_private *k, uint16_t value ) */
2193 /* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_INDXPOL ) | ( (value != 0) << STDBIT_INDXPOL ) ), FALSE ); */
2196 /* static uint16_t GetIndexPol(struct comedi_device *dev, struct enc_private *k ) */
2198 /* return ( k->GetMode(dev, k ) >> STDBIT_INDXPOL ) & 1; */
2201 /* Return/set the index source. */
2203 /* static void SetIndexSrc(struct comedi_device *dev, struct enc_private *k, uint16_t value ) */
2205 /* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_INDXSRC ) | ( (value != 0) << STDBIT_INDXSRC ) ), FALSE ); */
2208 /* static uint16_t GetIndexSrc(struct comedi_device *dev, struct enc_private *k ) */
2210 /* return ( k->GetMode(dev, k ) >> STDBIT_INDXSRC ) & 1; */
2213 /* Generate an index pulse. */
2215 static void PulseIndex_A(struct comedi_device *dev, struct enc_private *k)
2217 register uint16_t cra;
2219 cra = DEBIread(dev, k->MyCRA); /* Pulse index. */
2220 DEBIwrite(dev, k->MyCRA, (uint16_t) (cra ^ CRAMSK_INDXPOL_A));
2221 DEBIwrite(dev, k->MyCRA, cra);
2224 static void PulseIndex_B(struct comedi_device *dev, struct enc_private *k)
2226 register uint16_t crb;
2228 crb = DEBIread(dev, k->MyCRB) & ~CRBMSK_INTCTRL; /* Pulse index. */
2229 DEBIwrite(dev, k->MyCRB, (uint16_t) (crb ^ CRBMSK_INDXPOL_B));
2230 DEBIwrite(dev, k->MyCRB, crb);
2233 static struct enc_private enc_private_data[] = {
2235 .GetEnable = GetEnable_A,
2236 .GetIntSrc = GetIntSrc_A,
2237 .GetLoadTrig = GetLoadTrig_A,
2238 .GetMode = GetMode_A,
2239 .PulseIndex = PulseIndex_A,
2240 .SetEnable = SetEnable_A,
2241 .SetIntSrc = SetIntSrc_A,
2242 .SetLoadTrig = SetLoadTrig_A,
2243 .SetMode = SetMode_A,
2244 .ResetCapFlags = ResetCapFlags_A,
2247 .MyLatchLsw = LP_CNTR0ALSW,
2248 .MyEventBits = EVBITS(0),
2250 .GetEnable = GetEnable_A,
2251 .GetIntSrc = GetIntSrc_A,
2252 .GetLoadTrig = GetLoadTrig_A,
2253 .GetMode = GetMode_A,
2254 .PulseIndex = PulseIndex_A,
2255 .SetEnable = SetEnable_A,
2256 .SetIntSrc = SetIntSrc_A,
2257 .SetLoadTrig = SetLoadTrig_A,
2258 .SetMode = SetMode_A,
2259 .ResetCapFlags = ResetCapFlags_A,
2262 .MyLatchLsw = LP_CNTR1ALSW,
2263 .MyEventBits = EVBITS(1),
2265 .GetEnable = GetEnable_A,
2266 .GetIntSrc = GetIntSrc_A,
2267 .GetLoadTrig = GetLoadTrig_A,
2268 .GetMode = GetMode_A,
2269 .PulseIndex = PulseIndex_A,
2270 .SetEnable = SetEnable_A,
2271 .SetIntSrc = SetIntSrc_A,
2272 .SetLoadTrig = SetLoadTrig_A,
2273 .SetMode = SetMode_A,
2274 .ResetCapFlags = ResetCapFlags_A,
2277 .MyLatchLsw = LP_CNTR2ALSW,
2278 .MyEventBits = EVBITS(2),
2280 .GetEnable = GetEnable_B,
2281 .GetIntSrc = GetIntSrc_B,
2282 .GetLoadTrig = GetLoadTrig_B,
2283 .GetMode = GetMode_B,
2284 .PulseIndex = PulseIndex_B,
2285 .SetEnable = SetEnable_B,
2286 .SetIntSrc = SetIntSrc_B,
2287 .SetLoadTrig = SetLoadTrig_B,
2288 .SetMode = SetMode_B,
2289 .ResetCapFlags = ResetCapFlags_B,
2292 .MyLatchLsw = LP_CNTR0BLSW,
2293 .MyEventBits = EVBITS(3),
2295 .GetEnable = GetEnable_B,
2296 .GetIntSrc = GetIntSrc_B,
2297 .GetLoadTrig = GetLoadTrig_B,
2298 .GetMode = GetMode_B,
2299 .PulseIndex = PulseIndex_B,
2300 .SetEnable = SetEnable_B,
2301 .SetIntSrc = SetIntSrc_B,
2302 .SetLoadTrig = SetLoadTrig_B,
2303 .SetMode = SetMode_B,
2304 .ResetCapFlags = ResetCapFlags_B,
2307 .MyLatchLsw = LP_CNTR1BLSW,
2308 .MyEventBits = EVBITS(4),
2310 .GetEnable = GetEnable_B,
2311 .GetIntSrc = GetIntSrc_B,
2312 .GetLoadTrig = GetLoadTrig_B,
2313 .GetMode = GetMode_B,
2314 .PulseIndex = PulseIndex_B,
2315 .SetEnable = SetEnable_B,
2316 .SetIntSrc = SetIntSrc_B,
2317 .SetLoadTrig = SetLoadTrig_B,
2318 .SetMode = SetMode_B,
2319 .ResetCapFlags = ResetCapFlags_B,
2322 .MyLatchLsw = LP_CNTR2BLSW,
2323 .MyEventBits = EVBITS(5),
2327 static void CountersInit(struct comedi_device *dev)
2330 struct enc_private *k;
2331 uint16_t Setup = (LOADSRC_INDX << BF_LOADSRC) | /* Preload upon */
2333 (INDXSRC_SOFT << BF_INDXSRC) | /* Disable hardware index. */
2334 (CLKSRC_COUNTER << BF_CLKSRC) | /* Operating mode is counter. */
2335 (CLKPOL_POS << BF_CLKPOL) | /* Active high clock. */
2336 (CNTDIR_UP << BF_CLKPOL) | /* Count direction is up. */
2337 (CLKMULT_1X << BF_CLKMULT) | /* Clock multiplier is 1x. */
2338 (CLKENAB_INDEX << BF_CLKENAB); /* Enabled by index */
2340 /* Disable all counter interrupts and clear any captured counter events. */
2341 for (chan = 0; chan < S626_ENCODER_CHANNELS; chan++) {
2343 k->SetMode(dev, k, Setup, TRUE);
2344 k->SetIntSrc(dev, k, 0);
2345 k->ResetCapFlags(dev, k);
2346 k->SetEnable(dev, k, CLKENAB_ALWAYS);
2350 static int s626_allocate_dma_buffers(struct comedi_device *dev)
2352 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2353 struct s626_private *devpriv = dev->private;
2357 addr = pci_alloc_consistent(pcidev, DMABUF_SIZE, &appdma);
2360 devpriv->ANABuf.LogicalBase = addr;
2361 devpriv->ANABuf.PhysicalBase = appdma;
2363 addr = pci_alloc_consistent(pcidev, DMABUF_SIZE, &appdma);
2366 devpriv->RPSBuf.LogicalBase = addr;
2367 devpriv->RPSBuf.PhysicalBase = appdma;
2372 static void s626_initialize(struct comedi_device *dev)
2374 struct s626_private *devpriv = dev->private;
2375 dma_addr_t pPhysBuf;
2379 /* Enable DEBI and audio pins, enable I2C interface */
2380 s626_mc_enable(dev, MC1_DEBI | MC1_AUDIO | MC1_I2C, P_MC1);
2383 * Configure DEBI operating mode
2385 * Local bus is 16 bits wide
2386 * Declare DEBI transfer timeout interval
2387 * Set up byte lane steering
2388 * Intel-compatible local bus (DEBI never times out)
2390 WR7146(P_DEBICFG, DEBI_CFG_SLAVE16 |
2391 (DEBI_TOUT << DEBI_CFG_TOUT_BIT) |
2392 DEBI_SWAP | DEBI_CFG_INTEL);
2394 /* Disable MMU paging */
2395 WR7146(P_DEBIPAGE, DEBI_PAGE_DISABLE);
2397 /* Init GPIO so that ADC Start* is negated */
2398 WR7146(P_GPIO, GPIO_BASE | GPIO1_HI);
2400 /* I2C device address for onboard eeprom (revb) */
2401 devpriv->I2CAdrs = 0xA0;
2404 * Issue an I2C ABORT command to halt any I2C
2405 * operation in progress and reset BUSY flag.
2407 WR7146(P_I2CSTAT, I2C_CLKSEL | I2C_ABORT);
2408 s626_mc_enable(dev, MC2_UPLD_IIC, P_MC2);
2409 while ((RR7146(P_MC2) & MC2_UPLD_IIC) == 0)
2413 * Per SAA7146 data sheet, write to STATUS
2414 * reg twice to reset all I2C error flags.
2416 for (i = 0; i < 2; i++) {
2417 WR7146(P_I2CSTAT, I2C_CLKSEL);
2418 s626_mc_enable(dev, MC2_UPLD_IIC, P_MC2);
2419 while (!MC_TEST(P_MC2, MC2_UPLD_IIC))
2424 * Init audio interface functional attributes: set DAC/ADC
2425 * serial clock rates, invert DAC serial clock so that
2426 * DAC data setup times are satisfied, enable DAC serial
2429 WR7146(P_ACON2, ACON2_INIT);
2432 * Set up TSL1 slot list, which is used to control the
2433 * accumulation of ADC data: RSD1 = shift data in on SD1.
2434 * SIB_A1 = store data uint8_t at next available location
2435 * in FB BUFFER1 register.
2437 WR7146(P_TSL1, RSD1 | SIB_A1);
2438 WR7146(P_TSL1 + 4, RSD1 | SIB_A1 | EOS);
2440 /* Enable TSL1 slot list so that it executes all the time */
2441 WR7146(P_ACON1, ACON1_ADCSTART);
2444 * Initialize RPS registers used for ADC
2447 /* Physical start of RPS program */
2448 WR7146(P_RPSADDR1, (uint32_t)devpriv->RPSBuf.PhysicalBase);
2449 /* RPS program performs no explicit mem writes */
2450 WR7146(P_RPSPAGE1, 0);
2451 /* Disable RPS timeouts */
2452 WR7146(P_RPS1_TOUT, 0);
2456 * SAA7146 BUG WORKAROUND
2458 * Initialize SAA7146 ADC interface to a known state by
2459 * invoking ADCs until FB BUFFER 1 register shows that it
2460 * is correctly receiving ADC data. This is necessary
2461 * because the SAA7146 ADC interface does not start up in
2462 * a defined state after a PCI reset.
2470 unsigned int data[16];
2472 /* Create a simple polling list for analog input channel 0 */
2474 ResetADC(dev, &PollList);
2476 /* Get initial ADC value */
2477 s626_ai_rinsn(dev, dev->subdevices, NULL, data);
2481 * VERSION 2.01 CHANGE: TIMEOUT ADDED TO PREVENT HANGED EXECUTION.
2483 * Invoke ADCs until the new ADC value differs from the initial
2484 * value or a timeout occurs. The timeout protects against the
2485 * possibility that the driver is restarting and the ADC data is a
2486 * fixed value resulting from the applied ADC analog input being
2487 * unusually quiet or at the rail.
2489 for (index = 0; index < 500; index++) {
2490 s626_ai_rinsn(dev, dev->subdevices, NULL, data);
2492 if (AdcData != StartVal)
2497 #endif /* SAA7146 BUG WORKAROUND */
2500 * Initialize the DAC interface
2504 * Init Audio2's output DMAC attributes:
2505 * burst length = 1 DWORD
2506 * threshold = 1 DWORD.
2508 WR7146(P_PCI_BT_A, 0);
2511 * Init Audio2's output DMA physical addresses. The protection
2512 * address is set to 1 DWORD past the base address so that a
2513 * single DWORD will be transferred each time a DMA transfer is
2516 pPhysBuf = devpriv->ANABuf.PhysicalBase +
2517 (DAC_WDMABUF_OS * sizeof(uint32_t));
2518 WR7146(P_BASEA2_OUT, (uint32_t) pPhysBuf);
2519 WR7146(P_PROTA2_OUT, (uint32_t) (pPhysBuf + sizeof(uint32_t)));
2522 * Cache Audio2's output DMA buffer logical address. This is
2523 * where DAC data is buffered for A2 output DMA transfers.
2525 devpriv->pDacWBuf = (uint32_t *)devpriv->ANABuf.LogicalBase +
2529 * Audio2's output channels does not use paging. The
2530 * protection violation handling bit is set so that the
2531 * DMAC will automatically halt and its PCI address pointer
2532 * will be reset when the protection address is reached.
2534 WR7146(P_PAGEA2_OUT, 8);
2537 * Initialize time slot list 2 (TSL2), which is used to control
2538 * the clock generation for and serialization of data to be sent
2539 * to the DAC devices. Slot 0 is a NOP that is used to trap TSL
2540 * execution; this permits other slots to be safely modified
2541 * without first turning off the TSL sequencer (which is
2542 * apparently impossible to do). Also, SD3 (which is driven by a
2543 * pull-up resistor) is shifted in and stored to the MSB of
2544 * FB_BUFFER2 to be used as evidence that the slot sequence has
2545 * not yet finished executing.
2548 /* Slot 0: Trap TSL execution, shift 0xFF into FB_BUFFER2 */
2549 SETVECT(0, XSD2 | RSD3 | SIB_A2 | EOS);
2552 * Initialize slot 1, which is constant. Slot 1 causes a
2553 * DWORD to be transferred from audio channel 2's output FIFO
2554 * to the FIFO's output buffer so that it can be serialized
2555 * and sent to the DAC during subsequent slots. All remaining
2556 * slots are dynamically populated as required by the target
2560 /* Slot 1: Fetch DWORD from Audio2's output FIFO */
2563 /* Start DAC's audio interface (TSL2) running */
2564 WR7146(P_ACON1, ACON1_DACSTART);
2567 * Init Trim DACs to calibrated values. Do it twice because the
2568 * SAA7146 audio channel does not always reset properly and
2569 * sometimes causes the first few TrimDAC writes to malfunction.
2575 * Manually init all gate array hardware in case this is a soft
2576 * reset (we have no way of determining whether this is a warm
2577 * or cold start). This is necessary because the gate array will
2578 * reset only in response to a PCI hard reset; there is no soft
2583 * Init all DAC outputs to 0V and init all DAC setpoint and
2586 for (chan = 0; chan < S626_DAC_CHANNELS; chan++)
2587 SetDAC(dev, chan, 0);
2593 * Without modifying the state of the Battery Backup enab, disable
2594 * the watchdog timer, set DIO channels 0-5 to operate in the
2595 * standard DIO (vs. counter overflow) mode, disable the battery
2596 * charger, and reset the watchdog interval selector to zero.
2598 WriteMISC2(dev, (uint16_t)(DEBIread(dev, LP_RDMISC2) &
2599 MISC2_BATT_ENABLE));
2601 /* Initialize the digital I/O subsystem */
2604 /* enable interrupt test */
2605 /* writel(IRQ_GPIO3 | IRQ_RPS1, devpriv->base_addr + P_IER); */
2608 static int s626_auto_attach(struct comedi_device *dev,
2609 unsigned long context_unused)
2611 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2612 struct s626_private *devpriv;
2613 struct comedi_subdevice *s;
2616 dev->board_name = dev->driver->driver_name;
2618 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
2621 dev->private = devpriv;
2623 ret = comedi_pci_enable(dev);
2627 devpriv->base_addr = ioremap(pci_resource_start(pcidev, 0),
2628 pci_resource_len(pcidev, 0));
2629 if (!devpriv->base_addr)
2632 /* disable master interrupt */
2633 writel(0, devpriv->base_addr + P_IER);
2636 writel(MC1_SOFT_RESET, devpriv->base_addr + P_MC1);
2638 /* DMA FIXME DMA// */
2640 ret = s626_allocate_dma_buffers(dev);
2645 ret = request_irq(pcidev->irq, s626_irq_handler, IRQF_SHARED,
2646 dev->board_name, dev);
2649 dev->irq = pcidev->irq;
2652 ret = comedi_alloc_subdevices(dev, 6);
2656 s = dev->subdevices + 0;
2657 /* analog input subdevice */
2658 dev->read_subdev = s;
2659 /* we support single-ended (ground) and differential */
2660 s->type = COMEDI_SUBD_AI;
2661 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_CMD_READ;
2662 s->n_chan = S626_ADC_CHANNELS;
2663 s->maxdata = (0xffff >> 2);
2664 s->range_table = &s626_range_table;
2665 s->len_chanlist = S626_ADC_CHANNELS;
2666 s->insn_config = s626_ai_insn_config;
2667 s->insn_read = s626_ai_insn_read;
2668 s->do_cmd = s626_ai_cmd;
2669 s->do_cmdtest = s626_ai_cmdtest;
2670 s->cancel = s626_ai_cancel;
2672 s = dev->subdevices + 1;
2673 /* analog output subdevice */
2674 s->type = COMEDI_SUBD_AO;
2675 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2676 s->n_chan = S626_DAC_CHANNELS;
2677 s->maxdata = (0x3fff);
2678 s->range_table = &range_bipolar10;
2679 s->insn_write = s626_ao_winsn;
2680 s->insn_read = s626_ao_rinsn;
2682 s = dev->subdevices + 2;
2683 /* digital I/O subdevice */
2684 s->type = COMEDI_SUBD_DIO;
2685 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2688 s->io_bits = 0xffff;
2689 s->private = (void *)0; /* DIO group 0 */
2690 s->range_table = &range_digital;
2691 s->insn_config = s626_dio_insn_config;
2692 s->insn_bits = s626_dio_insn_bits;
2694 s = dev->subdevices + 3;
2695 /* digital I/O subdevice */
2696 s->type = COMEDI_SUBD_DIO;
2697 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2700 s->io_bits = 0xffff;
2701 s->private = (void *)1; /* DIO group 1 */
2702 s->range_table = &range_digital;
2703 s->insn_config = s626_dio_insn_config;
2704 s->insn_bits = s626_dio_insn_bits;
2706 s = dev->subdevices + 4;
2707 /* digital I/O subdevice */
2708 s->type = COMEDI_SUBD_DIO;
2709 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2712 s->io_bits = 0xffff;
2713 s->private = (void *)2; /* DIO group 2 */
2714 s->range_table = &range_digital;
2715 s->insn_config = s626_dio_insn_config;
2716 s->insn_bits = s626_dio_insn_bits;
2718 s = dev->subdevices + 5;
2719 /* encoder (counter) subdevice */
2720 s->type = COMEDI_SUBD_COUNTER;
2721 s->subdev_flags = SDF_WRITABLE | SDF_READABLE | SDF_LSAMPL;
2722 s->n_chan = S626_ENCODER_CHANNELS;
2723 s->private = enc_private_data;
2724 s->insn_config = s626_enc_insn_config;
2725 s->insn_read = s626_enc_insn_read;
2726 s->insn_write = s626_enc_insn_write;
2727 s->maxdata = 0xffffff;
2728 s->range_table = &range_unknown;
2730 s626_initialize(dev);
2732 dev_info(dev->class_dev, "%s attached\n", dev->board_name);
2737 static void s626_detach(struct comedi_device *dev)
2739 struct s626_private *devpriv = dev->private;
2742 /* stop ai_command */
2743 devpriv->ai_cmd_running = 0;
2745 if (devpriv->base_addr) {
2746 /* interrupt mask */
2747 WR7146(P_IER, 0); /* Disable master interrupt. */
2748 WR7146(P_ISR, IRQ_GPIO3 | IRQ_RPS1); /* Clear board's IRQ status flag. */
2750 /* Disable the watchdog timer and battery charger. */
2753 /* Close all interfaces on 7146 device. */
2754 WR7146(P_MC1, MC1_SHUTDOWN);
2755 WR7146(P_ACON1, ACON1_BASE);
2757 CloseDMAB(dev, &devpriv->RPSBuf, DMABUF_SIZE);
2758 CloseDMAB(dev, &devpriv->ANABuf, DMABUF_SIZE);
2762 free_irq(dev->irq, dev);
2763 if (devpriv->base_addr)
2764 iounmap(devpriv->base_addr);
2766 comedi_pci_disable(dev);
2769 static struct comedi_driver s626_driver = {
2770 .driver_name = "s626",
2771 .module = THIS_MODULE,
2772 .auto_attach = s626_auto_attach,
2773 .detach = s626_detach,
2776 static int s626_pci_probe(struct pci_dev *dev,
2777 const struct pci_device_id *id)
2779 return comedi_pci_auto_config(dev, &s626_driver, id->driver_data);
2783 * For devices with vendor:device id == 0x1131:0x7146 you must specify
2784 * also subvendor:subdevice ids, because otherwise it will conflict with
2785 * Philips SAA7146 media/dvb based cards.
2787 static DEFINE_PCI_DEVICE_TABLE(s626_pci_table) = {
2788 { PCI_VENDOR_ID_S626, PCI_DEVICE_ID_S626,
2789 PCI_SUBVENDOR_ID_S626, PCI_SUBDEVICE_ID_S626, 0, 0, 0 },
2792 MODULE_DEVICE_TABLE(pci, s626_pci_table);
2794 static struct pci_driver s626_pci_driver = {
2796 .id_table = s626_pci_table,
2797 .probe = s626_pci_probe,
2798 .remove = comedi_pci_auto_unconfig,
2800 module_comedi_pci_driver(s626_driver, s626_pci_driver);
2802 MODULE_AUTHOR("Gianluca Palli <gpalli@deis.unibo.it>");
2803 MODULE_DESCRIPTION("Sensoray 626 Comedi driver module");
2804 MODULE_LICENSE("GPL");