2 * Driver for the Conexant CX25821 PCIe bridge
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include "cx25821-medusa-video.h"
25 #include "cx25821-biffuncs.h"
28 * medusa_enable_bluefield_output()
30 * Enable the generation of blue filed output if no video
33 static void medusa_enable_bluefield_output(struct cx25821_dev *dev, int channel,
39 int out_ctrl = OUT_CTRL1;
40 int out_ctrl_ns = OUT_CTRL_NS;
47 out_ctrl = VDEC_B_OUT_CTRL1;
48 out_ctrl_ns = VDEC_B_OUT_CTRL_NS;
51 out_ctrl = VDEC_C_OUT_CTRL1;
52 out_ctrl_ns = VDEC_C_OUT_CTRL_NS;
55 out_ctrl = VDEC_D_OUT_CTRL1;
56 out_ctrl_ns = VDEC_D_OUT_CTRL_NS;
59 out_ctrl = VDEC_E_OUT_CTRL1;
60 out_ctrl_ns = VDEC_E_OUT_CTRL_NS;
63 out_ctrl = VDEC_F_OUT_CTRL1;
64 out_ctrl_ns = VDEC_F_OUT_CTRL_NS;
67 out_ctrl = VDEC_G_OUT_CTRL1;
68 out_ctrl_ns = VDEC_G_OUT_CTRL_NS;
71 out_ctrl = VDEC_H_OUT_CTRL1;
72 out_ctrl_ns = VDEC_H_OUT_CTRL_NS;
76 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl, &tmp);
77 value &= 0xFFFFFF7F; /* clear BLUE_FIELD_EN */
79 value |= 0x00000080; /* set BLUE_FIELD_EN */
80 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl, value);
82 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl_ns, &tmp);
85 value |= 0x00000080; /* set BLUE_FIELD_EN */
86 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl_ns, value);
89 static int medusa_initialize_ntsc(struct cx25821_dev *dev)
96 mutex_lock(&dev->lock);
98 for (i = 0; i < MAX_DECODERS; i++) {
99 /* set video format NTSC-M */
101 cx25821_i2c_read(&dev->i2c_bus[0], MODE_CTRL + (0x200 * i),
104 /* enable the fast locking mode bit[16] */
107 cx25821_i2c_write(&dev->i2c_bus[0], MODE_CTRL + (0x200 * i),
110 /* resolution NTSC 720x480 */
112 cx25821_i2c_read(&dev->i2c_bus[0],
113 HORIZ_TIM_CTRL + (0x200 * i), &tmp);
117 cx25821_i2c_write(&dev->i2c_bus[0],
118 HORIZ_TIM_CTRL + (0x200 * i), value);
121 cx25821_i2c_read(&dev->i2c_bus[0],
122 VERT_TIM_CTRL + (0x200 * i), &tmp);
124 value |= 0x1C1E001A; /* vblank_cnt + 2 to get camera ID */
126 cx25821_i2c_write(&dev->i2c_bus[0],
127 VERT_TIM_CTRL + (0x200 * i), value);
129 /* chroma subcarrier step size */
131 cx25821_i2c_write(&dev->i2c_bus[0],
132 SC_STEP_SIZE + (0x200 * i), 0x43E00000);
134 /* enable VIP optional active */
136 cx25821_i2c_read(&dev->i2c_bus[0],
137 OUT_CTRL_NS + (0x200 * i), &tmp);
141 cx25821_i2c_write(&dev->i2c_bus[0],
142 OUT_CTRL_NS + (0x200 * i), value);
144 /* enable VIP optional active (VIP_OPT_AL) for direct output. */
146 cx25821_i2c_read(&dev->i2c_bus[0], OUT_CTRL1 + (0x200 * i),
151 cx25821_i2c_write(&dev->i2c_bus[0], OUT_CTRL1 + (0x200 * i),
155 * clear VPRES_VERT_EN bit, fixes the chroma run away problem
156 * when the input switching rate < 16 fields
159 cx25821_i2c_read(&dev->i2c_bus[0],
160 MISC_TIM_CTRL + (0x200 * i), &tmp);
161 /* disable special play detection */
162 value = setBitAtPos(value, 14);
163 value = clearBitAtPos(value, 15);
165 cx25821_i2c_write(&dev->i2c_bus[0],
166 MISC_TIM_CTRL + (0x200 * i), value);
168 /* set vbi_gate_en to 0 */
170 cx25821_i2c_read(&dev->i2c_bus[0], DFE_CTRL1 + (0x200 * i),
172 value = clearBitAtPos(value, 29);
174 cx25821_i2c_write(&dev->i2c_bus[0], DFE_CTRL1 + (0x200 * i),
177 /* Enable the generation of blue field output if no video */
178 medusa_enable_bluefield_output(dev, i, 1);
181 for (i = 0; i < MAX_ENCODERS; i++) {
184 cx25821_i2c_read(&dev->i2c_bus[0],
185 DENC_A_REG_1 + (0x100 * i), &tmp);
189 cx25821_i2c_write(&dev->i2c_bus[0],
190 DENC_A_REG_1 + (0x100 * i), value);
192 /* burst begin and burst end */
194 cx25821_i2c_read(&dev->i2c_bus[0],
195 DENC_A_REG_2 + (0x100 * i), &tmp);
199 cx25821_i2c_write(&dev->i2c_bus[0],
200 DENC_A_REG_2 + (0x100 * i), value);
203 cx25821_i2c_read(&dev->i2c_bus[0],
204 DENC_A_REG_3 + (0x100 * i), &tmp);
208 cx25821_i2c_write(&dev->i2c_bus[0],
209 DENC_A_REG_3 + (0x100 * i), value);
211 /* set NTSC vblank, no phase alternation, 7.5 IRE pedestal */
213 cx25821_i2c_read(&dev->i2c_bus[0],
214 DENC_A_REG_4 + (0x100 * i), &tmp);
218 cx25821_i2c_write(&dev->i2c_bus[0],
219 DENC_A_REG_4 + (0x100 * i), value);
222 cx25821_i2c_read(&dev->i2c_bus[0],
223 DENC_A_REG_5 + (0x100 * i), &tmp);
227 cx25821_i2c_write(&dev->i2c_bus[0],
228 DENC_A_REG_5 + (0x100 * i), value);
231 cx25821_i2c_write(&dev->i2c_bus[0],
232 DENC_A_REG_6 + (0x100 * i), 0x009A89C1);
234 /* Subcarrier Increment */
236 cx25821_i2c_write(&dev->i2c_bus[0],
237 DENC_A_REG_7 + (0x100 * i), 0x21F07C1F);
240 /* set picture resolutions */
242 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], HSCALE_CTRL, 0x0);
244 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], VSCALE_CTRL, 0x0);
246 /* set Bypass input format to NTSC 525 lines */
247 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp);
249 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value);
251 mutex_unlock(&dev->lock);
256 static int medusa_PALCombInit(struct cx25821_dev *dev, int dec)
259 u32 value = 0, tmp = 0;
261 /* Setup for 2D threshold */
263 cx25821_i2c_write(&dev->i2c_bus[0], COMB_2D_HFS_CFG + (0x200 * dec),
266 cx25821_i2c_write(&dev->i2c_bus[0], COMB_2D_HFD_CFG + (0x200 * dec),
269 cx25821_i2c_write(&dev->i2c_bus[0], COMB_2D_LF_CFG + (0x200 * dec),
272 /* Setup flat chroma and luma thresholds */
274 cx25821_i2c_read(&dev->i2c_bus[0],
275 COMB_FLAT_THRESH_CTRL + (0x200 * dec), &tmp);
278 cx25821_i2c_write(&dev->i2c_bus[0],
279 COMB_FLAT_THRESH_CTRL + (0x200 * dec), value);
281 /* set comb 2D blend */
283 cx25821_i2c_write(&dev->i2c_bus[0], COMB_2D_BLEND + (0x200 * dec),
286 /* COMB MISC CONTROL */
288 cx25821_i2c_write(&dev->i2c_bus[0], COMB_MISC_CTRL + (0x200 * dec),
294 static int medusa_initialize_pal(struct cx25821_dev *dev)
301 mutex_lock(&dev->lock);
303 for (i = 0; i < MAX_DECODERS; i++) {
304 /* set video format PAL-BDGHI */
306 cx25821_i2c_read(&dev->i2c_bus[0], MODE_CTRL + (0x200 * i),
309 /* enable the fast locking mode bit[16] */
312 cx25821_i2c_write(&dev->i2c_bus[0], MODE_CTRL + (0x200 * i),
315 /* resolution PAL 720x576 */
317 cx25821_i2c_read(&dev->i2c_bus[0],
318 HORIZ_TIM_CTRL + (0x200 * i), &tmp);
322 cx25821_i2c_write(&dev->i2c_bus[0],
323 HORIZ_TIM_CTRL + (0x200 * i), value);
325 /* vblank656_cnt=x26, vactive_cnt=240h, vblank_cnt=x24 */
327 cx25821_i2c_read(&dev->i2c_bus[0],
328 VERT_TIM_CTRL + (0x200 * i), &tmp);
330 value |= 0x28240026; /* vblank_cnt + 2 to get camera ID */
332 cx25821_i2c_write(&dev->i2c_bus[0],
333 VERT_TIM_CTRL + (0x200 * i), value);
335 /* chroma subcarrier step size */
337 cx25821_i2c_write(&dev->i2c_bus[0],
338 SC_STEP_SIZE + (0x200 * i), 0x5411E2D0);
340 /* enable VIP optional active */
342 cx25821_i2c_read(&dev->i2c_bus[0],
343 OUT_CTRL_NS + (0x200 * i), &tmp);
347 cx25821_i2c_write(&dev->i2c_bus[0],
348 OUT_CTRL_NS + (0x200 * i), value);
350 /* enable VIP optional active (VIP_OPT_AL) for direct output. */
352 cx25821_i2c_read(&dev->i2c_bus[0], OUT_CTRL1 + (0x200 * i),
357 cx25821_i2c_write(&dev->i2c_bus[0], OUT_CTRL1 + (0x200 * i),
361 * clear VPRES_VERT_EN bit, fixes the chroma run away problem
362 * when the input switching rate < 16 fields
365 cx25821_i2c_read(&dev->i2c_bus[0],
366 MISC_TIM_CTRL + (0x200 * i), &tmp);
367 /* disable special play detection */
368 value = setBitAtPos(value, 14);
369 value = clearBitAtPos(value, 15);
371 cx25821_i2c_write(&dev->i2c_bus[0],
372 MISC_TIM_CTRL + (0x200 * i), value);
374 /* set vbi_gate_en to 0 */
376 cx25821_i2c_read(&dev->i2c_bus[0], DFE_CTRL1 + (0x200 * i),
378 value = clearBitAtPos(value, 29);
380 cx25821_i2c_write(&dev->i2c_bus[0], DFE_CTRL1 + (0x200 * i),
383 medusa_PALCombInit(dev, i);
385 /* Enable the generation of blue field output if no video */
386 medusa_enable_bluefield_output(dev, i, 1);
389 for (i = 0; i < MAX_ENCODERS; i++) {
392 cx25821_i2c_read(&dev->i2c_bus[0],
393 DENC_A_REG_1 + (0x100 * i), &tmp);
397 cx25821_i2c_write(&dev->i2c_bus[0],
398 DENC_A_REG_1 + (0x100 * i), value);
400 /* burst begin and burst end */
402 cx25821_i2c_read(&dev->i2c_bus[0],
403 DENC_A_REG_2 + (0x100 * i), &tmp);
407 cx25821_i2c_write(&dev->i2c_bus[0],
408 DENC_A_REG_2 + (0x100 * i), value);
410 /* hblank and vactive */
412 cx25821_i2c_read(&dev->i2c_bus[0],
413 DENC_A_REG_3 + (0x100 * i), &tmp);
417 cx25821_i2c_write(&dev->i2c_bus[0],
418 DENC_A_REG_3 + (0x100 * i), value);
420 /* set PAL vblank, phase alternation, 0 IRE pedestal */
422 cx25821_i2c_read(&dev->i2c_bus[0],
423 DENC_A_REG_4 + (0x100 * i), &tmp);
427 cx25821_i2c_write(&dev->i2c_bus[0],
428 DENC_A_REG_4 + (0x100 * i), value);
431 cx25821_i2c_read(&dev->i2c_bus[0],
432 DENC_A_REG_5 + (0x100 * i), &tmp);
436 cx25821_i2c_write(&dev->i2c_bus[0],
437 DENC_A_REG_5 + (0x100 * i), value);
440 cx25821_i2c_write(&dev->i2c_bus[0],
441 DENC_A_REG_6 + (0x100 * i), 0x00A493CF);
443 /* Subcarrier Increment */
445 cx25821_i2c_write(&dev->i2c_bus[0],
446 DENC_A_REG_7 + (0x100 * i), 0x2A098ACB);
449 /* set picture resolutions */
451 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], HSCALE_CTRL, 0x0);
453 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], VSCALE_CTRL, 0x0);
455 /* set Bypass input format to PAL 625 lines */
456 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp);
458 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value);
460 mutex_unlock(&dev->lock);
465 int medusa_set_videostandard(struct cx25821_dev *dev)
467 int status = STATUS_SUCCESS;
468 u32 value = 0, tmp = 0;
470 if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK)
471 status = medusa_initialize_pal(dev);
473 status = medusa_initialize_ntsc(dev);
475 /* Enable DENC_A output */
476 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_A_REG_4, &tmp);
477 value = setBitAtPos(value, 4);
478 status = cx25821_i2c_write(&dev->i2c_bus[0], DENC_A_REG_4, value);
480 /* Enable DENC_B output */
481 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_B_REG_4, &tmp);
482 value = setBitAtPos(value, 4);
483 status = cx25821_i2c_write(&dev->i2c_bus[0], DENC_B_REG_4, value);
488 void medusa_set_resolution(struct cx25821_dev *dev, int width,
492 int decoder_count = 0;
496 const int MAX_WIDTH = 720;
498 mutex_lock(&dev->lock);
500 /* validate the width - cannot be negative */
501 if (width > MAX_WIDTH) {
503 ("cx25821 %s() : width %d > MAX_WIDTH %d ! resetting to MAX_WIDTH\n",
504 __func__, width, MAX_WIDTH);
508 if (decoder_select <= 7 && decoder_select >= 0) {
509 decoder = decoder_select;
510 decoder_count = decoder_select + 1;
513 decoder_count = _num_decoders;
543 for (; decoder < decoder_count; decoder++) {
544 /* write scaling values for each decoder */
546 cx25821_i2c_write(&dev->i2c_bus[0],
547 HSCALE_CTRL + (0x200 * decoder), hscale);
549 cx25821_i2c_write(&dev->i2c_bus[0],
550 VSCALE_CTRL + (0x200 * decoder), vscale);
553 mutex_unlock(&dev->lock);
556 static void medusa_set_decoderduration(struct cx25821_dev *dev, int decoder,
562 u32 disp_cnt_reg = DISP_AB_CNT;
564 mutex_lock(&dev->lock);
567 if (decoder < VDEC_A && decoder > VDEC_H) {
568 mutex_unlock(&dev->lock);
577 disp_cnt_reg = DISP_CD_CNT;
581 disp_cnt_reg = DISP_EF_CNT;
585 disp_cnt_reg = DISP_GH_CNT;
589 _display_field_cnt[decoder] = duration;
591 /* update hardware */
592 fld_cnt = cx25821_i2c_read(&dev->i2c_bus[0], disp_cnt_reg, &tmp);
594 if (!(decoder % 2)) { /* EVEN decoder */
595 fld_cnt &= 0xFFFF0000;
598 fld_cnt &= 0x0000FFFF;
599 fld_cnt |= ((u32) duration) << 16;
602 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], disp_cnt_reg, fld_cnt);
604 mutex_unlock(&dev->lock);
607 /* Map to Medusa register setting */
608 static int mapM(int srcMin,
609 int srcMax, int srcVal, int dstMin, int dstMax, int *dstVal)
615 if ((srcMin == srcMax) || (srcVal < srcMin) || (srcVal > srcMax))
618 * This is the overall expression used:
620 * (srcVal - srcMin)*(dstMax - dstMin) / (srcMax - srcMin) + dstMin;
621 * but we need to account for rounding so below we use the modulus
622 * operator to find the remainder and increment if necessary.
624 numerator = (srcVal - srcMin) * (dstMax - dstMin);
625 denominator = srcMax - srcMin;
626 quotient = numerator / denominator;
628 if (2 * (numerator % denominator) >= denominator)
631 *dstVal = quotient + dstMin;
636 static unsigned long convert_to_twos(long numeric, unsigned long bits_len)
643 temp = ~(abs(numeric) & 0xFF);
649 int medusa_set_brightness(struct cx25821_dev *dev, int brightness, int decoder)
653 u32 val = 0, tmp = 0;
655 mutex_lock(&dev->lock);
656 if ((brightness > VIDEO_PROCAMP_MAX)
657 || (brightness < VIDEO_PROCAMP_MIN)) {
658 mutex_unlock(&dev->lock);
662 mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, brightness,
663 SIGNED_BYTE_MIN, SIGNED_BYTE_MAX, &value);
664 value = convert_to_twos(value, 8);
666 cx25821_i2c_read(&dev->i2c_bus[0],
667 VDEC_A_BRITE_CTRL + (0x200 * decoder), &tmp);
670 cx25821_i2c_write(&dev->i2c_bus[0],
671 VDEC_A_BRITE_CTRL + (0x200 * decoder),
673 mutex_unlock(&dev->lock);
677 int medusa_set_contrast(struct cx25821_dev *dev, int contrast, int decoder)
681 u32 val = 0, tmp = 0;
683 mutex_lock(&dev->lock);
685 if ((contrast > VIDEO_PROCAMP_MAX) || (contrast < VIDEO_PROCAMP_MIN)) {
686 mutex_unlock(&dev->lock);
691 mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, contrast,
692 UNSIGNED_BYTE_MIN, UNSIGNED_BYTE_MAX, &value);
694 cx25821_i2c_read(&dev->i2c_bus[0],
695 VDEC_A_CNTRST_CTRL + (0x200 * decoder), &tmp);
698 cx25821_i2c_write(&dev->i2c_bus[0],
699 VDEC_A_CNTRST_CTRL + (0x200 * decoder),
702 mutex_unlock(&dev->lock);
706 int medusa_set_hue(struct cx25821_dev *dev, int hue, int decoder)
710 u32 val = 0, tmp = 0;
712 mutex_lock(&dev->lock);
714 if ((hue > VIDEO_PROCAMP_MAX) || (hue < VIDEO_PROCAMP_MIN)) {
715 mutex_unlock(&dev->lock);
720 mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, hue, SIGNED_BYTE_MIN,
721 SIGNED_BYTE_MAX, &value);
723 value = convert_to_twos(value, 8);
725 cx25821_i2c_read(&dev->i2c_bus[0],
726 VDEC_A_HUE_CTRL + (0x200 * decoder), &tmp);
730 cx25821_i2c_write(&dev->i2c_bus[0],
731 VDEC_A_HUE_CTRL + (0x200 * decoder), val | value);
733 mutex_unlock(&dev->lock);
737 int medusa_set_saturation(struct cx25821_dev *dev, int saturation, int decoder)
741 u32 val = 0, tmp = 0;
743 mutex_lock(&dev->lock);
745 if ((saturation > VIDEO_PROCAMP_MAX)
746 || (saturation < VIDEO_PROCAMP_MIN)) {
747 mutex_unlock(&dev->lock);
752 mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, saturation,
753 UNSIGNED_BYTE_MIN, UNSIGNED_BYTE_MAX, &value);
756 cx25821_i2c_read(&dev->i2c_bus[0],
757 VDEC_A_USAT_CTRL + (0x200 * decoder), &tmp);
760 cx25821_i2c_write(&dev->i2c_bus[0],
761 VDEC_A_USAT_CTRL + (0x200 * decoder),
765 cx25821_i2c_read(&dev->i2c_bus[0],
766 VDEC_A_VSAT_CTRL + (0x200 * decoder), &tmp);
769 cx25821_i2c_write(&dev->i2c_bus[0],
770 VDEC_A_VSAT_CTRL + (0x200 * decoder),
773 mutex_unlock(&dev->lock);
777 /* Program the display sequence and monitor output. */
779 int medusa_video_init(struct cx25821_dev *dev)
781 u32 value = 0, tmp = 0;
785 mutex_lock(&dev->lock);
787 _num_decoders = dev->_max_num_decoders;
789 /* disable Auto source selection on all video decoders */
790 value = cx25821_i2c_read(&dev->i2c_bus[0], MON_A_CTRL, &tmp);
792 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], MON_A_CTRL, value);
797 /* Turn off Master source switch enable */
798 value = cx25821_i2c_read(&dev->i2c_bus[0], MON_A_CTRL, &tmp);
800 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], MON_A_CTRL, value);
805 mutex_unlock(&dev->lock);
807 for (i = 0; i < _num_decoders; i++)
808 medusa_set_decoderduration(dev, i, _display_field_cnt[i]);
810 mutex_lock(&dev->lock);
812 /* Select monitor as DENC A input, power up the DAC */
813 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_AB_CTRL, &tmp);
815 value |= 0x00090008; /* set en_active */
816 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], DENC_AB_CTRL, value);
821 /* enable input is VIP/656 */
822 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp);
823 value |= 0x00040100; /* enable VIP */
824 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value);
829 /* select AFE clock to output mode */
830 value = cx25821_i2c_read(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, &tmp);
833 cx25821_i2c_write(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL,
839 /* Turn on all of the data out and control output pins. */
840 value = cx25821_i2c_read(&dev->i2c_bus[0], PIN_OE_CTRL, &tmp);
842 if (_num_decoders == MAX_DECODERS) {
844 * Note: The octal board does not support control pins(bit16-19)
845 * These bits are ignored in the octal board.
847 * disable VDEC A-C port, default to Mobilygen Interface
851 /* disable VDEC A-C port, default to Mobilygen Interface */
856 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], PIN_OE_CTRL, value);
862 mutex_unlock(&dev->lock);
864 ret_val = medusa_set_videostandard(dev);
869 mutex_unlock(&dev->lock);