drivers/staging/cx25821/cx25821-video-upstream-ch2.c

   1 /*
   2  *  Driver for the Conexant CX25821 PCIe bridge
   3  *
   4  *  Copyright (C) 2009 Conexant Systems Inc.
   5  *  Authors  <hiep.huynh@conexant.com>, <shu.lin@conexant.com>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License as published by
   9  *  the Free Software Foundation; either version 2 of the License, or
  10  *  (at your option) any later version.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *
  16  *  GNU General Public License for more details.
  17  *
  18  *  You should have received a copy of the GNU General Public License
  19  *  along with this program; if not, write to the Free Software
  20  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  24
  25 #include "cx25821-video.h"
  26 #include "cx25821-video-upstream-ch2.h"
  27
  28 #include <linux/fs.h>
  29 #include <linux/errno.h>
  30 #include <linux/kernel.h>
  31 #include <linux/init.h>
  32 #include <linux/module.h>
  33 #include <linux/syscalls.h>
  34 #include <linux/file.h>
  35 #include <linux/fcntl.h>
  36 #include <linux/slab.h>
  37 #include <linux/uaccess.h>
  38
  39 MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards");
  40 MODULE_AUTHOR("Hiep Huynh <hiep.huynh@conexant.com>");
  41 MODULE_LICENSE("GPL");
  42
  43 static int _intr_msk =
  44         FLD_VID_SRC_RISC1 | FLD_VID_SRC_UF | FLD_VID_SRC_SYNC | FLD_VID_SRC_OPC_ERR;
  45
  46 static __le32 *cx25821_update_riscprogram_ch2(struct cx25821_dev *dev,
  47                                               __le32 *rp, unsigned int offset,
  48                                               unsigned int bpl, u32 sync_line,
  49                                               unsigned int lines,
  50                                               int fifo_enable, int field_type)
  51 {
  52         unsigned int line, i;
  53         int dist_betwn_starts = bpl * 2;
  54
  55         *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
  56
  57         if (USE_RISC_NOOP_VIDEO) {
  58                 for (i = 0; i < NUM_NO_OPS; i++)
  59                         *(rp++) = cpu_to_le32(RISC_NOOP);
  60         }
  61
  62         /* scan lines */
  63         for (line = 0; line < lines; line++) {
  64                 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
  65                 *(rp++) = cpu_to_le32(dev->_data_buf_phys_addr_ch2 + offset);
  66                 *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
  67
  68                 if ((lines <= NTSC_FIELD_HEIGHT)
  69                     || (line < (NTSC_FIELD_HEIGHT - 1))
  70                     || !(dev->_isNTSC_ch2)) {
  71                         offset += dist_betwn_starts;
  72                 }
  73         }
  74
  75         return rp;
  76 }
  77
  78 static __le32 *cx25821_risc_field_upstream_ch2(struct cx25821_dev *dev,
  79                                                __le32 *rp,
  80                                                dma_addr_t databuf_phys_addr,
  81                                                unsigned int offset,
  82                                                u32 sync_line, unsigned int bpl,
  83                                                unsigned int lines,
  84                                                int fifo_enable, int field_type)
  85 {
  86         unsigned int line, i;
  87         struct sram_channel *sram_ch =
  88            dev->channels[dev->_channel2_upstream_select].sram_channels;
  89         int dist_betwn_starts = bpl * 2;
  90
  91         /* sync instruction */
  92         if (sync_line != NO_SYNC_LINE)
  93                 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
  94
  95         if (USE_RISC_NOOP_VIDEO) {
  96                 for (i = 0; i < NUM_NO_OPS; i++)
  97                         *(rp++) = cpu_to_le32(RISC_NOOP);
  98         }
  99
 100         /* scan lines */
 101         for (line = 0; line < lines; line++) {
 102                 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
 103                 *(rp++) = cpu_to_le32(databuf_phys_addr + offset);
 104                 *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
 105
 106                 if ((lines <= NTSC_FIELD_HEIGHT)
 107                     || (line < (NTSC_FIELD_HEIGHT - 1))
 108                     || !(dev->_isNTSC_ch2)) {
 109                         offset += dist_betwn_starts;
 110                 }
 111
 112                /*
 113                  check if we need to enable the FIFO after the first 4 lines
 114                   For the upstream video channel, the risc engine will enable
 115                   the FIFO.
 116                */
 117                 if (fifo_enable && line == 3) {
 118                         *(rp++) = RISC_WRITECR;
 119                         *(rp++) = sram_ch->dma_ctl;
 120                         *(rp++) = FLD_VID_FIFO_EN;
 121                         *(rp++) = 0x00000001;
 122                 }
 123         }
 124
 125         return rp;
 126 }
 127
 128 int cx25821_risc_buffer_upstream_ch2(struct cx25821_dev *dev,
 129                                      struct pci_dev *pci,
 130                                      unsigned int top_offset, unsigned int bpl,
 131                                      unsigned int lines)
 132 {
 133         __le32 *rp;
 134         int fifo_enable = 0;
 135         int singlefield_lines = lines >> 1; /*get line count for single field */
 136         int odd_num_lines = singlefield_lines;
 137         int frame = 0;
 138         int frame_size = 0;
 139         int databuf_offset = 0;
 140         int risc_program_size = 0;
 141         int risc_flag = RISC_CNT_RESET;
 142         unsigned int bottom_offset = bpl;
 143         dma_addr_t risc_phys_jump_addr;
 144
 145         if (dev->_isNTSC_ch2) {
 146                 odd_num_lines = singlefield_lines + 1;
 147                 risc_program_size = FRAME1_VID_PROG_SIZE;
 148                 frame_size =
 149                     (bpl ==
 150                      Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
 151                     FRAME_SIZE_NTSC_Y422;
 152         } else {
 153                 risc_program_size = PAL_VID_PROG_SIZE;
 154                 frame_size =
 155                     (bpl ==
 156                      Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
 157         }
 158
 159         /* Virtual address of Risc buffer program */
 160         rp = dev->_dma_virt_addr_ch2;
 161
 162         for (frame = 0; frame < NUM_FRAMES; frame++) {
 163                 databuf_offset = frame_size * frame;
 164
 165                 if (UNSET != top_offset) {
 166                         fifo_enable = (frame == 0) ? FIFO_ENABLE : FIFO_DISABLE;
 167                         rp = cx25821_risc_field_upstream_ch2(dev, rp,
 168                                                              dev->
 169                                                              _data_buf_phys_addr_ch2
 170                                                              + databuf_offset,
 171                                                              top_offset, 0, bpl,
 172                                                              odd_num_lines,
 173                                                              fifo_enable,
 174                                                              ODD_FIELD);
 175                 }
 176
 177                 fifo_enable = FIFO_DISABLE;
 178
 179                /* Even field */
 180                 rp = cx25821_risc_field_upstream_ch2(dev, rp,
 181                                                      dev->
 182                                                      _data_buf_phys_addr_ch2 +
 183                                                      databuf_offset,
 184                                                      bottom_offset, 0x200, bpl,
 185                                                      singlefield_lines,
 186                                                      fifo_enable, EVEN_FIELD);
 187
 188                 if (frame == 0) {
 189                         risc_flag = RISC_CNT_RESET;
 190                         risc_phys_jump_addr =
 191                             dev->_dma_phys_start_addr_ch2 + risc_program_size;
 192                 } else {
 193                         risc_flag = RISC_CNT_INC;
 194                         risc_phys_jump_addr = dev->_dma_phys_start_addr_ch2;
 195                 }
 196
 197                /*
 198                   Loop to 2ndFrameRISC or to Start of
 199                   Risc program & generate IRQ
 200                */
 201                 *(rp++) = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | risc_flag);
 202                 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
 203                 *(rp++) = cpu_to_le32(0);
 204         }
 205
 206         return 0;
 207 }
 208
 209 void cx25821_stop_upstream_video_ch2(struct cx25821_dev *dev)
 210 {
 211         struct sram_channel *sram_ch =
 212            dev->channels[VID_UPSTREAM_SRAM_CHANNEL_J].sram_channels;
 213         u32 tmp = 0;
 214
 215         if (!dev->_is_running_ch2) {
 216                 pr_info("No video file is currently running so return!\n");
 217                 return;
 218         }
 219         /* Disable RISC interrupts */
 220         tmp = cx_read(sram_ch->int_msk);
 221         cx_write(sram_ch->int_msk, tmp & ~_intr_msk);
 222
 223         /* Turn OFF risc and fifo */
 224         tmp = cx_read(sram_ch->dma_ctl);
 225         cx_write(sram_ch->dma_ctl, tmp & ~(FLD_VID_FIFO_EN | FLD_VID_RISC_EN));
 226
 227         /* Clear data buffer memory */
 228         if (dev->_data_buf_virt_addr_ch2)
 229                 memset(dev->_data_buf_virt_addr_ch2, 0,
 230                        dev->_data_buf_size_ch2);
 231
 232         dev->_is_running_ch2 = 0;
 233         dev->_is_first_frame_ch2 = 0;
 234         dev->_frame_count_ch2 = 0;
 235         dev->_file_status_ch2 = END_OF_FILE;
 236
 237         if (dev->_irq_queues_ch2) {
 238                 kfree(dev->_irq_queues_ch2);
 239                 dev->_irq_queues_ch2 = NULL;
 240         }
 241
 242         if (dev->_filename_ch2 != NULL)
 243                 kfree(dev->_filename_ch2);
 244
 245         tmp = cx_read(VID_CH_MODE_SEL);
 246         cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
 247 }
 248
 249 void cx25821_free_mem_upstream_ch2(struct cx25821_dev *dev)
 250 {
 251         if (dev->_is_running_ch2)
 252                 cx25821_stop_upstream_video_ch2(dev);
 253
 254         if (dev->_dma_virt_addr_ch2) {
 255                 pci_free_consistent(dev->pci, dev->_risc_size_ch2,
 256                                     dev->_dma_virt_addr_ch2,
 257                                     dev->_dma_phys_addr_ch2);
 258                 dev->_dma_virt_addr_ch2 = NULL;
 259         }
 260
 261         if (dev->_data_buf_virt_addr_ch2) {
 262                 pci_free_consistent(dev->pci, dev->_data_buf_size_ch2,
 263                                     dev->_data_buf_virt_addr_ch2,
 264                                     dev->_data_buf_phys_addr_ch2);
 265                 dev->_data_buf_virt_addr_ch2 = NULL;
 266         }
 267 }
 268
 269 int cx25821_get_frame_ch2(struct cx25821_dev *dev, struct sram_channel *sram_ch)
 270 {
 271         struct file *myfile;
 272         int frame_index_temp = dev->_frame_index_ch2;
 273         int i = 0;
 274         int line_size =
 275             (dev->_pixel_format_ch2 ==
 276              PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
 277         int frame_size = 0;
 278         int frame_offset = 0;
 279         ssize_t vfs_read_retval = 0;
 280         char mybuf[line_size];
 281         loff_t file_offset;
 282         loff_t pos;
 283         mm_segment_t old_fs;
 284
 285         if (dev->_file_status_ch2 == END_OF_FILE)
 286                 return 0;
 287
 288         if (dev->_isNTSC_ch2) {
 289                 frame_size =
 290                     (line_size ==
 291                      Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
 292                     FRAME_SIZE_NTSC_Y422;
 293         } else {
 294                 frame_size =
 295                     (line_size ==
 296                      Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
 297         }
 298
 299         frame_offset = (frame_index_temp > 0) ? frame_size : 0;
 300         file_offset = dev->_frame_count_ch2 * frame_size;
 301
 302         myfile = filp_open(dev->_filename_ch2, O_RDONLY | O_LARGEFILE, 0);
 303         if (IS_ERR(myfile)) {
 304                 const int open_errno = -PTR_ERR(myfile);
 305                 pr_err("%s(): ERROR opening file(%s) with errno = %d!\n",
 306                        __func__, dev->_filename_ch2, open_errno);
 307                 return PTR_ERR(myfile);
 308         } else {
 309                 if (!(myfile->f_op)) {
 310                         pr_err("%s(): File has no file operations registered!\n",
 311                                __func__);
 312                         filp_close(myfile, NULL);
 313                         return -EIO;
 314                 }
 315
 316                 if (!myfile->f_op->read) {
 317                         pr_err("%s(): File has no READ operations registered!\n",
 318                                __func__);
 319                         filp_close(myfile, NULL);
 320                         return -EIO;
 321                 }
 322
 323                 pos = myfile->f_pos;
 324                 old_fs = get_fs();
 325                 set_fs(KERNEL_DS);
 326
 327                 for (i = 0; i < dev->_lines_count_ch2; i++) {
 328                         pos = file_offset;
 329
 330                         vfs_read_retval =
 331                             vfs_read(myfile, mybuf, line_size, &pos);
 332
 333                         if (vfs_read_retval > 0 && vfs_read_retval == line_size
 334                             && dev->_data_buf_virt_addr_ch2 != NULL) {
 335                                 memcpy((void *)(dev->_data_buf_virt_addr_ch2 +
 336                                                 frame_offset / 4), mybuf,
 337                                        vfs_read_retval);
 338                         }
 339
 340                         file_offset += vfs_read_retval;
 341                         frame_offset += vfs_read_retval;
 342
 343                         if (vfs_read_retval < line_size) {
 344                                 pr_info("Done: exit %s() since no more bytes to read from Video file\n",
 345                                         __func__);
 346                                 break;
 347                         }
 348                 }
 349
 350                 if (i > 0)
 351                         dev->_frame_count_ch2++;
 352
 353                 dev->_file_status_ch2 =
 354                     (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
 355
 356                 set_fs(old_fs);
 357                 filp_close(myfile, NULL);
 358         }
 359
 360         return 0;
 361 }
 362
 363 static void cx25821_vidups_handler_ch2(struct work_struct *work)
 364 {
 365         struct cx25821_dev *dev =
 366             container_of(work, struct cx25821_dev, _irq_work_entry_ch2);
 367
 368         if (!dev) {
 369                 pr_err("ERROR %s(): since container_of(work_struct) FAILED!\n",
 370                        __func__);
 371                 return;
 372         }
 373
 374         cx25821_get_frame_ch2(dev,
 375                              dev->channels[dev->
 376                                _channel2_upstream_select].sram_channels);
 377 }
 378
 379 int cx25821_openfile_ch2(struct cx25821_dev *dev, struct sram_channel *sram_ch)
 380 {
 381         struct file *myfile;
 382         int i = 0, j = 0;
 383         int line_size =
 384             (dev->_pixel_format_ch2 ==
 385              PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
 386         ssize_t vfs_read_retval = 0;
 387         char mybuf[line_size];
 388         loff_t pos;
 389         loff_t offset = (unsigned long)0;
 390         mm_segment_t old_fs;
 391
 392         myfile = filp_open(dev->_filename_ch2, O_RDONLY | O_LARGEFILE, 0);
 393
 394         if (IS_ERR(myfile)) {
 395                 const int open_errno = -PTR_ERR(myfile);
 396                 pr_err("%s(): ERROR opening file(%s) with errno = %d!\n",
 397                        __func__, dev->_filename_ch2, open_errno);
 398                 return PTR_ERR(myfile);
 399         } else {
 400                 if (!(myfile->f_op)) {
 401                         pr_err("%s(): File has no file operations registered!\n",
 402                                __func__);
 403                         filp_close(myfile, NULL);
 404                         return -EIO;
 405                 }
 406
 407                 if (!myfile->f_op->read) {
 408                         pr_err("%s(): File has no READ operations registered!  Returning\n",
 409                                __func__);
 410                         filp_close(myfile, NULL);
 411                         return -EIO;
 412                 }
 413
 414                 pos = myfile->f_pos;
 415                 old_fs = get_fs();
 416                 set_fs(KERNEL_DS);
 417
 418                 for (j = 0; j < NUM_FRAMES; j++) {
 419                         for (i = 0; i < dev->_lines_count_ch2; i++) {
 420                                 pos = offset;
 421
 422                                 vfs_read_retval =
 423                                     vfs_read(myfile, mybuf, line_size, &pos);
 424
 425                                 if (vfs_read_retval > 0
 426                                     && vfs_read_retval == line_size
 427                                     && dev->_data_buf_virt_addr_ch2 != NULL) {
 428                                         memcpy((void *)(dev->
 429                                                         _data_buf_virt_addr_ch2
 430                                                         + offset / 4), mybuf,
 431                                                vfs_read_retval);
 432                                 }
 433
 434                                 offset += vfs_read_retval;
 435
 436                                 if (vfs_read_retval < line_size) {
 437                                         pr_info("Done: exit %s() since no more bytes to read from Video file\n",
 438                                                 __func__);
 439                                         break;
 440                                 }
 441                         }
 442
 443                         if (i > 0)
 444                                 dev->_frame_count_ch2++;
 445
 446                         if (vfs_read_retval < line_size)
 447                                 break;
 448                 }
 449
 450                 dev->_file_status_ch2 =
 451                     (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
 452
 453                 set_fs(old_fs);
 454                 myfile->f_pos = 0;
 455                 filp_close(myfile, NULL);
 456         }
 457
 458         return 0;
 459 }
 460
 461 static int cx25821_upstream_buffer_prepare_ch2(struct cx25821_dev *dev,
 462                                                struct sram_channel *sram_ch,
 463                                                int bpl)
 464 {
 465         int ret = 0;
 466         dma_addr_t dma_addr;
 467         dma_addr_t data_dma_addr;
 468
 469         if (dev->_dma_virt_addr_ch2 != NULL) {
 470                 pci_free_consistent(dev->pci, dev->upstream_riscbuf_size_ch2,
 471                                     dev->_dma_virt_addr_ch2,
 472                                     dev->_dma_phys_addr_ch2);
 473         }
 474
 475         dev->_dma_virt_addr_ch2 =
 476             pci_alloc_consistent(dev->pci, dev->upstream_riscbuf_size_ch2,
 477                                  &dma_addr);
 478         dev->_dma_virt_start_addr_ch2 = dev->_dma_virt_addr_ch2;
 479         dev->_dma_phys_start_addr_ch2 = dma_addr;
 480         dev->_dma_phys_addr_ch2 = dma_addr;
 481         dev->_risc_size_ch2 = dev->upstream_riscbuf_size_ch2;
 482
 483         if (!dev->_dma_virt_addr_ch2) {
 484                 pr_err("FAILED to allocate memory for Risc buffer! Returning\n");
 485                 return -ENOMEM;
 486         }
 487
 488         /* Iniitize at this address until n bytes to 0 */
 489         memset(dev->_dma_virt_addr_ch2, 0, dev->_risc_size_ch2);
 490
 491         if (dev->_data_buf_virt_addr_ch2 != NULL) {
 492                 pci_free_consistent(dev->pci, dev->upstream_databuf_size_ch2,
 493                                     dev->_data_buf_virt_addr_ch2,
 494                                     dev->_data_buf_phys_addr_ch2);
 495         }
 496         /* For Video Data buffer allocation */
 497         dev->_data_buf_virt_addr_ch2 =
 498             pci_alloc_consistent(dev->pci, dev->upstream_databuf_size_ch2,
 499                                  &data_dma_addr);
 500         dev->_data_buf_phys_addr_ch2 = data_dma_addr;
 501         dev->_data_buf_size_ch2 = dev->upstream_databuf_size_ch2;
 502
 503         if (!dev->_data_buf_virt_addr_ch2) {
 504                 pr_err("FAILED to allocate memory for data buffer! Returning\n");
 505                 return -ENOMEM;
 506         }
 507
 508         /* Initialize at this address until n bytes to 0 */
 509         memset(dev->_data_buf_virt_addr_ch2, 0, dev->_data_buf_size_ch2);
 510
 511         ret = cx25821_openfile_ch2(dev, sram_ch);
 512         if (ret < 0)
 513                 return ret;
 514
 515         /* Creating RISC programs */
 516         ret =
 517             cx25821_risc_buffer_upstream_ch2(dev, dev->pci, 0, bpl,
 518                                              dev->_lines_count_ch2);
 519         if (ret < 0) {
 520                 pr_info("Failed creating Video Upstream Risc programs!\n");
 521                 goto error;
 522         }
 523
 524         return 0;
 525
 526         error:
 527         return ret;
 528 }
 529
 530 int cx25821_video_upstream_irq_ch2(struct cx25821_dev *dev, int chan_num,
 531                                    u32 status)
 532 {
 533         u32 int_msk_tmp;
 534         struct sram_channel *channel = dev->channels[chan_num].sram_channels;
 535         int singlefield_lines = NTSC_FIELD_HEIGHT;
 536         int line_size_in_bytes = Y422_LINE_SZ;
 537         int odd_risc_prog_size = 0;
 538         dma_addr_t risc_phys_jump_addr;
 539         __le32 *rp;
 540
 541         if (status & FLD_VID_SRC_RISC1) {
 542                 /* We should only process one program per call */
 543                 u32 prog_cnt = cx_read(channel->gpcnt);
 544
 545                 /*
 546                  *  Since we've identified our IRQ, clear our bits from the
 547                  *  interrupt mask and interrupt status registers
 548                  */
 549                 int_msk_tmp = cx_read(channel->int_msk);
 550                 cx_write(channel->int_msk, int_msk_tmp & ~_intr_msk);
 551                 cx_write(channel->int_stat, _intr_msk);
 552
 553                 spin_lock(&dev->slock);
 554
 555                 dev->_frame_index_ch2 = prog_cnt;
 556
 557                 queue_work(dev->_irq_queues_ch2, &dev->_irq_work_entry_ch2);
 558
 559                 if (dev->_is_first_frame_ch2) {
 560                         dev->_is_first_frame_ch2 = 0;
 561
 562                         if (dev->_isNTSC_ch2) {
 563                                 singlefield_lines += 1;
 564                                 odd_risc_prog_size = ODD_FLD_NTSC_PROG_SIZE;
 565                         } else {
 566                                 singlefield_lines = PAL_FIELD_HEIGHT;
 567                                 odd_risc_prog_size = ODD_FLD_PAL_PROG_SIZE;
 568                         }
 569
 570                         if (dev->_dma_virt_start_addr_ch2 != NULL) {
 571                                 line_size_in_bytes =
 572                                     (dev->_pixel_format_ch2 ==
 573                                      PIXEL_FRMT_411) ? Y411_LINE_SZ :
 574                                     Y422_LINE_SZ;
 575                                 risc_phys_jump_addr =
 576                                     dev->_dma_phys_start_addr_ch2 +
 577                                     odd_risc_prog_size;
 578
 579                                 rp = cx25821_update_riscprogram_ch2(dev,
 580                                                                     dev->
 581                                                                     _dma_virt_start_addr_ch2,
 582                                                                     TOP_OFFSET,
 583                                                                     line_size_in_bytes,
 584                                                                     0x0,
 585                                                                     singlefield_lines,
 586                                                                     FIFO_DISABLE,
 587                                                                     ODD_FIELD);
 588
 589                                /* Jump to Even Risc program of 1st Frame */
 590                                 *(rp++) = cpu_to_le32(RISC_JUMP);
 591                                 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
 592                                 *(rp++) = cpu_to_le32(0);
 593                         }
 594                 }
 595
 596                 spin_unlock(&dev->slock);
 597         }
 598
 599         if (dev->_file_status_ch2 == END_OF_FILE) {
 600                 pr_info("EOF Channel 2 Framecount = %d\n",
 601                         dev->_frame_count_ch2);
 602                 return -1;
 603         }
 604         /* ElSE, set the interrupt mask register, re-enable irq. */
 605         int_msk_tmp = cx_read(channel->int_msk);
 606         cx_write(channel->int_msk, int_msk_tmp |= _intr_msk);
 607
 608         return 0;
 609 }
 610
 611 static irqreturn_t cx25821_upstream_irq_ch2(int irq, void *dev_id)
 612 {
 613         struct cx25821_dev *dev = dev_id;
 614         u32 msk_stat, vid_status;
 615         int handled = 0;
 616         int channel_num = 0;
 617         struct sram_channel *sram_ch;
 618
 619         if (!dev)
 620                 return -1;
 621
 622         channel_num = VID_UPSTREAM_SRAM_CHANNEL_J;
 623         sram_ch = dev->channels[channel_num].sram_channels;
 624
 625         msk_stat = cx_read(sram_ch->int_mstat);
 626         vid_status = cx_read(sram_ch->int_stat);
 627
 628         /* Only deal with our interrupt */
 629         if (vid_status) {
 630                 handled =
 631                     cx25821_video_upstream_irq_ch2(dev, channel_num,
 632                                                    vid_status);
 633         }
 634
 635         if (handled < 0)
 636                 cx25821_stop_upstream_video_ch2(dev);
 637         else
 638                 handled += handled;
 639
 640         return IRQ_RETVAL(handled);
 641 }
 642
 643 static void cx25821_set_pixelengine_ch2(struct cx25821_dev *dev,
 644                                         struct sram_channel *ch, int pix_format)
 645 {
 646         int width = WIDTH_D1;
 647         int height = dev->_lines_count_ch2;
 648         int num_lines, odd_num_lines;
 649         u32 value;
 650         int vip_mode = PIXEL_ENGINE_VIP1;
 651
 652         value = ((pix_format & 0x3) << 12) | (vip_mode & 0x7);
 653         value &= 0xFFFFFFEF;
 654         value |= dev->_isNTSC_ch2 ? 0 : 0x10;
 655         cx_write(ch->vid_fmt_ctl, value);
 656
 657         /*
 658          *  set number of active pixels in each line. Default is 720
 659          * pixels in both NTSC and PAL format
 660          */
 661         cx_write(ch->vid_active_ctl1, width);
 662
 663         num_lines = (height / 2) & 0x3FF;
 664         odd_num_lines = num_lines;
 665
 666         if (dev->_isNTSC_ch2)
 667                 odd_num_lines += 1;
 668
 669         value = (num_lines << 16) | odd_num_lines;
 670
 671         /* set number of active lines in field 0 (top) and field 1 (bottom) */
 672         cx_write(ch->vid_active_ctl2, value);
 673
 674         cx_write(ch->vid_cdt_size, VID_CDT_SIZE >> 3);
 675 }
 676
 677 int cx25821_start_video_dma_upstream_ch2(struct cx25821_dev *dev,
 678                                          struct sram_channel *sram_ch)
 679 {
 680         u32 tmp = 0;
 681         int err = 0;
 682
 683         /*
 684          *  656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface
 685          * for channel A-C
 686          */
 687         tmp = cx_read(VID_CH_MODE_SEL);
 688         cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
 689
 690         /*
 691          *  Set the physical start address of the RISC program in the initial
 692          *  program counter(IPC) member of the cmds.
 693          */
 694         cx_write(sram_ch->cmds_start + 0, dev->_dma_phys_addr_ch2);
 695         cx_write(sram_ch->cmds_start + 4, 0); /* Risc IPC High 64 bits 63-32 */
 696
 697         /* reset counter */
 698         cx_write(sram_ch->gpcnt_ctl, 3);
 699
 700         /* Clear our bits from the interrupt status register. */
 701         cx_write(sram_ch->int_stat, _intr_msk);
 702
 703         /* Set the interrupt mask register, enable irq. */
 704         cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit));
 705         tmp = cx_read(sram_ch->int_msk);
 706         cx_write(sram_ch->int_msk, tmp |= _intr_msk);
 707
 708         err =
 709             request_irq(dev->pci->irq, cx25821_upstream_irq_ch2,
 710                         IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
 711         if (err < 0) {
 712                 pr_err("%s: can't get upstream IRQ %d\n",
 713                        dev->name, dev->pci->irq);
 714                 goto fail_irq;
 715         }
 716         /* Start the DMA  engine */
 717         tmp = cx_read(sram_ch->dma_ctl);
 718         cx_set(sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN);
 719
 720         dev->_is_running_ch2 = 1;
 721         dev->_is_first_frame_ch2 = 1;
 722
 723         return 0;
 724
 725         fail_irq:
 726         cx25821_dev_unregister(dev);
 727         return err;
 728 }
 729
 730 int cx25821_vidupstream_init_ch2(struct cx25821_dev *dev, int channel_select,
 731                                  int pixel_format)
 732 {
 733         struct sram_channel *sram_ch;
 734         u32 tmp;
 735         int retval = 0;
 736         int err = 0;
 737         int data_frame_size = 0;
 738         int risc_buffer_size = 0;
 739         int str_length = 0;
 740
 741         if (dev->_is_running_ch2) {
 742                 pr_info("Video Channel is still running so return!\n");
 743                 return 0;
 744         }
 745
 746         dev->_channel2_upstream_select = channel_select;
 747         sram_ch = dev->channels[channel_select].sram_channels;
 748
 749         INIT_WORK(&dev->_irq_work_entry_ch2, cx25821_vidups_handler_ch2);
 750         dev->_irq_queues_ch2 =
 751             create_singlethread_workqueue("cx25821_workqueue2");
 752
 753         if (!dev->_irq_queues_ch2) {
 754                 pr_err("create_singlethread_workqueue() for Video FAILED!\n");
 755                 return -ENOMEM;
 756         }
 757         /*
 758          * 656/VIP SRC Upstream Channel I & J and 7 -
 759          * Host Bus Interface for channel A-C
 760          */
 761         tmp = cx_read(VID_CH_MODE_SEL);
 762         cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
 763
 764         dev->_is_running_ch2 = 0;
 765         dev->_frame_count_ch2 = 0;
 766         dev->_file_status_ch2 = RESET_STATUS;
 767         dev->_lines_count_ch2 = dev->_isNTSC_ch2 ? 480 : 576;
 768         dev->_pixel_format_ch2 = pixel_format;
 769         dev->_line_size_ch2 =
 770             (dev->_pixel_format_ch2 ==
 771              PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
 772         data_frame_size = dev->_isNTSC_ch2 ? NTSC_DATA_BUF_SZ : PAL_DATA_BUF_SZ;
 773         risc_buffer_size =
 774             dev->_isNTSC_ch2 ? NTSC_RISC_BUF_SIZE : PAL_RISC_BUF_SIZE;
 775
 776         if (dev->input_filename_ch2) {
 777                 str_length = strlen(dev->input_filename_ch2);
 778                 dev->_filename_ch2 = kmalloc(str_length + 1, GFP_KERNEL);
 779
 780                 if (!dev->_filename_ch2)
 781                         goto error;
 782
 783                 memcpy(dev->_filename_ch2, dev->input_filename_ch2,
 784                        str_length + 1);
 785         } else {
 786                 str_length = strlen(dev->_defaultname_ch2);
 787                 dev->_filename_ch2 = kmalloc(str_length + 1, GFP_KERNEL);
 788
 789                 if (!dev->_filename_ch2)
 790                         goto error;
 791
 792                 memcpy(dev->_filename_ch2, dev->_defaultname_ch2,
 793                        str_length + 1);
 794         }
 795
 796         /* Default if filename is empty string */
 797         if (strcmp(dev->input_filename_ch2, "") == 0) {
 798                 if (dev->_isNTSC_ch2) {
 799                         dev->_filename_ch2 =
 800                             (dev->_pixel_format_ch2 ==
 801                              PIXEL_FRMT_411) ? "/root/vid411.yuv" :
 802                             "/root/vidtest.yuv";
 803                 } else {
 804                         dev->_filename_ch2 =
 805                             (dev->_pixel_format_ch2 ==
 806                              PIXEL_FRMT_411) ? "/root/pal411.yuv" :
 807                             "/root/pal422.yuv";
 808                 }
 809         }
 810
 811         retval =
 812             cx25821_sram_channel_setup_upstream(dev, sram_ch,
 813                                                 dev->_line_size_ch2, 0);
 814
 815         /* setup fifo + format */
 816         cx25821_set_pixelengine_ch2(dev, sram_ch, dev->_pixel_format_ch2);
 817
 818         dev->upstream_riscbuf_size_ch2 = risc_buffer_size * 2;
 819         dev->upstream_databuf_size_ch2 = data_frame_size * 2;
 820
 821         /* Allocating buffers and prepare RISC program */
 822         retval =
 823             cx25821_upstream_buffer_prepare_ch2(dev, sram_ch,
 824                                                 dev->_line_size_ch2);
 825         if (retval < 0) {
 826                 pr_err("%s: Failed to set up Video upstream buffers!\n",
 827                        dev->name);
 828                 goto error;
 829         }
 830
 831         cx25821_start_video_dma_upstream_ch2(dev, sram_ch);
 832
 833         return 0;
 834
 835         error:
 836         cx25821_dev_unregister(dev);
 837
 838         return err;
 839 }