2 * Driver for the Conexant CX25821 PCIe bridge
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <hiep.huynh@conexant.com>, <shu.lin@conexant.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25 #include "cx25821-video.h"
26 #include "cx25821-video-upstream-ch2.h"
29 #include <linux/errno.h>
30 #include <linux/kernel.h>
31 #include <linux/init.h>
32 #include <linux/module.h>
33 #include <linux/syscalls.h>
34 #include <linux/file.h>
35 #include <linux/fcntl.h>
36 #include <linux/slab.h>
37 #include <linux/uaccess.h>
39 MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards");
40 MODULE_AUTHOR("Hiep Huynh <hiep.huynh@conexant.com>");
41 MODULE_LICENSE("GPL");
43 static int _intr_msk =
44 FLD_VID_SRC_RISC1 | FLD_VID_SRC_UF | FLD_VID_SRC_SYNC | FLD_VID_SRC_OPC_ERR;
46 static __le32 *cx25821_update_riscprogram_ch2(struct cx25821_dev *dev,
47 __le32 *rp, unsigned int offset,
48 unsigned int bpl, u32 sync_line,
50 int fifo_enable, int field_type)
53 int dist_betwn_starts = bpl * 2;
55 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
57 if (USE_RISC_NOOP_VIDEO) {
58 for (i = 0; i < NUM_NO_OPS; i++)
59 *(rp++) = cpu_to_le32(RISC_NOOP);
63 for (line = 0; line < lines; line++) {
64 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
65 *(rp++) = cpu_to_le32(dev->_data_buf_phys_addr_ch2 + offset);
66 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
68 if ((lines <= NTSC_FIELD_HEIGHT)
69 || (line < (NTSC_FIELD_HEIGHT - 1))
70 || !(dev->_isNTSC_ch2)) {
71 offset += dist_betwn_starts;
78 static __le32 *cx25821_risc_field_upstream_ch2(struct cx25821_dev *dev,
80 dma_addr_t databuf_phys_addr,
82 u32 sync_line, unsigned int bpl,
84 int fifo_enable, int field_type)
87 struct sram_channel *sram_ch =
88 dev->channels[dev->_channel2_upstream_select].sram_channels;
89 int dist_betwn_starts = bpl * 2;
91 /* sync instruction */
92 if (sync_line != NO_SYNC_LINE)
93 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
95 if (USE_RISC_NOOP_VIDEO) {
96 for (i = 0; i < NUM_NO_OPS; i++)
97 *(rp++) = cpu_to_le32(RISC_NOOP);
101 for (line = 0; line < lines; line++) {
102 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
103 *(rp++) = cpu_to_le32(databuf_phys_addr + offset);
104 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
106 if ((lines <= NTSC_FIELD_HEIGHT)
107 || (line < (NTSC_FIELD_HEIGHT - 1))
108 || !(dev->_isNTSC_ch2)) {
109 offset += dist_betwn_starts;
113 check if we need to enable the FIFO after the first 4 lines
114 For the upstream video channel, the risc engine will enable
117 if (fifo_enable && line == 3) {
118 *(rp++) = RISC_WRITECR;
119 *(rp++) = sram_ch->dma_ctl;
120 *(rp++) = FLD_VID_FIFO_EN;
121 *(rp++) = 0x00000001;
128 int cx25821_risc_buffer_upstream_ch2(struct cx25821_dev *dev,
130 unsigned int top_offset, unsigned int bpl,
135 int singlefield_lines = lines >> 1; /*get line count for single field */
136 int odd_num_lines = singlefield_lines;
139 int databuf_offset = 0;
140 int risc_program_size = 0;
141 int risc_flag = RISC_CNT_RESET;
142 unsigned int bottom_offset = bpl;
143 dma_addr_t risc_phys_jump_addr;
145 if (dev->_isNTSC_ch2) {
146 odd_num_lines = singlefield_lines + 1;
147 risc_program_size = FRAME1_VID_PROG_SIZE;
150 Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
151 FRAME_SIZE_NTSC_Y422;
153 risc_program_size = PAL_VID_PROG_SIZE;
156 Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
159 /* Virtual address of Risc buffer program */
160 rp = dev->_dma_virt_addr_ch2;
162 for (frame = 0; frame < NUM_FRAMES; frame++) {
163 databuf_offset = frame_size * frame;
165 if (UNSET != top_offset) {
166 fifo_enable = (frame == 0) ? FIFO_ENABLE : FIFO_DISABLE;
167 rp = cx25821_risc_field_upstream_ch2(dev, rp,
169 _data_buf_phys_addr_ch2
177 fifo_enable = FIFO_DISABLE;
180 rp = cx25821_risc_field_upstream_ch2(dev, rp,
182 _data_buf_phys_addr_ch2 +
184 bottom_offset, 0x200, bpl,
186 fifo_enable, EVEN_FIELD);
189 risc_flag = RISC_CNT_RESET;
190 risc_phys_jump_addr =
191 dev->_dma_phys_start_addr_ch2 + risc_program_size;
193 risc_flag = RISC_CNT_INC;
194 risc_phys_jump_addr = dev->_dma_phys_start_addr_ch2;
198 Loop to 2ndFrameRISC or to Start of
199 Risc program & generate IRQ
201 *(rp++) = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | risc_flag);
202 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
203 *(rp++) = cpu_to_le32(0);
209 void cx25821_stop_upstream_video_ch2(struct cx25821_dev *dev)
211 struct sram_channel *sram_ch =
212 dev->channels[VID_UPSTREAM_SRAM_CHANNEL_J].sram_channels;
215 if (!dev->_is_running_ch2) {
216 pr_info("No video file is currently running so return!\n");
219 /* Disable RISC interrupts */
220 tmp = cx_read(sram_ch->int_msk);
221 cx_write(sram_ch->int_msk, tmp & ~_intr_msk);
223 /* Turn OFF risc and fifo */
224 tmp = cx_read(sram_ch->dma_ctl);
225 cx_write(sram_ch->dma_ctl, tmp & ~(FLD_VID_FIFO_EN | FLD_VID_RISC_EN));
227 /* Clear data buffer memory */
228 if (dev->_data_buf_virt_addr_ch2)
229 memset(dev->_data_buf_virt_addr_ch2, 0,
230 dev->_data_buf_size_ch2);
232 dev->_is_running_ch2 = 0;
233 dev->_is_first_frame_ch2 = 0;
234 dev->_frame_count_ch2 = 0;
235 dev->_file_status_ch2 = END_OF_FILE;
237 if (dev->_irq_queues_ch2) {
238 kfree(dev->_irq_queues_ch2);
239 dev->_irq_queues_ch2 = NULL;
242 if (dev->_filename_ch2 != NULL)
243 kfree(dev->_filename_ch2);
245 tmp = cx_read(VID_CH_MODE_SEL);
246 cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
249 void cx25821_free_mem_upstream_ch2(struct cx25821_dev *dev)
251 if (dev->_is_running_ch2)
252 cx25821_stop_upstream_video_ch2(dev);
254 if (dev->_dma_virt_addr_ch2) {
255 pci_free_consistent(dev->pci, dev->_risc_size_ch2,
256 dev->_dma_virt_addr_ch2,
257 dev->_dma_phys_addr_ch2);
258 dev->_dma_virt_addr_ch2 = NULL;
261 if (dev->_data_buf_virt_addr_ch2) {
262 pci_free_consistent(dev->pci, dev->_data_buf_size_ch2,
263 dev->_data_buf_virt_addr_ch2,
264 dev->_data_buf_phys_addr_ch2);
265 dev->_data_buf_virt_addr_ch2 = NULL;
269 int cx25821_get_frame_ch2(struct cx25821_dev *dev, struct sram_channel *sram_ch)
272 int frame_index_temp = dev->_frame_index_ch2;
275 (dev->_pixel_format_ch2 ==
276 PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
278 int frame_offset = 0;
279 ssize_t vfs_read_retval = 0;
280 char mybuf[line_size];
285 if (dev->_file_status_ch2 == END_OF_FILE)
288 if (dev->_isNTSC_ch2) {
291 Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
292 FRAME_SIZE_NTSC_Y422;
296 Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
299 frame_offset = (frame_index_temp > 0) ? frame_size : 0;
300 file_offset = dev->_frame_count_ch2 * frame_size;
302 myfile = filp_open(dev->_filename_ch2, O_RDONLY | O_LARGEFILE, 0);
303 if (IS_ERR(myfile)) {
304 const int open_errno = -PTR_ERR(myfile);
305 pr_err("%s(): ERROR opening file(%s) with errno = %d!\n",
306 __func__, dev->_filename_ch2, open_errno);
307 return PTR_ERR(myfile);
309 if (!(myfile->f_op)) {
310 pr_err("%s(): File has no file operations registered!\n",
312 filp_close(myfile, NULL);
316 if (!myfile->f_op->read) {
317 pr_err("%s(): File has no READ operations registered!\n",
319 filp_close(myfile, NULL);
327 for (i = 0; i < dev->_lines_count_ch2; i++) {
331 vfs_read(myfile, mybuf, line_size, &pos);
333 if (vfs_read_retval > 0 && vfs_read_retval == line_size
334 && dev->_data_buf_virt_addr_ch2 != NULL) {
335 memcpy((void *)(dev->_data_buf_virt_addr_ch2 +
336 frame_offset / 4), mybuf,
340 file_offset += vfs_read_retval;
341 frame_offset += vfs_read_retval;
343 if (vfs_read_retval < line_size) {
344 pr_info("Done: exit %s() since no more bytes to read from Video file\n",
351 dev->_frame_count_ch2++;
353 dev->_file_status_ch2 =
354 (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
357 filp_close(myfile, NULL);
363 static void cx25821_vidups_handler_ch2(struct work_struct *work)
365 struct cx25821_dev *dev =
366 container_of(work, struct cx25821_dev, _irq_work_entry_ch2);
369 pr_err("ERROR %s(): since container_of(work_struct) FAILED!\n",
374 cx25821_get_frame_ch2(dev,
376 _channel2_upstream_select].sram_channels);
379 int cx25821_openfile_ch2(struct cx25821_dev *dev, struct sram_channel *sram_ch)
384 (dev->_pixel_format_ch2 ==
385 PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
386 ssize_t vfs_read_retval = 0;
387 char mybuf[line_size];
389 loff_t offset = (unsigned long)0;
392 myfile = filp_open(dev->_filename_ch2, O_RDONLY | O_LARGEFILE, 0);
394 if (IS_ERR(myfile)) {
395 const int open_errno = -PTR_ERR(myfile);
396 pr_err("%s(): ERROR opening file(%s) with errno = %d!\n",
397 __func__, dev->_filename_ch2, open_errno);
398 return PTR_ERR(myfile);
400 if (!(myfile->f_op)) {
401 pr_err("%s(): File has no file operations registered!\n",
403 filp_close(myfile, NULL);
407 if (!myfile->f_op->read) {
408 pr_err("%s(): File has no READ operations registered! Returning\n",
410 filp_close(myfile, NULL);
418 for (j = 0; j < NUM_FRAMES; j++) {
419 for (i = 0; i < dev->_lines_count_ch2; i++) {
423 vfs_read(myfile, mybuf, line_size, &pos);
425 if (vfs_read_retval > 0
426 && vfs_read_retval == line_size
427 && dev->_data_buf_virt_addr_ch2 != NULL) {
428 memcpy((void *)(dev->
429 _data_buf_virt_addr_ch2
430 + offset / 4), mybuf,
434 offset += vfs_read_retval;
436 if (vfs_read_retval < line_size) {
437 pr_info("Done: exit %s() since no more bytes to read from Video file\n",
444 dev->_frame_count_ch2++;
446 if (vfs_read_retval < line_size)
450 dev->_file_status_ch2 =
451 (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
455 filp_close(myfile, NULL);
461 static int cx25821_upstream_buffer_prepare_ch2(struct cx25821_dev *dev,
462 struct sram_channel *sram_ch,
467 dma_addr_t data_dma_addr;
469 if (dev->_dma_virt_addr_ch2 != NULL) {
470 pci_free_consistent(dev->pci, dev->upstream_riscbuf_size_ch2,
471 dev->_dma_virt_addr_ch2,
472 dev->_dma_phys_addr_ch2);
475 dev->_dma_virt_addr_ch2 =
476 pci_alloc_consistent(dev->pci, dev->upstream_riscbuf_size_ch2,
478 dev->_dma_virt_start_addr_ch2 = dev->_dma_virt_addr_ch2;
479 dev->_dma_phys_start_addr_ch2 = dma_addr;
480 dev->_dma_phys_addr_ch2 = dma_addr;
481 dev->_risc_size_ch2 = dev->upstream_riscbuf_size_ch2;
483 if (!dev->_dma_virt_addr_ch2) {
484 pr_err("FAILED to allocate memory for Risc buffer! Returning\n");
488 /* Iniitize at this address until n bytes to 0 */
489 memset(dev->_dma_virt_addr_ch2, 0, dev->_risc_size_ch2);
491 if (dev->_data_buf_virt_addr_ch2 != NULL) {
492 pci_free_consistent(dev->pci, dev->upstream_databuf_size_ch2,
493 dev->_data_buf_virt_addr_ch2,
494 dev->_data_buf_phys_addr_ch2);
496 /* For Video Data buffer allocation */
497 dev->_data_buf_virt_addr_ch2 =
498 pci_alloc_consistent(dev->pci, dev->upstream_databuf_size_ch2,
500 dev->_data_buf_phys_addr_ch2 = data_dma_addr;
501 dev->_data_buf_size_ch2 = dev->upstream_databuf_size_ch2;
503 if (!dev->_data_buf_virt_addr_ch2) {
504 pr_err("FAILED to allocate memory for data buffer! Returning\n");
508 /* Initialize at this address until n bytes to 0 */
509 memset(dev->_data_buf_virt_addr_ch2, 0, dev->_data_buf_size_ch2);
511 ret = cx25821_openfile_ch2(dev, sram_ch);
515 /* Creating RISC programs */
517 cx25821_risc_buffer_upstream_ch2(dev, dev->pci, 0, bpl,
518 dev->_lines_count_ch2);
520 pr_info("Failed creating Video Upstream Risc programs!\n");
530 int cx25821_video_upstream_irq_ch2(struct cx25821_dev *dev, int chan_num,
534 struct sram_channel *channel = dev->channels[chan_num].sram_channels;
535 int singlefield_lines = NTSC_FIELD_HEIGHT;
536 int line_size_in_bytes = Y422_LINE_SZ;
537 int odd_risc_prog_size = 0;
538 dma_addr_t risc_phys_jump_addr;
541 if (status & FLD_VID_SRC_RISC1) {
542 /* We should only process one program per call */
543 u32 prog_cnt = cx_read(channel->gpcnt);
546 * Since we've identified our IRQ, clear our bits from the
547 * interrupt mask and interrupt status registers
549 int_msk_tmp = cx_read(channel->int_msk);
550 cx_write(channel->int_msk, int_msk_tmp & ~_intr_msk);
551 cx_write(channel->int_stat, _intr_msk);
553 spin_lock(&dev->slock);
555 dev->_frame_index_ch2 = prog_cnt;
557 queue_work(dev->_irq_queues_ch2, &dev->_irq_work_entry_ch2);
559 if (dev->_is_first_frame_ch2) {
560 dev->_is_first_frame_ch2 = 0;
562 if (dev->_isNTSC_ch2) {
563 singlefield_lines += 1;
564 odd_risc_prog_size = ODD_FLD_NTSC_PROG_SIZE;
566 singlefield_lines = PAL_FIELD_HEIGHT;
567 odd_risc_prog_size = ODD_FLD_PAL_PROG_SIZE;
570 if (dev->_dma_virt_start_addr_ch2 != NULL) {
572 (dev->_pixel_format_ch2 ==
573 PIXEL_FRMT_411) ? Y411_LINE_SZ :
575 risc_phys_jump_addr =
576 dev->_dma_phys_start_addr_ch2 +
579 rp = cx25821_update_riscprogram_ch2(dev,
581 _dma_virt_start_addr_ch2,
589 /* Jump to Even Risc program of 1st Frame */
590 *(rp++) = cpu_to_le32(RISC_JUMP);
591 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
592 *(rp++) = cpu_to_le32(0);
596 spin_unlock(&dev->slock);
599 if (dev->_file_status_ch2 == END_OF_FILE) {
600 pr_info("EOF Channel 2 Framecount = %d\n",
601 dev->_frame_count_ch2);
604 /* ElSE, set the interrupt mask register, re-enable irq. */
605 int_msk_tmp = cx_read(channel->int_msk);
606 cx_write(channel->int_msk, int_msk_tmp |= _intr_msk);
611 static irqreturn_t cx25821_upstream_irq_ch2(int irq, void *dev_id)
613 struct cx25821_dev *dev = dev_id;
614 u32 msk_stat, vid_status;
617 struct sram_channel *sram_ch;
622 channel_num = VID_UPSTREAM_SRAM_CHANNEL_J;
623 sram_ch = dev->channels[channel_num].sram_channels;
625 msk_stat = cx_read(sram_ch->int_mstat);
626 vid_status = cx_read(sram_ch->int_stat);
628 /* Only deal with our interrupt */
631 cx25821_video_upstream_irq_ch2(dev, channel_num,
636 cx25821_stop_upstream_video_ch2(dev);
640 return IRQ_RETVAL(handled);
643 static void cx25821_set_pixelengine_ch2(struct cx25821_dev *dev,
644 struct sram_channel *ch, int pix_format)
646 int width = WIDTH_D1;
647 int height = dev->_lines_count_ch2;
648 int num_lines, odd_num_lines;
650 int vip_mode = PIXEL_ENGINE_VIP1;
652 value = ((pix_format & 0x3) << 12) | (vip_mode & 0x7);
654 value |= dev->_isNTSC_ch2 ? 0 : 0x10;
655 cx_write(ch->vid_fmt_ctl, value);
658 * set number of active pixels in each line. Default is 720
659 * pixels in both NTSC and PAL format
661 cx_write(ch->vid_active_ctl1, width);
663 num_lines = (height / 2) & 0x3FF;
664 odd_num_lines = num_lines;
666 if (dev->_isNTSC_ch2)
669 value = (num_lines << 16) | odd_num_lines;
671 /* set number of active lines in field 0 (top) and field 1 (bottom) */
672 cx_write(ch->vid_active_ctl2, value);
674 cx_write(ch->vid_cdt_size, VID_CDT_SIZE >> 3);
677 int cx25821_start_video_dma_upstream_ch2(struct cx25821_dev *dev,
678 struct sram_channel *sram_ch)
684 * 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface
687 tmp = cx_read(VID_CH_MODE_SEL);
688 cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
691 * Set the physical start address of the RISC program in the initial
692 * program counter(IPC) member of the cmds.
694 cx_write(sram_ch->cmds_start + 0, dev->_dma_phys_addr_ch2);
695 cx_write(sram_ch->cmds_start + 4, 0); /* Risc IPC High 64 bits 63-32 */
698 cx_write(sram_ch->gpcnt_ctl, 3);
700 /* Clear our bits from the interrupt status register. */
701 cx_write(sram_ch->int_stat, _intr_msk);
703 /* Set the interrupt mask register, enable irq. */
704 cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit));
705 tmp = cx_read(sram_ch->int_msk);
706 cx_write(sram_ch->int_msk, tmp |= _intr_msk);
709 request_irq(dev->pci->irq, cx25821_upstream_irq_ch2,
710 IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
712 pr_err("%s: can't get upstream IRQ %d\n",
713 dev->name, dev->pci->irq);
716 /* Start the DMA engine */
717 tmp = cx_read(sram_ch->dma_ctl);
718 cx_set(sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN);
720 dev->_is_running_ch2 = 1;
721 dev->_is_first_frame_ch2 = 1;
726 cx25821_dev_unregister(dev);
730 int cx25821_vidupstream_init_ch2(struct cx25821_dev *dev, int channel_select,
733 struct sram_channel *sram_ch;
737 int data_frame_size = 0;
738 int risc_buffer_size = 0;
741 if (dev->_is_running_ch2) {
742 pr_info("Video Channel is still running so return!\n");
746 dev->_channel2_upstream_select = channel_select;
747 sram_ch = dev->channels[channel_select].sram_channels;
749 INIT_WORK(&dev->_irq_work_entry_ch2, cx25821_vidups_handler_ch2);
750 dev->_irq_queues_ch2 =
751 create_singlethread_workqueue("cx25821_workqueue2");
753 if (!dev->_irq_queues_ch2) {
754 pr_err("create_singlethread_workqueue() for Video FAILED!\n");
758 * 656/VIP SRC Upstream Channel I & J and 7 -
759 * Host Bus Interface for channel A-C
761 tmp = cx_read(VID_CH_MODE_SEL);
762 cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
764 dev->_is_running_ch2 = 0;
765 dev->_frame_count_ch2 = 0;
766 dev->_file_status_ch2 = RESET_STATUS;
767 dev->_lines_count_ch2 = dev->_isNTSC_ch2 ? 480 : 576;
768 dev->_pixel_format_ch2 = pixel_format;
769 dev->_line_size_ch2 =
770 (dev->_pixel_format_ch2 ==
771 PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
772 data_frame_size = dev->_isNTSC_ch2 ? NTSC_DATA_BUF_SZ : PAL_DATA_BUF_SZ;
774 dev->_isNTSC_ch2 ? NTSC_RISC_BUF_SIZE : PAL_RISC_BUF_SIZE;
776 if (dev->input_filename_ch2) {
777 str_length = strlen(dev->input_filename_ch2);
778 dev->_filename_ch2 = kmalloc(str_length + 1, GFP_KERNEL);
780 if (!dev->_filename_ch2)
783 memcpy(dev->_filename_ch2, dev->input_filename_ch2,
786 str_length = strlen(dev->_defaultname_ch2);
787 dev->_filename_ch2 = kmalloc(str_length + 1, GFP_KERNEL);
789 if (!dev->_filename_ch2)
792 memcpy(dev->_filename_ch2, dev->_defaultname_ch2,
796 /* Default if filename is empty string */
797 if (strcmp(dev->input_filename_ch2, "") == 0) {
798 if (dev->_isNTSC_ch2) {
800 (dev->_pixel_format_ch2 ==
801 PIXEL_FRMT_411) ? "/root/vid411.yuv" :
805 (dev->_pixel_format_ch2 ==
806 PIXEL_FRMT_411) ? "/root/pal411.yuv" :
812 cx25821_sram_channel_setup_upstream(dev, sram_ch,
813 dev->_line_size_ch2, 0);
815 /* setup fifo + format */
816 cx25821_set_pixelengine_ch2(dev, sram_ch, dev->_pixel_format_ch2);
818 dev->upstream_riscbuf_size_ch2 = risc_buffer_size * 2;
819 dev->upstream_databuf_size_ch2 = data_frame_size * 2;
821 /* Allocating buffers and prepare RISC program */
823 cx25821_upstream_buffer_prepare_ch2(dev, sram_ch,
824 dev->_line_size_ch2);
826 pr_err("%s: Failed to set up Video upstream buffers!\n",
831 cx25821_start_video_dma_upstream_ch2(dev, sram_ch);
836 cx25821_dev_unregister(dev);