2 * Driver for the Conexant CX25821 PCIe bridge
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <hiep.huynh@conexant.com>, <shu.lin@conexant.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25 #include "cx25821-video.h"
26 #include "cx25821-video-upstream.h"
29 #include <linux/errno.h>
30 #include <linux/kernel.h>
31 #include <linux/init.h>
32 #include <linux/module.h>
33 #include <linux/syscalls.h>
34 #include <linux/file.h>
35 #include <linux/fcntl.h>
36 #include <linux/slab.h>
37 #include <linux/uaccess.h>
39 MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards");
40 MODULE_AUTHOR("Hiep Huynh <hiep.huynh@conexant.com>");
41 MODULE_LICENSE("GPL");
43 static int _intr_msk =
44 FLD_VID_SRC_RISC1 | FLD_VID_SRC_UF | FLD_VID_SRC_SYNC | FLD_VID_SRC_OPC_ERR;
46 int cx25821_sram_channel_setup_upstream(struct cx25821_dev *dev,
47 struct sram_channel *ch,
48 unsigned int bpl, u32 risc)
50 unsigned int i, lines;
53 if (ch->cmds_start == 0) {
54 cx_write(ch->ptr1_reg, 0);
55 cx_write(ch->ptr2_reg, 0);
56 cx_write(ch->cnt2_reg, 0);
57 cx_write(ch->cnt1_reg, 0);
61 bpl = (bpl + 7) & ~7; /* alignment */
63 lines = ch->fifo_size / bpl;
71 for (i = 0; i < lines; i++) {
72 cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
73 cx_write(cdt + 16 * i + 4, 0);
74 cx_write(cdt + 16 * i + 8, 0);
75 cx_write(cdt + 16 * i + 12, 0);
79 cx_write(ch->cmds_start + 0, risc);
81 cx_write(ch->cmds_start + 4, 0);
82 cx_write(ch->cmds_start + 8, cdt);
83 cx_write(ch->cmds_start + 12, (lines * 16) >> 3);
84 cx_write(ch->cmds_start + 16, ch->ctrl_start);
86 cx_write(ch->cmds_start + 20, VID_IQ_SIZE_DW);
88 for (i = 24; i < 80; i += 4)
89 cx_write(ch->cmds_start + i, 0);
92 cx_write(ch->ptr1_reg, ch->fifo_start);
93 cx_write(ch->ptr2_reg, cdt);
94 cx_write(ch->cnt2_reg, (lines * 16) >> 3);
95 cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
100 static __le32 *cx25821_update_riscprogram(struct cx25821_dev *dev,
101 __le32 *rp, unsigned int offset,
102 unsigned int bpl, u32 sync_line,
103 unsigned int lines, int fifo_enable,
106 unsigned int line, i;
107 int dist_betwn_starts = bpl * 2;
109 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
111 if (USE_RISC_NOOP_VIDEO) {
112 for (i = 0; i < NUM_NO_OPS; i++)
113 *(rp++) = cpu_to_le32(RISC_NOOP);
117 for (line = 0; line < lines; line++) {
118 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
119 *(rp++) = cpu_to_le32(dev->_data_buf_phys_addr + offset);
120 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
122 if ((lines <= NTSC_FIELD_HEIGHT)
123 || (line < (NTSC_FIELD_HEIGHT - 1)) || !(dev->_isNTSC)) {
124 offset += dist_betwn_starts;
131 static __le32 *cx25821_risc_field_upstream(struct cx25821_dev *dev, __le32 * rp,
132 dma_addr_t databuf_phys_addr,
133 unsigned int offset, u32 sync_line,
134 unsigned int bpl, unsigned int lines,
135 int fifo_enable, int field_type)
137 unsigned int line, i;
138 struct sram_channel *sram_ch =
139 dev->channels[dev->_channel_upstream_select].sram_channels;
140 int dist_betwn_starts = bpl * 2;
142 /* sync instruction */
143 if (sync_line != NO_SYNC_LINE)
144 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
146 if (USE_RISC_NOOP_VIDEO) {
147 for (i = 0; i < NUM_NO_OPS; i++)
148 *(rp++) = cpu_to_le32(RISC_NOOP);
152 for (line = 0; line < lines; line++) {
153 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
154 *(rp++) = cpu_to_le32(databuf_phys_addr + offset);
155 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
157 if ((lines <= NTSC_FIELD_HEIGHT)
158 || (line < (NTSC_FIELD_HEIGHT - 1)) || !(dev->_isNTSC))
159 /* to skip the other field line */
160 offset += dist_betwn_starts;
162 /* check if we need to enable the FIFO after the first 4 lines
163 * For the upstream video channel, the risc engine will enable
165 if (fifo_enable && line == 3) {
166 *(rp++) = RISC_WRITECR;
167 *(rp++) = sram_ch->dma_ctl;
168 *(rp++) = FLD_VID_FIFO_EN;
169 *(rp++) = 0x00000001;
176 int cx25821_risc_buffer_upstream(struct cx25821_dev *dev,
178 unsigned int top_offset,
179 unsigned int bpl, unsigned int lines)
183 /* get line count for single field */
184 int singlefield_lines = lines >> 1;
185 int odd_num_lines = singlefield_lines;
188 int databuf_offset = 0;
189 int risc_program_size = 0;
190 int risc_flag = RISC_CNT_RESET;
191 unsigned int bottom_offset = bpl;
192 dma_addr_t risc_phys_jump_addr;
195 odd_num_lines = singlefield_lines + 1;
196 risc_program_size = FRAME1_VID_PROG_SIZE;
199 Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
200 FRAME_SIZE_NTSC_Y422;
202 risc_program_size = PAL_VID_PROG_SIZE;
205 Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
208 /* Virtual address of Risc buffer program */
209 rp = dev->_dma_virt_addr;
211 for (frame = 0; frame < NUM_FRAMES; frame++) {
212 databuf_offset = frame_size * frame;
214 if (UNSET != top_offset) {
215 fifo_enable = (frame == 0) ? FIFO_ENABLE : FIFO_DISABLE;
216 rp = cx25821_risc_field_upstream(dev, rp,
218 _data_buf_phys_addr +
226 fifo_enable = FIFO_DISABLE;
229 rp = cx25821_risc_field_upstream(dev, rp,
230 dev->_data_buf_phys_addr +
231 databuf_offset, bottom_offset,
232 0x200, bpl, singlefield_lines,
233 fifo_enable, EVEN_FIELD);
236 risc_flag = RISC_CNT_RESET;
237 risc_phys_jump_addr =
238 dev->_dma_phys_start_addr + risc_program_size;
240 risc_phys_jump_addr = dev->_dma_phys_start_addr;
241 risc_flag = RISC_CNT_INC;
244 /* Loop to 2ndFrameRISC or to Start of Risc
245 * program & generate IRQ
247 *(rp++) = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | risc_flag);
248 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
249 *(rp++) = cpu_to_le32(0);
255 void cx25821_stop_upstream_video_ch1(struct cx25821_dev *dev)
257 struct sram_channel *sram_ch =
258 dev->channels[VID_UPSTREAM_SRAM_CHANNEL_I].sram_channels;
261 if (!dev->_is_running) {
262 pr_info("No video file is currently running so return!\n");
265 /* Disable RISC interrupts */
266 tmp = cx_read(sram_ch->int_msk);
267 cx_write(sram_ch->int_msk, tmp & ~_intr_msk);
269 /* Turn OFF risc and fifo enable */
270 tmp = cx_read(sram_ch->dma_ctl);
271 cx_write(sram_ch->dma_ctl, tmp & ~(FLD_VID_FIFO_EN | FLD_VID_RISC_EN));
273 /* Clear data buffer memory */
274 if (dev->_data_buf_virt_addr)
275 memset(dev->_data_buf_virt_addr, 0, dev->_data_buf_size);
277 dev->_is_running = 0;
278 dev->_is_first_frame = 0;
279 dev->_frame_count = 0;
280 dev->_file_status = END_OF_FILE;
282 kfree(dev->_irq_queues);
283 dev->_irq_queues = NULL;
285 kfree(dev->_filename);
287 tmp = cx_read(VID_CH_MODE_SEL);
288 cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
291 void cx25821_free_mem_upstream_ch1(struct cx25821_dev *dev)
293 if (dev->_is_running)
294 cx25821_stop_upstream_video_ch1(dev);
296 if (dev->_dma_virt_addr) {
297 pci_free_consistent(dev->pci, dev->_risc_size,
298 dev->_dma_virt_addr, dev->_dma_phys_addr);
299 dev->_dma_virt_addr = NULL;
302 if (dev->_data_buf_virt_addr) {
303 pci_free_consistent(dev->pci, dev->_data_buf_size,
304 dev->_data_buf_virt_addr,
305 dev->_data_buf_phys_addr);
306 dev->_data_buf_virt_addr = NULL;
310 int cx25821_get_frame(struct cx25821_dev *dev, struct sram_channel *sram_ch)
313 int frame_index_temp = dev->_frame_index;
316 (dev->_pixel_format ==
317 PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
319 int frame_offset = 0;
320 ssize_t vfs_read_retval = 0;
321 char mybuf[line_size];
326 if (dev->_file_status == END_OF_FILE)
332 Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
333 FRAME_SIZE_NTSC_Y422;
337 Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
340 frame_offset = (frame_index_temp > 0) ? frame_size : 0;
341 file_offset = dev->_frame_count * frame_size;
343 myfile = filp_open(dev->_filename, O_RDONLY | O_LARGEFILE, 0);
345 if (IS_ERR(myfile)) {
346 const int open_errno = -PTR_ERR(myfile);
347 pr_err("%s(): ERROR opening file(%s) with errno = %d!\n",
348 __func__, dev->_filename, open_errno);
349 return PTR_ERR(myfile);
351 if (!(myfile->f_op)) {
352 pr_err("%s(): File has no file operations registered!\n",
354 filp_close(myfile, NULL);
358 if (!myfile->f_op->read) {
359 pr_err("%s(): File has no READ operations registered!\n",
361 filp_close(myfile, NULL);
369 for (i = 0; i < dev->_lines_count; i++) {
373 vfs_read(myfile, mybuf, line_size, &pos);
375 if (vfs_read_retval > 0 && vfs_read_retval == line_size
376 && dev->_data_buf_virt_addr != NULL) {
377 memcpy((void *)(dev->_data_buf_virt_addr +
378 frame_offset / 4), mybuf,
382 file_offset += vfs_read_retval;
383 frame_offset += vfs_read_retval;
385 if (vfs_read_retval < line_size) {
386 pr_info("Done: exit %s() since no more bytes to read from Video file\n",
396 (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
399 filp_close(myfile, NULL);
405 static void cx25821_vidups_handler(struct work_struct *work)
407 struct cx25821_dev *dev =
408 container_of(work, struct cx25821_dev, _irq_work_entry);
411 pr_err("ERROR %s(): since container_of(work_struct) FAILED!\n",
416 cx25821_get_frame(dev,
417 dev->channels[dev->_channel_upstream_select].
421 int cx25821_openfile(struct cx25821_dev *dev, struct sram_channel *sram_ch)
426 (dev->_pixel_format ==
427 PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
428 ssize_t vfs_read_retval = 0;
429 char mybuf[line_size];
431 loff_t offset = (unsigned long)0;
434 myfile = filp_open(dev->_filename, O_RDONLY | O_LARGEFILE, 0);
436 if (IS_ERR(myfile)) {
437 const int open_errno = -PTR_ERR(myfile);
438 pr_err("%s(): ERROR opening file(%s) with errno = %d!\n",
439 __func__, dev->_filename, open_errno);
440 return PTR_ERR(myfile);
442 if (!(myfile->f_op)) {
443 pr_err("%s(): File has no file operations registered!\n",
445 filp_close(myfile, NULL);
449 if (!myfile->f_op->read) {
450 pr_err("%s(): File has no READ operations registered! Returning\n",
452 filp_close(myfile, NULL);
460 for (j = 0; j < NUM_FRAMES; j++) {
461 for (i = 0; i < dev->_lines_count; i++) {
465 vfs_read(myfile, mybuf, line_size, &pos);
467 if (vfs_read_retval > 0
468 && vfs_read_retval == line_size
469 && dev->_data_buf_virt_addr != NULL) {
470 memcpy((void *)(dev->
471 _data_buf_virt_addr +
476 offset += vfs_read_retval;
478 if (vfs_read_retval < line_size) {
479 pr_info("Done: exit %s() since no more bytes to read from Video file\n",
488 if (vfs_read_retval < line_size)
493 (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
497 filp_close(myfile, NULL);
503 int cx25821_upstream_buffer_prepare(struct cx25821_dev *dev,
504 struct sram_channel *sram_ch, int bpl)
508 dma_addr_t data_dma_addr;
510 if (dev->_dma_virt_addr != NULL) {
511 pci_free_consistent(dev->pci, dev->upstream_riscbuf_size,
512 dev->_dma_virt_addr, dev->_dma_phys_addr);
515 dev->_dma_virt_addr =
516 pci_alloc_consistent(dev->pci, dev->upstream_riscbuf_size,
518 dev->_dma_virt_start_addr = dev->_dma_virt_addr;
519 dev->_dma_phys_start_addr = dma_addr;
520 dev->_dma_phys_addr = dma_addr;
521 dev->_risc_size = dev->upstream_riscbuf_size;
523 if (!dev->_dma_virt_addr) {
524 pr_err("FAILED to allocate memory for Risc buffer! Returning\n");
528 /* Clear memory at address */
529 memset(dev->_dma_virt_addr, 0, dev->_risc_size);
531 if (dev->_data_buf_virt_addr != NULL) {
532 pci_free_consistent(dev->pci, dev->upstream_databuf_size,
533 dev->_data_buf_virt_addr,
534 dev->_data_buf_phys_addr);
536 /* For Video Data buffer allocation */
537 dev->_data_buf_virt_addr =
538 pci_alloc_consistent(dev->pci, dev->upstream_databuf_size,
540 dev->_data_buf_phys_addr = data_dma_addr;
541 dev->_data_buf_size = dev->upstream_databuf_size;
543 if (!dev->_data_buf_virt_addr) {
544 pr_err("FAILED to allocate memory for data buffer! Returning\n");
548 /* Clear memory at address */
549 memset(dev->_data_buf_virt_addr, 0, dev->_data_buf_size);
551 ret = cx25821_openfile(dev, sram_ch);
555 /* Create RISC programs */
557 cx25821_risc_buffer_upstream(dev, dev->pci, 0, bpl,
560 pr_info("Failed creating Video Upstream Risc programs!\n");
570 int cx25821_video_upstream_irq(struct cx25821_dev *dev, int chan_num,
574 struct sram_channel *channel = dev->channels[chan_num].sram_channels;
575 int singlefield_lines = NTSC_FIELD_HEIGHT;
576 int line_size_in_bytes = Y422_LINE_SZ;
577 int odd_risc_prog_size = 0;
578 dma_addr_t risc_phys_jump_addr;
581 if (status & FLD_VID_SRC_RISC1) {
582 /* We should only process one program per call */
583 u32 prog_cnt = cx_read(channel->gpcnt);
585 /* Since we've identified our IRQ, clear our bits from the
586 * interrupt mask and interrupt status registers */
587 int_msk_tmp = cx_read(channel->int_msk);
588 cx_write(channel->int_msk, int_msk_tmp & ~_intr_msk);
589 cx_write(channel->int_stat, _intr_msk);
591 spin_lock(&dev->slock);
593 dev->_frame_index = prog_cnt;
595 queue_work(dev->_irq_queues, &dev->_irq_work_entry);
597 if (dev->_is_first_frame) {
598 dev->_is_first_frame = 0;
601 singlefield_lines += 1;
602 odd_risc_prog_size = ODD_FLD_NTSC_PROG_SIZE;
604 singlefield_lines = PAL_FIELD_HEIGHT;
605 odd_risc_prog_size = ODD_FLD_PAL_PROG_SIZE;
608 if (dev->_dma_virt_start_addr != NULL) {
610 (dev->_pixel_format ==
611 PIXEL_FRMT_411) ? Y411_LINE_SZ :
613 risc_phys_jump_addr =
614 dev->_dma_phys_start_addr +
617 rp = cx25821_update_riscprogram(dev,
619 _dma_virt_start_addr,
627 /* Jump to Even Risc program of 1st Frame */
628 *(rp++) = cpu_to_le32(RISC_JUMP);
629 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
630 *(rp++) = cpu_to_le32(0);
634 spin_unlock(&dev->slock);
636 if (status & FLD_VID_SRC_UF)
637 pr_err("%s(): Video Received Underflow Error Interrupt!\n",
640 if (status & FLD_VID_SRC_SYNC)
641 pr_err("%s(): Video Received Sync Error Interrupt!\n",
644 if (status & FLD_VID_SRC_OPC_ERR)
645 pr_err("%s(): Video Received OpCode Error Interrupt!\n",
649 if (dev->_file_status == END_OF_FILE) {
650 pr_err("EOF Channel 1 Framecount = %d\n", dev->_frame_count);
653 /* ElSE, set the interrupt mask register, re-enable irq. */
654 int_msk_tmp = cx_read(channel->int_msk);
655 cx_write(channel->int_msk, int_msk_tmp |= _intr_msk);
660 static irqreturn_t cx25821_upstream_irq(int irq, void *dev_id)
662 struct cx25821_dev *dev = dev_id;
663 u32 msk_stat, vid_status;
666 struct sram_channel *sram_ch;
671 channel_num = VID_UPSTREAM_SRAM_CHANNEL_I;
673 sram_ch = dev->channels[channel_num].sram_channels;
675 msk_stat = cx_read(sram_ch->int_mstat);
676 vid_status = cx_read(sram_ch->int_stat);
678 /* Only deal with our interrupt */
681 cx25821_video_upstream_irq(dev, channel_num, vid_status);
685 cx25821_stop_upstream_video_ch1(dev);
689 return IRQ_RETVAL(handled);
692 void cx25821_set_pixelengine(struct cx25821_dev *dev, struct sram_channel *ch,
695 int width = WIDTH_D1;
696 int height = dev->_lines_count;
697 int num_lines, odd_num_lines;
699 int vip_mode = OUTPUT_FRMT_656;
701 value = ((pix_format & 0x3) << 12) | (vip_mode & 0x7);
703 value |= dev->_isNTSC ? 0 : 0x10;
704 cx_write(ch->vid_fmt_ctl, value);
706 /* set number of active pixels in each line.
707 * Default is 720 pixels in both NTSC and PAL format */
708 cx_write(ch->vid_active_ctl1, width);
710 num_lines = (height / 2) & 0x3FF;
711 odd_num_lines = num_lines;
716 value = (num_lines << 16) | odd_num_lines;
718 /* set number of active lines in field 0 (top) and field 1 (bottom) */
719 cx_write(ch->vid_active_ctl2, value);
721 cx_write(ch->vid_cdt_size, VID_CDT_SIZE >> 3);
724 int cx25821_start_video_dma_upstream(struct cx25821_dev *dev,
725 struct sram_channel *sram_ch)
730 /* 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for
733 tmp = cx_read(VID_CH_MODE_SEL);
734 cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
736 /* Set the physical start address of the RISC program in the initial
737 * program counter(IPC) member of the cmds.
739 cx_write(sram_ch->cmds_start + 0, dev->_dma_phys_addr);
740 /* Risc IPC High 64 bits 63-32 */
741 cx_write(sram_ch->cmds_start + 4, 0);
744 cx_write(sram_ch->gpcnt_ctl, 3);
746 /* Clear our bits from the interrupt status register. */
747 cx_write(sram_ch->int_stat, _intr_msk);
749 /* Set the interrupt mask register, enable irq. */
750 cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit));
751 tmp = cx_read(sram_ch->int_msk);
752 cx_write(sram_ch->int_msk, tmp |= _intr_msk);
755 request_irq(dev->pci->irq, cx25821_upstream_irq,
756 IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
758 pr_err("%s: can't get upstream IRQ %d\n",
759 dev->name, dev->pci->irq);
763 /* Start the DMA engine */
764 tmp = cx_read(sram_ch->dma_ctl);
765 cx_set(sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN);
767 dev->_is_running = 1;
768 dev->_is_first_frame = 1;
773 cx25821_dev_unregister(dev);
777 int cx25821_vidupstream_init_ch1(struct cx25821_dev *dev, int channel_select,
780 struct sram_channel *sram_ch;
784 int data_frame_size = 0;
785 int risc_buffer_size = 0;
788 if (dev->_is_running) {
789 pr_info("Video Channel is still running so return!\n");
793 dev->_channel_upstream_select = channel_select;
794 sram_ch = dev->channels[channel_select].sram_channels;
796 INIT_WORK(&dev->_irq_work_entry, cx25821_vidups_handler);
797 dev->_irq_queues = create_singlethread_workqueue("cx25821_workqueue");
799 if (!dev->_irq_queues) {
800 pr_err("create_singlethread_workqueue() for Video FAILED!\n");
803 /* 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for
806 tmp = cx_read(VID_CH_MODE_SEL);
807 cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
809 dev->_is_running = 0;
810 dev->_frame_count = 0;
811 dev->_file_status = RESET_STATUS;
812 dev->_lines_count = dev->_isNTSC ? 480 : 576;
813 dev->_pixel_format = pixel_format;
815 (dev->_pixel_format ==
816 PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
817 data_frame_size = dev->_isNTSC ? NTSC_DATA_BUF_SZ : PAL_DATA_BUF_SZ;
819 dev->_isNTSC ? NTSC_RISC_BUF_SIZE : PAL_RISC_BUF_SIZE;
821 if (dev->input_filename) {
822 str_length = strlen(dev->input_filename);
823 dev->_filename = kmalloc(str_length + 1, GFP_KERNEL);
828 memcpy(dev->_filename, dev->input_filename, str_length + 1);
830 str_length = strlen(dev->_defaultname);
831 dev->_filename = kmalloc(str_length + 1, GFP_KERNEL);
836 memcpy(dev->_filename, dev->_defaultname, str_length + 1);
839 /* Default if filename is empty string */
840 if (strcmp(dev->input_filename, "") == 0) {
843 (dev->_pixel_format ==
844 PIXEL_FRMT_411) ? "/root/vid411.yuv" :
848 (dev->_pixel_format ==
849 PIXEL_FRMT_411) ? "/root/pal411.yuv" :
854 dev->_is_running = 0;
855 dev->_frame_count = 0;
856 dev->_file_status = RESET_STATUS;
857 dev->_lines_count = dev->_isNTSC ? 480 : 576;
858 dev->_pixel_format = pixel_format;
860 (dev->_pixel_format ==
861 PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
864 cx25821_sram_channel_setup_upstream(dev, sram_ch, dev->_line_size,
867 /* setup fifo + format */
868 cx25821_set_pixelengine(dev, sram_ch, dev->_pixel_format);
870 dev->upstream_riscbuf_size = risc_buffer_size * 2;
871 dev->upstream_databuf_size = data_frame_size * 2;
873 /* Allocating buffers and prepare RISC program */
874 retval = cx25821_upstream_buffer_prepare(dev, sram_ch, dev->_line_size);
876 pr_err("%s: Failed to set up Video upstream buffers!\n",
881 cx25821_start_video_dma_upstream(dev, sram_ch);
886 cx25821_dev_unregister(dev);