2 * core.c - DesignWare HS OTG Controller common routines
4 * Copyright (C) 2004-2013 Synopsys, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
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11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
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17 * specific prior written permission.
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 * The Core code provides basic services for accessing and managing the
39 * DWC_otg hardware. These services are used by both the Host Controller
40 * Driver and the Peripheral Controller Driver.
42 #include <linux/kernel.h>
43 #include <linux/module.h>
44 #include <linux/moduleparam.h>
45 #include <linux/spinlock.h>
46 #include <linux/interrupt.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/delay.h>
50 #include <linux/slab.h>
51 #include <linux/usb.h>
53 #include <linux/usb/hcd.h>
54 #include <linux/usb/ch11.h>
60 * dwc2_enable_common_interrupts() - Initializes the commmon interrupts,
61 * used in both device and host modes
63 * @hsotg: Programming view of the DWC_otg controller
65 static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
69 /* Clear any pending OTG Interrupts */
70 writel(0xffffffff, hsotg->regs + GOTGINT);
72 /* Clear any pending interrupts */
73 writel(0xffffffff, hsotg->regs + GINTSTS);
75 /* Enable the interrupts in the GINTMSK */
76 intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT;
78 if (hsotg->core_params->dma_enable <= 0)
79 intmsk |= GINTSTS_RXFLVL;
81 intmsk |= GINTSTS_CONIDSTSCHNG | GINTSTS_WKUPINT | GINTSTS_USBSUSP |
84 writel(intmsk, hsotg->regs + GINTMSK);
88 * Initializes the FSLSPClkSel field of the HCFG register depending on the
91 static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
95 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
96 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
97 hsotg->core_params->ulpi_fs_ls > 0) ||
98 hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) {
100 val = HCFG_FSLSPCLKSEL_48_MHZ;
102 /* High speed PHY running at full speed or high speed */
103 val = HCFG_FSLSPCLKSEL_30_60_MHZ;
106 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
107 hcfg = readl(hsotg->regs + HCFG);
108 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
109 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
110 writel(hcfg, hsotg->regs + HCFG);
114 * Do core a soft reset of the core. Be careful with this because it
115 * resets all the internal state machines of the core.
117 static void dwc2_core_reset(struct dwc2_hsotg *hsotg)
122 dev_vdbg(hsotg->dev, "%s()\n", __func__);
124 /* Wait for AHB master IDLE state */
126 usleep_range(20000, 40000);
127 greset = readl(hsotg->regs + GRSTCTL);
130 "%s() HANG! AHB Idle GRSTCTL=%0x\n",
134 } while (!(greset & GRSTCTL_AHBIDLE));
136 /* Core Soft Reset */
138 greset |= GRSTCTL_CSFTRST;
139 writel(greset, hsotg->regs + GRSTCTL);
141 usleep_range(20000, 40000);
142 greset = readl(hsotg->regs + GRSTCTL);
145 "%s() HANG! Soft Reset GRSTCTL=%0x\n",
149 } while (greset & GRSTCTL_CSFTRST);
152 * NOTE: This long sleep is _very_ important, otherwise the core will
153 * not stay in host mode after a connector ID change!
155 usleep_range(150000, 200000);
158 static void dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
163 * core_init() is now called on every switch so only call the
164 * following for the first time through
167 dev_dbg(hsotg->dev, "FS PHY selected\n");
168 usbcfg = readl(hsotg->regs + GUSBCFG);
169 usbcfg |= GUSBCFG_PHYSEL;
170 writel(usbcfg, hsotg->regs + GUSBCFG);
172 /* Reset after a PHY select */
173 dwc2_core_reset(hsotg);
177 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
178 * do this on HNP Dev/Host mode switches (done in dev_init and
181 if (dwc2_is_host_mode(hsotg))
182 dwc2_init_fs_ls_pclk_sel(hsotg);
184 if (hsotg->core_params->i2c_enable > 0) {
185 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
187 /* Program GUSBCFG.OtgUtmiFsSel to I2C */
188 usbcfg = readl(hsotg->regs + GUSBCFG);
189 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
190 writel(usbcfg, hsotg->regs + GUSBCFG);
192 /* Program GI2CCTL.I2CEn */
193 i2cctl = readl(hsotg->regs + GI2CCTL);
194 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
195 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
196 i2cctl &= ~GI2CCTL_I2CEN;
197 writel(i2cctl, hsotg->regs + GI2CCTL);
198 i2cctl |= GI2CCTL_I2CEN;
199 writel(i2cctl, hsotg->regs + GI2CCTL);
203 static void dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
210 usbcfg = readl(hsotg->regs + GUSBCFG);
213 * HS PHY parameters. These parameters are preserved during soft reset
214 * so only program the first time. Do a soft reset immediately after
217 switch (hsotg->core_params->phy_type) {
218 case DWC2_PHY_TYPE_PARAM_ULPI:
220 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");
221 usbcfg |= GUSBCFG_ULPI_UTMI_SEL;
222 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
223 if (hsotg->core_params->phy_ulpi_ddr > 0)
224 usbcfg |= GUSBCFG_DDRSEL;
226 case DWC2_PHY_TYPE_PARAM_UTMI:
227 /* UTMI+ interface */
228 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");
229 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
230 if (hsotg->core_params->phy_utmi_width == 16)
231 usbcfg |= GUSBCFG_PHYIF16;
234 dev_err(hsotg->dev, "FS PHY selected at HS!\n");
238 writel(usbcfg, hsotg->regs + GUSBCFG);
240 /* Reset after setting the PHY parameters */
241 dwc2_core_reset(hsotg);
244 static void dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
248 if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL &&
249 hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) {
250 /* If FS mode with FS PHY */
251 dwc2_fs_phy_init(hsotg, select_phy);
254 dwc2_hs_phy_init(hsotg, select_phy);
257 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
258 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
259 hsotg->core_params->ulpi_fs_ls > 0) {
260 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
261 usbcfg = readl(hsotg->regs + GUSBCFG);
262 usbcfg |= GUSBCFG_ULPI_FS_LS;
263 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
264 writel(usbcfg, hsotg->regs + GUSBCFG);
266 usbcfg = readl(hsotg->regs + GUSBCFG);
267 usbcfg &= ~GUSBCFG_ULPI_FS_LS;
268 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
269 writel(usbcfg, hsotg->regs + GUSBCFG);
273 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
275 u32 ahbcfg = readl(hsotg->regs + GAHBCFG);
277 switch (hsotg->hw_params.arch) {
278 case GHWCFG2_EXT_DMA_ARCH:
279 dev_err(hsotg->dev, "External DMA Mode not supported\n");
282 case GHWCFG2_INT_DMA_ARCH:
283 dev_dbg(hsotg->dev, "Internal DMA Mode\n");
284 if (hsotg->core_params->ahbcfg != -1) {
285 ahbcfg &= GAHBCFG_CTRL_MASK;
286 ahbcfg |= hsotg->core_params->ahbcfg &
291 case GHWCFG2_SLAVE_ONLY_ARCH:
293 dev_dbg(hsotg->dev, "Slave Only Mode\n");
297 dev_dbg(hsotg->dev, "dma_enable:%d dma_desc_enable:%d\n",
298 hsotg->core_params->dma_enable,
299 hsotg->core_params->dma_desc_enable);
301 if (hsotg->core_params->dma_enable > 0) {
302 if (hsotg->core_params->dma_desc_enable > 0)
303 dev_dbg(hsotg->dev, "Using Descriptor DMA mode\n");
305 dev_dbg(hsotg->dev, "Using Buffer DMA mode\n");
307 dev_dbg(hsotg->dev, "Using Slave mode\n");
308 hsotg->core_params->dma_desc_enable = 0;
311 if (hsotg->core_params->dma_enable > 0)
312 ahbcfg |= GAHBCFG_DMA_EN;
314 writel(ahbcfg, hsotg->regs + GAHBCFG);
319 static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
323 usbcfg = readl(hsotg->regs + GUSBCFG);
324 usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
326 switch (hsotg->hw_params.op_mode) {
327 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
328 if (hsotg->core_params->otg_cap ==
329 DWC2_CAP_PARAM_HNP_SRP_CAPABLE)
330 usbcfg |= GUSBCFG_HNPCAP;
331 if (hsotg->core_params->otg_cap !=
332 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
333 usbcfg |= GUSBCFG_SRPCAP;
336 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
337 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
338 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
339 if (hsotg->core_params->otg_cap !=
340 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
341 usbcfg |= GUSBCFG_SRPCAP;
344 case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE:
345 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE:
346 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST:
351 writel(usbcfg, hsotg->regs + GUSBCFG);
355 * dwc2_core_init() - Initializes the DWC_otg controller registers and
356 * prepares the core for device mode or host mode operation
358 * @hsotg: Programming view of the DWC_otg controller
359 * @select_phy: If true then also set the Phy type
360 * @irq: If >= 0, the irq to register
362 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy, int irq)
367 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
369 usbcfg = readl(hsotg->regs + GUSBCFG);
371 /* Set ULPI External VBUS bit if needed */
372 usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV;
373 if (hsotg->core_params->phy_ulpi_ext_vbus ==
374 DWC2_PHY_ULPI_EXTERNAL_VBUS)
375 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV;
377 /* Set external TS Dline pulsing bit if needed */
378 usbcfg &= ~GUSBCFG_TERMSELDLPULSE;
379 if (hsotg->core_params->ts_dline > 0)
380 usbcfg |= GUSBCFG_TERMSELDLPULSE;
382 writel(usbcfg, hsotg->regs + GUSBCFG);
384 /* Reset the Controller */
385 dwc2_core_reset(hsotg);
388 * This needs to happen in FS mode before any other programming occurs
390 dwc2_phy_init(hsotg, select_phy);
392 /* Program the GAHBCFG Register */
393 retval = dwc2_gahbcfg_init(hsotg);
397 /* Program the GUSBCFG register */
398 dwc2_gusbcfg_init(hsotg);
400 /* Program the GOTGCTL register */
401 otgctl = readl(hsotg->regs + GOTGCTL);
402 otgctl &= ~GOTGCTL_OTGVER;
403 if (hsotg->core_params->otg_ver > 0)
404 otgctl |= GOTGCTL_OTGVER;
405 writel(otgctl, hsotg->regs + GOTGCTL);
406 dev_dbg(hsotg->dev, "OTG VER PARAM: %d\n", hsotg->core_params->otg_ver);
408 /* Clear the SRP success bit for FS-I2c */
409 hsotg->srp_success = 0;
412 dev_dbg(hsotg->dev, "registering common handler for irq%d\n",
414 retval = devm_request_irq(hsotg->dev, irq,
415 dwc2_handle_common_intr, IRQF_SHARED,
416 dev_name(hsotg->dev), hsotg);
421 /* Enable common interrupts */
422 dwc2_enable_common_interrupts(hsotg);
425 * Do device or host intialization based on mode during PCD and
428 if (dwc2_is_host_mode(hsotg)) {
429 dev_dbg(hsotg->dev, "Host Mode\n");
430 hsotg->op_state = OTG_STATE_A_HOST;
432 dev_dbg(hsotg->dev, "Device Mode\n");
433 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
440 * dwc2_enable_host_interrupts() - Enables the Host mode interrupts
442 * @hsotg: Programming view of DWC_otg controller
444 void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg)
448 dev_dbg(hsotg->dev, "%s()\n", __func__);
450 /* Disable all interrupts */
451 writel(0, hsotg->regs + GINTMSK);
452 writel(0, hsotg->regs + HAINTMSK);
454 /* Clear any pending interrupts */
455 writel(0xffffffff, hsotg->regs + GINTSTS);
457 /* Enable the common interrupts */
458 dwc2_enable_common_interrupts(hsotg);
460 /* Enable host mode interrupts without disturbing common interrupts */
461 intmsk = readl(hsotg->regs + GINTMSK);
462 intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT;
463 writel(intmsk, hsotg->regs + GINTMSK);
467 * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts
469 * @hsotg: Programming view of DWC_otg controller
471 void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg)
473 u32 intmsk = readl(hsotg->regs + GINTMSK);
475 /* Disable host mode interrupts without disturbing common interrupts */
476 intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT |
477 GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP);
478 writel(intmsk, hsotg->regs + GINTMSK);
481 static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
483 struct dwc2_core_params *params = hsotg->core_params;
484 u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz;
486 if (!params->enable_dynamic_fifo)
490 grxfsiz = readl(hsotg->regs + GRXFSIZ);
491 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz);
492 grxfsiz &= ~GRXFSIZ_DEPTH_MASK;
493 grxfsiz |= params->host_rx_fifo_size <<
494 GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK;
495 writel(grxfsiz, hsotg->regs + GRXFSIZ);
496 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", readl(hsotg->regs + GRXFSIZ));
498 /* Non-periodic Tx FIFO */
499 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n",
500 readl(hsotg->regs + GNPTXFSIZ));
501 nptxfsiz = params->host_nperio_tx_fifo_size <<
502 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
503 nptxfsiz |= params->host_rx_fifo_size <<
504 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
505 writel(nptxfsiz, hsotg->regs + GNPTXFSIZ);
506 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n",
507 readl(hsotg->regs + GNPTXFSIZ));
509 /* Periodic Tx FIFO */
510 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n",
511 readl(hsotg->regs + HPTXFSIZ));
512 hptxfsiz = params->host_perio_tx_fifo_size <<
513 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
514 hptxfsiz |= (params->host_rx_fifo_size +
515 params->host_nperio_tx_fifo_size) <<
516 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
517 writel(hptxfsiz, hsotg->regs + HPTXFSIZ);
518 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n",
519 readl(hsotg->regs + HPTXFSIZ));
521 if (hsotg->core_params->en_multiple_tx_fifo > 0 &&
522 hsotg->hw_params.snpsid <= DWC2_CORE_REV_2_94a) {
524 * Global DFIFOCFG calculation for Host mode -
525 * include RxFIFO, NPTXFIFO and HPTXFIFO
527 dfifocfg = readl(hsotg->regs + GDFIFOCFG);
528 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK;
529 dfifocfg |= (params->host_rx_fifo_size +
530 params->host_nperio_tx_fifo_size +
531 params->host_perio_tx_fifo_size) <<
532 GDFIFOCFG_EPINFOBASE_SHIFT &
533 GDFIFOCFG_EPINFOBASE_MASK;
534 writel(dfifocfg, hsotg->regs + GDFIFOCFG);
539 * dwc2_core_host_init() - Initializes the DWC_otg controller registers for
542 * @hsotg: Programming view of DWC_otg controller
544 * This function flushes the Tx and Rx FIFOs and flushes any entries in the
545 * request queues. Host channels are reset to ensure that they are ready for
546 * performing transfers.
548 void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
550 u32 hcfg, hfir, otgctl;
552 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
554 /* Restart the Phy Clock */
555 writel(0, hsotg->regs + PCGCTL);
557 /* Initialize Host Configuration Register */
558 dwc2_init_fs_ls_pclk_sel(hsotg);
559 if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL) {
560 hcfg = readl(hsotg->regs + HCFG);
561 hcfg |= HCFG_FSLSSUPP;
562 writel(hcfg, hsotg->regs + HCFG);
566 * This bit allows dynamic reloading of the HFIR register during
567 * runtime. This bit needs to be programmed during initial configuration
568 * and its value must not be changed during runtime.
570 if (hsotg->core_params->reload_ctl > 0) {
571 hfir = readl(hsotg->regs + HFIR);
572 hfir |= HFIR_RLDCTRL;
573 writel(hfir, hsotg->regs + HFIR);
576 if (hsotg->core_params->dma_desc_enable > 0) {
577 u32 op_mode = hsotg->hw_params.op_mode;
578 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a ||
579 !hsotg->hw_params.dma_desc_enable ||
580 op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
581 op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
582 op_mode == GHWCFG2_OP_MODE_UNDEFINED) {
584 "Hardware does not support descriptor DMA mode -\n");
586 "falling back to buffer DMA mode.\n");
587 hsotg->core_params->dma_desc_enable = 0;
589 hcfg = readl(hsotg->regs + HCFG);
590 hcfg |= HCFG_DESCDMA;
591 writel(hcfg, hsotg->regs + HCFG);
595 /* Configure data FIFO sizes */
596 dwc2_config_fifos(hsotg);
598 /* TODO - check this */
599 /* Clear Host Set HNP Enable in the OTG Control Register */
600 otgctl = readl(hsotg->regs + GOTGCTL);
601 otgctl &= ~GOTGCTL_HSTSETHNPEN;
602 writel(otgctl, hsotg->regs + GOTGCTL);
604 /* Make sure the FIFOs are flushed */
605 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */);
606 dwc2_flush_rx_fifo(hsotg);
608 /* Clear Host Set HNP Enable in the OTG Control Register */
609 otgctl = readl(hsotg->regs + GOTGCTL);
610 otgctl &= ~GOTGCTL_HSTSETHNPEN;
611 writel(otgctl, hsotg->regs + GOTGCTL);
613 if (hsotg->core_params->dma_desc_enable <= 0) {
617 /* Flush out any leftover queued requests */
618 num_channels = hsotg->core_params->host_channels;
619 for (i = 0; i < num_channels; i++) {
620 hcchar = readl(hsotg->regs + HCCHAR(i));
621 hcchar &= ~HCCHAR_CHENA;
622 hcchar |= HCCHAR_CHDIS;
623 hcchar &= ~HCCHAR_EPDIR;
624 writel(hcchar, hsotg->regs + HCCHAR(i));
627 /* Halt all channels to put them into a known state */
628 for (i = 0; i < num_channels; i++) {
631 hcchar = readl(hsotg->regs + HCCHAR(i));
632 hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS;
633 hcchar &= ~HCCHAR_EPDIR;
634 writel(hcchar, hsotg->regs + HCCHAR(i));
635 dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
638 hcchar = readl(hsotg->regs + HCCHAR(i));
639 if (++count > 1000) {
641 "Unable to clear enable on channel %d\n",
646 } while (hcchar & HCCHAR_CHENA);
650 /* Turn on the vbus power */
651 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state);
652 if (hsotg->op_state == OTG_STATE_A_HOST) {
653 u32 hprt0 = dwc2_read_hprt0(hsotg);
655 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n",
656 !!(hprt0 & HPRT0_PWR));
657 if (!(hprt0 & HPRT0_PWR)) {
659 writel(hprt0, hsotg->regs + HPRT0);
663 dwc2_enable_host_interrupts(hsotg);
666 static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg,
667 struct dwc2_host_chan *chan)
669 u32 hcintmsk = HCINTMSK_CHHLTD;
671 switch (chan->ep_type) {
672 case USB_ENDPOINT_XFER_CONTROL:
673 case USB_ENDPOINT_XFER_BULK:
674 dev_vdbg(hsotg->dev, "control/bulk\n");
675 hcintmsk |= HCINTMSK_XFERCOMPL;
676 hcintmsk |= HCINTMSK_STALL;
677 hcintmsk |= HCINTMSK_XACTERR;
678 hcintmsk |= HCINTMSK_DATATGLERR;
679 if (chan->ep_is_in) {
680 hcintmsk |= HCINTMSK_BBLERR;
682 hcintmsk |= HCINTMSK_NAK;
683 hcintmsk |= HCINTMSK_NYET;
685 hcintmsk |= HCINTMSK_ACK;
688 if (chan->do_split) {
689 hcintmsk |= HCINTMSK_NAK;
690 if (chan->complete_split)
691 hcintmsk |= HCINTMSK_NYET;
693 hcintmsk |= HCINTMSK_ACK;
696 if (chan->error_state)
697 hcintmsk |= HCINTMSK_ACK;
700 case USB_ENDPOINT_XFER_INT:
702 dev_vdbg(hsotg->dev, "intr\n");
703 hcintmsk |= HCINTMSK_XFERCOMPL;
704 hcintmsk |= HCINTMSK_NAK;
705 hcintmsk |= HCINTMSK_STALL;
706 hcintmsk |= HCINTMSK_XACTERR;
707 hcintmsk |= HCINTMSK_DATATGLERR;
708 hcintmsk |= HCINTMSK_FRMOVRUN;
711 hcintmsk |= HCINTMSK_BBLERR;
712 if (chan->error_state)
713 hcintmsk |= HCINTMSK_ACK;
714 if (chan->do_split) {
715 if (chan->complete_split)
716 hcintmsk |= HCINTMSK_NYET;
718 hcintmsk |= HCINTMSK_ACK;
722 case USB_ENDPOINT_XFER_ISOC:
724 dev_vdbg(hsotg->dev, "isoc\n");
725 hcintmsk |= HCINTMSK_XFERCOMPL;
726 hcintmsk |= HCINTMSK_FRMOVRUN;
727 hcintmsk |= HCINTMSK_ACK;
729 if (chan->ep_is_in) {
730 hcintmsk |= HCINTMSK_XACTERR;
731 hcintmsk |= HCINTMSK_BBLERR;
735 dev_err(hsotg->dev, "## Unknown EP type ##\n");
739 writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
741 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
744 static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg,
745 struct dwc2_host_chan *chan)
747 u32 hcintmsk = HCINTMSK_CHHLTD;
750 * For Descriptor DMA mode core halts the channel on AHB error.
751 * Interrupt is not required.
753 if (hsotg->core_params->dma_desc_enable <= 0) {
755 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
756 hcintmsk |= HCINTMSK_AHBERR;
759 dev_vdbg(hsotg->dev, "desc DMA enabled\n");
760 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
761 hcintmsk |= HCINTMSK_XFERCOMPL;
764 if (chan->error_state && !chan->do_split &&
765 chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
767 dev_vdbg(hsotg->dev, "setting ACK\n");
768 hcintmsk |= HCINTMSK_ACK;
769 if (chan->ep_is_in) {
770 hcintmsk |= HCINTMSK_DATATGLERR;
771 if (chan->ep_type != USB_ENDPOINT_XFER_INT)
772 hcintmsk |= HCINTMSK_NAK;
776 writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
778 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
781 static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg,
782 struct dwc2_host_chan *chan)
786 if (hsotg->core_params->dma_enable > 0) {
788 dev_vdbg(hsotg->dev, "DMA enabled\n");
789 dwc2_hc_enable_dma_ints(hsotg, chan);
792 dev_vdbg(hsotg->dev, "DMA disabled\n");
793 dwc2_hc_enable_slave_ints(hsotg, chan);
796 /* Enable the top level host channel interrupt */
797 intmsk = readl(hsotg->regs + HAINTMSK);
798 intmsk |= 1 << chan->hc_num;
799 writel(intmsk, hsotg->regs + HAINTMSK);
801 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk);
803 /* Make sure host channel interrupts are enabled */
804 intmsk = readl(hsotg->regs + GINTMSK);
805 intmsk |= GINTSTS_HCHINT;
806 writel(intmsk, hsotg->regs + GINTMSK);
808 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk);
812 * dwc2_hc_init() - Prepares a host channel for transferring packets to/from
813 * a specific endpoint
815 * @hsotg: Programming view of DWC_otg controller
816 * @chan: Information needed to initialize the host channel
818 * The HCCHARn register is set up with the characteristics specified in chan.
819 * Host channel interrupts that may need to be serviced while this transfer is
820 * in progress are enabled.
822 void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
824 u8 hc_num = chan->hc_num;
830 dev_vdbg(hsotg->dev, "%s()\n", __func__);
832 /* Clear old interrupt conditions for this host channel */
833 hcintmsk = 0xffffffff;
834 hcintmsk &= ~HCINTMSK_RESERVED14_31;
835 writel(hcintmsk, hsotg->regs + HCINT(hc_num));
837 /* Enable channel interrupts required for this transfer */
838 dwc2_hc_enable_ints(hsotg, chan);
841 * Program the HCCHARn register with the endpoint characteristics for
842 * the current transfer
844 hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK;
845 hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK;
847 hcchar |= HCCHAR_EPDIR;
848 if (chan->speed == USB_SPEED_LOW)
849 hcchar |= HCCHAR_LSPDDEV;
850 hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK;
851 hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK;
852 writel(hcchar, hsotg->regs + HCCHAR(hc_num));
854 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n",
857 dev_vdbg(hsotg->dev, "%s: Channel %d\n",
859 dev_vdbg(hsotg->dev, " Dev Addr: %d\n",
861 dev_vdbg(hsotg->dev, " Ep Num: %d\n",
863 dev_vdbg(hsotg->dev, " Is In: %d\n",
865 dev_vdbg(hsotg->dev, " Is Low Speed: %d\n",
866 chan->speed == USB_SPEED_LOW);
867 dev_vdbg(hsotg->dev, " Ep Type: %d\n",
869 dev_vdbg(hsotg->dev, " Max Pkt: %d\n",
873 /* Program the HCSPLT register for SPLITs */
874 if (chan->do_split) {
877 "Programming HC %d with split --> %s\n",
879 chan->complete_split ? "CSPLIT" : "SSPLIT");
880 if (chan->complete_split)
881 hcsplt |= HCSPLT_COMPSPLT;
882 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT &
884 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT &
886 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT &
889 dev_vdbg(hsotg->dev, " comp split %d\n",
890 chan->complete_split);
891 dev_vdbg(hsotg->dev, " xact pos %d\n",
893 dev_vdbg(hsotg->dev, " hub addr %d\n",
895 dev_vdbg(hsotg->dev, " hub port %d\n",
897 dev_vdbg(hsotg->dev, " is_in %d\n",
899 dev_vdbg(hsotg->dev, " Max Pkt %d\n",
901 dev_vdbg(hsotg->dev, " xferlen %d\n",
906 writel(hcsplt, hsotg->regs + HCSPLT(hc_num));
910 * dwc2_hc_halt() - Attempts to halt a host channel
912 * @hsotg: Controller register interface
913 * @chan: Host channel to halt
914 * @halt_status: Reason for halting the channel
916 * This function should only be called in Slave mode or to abort a transfer in
917 * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the
918 * controller halts the channel when the transfer is complete or a condition
919 * occurs that requires application intervention.
921 * In slave mode, checks for a free request queue entry, then sets the Channel
922 * Enable and Channel Disable bits of the Host Channel Characteristics
923 * register of the specified channel to intiate the halt. If there is no free
924 * request queue entry, sets only the Channel Disable bit of the HCCHARn
925 * register to flush requests for this channel. In the latter case, sets a
926 * flag to indicate that the host channel needs to be halted when a request
927 * queue slot is open.
929 * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
930 * HCCHARn register. The controller ensures there is space in the request
931 * queue before submitting the halt request.
933 * Some time may elapse before the core flushes any posted requests for this
934 * host channel and halts. The Channel Halted interrupt handler completes the
935 * deactivation of the host channel.
937 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
938 enum dwc2_halt_status halt_status)
940 u32 nptxsts, hptxsts, hcchar;
943 dev_vdbg(hsotg->dev, "%s()\n", __func__);
944 if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS)
945 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status);
947 if (halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
948 halt_status == DWC2_HC_XFER_AHB_ERR) {
950 * Disable all channel interrupts except Ch Halted. The QTD
951 * and QH state associated with this transfer has been cleared
952 * (in the case of URB_DEQUEUE), so the channel needs to be
953 * shut down carefully to prevent crashes.
955 u32 hcintmsk = HCINTMSK_CHHLTD;
957 dev_vdbg(hsotg->dev, "dequeue/error\n");
958 writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
961 * Make sure no other interrupts besides halt are currently
962 * pending. Handling another interrupt could cause a crash due
963 * to the QTD and QH state.
965 writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num));
968 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
969 * even if the channel was already halted for some other
972 chan->halt_status = halt_status;
974 hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
975 if (!(hcchar & HCCHAR_CHENA)) {
977 * The channel is either already halted or it hasn't
978 * started yet. In DMA mode, the transfer may halt if
979 * it finishes normally or a condition occurs that
980 * requires driver intervention. Don't want to halt
981 * the channel again. In either Slave or DMA mode,
982 * it's possible that the transfer has been assigned
983 * to a channel, but not started yet when an URB is
984 * dequeued. Don't want to halt a channel that hasn't
990 if (chan->halt_pending) {
992 * A halt has already been issued for this channel. This might
993 * happen when a transfer is aborted by a higher level in
997 "*** %s: Channel %d, chan->halt_pending already set ***\n",
998 __func__, chan->hc_num);
1002 hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
1004 /* No need to set the bit in DDMA for disabling the channel */
1005 /* TODO check it everywhere channel is disabled */
1006 if (hsotg->core_params->dma_desc_enable <= 0) {
1008 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
1009 hcchar |= HCCHAR_CHENA;
1012 dev_dbg(hsotg->dev, "desc DMA enabled\n");
1014 hcchar |= HCCHAR_CHDIS;
1016 if (hsotg->core_params->dma_enable <= 0) {
1018 dev_vdbg(hsotg->dev, "DMA not enabled\n");
1019 hcchar |= HCCHAR_CHENA;
1021 /* Check for space in the request queue to issue the halt */
1022 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1023 chan->ep_type == USB_ENDPOINT_XFER_BULK) {
1024 dev_vdbg(hsotg->dev, "control/bulk\n");
1025 nptxsts = readl(hsotg->regs + GNPTXSTS);
1026 if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) {
1027 dev_vdbg(hsotg->dev, "Disabling channel\n");
1028 hcchar &= ~HCCHAR_CHENA;
1032 dev_vdbg(hsotg->dev, "isoc/intr\n");
1033 hptxsts = readl(hsotg->regs + HPTXSTS);
1034 if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 ||
1035 hsotg->queuing_high_bandwidth) {
1037 dev_vdbg(hsotg->dev, "Disabling channel\n");
1038 hcchar &= ~HCCHAR_CHENA;
1043 dev_vdbg(hsotg->dev, "DMA enabled\n");
1046 writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1047 chan->halt_status = halt_status;
1049 if (hcchar & HCCHAR_CHENA) {
1051 dev_vdbg(hsotg->dev, "Channel enabled\n");
1052 chan->halt_pending = 1;
1053 chan->halt_on_queue = 0;
1056 dev_vdbg(hsotg->dev, "Channel disabled\n");
1057 chan->halt_on_queue = 1;
1061 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1063 dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n",
1065 dev_vdbg(hsotg->dev, " halt_pending: %d\n",
1066 chan->halt_pending);
1067 dev_vdbg(hsotg->dev, " halt_on_queue: %d\n",
1068 chan->halt_on_queue);
1069 dev_vdbg(hsotg->dev, " halt_status: %d\n",
1075 * dwc2_hc_cleanup() - Clears the transfer state for a host channel
1077 * @hsotg: Programming view of DWC_otg controller
1078 * @chan: Identifies the host channel to clean up
1080 * This function is normally called after a transfer is done and the host
1081 * channel is being released
1083 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
1087 chan->xfer_started = 0;
1090 * Clear channel interrupt enables and any unhandled channel interrupt
1093 writel(0, hsotg->regs + HCINTMSK(chan->hc_num));
1094 hcintmsk = 0xffffffff;
1095 hcintmsk &= ~HCINTMSK_RESERVED14_31;
1096 writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num));
1100 * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in
1101 * which frame a periodic transfer should occur
1103 * @hsotg: Programming view of DWC_otg controller
1104 * @chan: Identifies the host channel to set up and its properties
1105 * @hcchar: Current value of the HCCHAR register for the specified host channel
1107 * This function has no effect on non-periodic transfers
1109 static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg,
1110 struct dwc2_host_chan *chan, u32 *hcchar)
1112 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1113 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1114 /* 1 if _next_ frame is odd, 0 if it's even */
1115 if (!(dwc2_hcd_get_frame_number(hsotg) & 0x1))
1116 *hcchar |= HCCHAR_ODDFRM;
1120 static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan)
1122 /* Set up the initial PID for the transfer */
1123 if (chan->speed == USB_SPEED_HIGH) {
1124 if (chan->ep_is_in) {
1125 if (chan->multi_count == 1)
1126 chan->data_pid_start = DWC2_HC_PID_DATA0;
1127 else if (chan->multi_count == 2)
1128 chan->data_pid_start = DWC2_HC_PID_DATA1;
1130 chan->data_pid_start = DWC2_HC_PID_DATA2;
1132 if (chan->multi_count == 1)
1133 chan->data_pid_start = DWC2_HC_PID_DATA0;
1135 chan->data_pid_start = DWC2_HC_PID_MDATA;
1138 chan->data_pid_start = DWC2_HC_PID_DATA0;
1143 * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with
1146 * @hsotg: Programming view of DWC_otg controller
1147 * @chan: Information needed to initialize the host channel
1149 * This function should only be called in Slave mode. For a channel associated
1150 * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel
1151 * associated with a periodic EP, the periodic Tx FIFO is written.
1153 * Upon return the xfer_buf and xfer_count fields in chan are incremented by
1154 * the number of bytes written to the Tx FIFO.
1156 static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg,
1157 struct dwc2_host_chan *chan)
1160 u32 remaining_count;
1163 u32 __iomem *data_fifo;
1164 u32 *data_buf = (u32 *)chan->xfer_buf;
1167 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1169 data_fifo = (u32 __iomem *)(hsotg->regs + HCFIFO(chan->hc_num));
1171 remaining_count = chan->xfer_len - chan->xfer_count;
1172 if (remaining_count > chan->max_packet)
1173 byte_count = chan->max_packet;
1175 byte_count = remaining_count;
1177 dword_count = (byte_count + 3) / 4;
1179 if (((unsigned long)data_buf & 0x3) == 0) {
1180 /* xfer_buf is DWORD aligned */
1181 for (i = 0; i < dword_count; i++, data_buf++)
1182 writel(*data_buf, data_fifo);
1184 /* xfer_buf is not DWORD aligned */
1185 for (i = 0; i < dword_count; i++, data_buf++) {
1186 u32 data = data_buf[0] | data_buf[1] << 8 |
1187 data_buf[2] << 16 | data_buf[3] << 24;
1188 writel(data, data_fifo);
1192 chan->xfer_count += byte_count;
1193 chan->xfer_buf += byte_count;
1197 * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host
1198 * channel and starts the transfer
1200 * @hsotg: Programming view of DWC_otg controller
1201 * @chan: Information needed to initialize the host channel. The xfer_len value
1202 * may be reduced to accommodate the max widths of the XferSize and
1203 * PktCnt fields in the HCTSIZn register. The multi_count value may be
1204 * changed to reflect the final xfer_len value.
1206 * This function may be called in either Slave mode or DMA mode. In Slave mode,
1207 * the caller must ensure that there is sufficient space in the request queue
1210 * For an OUT transfer in Slave mode, it loads a data packet into the
1211 * appropriate FIFO. If necessary, additional data packets are loaded in the
1214 * For an IN transfer in Slave mode, a data packet is requested. The data
1215 * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
1216 * additional data packets are requested in the Host ISR.
1218 * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
1219 * register along with a packet count of 1 and the channel is enabled. This
1220 * causes a single PING transaction to occur. Other fields in HCTSIZ are
1221 * simply set to 0 since no data transfer occurs in this case.
1223 * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
1224 * all the information required to perform the subsequent data transfer. In
1225 * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
1226 * controller performs the entire PING protocol, then starts the data
1229 void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
1230 struct dwc2_host_chan *chan)
1232 u32 max_hc_xfer_size = hsotg->core_params->max_transfer_size;
1233 u16 max_hc_pkt_count = hsotg->core_params->max_packet_count;
1239 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1241 if (chan->do_ping) {
1242 if (hsotg->core_params->dma_enable <= 0) {
1244 dev_vdbg(hsotg->dev, "ping, no DMA\n");
1245 dwc2_hc_do_ping(hsotg, chan);
1246 chan->xfer_started = 1;
1250 dev_vdbg(hsotg->dev, "ping, DMA\n");
1251 hctsiz |= TSIZ_DOPNG;
1255 if (chan->do_split) {
1257 dev_vdbg(hsotg->dev, "split\n");
1260 if (chan->complete_split && !chan->ep_is_in)
1262 * For CSPLIT OUT Transfer, set the size to 0 so the
1263 * core doesn't expect any data written to the FIFO
1266 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet)
1267 chan->xfer_len = chan->max_packet;
1268 else if (!chan->ep_is_in && chan->xfer_len > 188)
1269 chan->xfer_len = 188;
1271 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1275 dev_vdbg(hsotg->dev, "no split\n");
1277 * Ensure that the transfer length and packet count will fit
1278 * in the widths allocated for them in the HCTSIZn register
1280 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1281 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1283 * Make sure the transfer size is no larger than one
1284 * (micro)frame's worth of data. (A check was done
1285 * when the periodic transfer was accepted to ensure
1286 * that a (micro)frame's worth of data can be
1287 * programmed into a channel.)
1289 u32 max_periodic_len =
1290 chan->multi_count * chan->max_packet;
1292 if (chan->xfer_len > max_periodic_len)
1293 chan->xfer_len = max_periodic_len;
1294 } else if (chan->xfer_len > max_hc_xfer_size) {
1296 * Make sure that xfer_len is a multiple of max packet
1300 max_hc_xfer_size - chan->max_packet + 1;
1303 if (chan->xfer_len > 0) {
1304 num_packets = (chan->xfer_len + chan->max_packet - 1) /
1306 if (num_packets > max_hc_pkt_count) {
1307 num_packets = max_hc_pkt_count;
1308 chan->xfer_len = num_packets * chan->max_packet;
1311 /* Need 1 packet for transfer length of 0 */
1317 * Always program an integral # of max packets for IN
1320 chan->xfer_len = num_packets * chan->max_packet;
1322 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1323 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1325 * Make sure that the multi_count field matches the
1326 * actual transfer length
1328 chan->multi_count = num_packets;
1330 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1331 dwc2_set_pid_isoc(chan);
1333 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1337 chan->start_pkt_count = num_packets;
1338 hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK;
1339 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1340 TSIZ_SC_MC_PID_MASK;
1341 writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1343 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n",
1344 hctsiz, chan->hc_num);
1346 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1348 dev_vdbg(hsotg->dev, " Xfer Size: %d\n",
1349 (hctsiz & TSIZ_XFERSIZE_MASK) >>
1350 TSIZ_XFERSIZE_SHIFT);
1351 dev_vdbg(hsotg->dev, " Num Pkts: %d\n",
1352 (hctsiz & TSIZ_PKTCNT_MASK) >>
1354 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1355 (hctsiz & TSIZ_SC_MC_PID_MASK) >>
1356 TSIZ_SC_MC_PID_SHIFT);
1359 if (hsotg->core_params->dma_enable > 0) {
1360 dma_addr_t dma_addr;
1362 if (chan->align_buf) {
1364 dev_vdbg(hsotg->dev, "align_buf\n");
1365 dma_addr = chan->align_buf;
1367 dma_addr = chan->xfer_dma;
1369 writel((u32)dma_addr, hsotg->regs + HCDMA(chan->hc_num));
1371 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n",
1372 (unsigned long)dma_addr, chan->hc_num);
1375 /* Start the split */
1376 if (chan->do_split) {
1377 u32 hcsplt = readl(hsotg->regs + HCSPLT(chan->hc_num));
1379 hcsplt |= HCSPLT_SPLTENA;
1380 writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num));
1383 hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
1384 hcchar &= ~HCCHAR_MULTICNT_MASK;
1385 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
1386 HCCHAR_MULTICNT_MASK;
1387 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1389 if (hcchar & HCCHAR_CHDIS)
1390 dev_warn(hsotg->dev,
1391 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1392 __func__, chan->hc_num, hcchar);
1394 /* Set host channel enable after all other setup is complete */
1395 hcchar |= HCCHAR_CHENA;
1396 hcchar &= ~HCCHAR_CHDIS;
1399 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1400 (hcchar & HCCHAR_MULTICNT_MASK) >>
1401 HCCHAR_MULTICNT_SHIFT);
1403 writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1405 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1408 chan->xfer_started = 1;
1411 if (hsotg->core_params->dma_enable <= 0 &&
1412 !chan->ep_is_in && chan->xfer_len > 0)
1413 /* Load OUT packet into the appropriate Tx FIFO */
1414 dwc2_hc_write_packet(hsotg, chan);
1418 * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a
1419 * host channel and starts the transfer in Descriptor DMA mode
1421 * @hsotg: Programming view of DWC_otg controller
1422 * @chan: Information needed to initialize the host channel
1424 * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
1425 * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field
1426 * with micro-frame bitmap.
1428 * Initializes HCDMA register with descriptor list address and CTD value then
1429 * starts the transfer via enabling the channel.
1431 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
1432 struct dwc2_host_chan *chan)
1439 hctsiz |= TSIZ_DOPNG;
1441 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1442 dwc2_set_pid_isoc(chan);
1444 /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
1445 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1446 TSIZ_SC_MC_PID_MASK;
1448 /* 0 - 1 descriptor, 1 - 2 descriptors, etc */
1449 hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK;
1451 /* Non-zero only for high-speed interrupt endpoints */
1452 hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK;
1455 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1457 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1458 chan->data_pid_start);
1459 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1);
1462 writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1464 hc_dma = (u32)chan->desc_list_addr & HCDMA_DMA_ADDR_MASK;
1466 /* Always start from first descriptor */
1467 hc_dma &= ~HCDMA_CTD_MASK;
1468 writel(hc_dma, hsotg->regs + HCDMA(chan->hc_num));
1470 dev_vdbg(hsotg->dev, "Wrote %08x to HCDMA(%d)\n",
1471 hc_dma, chan->hc_num);
1473 hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
1474 hcchar &= ~HCCHAR_MULTICNT_MASK;
1475 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
1476 HCCHAR_MULTICNT_MASK;
1478 if (hcchar & HCCHAR_CHDIS)
1479 dev_warn(hsotg->dev,
1480 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1481 __func__, chan->hc_num, hcchar);
1483 /* Set host channel enable after all other setup is complete */
1484 hcchar |= HCCHAR_CHENA;
1485 hcchar &= ~HCCHAR_CHDIS;
1488 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1489 (hcchar & HCCHAR_MULTICNT_MASK) >>
1490 HCCHAR_MULTICNT_SHIFT);
1492 writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1494 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1497 chan->xfer_started = 1;
1502 * dwc2_hc_continue_transfer() - Continues a data transfer that was started by
1503 * a previous call to dwc2_hc_start_transfer()
1505 * @hsotg: Programming view of DWC_otg controller
1506 * @chan: Information needed to initialize the host channel
1508 * The caller must ensure there is sufficient space in the request queue and Tx
1509 * Data FIFO. This function should only be called in Slave mode. In DMA mode,
1510 * the controller acts autonomously to complete transfers programmed to a host
1513 * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
1514 * if there is any data remaining to be queued. For an IN transfer, another
1515 * data packet is always requested. For the SETUP phase of a control transfer,
1516 * this function does nothing.
1518 * Return: 1 if a new request is queued, 0 if no more requests are required
1521 int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
1522 struct dwc2_host_chan *chan)
1525 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1529 /* SPLITs always queue just once per channel */
1532 if (chan->data_pid_start == DWC2_HC_PID_SETUP)
1533 /* SETUPs are queued only once since they can't be NAK'd */
1536 if (chan->ep_is_in) {
1538 * Always queue another request for other IN transfers. If
1539 * back-to-back INs are issued and NAKs are received for both,
1540 * the driver may still be processing the first NAK when the
1541 * second NAK is received. When the interrupt handler clears
1542 * the NAK interrupt for the first NAK, the second NAK will
1543 * not be seen. So we can't depend on the NAK interrupt
1544 * handler to requeue a NAK'd request. Instead, IN requests
1545 * are issued each time this function is called. When the
1546 * transfer completes, the extra requests for the channel will
1549 u32 hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
1551 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1552 hcchar |= HCCHAR_CHENA;
1553 hcchar &= ~HCCHAR_CHDIS;
1555 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n",
1557 writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1564 if (chan->xfer_count < chan->xfer_len) {
1565 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1566 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1567 u32 hcchar = readl(hsotg->regs +
1568 HCCHAR(chan->hc_num));
1570 dwc2_hc_set_even_odd_frame(hsotg, chan,
1574 /* Load OUT packet into the appropriate Tx FIFO */
1575 dwc2_hc_write_packet(hsotg, chan);
1584 * dwc2_hc_do_ping() - Starts a PING transfer
1586 * @hsotg: Programming view of DWC_otg controller
1587 * @chan: Information needed to initialize the host channel
1589 * This function should only be called in Slave mode. The Do Ping bit is set in
1590 * the HCTSIZ register, then the channel is enabled.
1592 void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
1598 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1602 hctsiz = TSIZ_DOPNG;
1603 hctsiz |= 1 << TSIZ_PKTCNT_SHIFT;
1604 writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1606 hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
1607 hcchar |= HCCHAR_CHENA;
1608 hcchar &= ~HCCHAR_CHDIS;
1609 writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1613 * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for
1614 * the HFIR register according to PHY type and speed
1616 * @hsotg: Programming view of DWC_otg controller
1618 * NOTE: The caller can modify the value of the HFIR register only after the
1619 * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort)
1622 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
1626 int clock = 60; /* default value */
1628 usbcfg = readl(hsotg->regs + GUSBCFG);
1629 hprt0 = readl(hsotg->regs + HPRT0);
1631 if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) &&
1632 !(usbcfg & GUSBCFG_PHYIF16))
1634 if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type ==
1635 GHWCFG2_FS_PHY_TYPE_SHARED_ULPI)
1637 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
1638 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
1640 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
1641 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16))
1643 if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
1644 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
1646 if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) &&
1647 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI)
1649 if ((usbcfg & GUSBCFG_PHYSEL) &&
1650 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
1653 if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED)
1654 /* High speed case */
1658 return 1000 * clock;
1662 * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination
1665 * @core_if: Programming view of DWC_otg controller
1666 * @dest: Destination buffer for the packet
1667 * @bytes: Number of bytes to copy to the destination
1669 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes)
1671 u32 __iomem *fifo = hsotg->regs + HCFIFO(0);
1672 u32 *data_buf = (u32 *)dest;
1673 int word_count = (bytes + 3) / 4;
1677 * Todo: Account for the case where dest is not dword aligned. This
1678 * requires reading data from the FIFO into a u32 temp buffer, then
1679 * moving it into the data buffer.
1682 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes);
1684 for (i = 0; i < word_count; i++, data_buf++)
1685 *data_buf = readl(fifo);
1689 * dwc2_dump_host_registers() - Prints the host registers
1691 * @hsotg: Programming view of DWC_otg controller
1693 * NOTE: This function will be removed once the peripheral controller code
1694 * is integrated and the driver is stable
1696 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg)
1702 dev_dbg(hsotg->dev, "Host Global Registers\n");
1703 addr = hsotg->regs + HCFG;
1704 dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n",
1705 (unsigned long)addr, readl(addr));
1706 addr = hsotg->regs + HFIR;
1707 dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n",
1708 (unsigned long)addr, readl(addr));
1709 addr = hsotg->regs + HFNUM;
1710 dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n",
1711 (unsigned long)addr, readl(addr));
1712 addr = hsotg->regs + HPTXSTS;
1713 dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n",
1714 (unsigned long)addr, readl(addr));
1715 addr = hsotg->regs + HAINT;
1716 dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n",
1717 (unsigned long)addr, readl(addr));
1718 addr = hsotg->regs + HAINTMSK;
1719 dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n",
1720 (unsigned long)addr, readl(addr));
1721 if (hsotg->core_params->dma_desc_enable > 0) {
1722 addr = hsotg->regs + HFLBADDR;
1723 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",
1724 (unsigned long)addr, readl(addr));
1727 addr = hsotg->regs + HPRT0;
1728 dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n",
1729 (unsigned long)addr, readl(addr));
1731 for (i = 0; i < hsotg->core_params->host_channels; i++) {
1732 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);
1733 addr = hsotg->regs + HCCHAR(i);
1734 dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n",
1735 (unsigned long)addr, readl(addr));
1736 addr = hsotg->regs + HCSPLT(i);
1737 dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n",
1738 (unsigned long)addr, readl(addr));
1739 addr = hsotg->regs + HCINT(i);
1740 dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n",
1741 (unsigned long)addr, readl(addr));
1742 addr = hsotg->regs + HCINTMSK(i);
1743 dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n",
1744 (unsigned long)addr, readl(addr));
1745 addr = hsotg->regs + HCTSIZ(i);
1746 dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n",
1747 (unsigned long)addr, readl(addr));
1748 addr = hsotg->regs + HCDMA(i);
1749 dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n",
1750 (unsigned long)addr, readl(addr));
1751 if (hsotg->core_params->dma_desc_enable > 0) {
1752 addr = hsotg->regs + HCDMAB(i);
1753 dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n",
1754 (unsigned long)addr, readl(addr));
1761 * dwc2_dump_global_registers() - Prints the core global registers
1763 * @hsotg: Programming view of DWC_otg controller
1765 * NOTE: This function will be removed once the peripheral controller code
1766 * is integrated and the driver is stable
1768 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg)
1773 dev_dbg(hsotg->dev, "Core Global Registers\n");
1774 addr = hsotg->regs + GOTGCTL;
1775 dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n",
1776 (unsigned long)addr, readl(addr));
1777 addr = hsotg->regs + GOTGINT;
1778 dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n",
1779 (unsigned long)addr, readl(addr));
1780 addr = hsotg->regs + GAHBCFG;
1781 dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n",
1782 (unsigned long)addr, readl(addr));
1783 addr = hsotg->regs + GUSBCFG;
1784 dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n",
1785 (unsigned long)addr, readl(addr));
1786 addr = hsotg->regs + GRSTCTL;
1787 dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n",
1788 (unsigned long)addr, readl(addr));
1789 addr = hsotg->regs + GINTSTS;
1790 dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n",
1791 (unsigned long)addr, readl(addr));
1792 addr = hsotg->regs + GINTMSK;
1793 dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n",
1794 (unsigned long)addr, readl(addr));
1795 addr = hsotg->regs + GRXSTSR;
1796 dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n",
1797 (unsigned long)addr, readl(addr));
1798 addr = hsotg->regs + GRXFSIZ;
1799 dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n",
1800 (unsigned long)addr, readl(addr));
1801 addr = hsotg->regs + GNPTXFSIZ;
1802 dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n",
1803 (unsigned long)addr, readl(addr));
1804 addr = hsotg->regs + GNPTXSTS;
1805 dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n",
1806 (unsigned long)addr, readl(addr));
1807 addr = hsotg->regs + GI2CCTL;
1808 dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n",
1809 (unsigned long)addr, readl(addr));
1810 addr = hsotg->regs + GPVNDCTL;
1811 dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n",
1812 (unsigned long)addr, readl(addr));
1813 addr = hsotg->regs + GGPIO;
1814 dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n",
1815 (unsigned long)addr, readl(addr));
1816 addr = hsotg->regs + GUID;
1817 dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n",
1818 (unsigned long)addr, readl(addr));
1819 addr = hsotg->regs + GSNPSID;
1820 dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n",
1821 (unsigned long)addr, readl(addr));
1822 addr = hsotg->regs + GHWCFG1;
1823 dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n",
1824 (unsigned long)addr, readl(addr));
1825 addr = hsotg->regs + GHWCFG2;
1826 dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n",
1827 (unsigned long)addr, readl(addr));
1828 addr = hsotg->regs + GHWCFG3;
1829 dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n",
1830 (unsigned long)addr, readl(addr));
1831 addr = hsotg->regs + GHWCFG4;
1832 dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n",
1833 (unsigned long)addr, readl(addr));
1834 addr = hsotg->regs + GLPMCFG;
1835 dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n",
1836 (unsigned long)addr, readl(addr));
1837 addr = hsotg->regs + GPWRDN;
1838 dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n",
1839 (unsigned long)addr, readl(addr));
1840 addr = hsotg->regs + GDFIFOCFG;
1841 dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n",
1842 (unsigned long)addr, readl(addr));
1843 addr = hsotg->regs + HPTXFSIZ;
1844 dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n",
1845 (unsigned long)addr, readl(addr));
1847 addr = hsotg->regs + PCGCTL;
1848 dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n",
1849 (unsigned long)addr, readl(addr));
1854 * dwc2_flush_tx_fifo() - Flushes a Tx FIFO
1856 * @hsotg: Programming view of DWC_otg controller
1857 * @num: Tx FIFO to flush
1859 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num)
1864 dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num);
1866 greset = GRSTCTL_TXFFLSH;
1867 greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK;
1868 writel(greset, hsotg->regs + GRSTCTL);
1871 greset = readl(hsotg->regs + GRSTCTL);
1872 if (++count > 10000) {
1873 dev_warn(hsotg->dev,
1874 "%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
1876 readl(hsotg->regs + GNPTXSTS));
1880 } while (greset & GRSTCTL_TXFFLSH);
1882 /* Wait for at least 3 PHY Clocks */
1887 * dwc2_flush_rx_fifo() - Flushes the Rx FIFO
1889 * @hsotg: Programming view of DWC_otg controller
1891 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg)
1896 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1898 greset = GRSTCTL_RXFFLSH;
1899 writel(greset, hsotg->regs + GRSTCTL);
1902 greset = readl(hsotg->regs + GRSTCTL);
1903 if (++count > 10000) {
1904 dev_warn(hsotg->dev, "%s() HANG! GRSTCTL=%0x\n",
1909 } while (greset & GRSTCTL_RXFFLSH);
1911 /* Wait for at least 3 PHY Clocks */
1915 #define DWC2_PARAM_TEST(a, b, c) ((a) < (b) || (a) > (c))
1917 /* Parameter access functions */
1918 int dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val)
1924 case DWC2_CAP_PARAM_HNP_SRP_CAPABLE:
1925 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
1928 case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE:
1929 switch (hsotg->hw_params.op_mode) {
1930 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
1931 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
1932 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
1933 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
1940 case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE:
1951 "%d invalid for otg_cap parameter. Check HW configuration.\n",
1953 switch (hsotg->hw_params.op_mode) {
1954 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
1955 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE;
1957 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
1958 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
1959 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
1960 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE;
1963 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
1966 dev_dbg(hsotg->dev, "Setting otg_cap to %d\n", val);
1970 hsotg->core_params->otg_cap = val;
1974 int dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val)
1979 if (val > 0 && hsotg->hw_params.arch == GHWCFG2_SLAVE_ONLY_ARCH)
1987 "%d invalid for dma_enable parameter. Check HW configuration.\n",
1989 val = hsotg->hw_params.arch != GHWCFG2_SLAVE_ONLY_ARCH;
1990 dev_dbg(hsotg->dev, "Setting dma_enable to %d\n", val);
1994 hsotg->core_params->dma_enable = val;
1998 int dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val)
2003 if (val > 0 && (hsotg->core_params->dma_enable <= 0 ||
2004 !hsotg->hw_params.dma_desc_enable))
2012 "%d invalid for dma_desc_enable parameter. Check HW configuration.\n",
2014 val = (hsotg->core_params->dma_enable > 0 &&
2015 hsotg->hw_params.dma_desc_enable);
2016 dev_dbg(hsotg->dev, "Setting dma_desc_enable to %d\n", val);
2020 hsotg->core_params->dma_desc_enable = val;
2024 int dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg *hsotg,
2029 if (DWC2_PARAM_TEST(val, 0, 1)) {
2032 "Wrong value for host_support_fs_low_power\n");
2034 "host_support_fs_low_power must be 0 or 1\n");
2038 "Setting host_support_fs_low_power to %d\n", val);
2042 hsotg->core_params->host_support_fs_ls_low_power = val;
2046 int dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, int val)
2051 if (val > 0 && !hsotg->hw_params.enable_dynamic_fifo)
2059 "%d invalid for enable_dynamic_fifo parameter. Check HW configuration.\n",
2061 val = hsotg->hw_params.enable_dynamic_fifo;
2062 dev_dbg(hsotg->dev, "Setting enable_dynamic_fifo to %d\n", val);
2066 hsotg->core_params->enable_dynamic_fifo = val;
2070 int dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val)
2075 if (val < 16 || val > hsotg->hw_params.host_rx_fifo_size)
2081 "%d invalid for host_rx_fifo_size. Check HW configuration.\n",
2083 val = hsotg->hw_params.host_rx_fifo_size;
2084 dev_dbg(hsotg->dev, "Setting host_rx_fifo_size to %d\n", val);
2088 hsotg->core_params->host_rx_fifo_size = val;
2092 int dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val)
2097 if (val < 16 || val > hsotg->hw_params.host_nperio_tx_fifo_size)
2103 "%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n",
2105 val = hsotg->hw_params.host_nperio_tx_fifo_size;
2106 dev_dbg(hsotg->dev, "Setting host_nperio_tx_fifo_size to %d\n",
2111 hsotg->core_params->host_nperio_tx_fifo_size = val;
2115 int dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val)
2120 if (val < 16 || val > hsotg->hw_params.host_perio_tx_fifo_size)
2126 "%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n",
2128 val = hsotg->hw_params.host_perio_tx_fifo_size;
2129 dev_dbg(hsotg->dev, "Setting host_perio_tx_fifo_size to %d\n",
2134 hsotg->core_params->host_perio_tx_fifo_size = val;
2138 int dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val)
2143 if (val < 2047 || val > hsotg->hw_params.max_transfer_size)
2149 "%d invalid for max_transfer_size. Check HW configuration.\n",
2151 val = hsotg->hw_params.max_transfer_size;
2152 dev_dbg(hsotg->dev, "Setting max_transfer_size to %d\n", val);
2156 hsotg->core_params->max_transfer_size = val;
2160 int dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val)
2165 if (val < 15 || val > hsotg->hw_params.max_packet_count)
2171 "%d invalid for max_packet_count. Check HW configuration.\n",
2173 val = hsotg->hw_params.max_packet_count;
2174 dev_dbg(hsotg->dev, "Setting max_packet_count to %d\n", val);
2178 hsotg->core_params->max_packet_count = val;
2182 int dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val)
2187 if (val < 1 || val > hsotg->hw_params.host_channels)
2193 "%d invalid for host_channels. Check HW configuration.\n",
2195 val = hsotg->hw_params.host_channels;
2196 dev_dbg(hsotg->dev, "Setting host_channels to %d\n", val);
2200 hsotg->core_params->host_channels = val;
2204 int dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val)
2206 #ifndef NO_FS_PHY_HW_CHECKS
2208 u32 hs_phy_type, fs_phy_type;
2212 if (DWC2_PARAM_TEST(val, DWC2_PHY_TYPE_PARAM_FS,
2213 DWC2_PHY_TYPE_PARAM_ULPI)) {
2215 dev_err(hsotg->dev, "Wrong value for phy_type\n");
2216 dev_err(hsotg->dev, "phy_type must be 0, 1 or 2\n");
2219 #ifndef NO_FS_PHY_HW_CHECKS
2222 val = DWC2_PHY_TYPE_PARAM_FS;
2223 dev_dbg(hsotg->dev, "Setting phy_type to %d\n", val);
2228 #ifndef NO_FS_PHY_HW_CHECKS
2229 hs_phy_type = hsotg->hw_params.hs_phy_type;
2230 fs_phy_type = hsotg->hw_params.fs_phy_type;
2231 if (val == DWC2_PHY_TYPE_PARAM_UTMI &&
2232 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
2233 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
2235 else if (val == DWC2_PHY_TYPE_PARAM_ULPI &&
2236 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI ||
2237 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
2239 else if (val == DWC2_PHY_TYPE_PARAM_FS &&
2240 fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
2246 "%d invalid for phy_type. Check HW configuration.\n",
2248 val = DWC2_PHY_TYPE_PARAM_FS;
2249 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) {
2250 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
2251 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)
2252 val = DWC2_PHY_TYPE_PARAM_UTMI;
2254 val = DWC2_PHY_TYPE_PARAM_ULPI;
2256 dev_dbg(hsotg->dev, "Setting phy_type to %d\n", val);
2261 hsotg->core_params->phy_type = val;
2265 static int dwc2_get_param_phy_type(struct dwc2_hsotg *hsotg)
2267 return hsotg->core_params->phy_type;
2270 int dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val)
2275 if (DWC2_PARAM_TEST(val, 0, 1)) {
2277 dev_err(hsotg->dev, "Wrong value for speed parameter\n");
2278 dev_err(hsotg->dev, "max_speed parameter must be 0 or 1\n");
2283 if (val == DWC2_SPEED_PARAM_HIGH &&
2284 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS)
2290 "%d invalid for speed parameter. Check HW configuration.\n",
2292 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS ?
2293 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH;
2294 dev_dbg(hsotg->dev, "Setting speed to %d\n", val);
2298 hsotg->core_params->speed = val;
2302 int dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, int val)
2307 if (DWC2_PARAM_TEST(val, DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ,
2308 DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)) {
2311 "Wrong value for host_ls_low_power_phy_clk parameter\n");
2313 "host_ls_low_power_phy_clk must be 0 or 1\n");
2318 if (val == DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ &&
2319 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS)
2325 "%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n",
2327 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS
2328 ? DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ
2329 : DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ;
2330 dev_dbg(hsotg->dev, "Setting host_ls_low_power_phy_clk to %d\n",
2335 hsotg->core_params->host_ls_low_power_phy_clk = val;
2339 int dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val)
2343 if (DWC2_PARAM_TEST(val, 0, 1)) {
2345 dev_err(hsotg->dev, "Wrong value for phy_ulpi_ddr\n");
2346 dev_err(hsotg->dev, "phy_upli_ddr must be 0 or 1\n");
2349 dev_dbg(hsotg->dev, "Setting phy_upli_ddr to %d\n", val);
2353 hsotg->core_params->phy_ulpi_ddr = val;
2357 int dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val)
2361 if (DWC2_PARAM_TEST(val, 0, 1)) {
2364 "Wrong value for phy_ulpi_ext_vbus\n");
2366 "phy_ulpi_ext_vbus must be 0 or 1\n");
2369 dev_dbg(hsotg->dev, "Setting phy_ulpi_ext_vbus to %d\n", val);
2373 hsotg->core_params->phy_ulpi_ext_vbus = val;
2377 int dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val)
2382 switch (hsotg->hw_params.utmi_phy_data_width) {
2383 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8:
2386 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16:
2387 valid = (val == 16);
2389 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16:
2390 valid = (val == 8 || val == 16);
2397 "%d invalid for phy_utmi_width. Check HW configuration.\n",
2400 val = (hsotg->hw_params.utmi_phy_data_width ==
2401 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
2402 dev_dbg(hsotg->dev, "Setting phy_utmi_width to %d\n", val);
2406 hsotg->core_params->phy_utmi_width = val;
2410 int dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val)
2414 if (DWC2_PARAM_TEST(val, 0, 1)) {
2416 dev_err(hsotg->dev, "Wrong value for ulpi_fs_ls\n");
2417 dev_err(hsotg->dev, "ulpi_fs_ls must be 0 or 1\n");
2420 dev_dbg(hsotg->dev, "Setting ulpi_fs_ls to %d\n", val);
2424 hsotg->core_params->ulpi_fs_ls = val;
2428 int dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val)
2432 if (DWC2_PARAM_TEST(val, 0, 1)) {
2434 dev_err(hsotg->dev, "Wrong value for ts_dline\n");
2435 dev_err(hsotg->dev, "ts_dline must be 0 or 1\n");
2438 dev_dbg(hsotg->dev, "Setting ts_dline to %d\n", val);
2442 hsotg->core_params->ts_dline = val;
2446 int dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val)
2448 #ifndef NO_FS_PHY_HW_CHECKS
2453 if (DWC2_PARAM_TEST(val, 0, 1)) {
2455 dev_err(hsotg->dev, "Wrong value for i2c_enable\n");
2456 dev_err(hsotg->dev, "i2c_enable must be 0 or 1\n");
2459 #ifndef NO_FS_PHY_HW_CHECKS
2463 dev_dbg(hsotg->dev, "Setting i2c_enable to %d\n", val);
2468 #ifndef NO_FS_PHY_HW_CHECKS
2469 if (val == 1 && !(hsotg->hw_params.i2c_enable))
2475 "%d invalid for i2c_enable. Check HW configuration.\n",
2477 val = hsotg->hw_params.i2c_enable;
2478 dev_dbg(hsotg->dev, "Setting i2c_enable to %d\n", val);
2483 hsotg->core_params->i2c_enable = val;
2487 int dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, int val)
2492 if (DWC2_PARAM_TEST(val, 0, 1)) {
2495 "Wrong value for en_multiple_tx_fifo,\n");
2497 "en_multiple_tx_fifo must be 0 or 1\n");
2502 if (val == 1 && !hsotg->hw_params.en_multiple_tx_fifo)
2508 "%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n",
2510 val = hsotg->hw_params.en_multiple_tx_fifo;
2511 dev_dbg(hsotg->dev, "Setting en_multiple_tx_fifo to %d\n", val);
2515 hsotg->core_params->en_multiple_tx_fifo = val;
2519 int dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val)
2524 if (DWC2_PARAM_TEST(val, 0, 1)) {
2527 "'%d' invalid for parameter reload_ctl\n", val);
2528 dev_err(hsotg->dev, "reload_ctl must be 0 or 1\n");
2533 if (val == 1 && hsotg->hw_params.snpsid < DWC2_CORE_REV_2_92a)
2539 "%d invalid for parameter reload_ctl. Check HW configuration.\n",
2541 val = hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_92a;
2542 dev_dbg(hsotg->dev, "Setting reload_ctl to %d\n", val);
2546 hsotg->core_params->reload_ctl = val;
2550 int dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val)
2553 hsotg->core_params->ahbcfg = val;
2555 hsotg->core_params->ahbcfg = GAHBCFG_HBSTLEN_INCR4 <<
2556 GAHBCFG_HBSTLEN_SHIFT;
2560 int dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val)
2564 if (DWC2_PARAM_TEST(val, 0, 1)) {
2567 "'%d' invalid for parameter otg_ver\n", val);
2569 "otg_ver must be 0 (for OTG 1.3 support) or 1 (for OTG 2.0 support)\n");
2572 dev_dbg(hsotg->dev, "Setting otg_ver to %d\n", val);
2576 hsotg->core_params->otg_ver = val;
2581 * During device initialization, read various hardware configuration
2582 * registers and interpret the contents.
2584 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
2586 struct dwc2_hw_params *hw = &hsotg->hw_params;
2588 u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;
2589 u32 hptxfsiz, grxfsiz, gnptxfsiz;
2593 * Attempt to ensure this device is really a DWC_otg Controller.
2594 * Read and verify the GSNPSID register contents. The value should be
2595 * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3",
2596 * as in "OTG version 2.xx" or "OTG version 3.xx".
2598 hw->snpsid = readl(hsotg->regs + GSNPSID);
2599 if ((hw->snpsid & 0xfffff000) != 0x4f542000 &&
2600 (hw->snpsid & 0xfffff000) != 0x4f543000) {
2601 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n",
2606 dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n",
2607 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf,
2608 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid);
2610 hwcfg1 = readl(hsotg->regs + GHWCFG1);
2611 hwcfg2 = readl(hsotg->regs + GHWCFG2);
2612 hwcfg3 = readl(hsotg->regs + GHWCFG3);
2613 hwcfg4 = readl(hsotg->regs + GHWCFG4);
2614 gnptxfsiz = readl(hsotg->regs + GNPTXFSIZ);
2615 grxfsiz = readl(hsotg->regs + GRXFSIZ);
2617 dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hwcfg1);
2618 dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hwcfg2);
2619 dev_dbg(hsotg->dev, "hwcfg3=%08x\n", hwcfg3);
2620 dev_dbg(hsotg->dev, "hwcfg4=%08x\n", hwcfg4);
2621 dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz);
2622 dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz);
2624 /* Force host mode to get HPTXFSIZ exact power on value */
2625 gusbcfg = readl(hsotg->regs + GUSBCFG);
2626 gusbcfg |= GUSBCFG_FORCEHOSTMODE;
2627 writel(gusbcfg, hsotg->regs + GUSBCFG);
2628 usleep_range(100000, 150000);
2630 hptxfsiz = readl(hsotg->regs + HPTXFSIZ);
2631 dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz);
2632 gusbcfg = readl(hsotg->regs + GUSBCFG);
2633 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
2634 writel(gusbcfg, hsotg->regs + GUSBCFG);
2635 usleep_range(100000, 150000);
2638 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
2639 GHWCFG2_OP_MODE_SHIFT;
2640 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
2641 GHWCFG2_ARCHITECTURE_SHIFT;
2642 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO);
2643 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >>
2644 GHWCFG2_NUM_HOST_CHAN_SHIFT);
2645 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
2646 GHWCFG2_HS_PHY_TYPE_SHIFT;
2647 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
2648 GHWCFG2_FS_PHY_TYPE_SHIFT;
2649 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >>
2650 GHWCFG2_NUM_DEV_EP_SHIFT;
2651 hw->nperio_tx_q_depth =
2652 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >>
2653 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1;
2654 hw->host_perio_tx_q_depth =
2655 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >>
2656 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1;
2657 hw->dev_token_q_depth =
2658 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >>
2659 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT;
2662 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >>
2663 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT;
2664 hw->max_transfer_size = (1 << (width + 11)) - 1;
2665 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >>
2666 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
2667 hw->max_packet_count = (1 << (width + 4)) - 1;
2668 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C);
2669 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >>
2670 GHWCFG3_DFIFO_DEPTH_SHIFT;
2673 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN);
2674 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >>
2675 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT;
2676 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA);
2677 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ);
2678 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >>
2679 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT;
2682 hw->host_rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >>
2683 GRXFSIZ_DEPTH_SHIFT;
2684 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
2685 FIFOSIZE_DEPTH_SHIFT;
2686 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >>
2687 FIFOSIZE_DEPTH_SHIFT;
2689 dev_dbg(hsotg->dev, "Detected values from hardware:\n");
2690 dev_dbg(hsotg->dev, " op_mode=%d\n",
2692 dev_dbg(hsotg->dev, " arch=%d\n",
2694 dev_dbg(hsotg->dev, " dma_desc_enable=%d\n",
2695 hw->dma_desc_enable);
2696 dev_dbg(hsotg->dev, " power_optimized=%d\n",
2697 hw->power_optimized);
2698 dev_dbg(hsotg->dev, " i2c_enable=%d\n",
2700 dev_dbg(hsotg->dev, " hs_phy_type=%d\n",
2702 dev_dbg(hsotg->dev, " fs_phy_type=%d\n",
2704 dev_dbg(hsotg->dev, " utmi_phy_data_wdith=%d\n",
2705 hw->utmi_phy_data_width);
2706 dev_dbg(hsotg->dev, " num_dev_ep=%d\n",
2708 dev_dbg(hsotg->dev, " num_dev_perio_in_ep=%d\n",
2709 hw->num_dev_perio_in_ep);
2710 dev_dbg(hsotg->dev, " host_channels=%d\n",
2712 dev_dbg(hsotg->dev, " max_transfer_size=%d\n",
2713 hw->max_transfer_size);
2714 dev_dbg(hsotg->dev, " max_packet_count=%d\n",
2715 hw->max_packet_count);
2716 dev_dbg(hsotg->dev, " nperio_tx_q_depth=0x%0x\n",
2717 hw->nperio_tx_q_depth);
2718 dev_dbg(hsotg->dev, " host_perio_tx_q_depth=0x%0x\n",
2719 hw->host_perio_tx_q_depth);
2720 dev_dbg(hsotg->dev, " dev_token_q_depth=0x%0x\n",
2721 hw->dev_token_q_depth);
2722 dev_dbg(hsotg->dev, " enable_dynamic_fifo=%d\n",
2723 hw->enable_dynamic_fifo);
2724 dev_dbg(hsotg->dev, " en_multiple_tx_fifo=%d\n",
2725 hw->en_multiple_tx_fifo);
2726 dev_dbg(hsotg->dev, " total_fifo_size=%d\n",
2727 hw->total_fifo_size);
2728 dev_dbg(hsotg->dev, " host_rx_fifo_size=%d\n",
2729 hw->host_rx_fifo_size);
2730 dev_dbg(hsotg->dev, " host_nperio_tx_fifo_size=%d\n",
2731 hw->host_nperio_tx_fifo_size);
2732 dev_dbg(hsotg->dev, " host_perio_tx_fifo_size=%d\n",
2733 hw->host_perio_tx_fifo_size);
2734 dev_dbg(hsotg->dev, "\n");
2739 int dwc2_set_param_uframe_sched(struct dwc2_hsotg *hsotg, int val)
2743 if (DWC2_PARAM_TEST(val, 0, 1)) {
2746 "'%d' invalid for parameter uframe_sched\n",
2748 dev_err(hsotg->dev, "uframe_sched must be 0 or 1\n");
2751 dev_dbg(hsotg->dev, "Setting uframe_sched to %d\n", val);
2755 hsotg->core_params->uframe_sched = val;
2760 * This function is called during module intialization to pass module parameters
2761 * for the DWC_otg core. It returns non-0 if any parameters are invalid.
2763 int dwc2_set_parameters(struct dwc2_hsotg *hsotg,
2764 const struct dwc2_core_params *params)
2768 dev_dbg(hsotg->dev, "%s()\n", __func__);
2770 retval |= dwc2_set_param_otg_cap(hsotg, params->otg_cap);
2771 retval |= dwc2_set_param_dma_enable(hsotg, params->dma_enable);
2772 retval |= dwc2_set_param_dma_desc_enable(hsotg,
2773 params->dma_desc_enable);
2774 retval |= dwc2_set_param_host_support_fs_ls_low_power(hsotg,
2775 params->host_support_fs_ls_low_power);
2776 retval |= dwc2_set_param_enable_dynamic_fifo(hsotg,
2777 params->enable_dynamic_fifo);
2778 retval |= dwc2_set_param_host_rx_fifo_size(hsotg,
2779 params->host_rx_fifo_size);
2780 retval |= dwc2_set_param_host_nperio_tx_fifo_size(hsotg,
2781 params->host_nperio_tx_fifo_size);
2782 retval |= dwc2_set_param_host_perio_tx_fifo_size(hsotg,
2783 params->host_perio_tx_fifo_size);
2784 retval |= dwc2_set_param_max_transfer_size(hsotg,
2785 params->max_transfer_size);
2786 retval |= dwc2_set_param_max_packet_count(hsotg,
2787 params->max_packet_count);
2788 retval |= dwc2_set_param_host_channels(hsotg, params->host_channels);
2789 retval |= dwc2_set_param_phy_type(hsotg, params->phy_type);
2790 retval |= dwc2_set_param_speed(hsotg, params->speed);
2791 retval |= dwc2_set_param_host_ls_low_power_phy_clk(hsotg,
2792 params->host_ls_low_power_phy_clk);
2793 retval |= dwc2_set_param_phy_ulpi_ddr(hsotg, params->phy_ulpi_ddr);
2794 retval |= dwc2_set_param_phy_ulpi_ext_vbus(hsotg,
2795 params->phy_ulpi_ext_vbus);
2796 retval |= dwc2_set_param_phy_utmi_width(hsotg, params->phy_utmi_width);
2797 retval |= dwc2_set_param_ulpi_fs_ls(hsotg, params->ulpi_fs_ls);
2798 retval |= dwc2_set_param_ts_dline(hsotg, params->ts_dline);
2799 retval |= dwc2_set_param_i2c_enable(hsotg, params->i2c_enable);
2800 retval |= dwc2_set_param_en_multiple_tx_fifo(hsotg,
2801 params->en_multiple_tx_fifo);
2802 retval |= dwc2_set_param_reload_ctl(hsotg, params->reload_ctl);
2803 retval |= dwc2_set_param_ahbcfg(hsotg, params->ahbcfg);
2804 retval |= dwc2_set_param_otg_ver(hsotg, params->otg_ver);
2805 retval |= dwc2_set_param_uframe_sched(hsotg, params->uframe_sched);
2810 u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg)
2812 return (u16)(hsotg->core_params->otg_ver == 1 ? 0x0200 : 0x0103);
2815 int dwc2_check_core_status(struct dwc2_hsotg *hsotg)
2817 if (readl(hsotg->regs + GSNPSID) == 0xffffffff)
2824 * dwc2_enable_global_interrupts() - Enables the controller's Global
2825 * Interrupt in the AHB Config register
2827 * @hsotg: Programming view of DWC_otg controller
2829 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)
2831 u32 ahbcfg = readl(hsotg->regs + GAHBCFG);
2833 ahbcfg |= GAHBCFG_GLBL_INTR_EN;
2834 writel(ahbcfg, hsotg->regs + GAHBCFG);
2838 * dwc2_disable_global_interrupts() - Disables the controller's Global
2839 * Interrupt in the AHB Config register
2841 * @hsotg: Programming view of DWC_otg controller
2843 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)
2845 u32 ahbcfg = readl(hsotg->regs + GAHBCFG);
2847 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
2848 writel(ahbcfg, hsotg->regs + GAHBCFG);
2851 MODULE_DESCRIPTION("DESIGNWARE HS OTG Core");
2852 MODULE_AUTHOR("Synopsys, Inc.");
2853 MODULE_LICENSE("Dual BSD/GPL");