2 * hcd.c - DesignWare HS OTG Controller host-mode routines
4 * Copyright (C) 2004-2013 Synopsys, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 * This file contains the core HCD code, and implements the Linux hc_driver
41 #include <linux/kernel.h>
42 #include <linux/module.h>
43 #include <linux/spinlock.h>
44 #include <linux/interrupt.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/delay.h>
48 #include <linux/slab.h>
49 #include <linux/usb.h>
51 #include <linux/usb/hcd.h>
52 #include <linux/usb/ch11.h>
58 * dwc2_dump_channel_info() - Prints the state of a host channel
60 * @hsotg: Programming view of DWC_otg controller
61 * @chan: Pointer to the channel to dump
63 * Must be called with interrupt disabled and spinlock held
65 * NOTE: This function will be removed once the peripheral controller code
66 * is integrated and the driver is stable
68 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
69 struct dwc2_host_chan *chan)
72 int num_channels = hsotg->core_params->host_channels;
83 hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
84 hcsplt = readl(hsotg->regs + HCSPLT(chan->hc_num));
85 hctsiz = readl(hsotg->regs + HCTSIZ(chan->hc_num));
86 hc_dma = readl(hsotg->regs + HCDMA(chan->hc_num));
88 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan);
89 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n",
91 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n",
93 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
94 chan->dev_addr, chan->ep_num, chan->ep_is_in);
95 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
96 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
97 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start);
98 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started);
99 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
100 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
101 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
102 (unsigned long)chan->xfer_dma);
103 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
104 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
105 dev_dbg(hsotg->dev, " NP inactive sched:\n");
106 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,
108 dev_dbg(hsotg->dev, " %p\n", qh);
109 dev_dbg(hsotg->dev, " NP active sched:\n");
110 list_for_each_entry(qh, &hsotg->non_periodic_sched_active,
112 dev_dbg(hsotg->dev, " %p\n", qh);
113 dev_dbg(hsotg->dev, " Channels:\n");
114 for (i = 0; i < num_channels; i++) {
115 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
117 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan);
119 #endif /* VERBOSE_DEBUG */
123 * Processes all the URBs in a single list of QHs. Completes them with
124 * -ETIMEDOUT and frees the QTD.
126 * Must be called with interrupt disabled and spinlock held
128 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg,
129 struct list_head *qh_list)
131 struct dwc2_qh *qh, *qh_tmp;
132 struct dwc2_qtd *qtd, *qtd_tmp;
134 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
135 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
137 dwc2_host_complete(hsotg, qtd, -ETIMEDOUT);
138 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
143 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg,
144 struct list_head *qh_list)
146 struct dwc2_qtd *qtd, *qtd_tmp;
147 struct dwc2_qh *qh, *qh_tmp;
151 /* The list hasn't been initialized yet */
154 spin_lock_irqsave(&hsotg->lock, flags);
156 /* Ensure there are no QTDs or URBs left */
157 dwc2_kill_urbs_in_qh_list(hsotg, qh_list);
159 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
160 dwc2_hcd_qh_unlink(hsotg, qh);
162 /* Free each QTD in the QH's QTD list */
163 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
165 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
167 spin_unlock_irqrestore(&hsotg->lock, flags);
168 dwc2_hcd_qh_free(hsotg, qh);
169 spin_lock_irqsave(&hsotg->lock, flags);
172 spin_unlock_irqrestore(&hsotg->lock, flags);
176 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
177 * and periodic schedules. The QTD associated with each URB is removed from
178 * the schedule and freed. This function may be called when a disconnect is
179 * detected or when the HCD is being stopped.
181 * Must be called with interrupt disabled and spinlock held
183 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)
185 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);
186 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);
187 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);
188 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
189 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned);
190 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued);
194 * dwc2_hcd_start() - Starts the HCD when switching to Host mode
196 * @hsotg: Pointer to struct dwc2_hsotg
198 void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
202 if (hsotg->op_state == OTG_STATE_B_HOST) {
204 * Reset the port. During a HNP mode switch the reset
205 * needs to occur within 1ms and have a duration of at
208 hprt0 = dwc2_read_hprt0(hsotg);
210 writel(hprt0, hsotg->regs + HPRT0);
213 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
214 msecs_to_jiffies(50));
217 /* Must be called with interrupt disabled and spinlock held */
218 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
220 int num_channels = hsotg->core_params->host_channels;
221 struct dwc2_host_chan *channel;
225 if (hsotg->core_params->dma_enable <= 0) {
226 /* Flush out any channel requests in slave mode */
227 for (i = 0; i < num_channels; i++) {
228 channel = hsotg->hc_ptr_array[i];
229 if (!list_empty(&channel->hc_list_entry))
231 hcchar = readl(hsotg->regs + HCCHAR(i));
232 if (hcchar & HCCHAR_CHENA) {
233 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
234 hcchar |= HCCHAR_CHDIS;
235 writel(hcchar, hsotg->regs + HCCHAR(i));
240 for (i = 0; i < num_channels; i++) {
241 channel = hsotg->hc_ptr_array[i];
242 if (!list_empty(&channel->hc_list_entry))
244 hcchar = readl(hsotg->regs + HCCHAR(i));
245 if (hcchar & HCCHAR_CHENA) {
246 /* Halt the channel */
247 hcchar |= HCCHAR_CHDIS;
248 writel(hcchar, hsotg->regs + HCCHAR(i));
251 dwc2_hc_cleanup(hsotg, channel);
252 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
254 * Added for Descriptor DMA to prevent channel double cleanup in
255 * release_channel_ddma(), which is called from ep_disable when
263 * dwc2_hcd_disconnect() - Handles disconnect of the HCD
265 * @hsotg: Pointer to struct dwc2_hsotg
267 * Must be called with interrupt disabled and spinlock held
269 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg)
273 /* Set status flags for the hub driver */
274 hsotg->flags.b.port_connect_status_change = 1;
275 hsotg->flags.b.port_connect_status = 0;
278 * Shutdown any transfers in process by clearing the Tx FIFO Empty
279 * interrupt mask and status bits and disabling subsequent host
280 * channel interrupts.
282 intr = readl(hsotg->regs + GINTMSK);
283 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
284 writel(intr, hsotg->regs + GINTMSK);
285 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
286 writel(intr, hsotg->regs + GINTSTS);
289 * Turn off the vbus power only if the core has transitioned to device
290 * mode. If still in host mode, need to keep power on to detect a
293 if (dwc2_is_device_mode(hsotg)) {
294 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
295 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
296 writel(0, hsotg->regs + HPRT0);
299 dwc2_disable_host_interrupts(hsotg);
302 /* Respond with an error status to all URBs in the schedule */
303 dwc2_kill_all_urbs(hsotg);
305 if (dwc2_is_host_mode(hsotg))
306 /* Clean up any host channels that were in use */
307 dwc2_hcd_cleanup_channels(hsotg);
309 dwc2_host_disconnect(hsotg);
313 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
315 * @hsotg: Pointer to struct dwc2_hsotg
317 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg)
319 if (hsotg->lx_state == DWC2_L2)
320 hsotg->flags.b.port_suspend_change = 1;
322 hsotg->flags.b.port_l1_change = 1;
326 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
328 * @hsotg: Pointer to struct dwc2_hsotg
330 * Must be called with interrupt disabled and spinlock held
332 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
334 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n");
337 * The root hub should be disconnected before this function is called.
338 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
339 * and the QH lists (via ..._hcd_endpoint_disable).
342 /* Turn off all host-specific interrupts */
343 dwc2_disable_host_interrupts(hsotg);
345 /* Turn off the vbus power */
346 dev_dbg(hsotg->dev, "PortPower off\n");
347 writel(0, hsotg->regs + HPRT0);
350 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
351 struct dwc2_hcd_urb *urb, void **ep_handle,
354 struct dwc2_qtd *qtd;
359 if (!hsotg->flags.b.port_connect_status) {
360 /* No longer connected */
361 dev_err(hsotg->dev, "Not connected\n");
365 qtd = kzalloc(sizeof(*qtd), mem_flags);
369 dwc2_hcd_qtd_init(qtd, urb);
370 retval = dwc2_hcd_qtd_add(hsotg, qtd, (struct dwc2_qh **)ep_handle,
374 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n",
380 intr_mask = readl(hsotg->regs + GINTMSK);
381 if (!(intr_mask & GINTSTS_SOF) && retval == 0) {
382 enum dwc2_transaction_type tr_type;
384 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK &&
385 !(qtd->urb->flags & URB_GIVEBACK_ASAP))
387 * Do not schedule SG transactions until qtd has
388 * URB_GIVEBACK_ASAP set
392 spin_lock_irqsave(&hsotg->lock, flags);
393 tr_type = dwc2_hcd_select_transactions(hsotg);
394 if (tr_type != DWC2_TRANSACTION_NONE)
395 dwc2_hcd_queue_transactions(hsotg, tr_type);
396 spin_unlock_irqrestore(&hsotg->lock, flags);
402 /* Must be called with interrupt disabled and spinlock held */
403 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
404 struct dwc2_hcd_urb *urb)
407 struct dwc2_qtd *urb_qtd;
411 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n");
417 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n");
423 if (urb_qtd->in_process && qh->channel) {
424 dwc2_dump_channel_info(hsotg, qh->channel);
426 /* The QTD is in process (it has been assigned to a channel) */
427 if (hsotg->flags.b.port_connect_status)
429 * If still connected (i.e. in host mode), halt the
430 * channel so it can be used for other transfers. If
431 * no longer connected, the host registers can't be
432 * written to halt the channel since the core is in
435 dwc2_hc_halt(hsotg, qh->channel,
436 DWC2_HC_XFER_URB_DEQUEUE);
440 * Free the QTD and clean up the associated QH. Leave the QH in the
441 * schedule if it has any remaining QTDs.
443 if (hsotg->core_params->dma_desc_enable <= 0) {
444 u8 in_process = urb_qtd->in_process;
446 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
448 dwc2_hcd_qh_deactivate(hsotg, qh, 0);
450 } else if (list_empty(&qh->qtd_list)) {
451 dwc2_hcd_qh_unlink(hsotg, qh);
454 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
460 /* Must NOT be called with interrupt disabled or spinlock held */
461 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg,
462 struct usb_host_endpoint *ep, int retry)
464 struct dwc2_qtd *qtd, *qtd_tmp;
469 spin_lock_irqsave(&hsotg->lock, flags);
477 while (!list_empty(&qh->qtd_list) && retry--) {
480 "## timeout in dwc2_hcd_endpoint_disable() ##\n");
485 spin_unlock_irqrestore(&hsotg->lock, flags);
486 usleep_range(20000, 40000);
487 spin_lock_irqsave(&hsotg->lock, flags);
495 dwc2_hcd_qh_unlink(hsotg, qh);
497 /* Free each QTD in the QH's QTD list */
498 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry)
499 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
502 spin_unlock_irqrestore(&hsotg->lock, flags);
503 dwc2_hcd_qh_free(hsotg, qh);
509 spin_unlock_irqrestore(&hsotg->lock, flags);
514 /* Must be called with interrupt disabled and spinlock held */
515 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg,
516 struct usb_host_endpoint *ep)
518 struct dwc2_qh *qh = ep->hcpriv;
523 qh->data_toggle = DWC2_HC_PID_DATA0;
529 * Initializes dynamic portions of the DWC_otg HCD state
531 * Must be called with interrupt disabled and spinlock held
533 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
535 struct dwc2_host_chan *chan, *chan_tmp;
539 hsotg->flags.d32 = 0;
540 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
542 if (hsotg->core_params->uframe_sched > 0) {
543 hsotg->available_host_channels =
544 hsotg->core_params->host_channels;
546 hsotg->non_periodic_channels = 0;
547 hsotg->periodic_channels = 0;
551 * Put all channels in the free channel list and clean up channel
554 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list,
556 list_del_init(&chan->hc_list_entry);
558 num_channels = hsotg->core_params->host_channels;
559 for (i = 0; i < num_channels; i++) {
560 chan = hsotg->hc_ptr_array[i];
561 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
562 dwc2_hc_cleanup(hsotg, chan);
565 /* Initialize the DWC core for host mode operation */
566 dwc2_core_host_init(hsotg);
569 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg,
570 struct dwc2_host_chan *chan,
571 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
573 int hub_addr, hub_port;
576 chan->xact_pos = qtd->isoc_split_pos;
577 chan->complete_split = qtd->complete_split;
578 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
579 chan->hub_addr = (u8)hub_addr;
580 chan->hub_port = (u8)hub_port;
583 static void *dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
584 struct dwc2_host_chan *chan,
585 struct dwc2_qtd *qtd, void *bufptr)
587 struct dwc2_hcd_urb *urb = qtd->urb;
588 struct dwc2_hcd_iso_packet_desc *frame_desc;
590 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
591 case USB_ENDPOINT_XFER_CONTROL:
592 chan->ep_type = USB_ENDPOINT_XFER_CONTROL;
594 switch (qtd->control_phase) {
595 case DWC2_CONTROL_SETUP:
596 dev_vdbg(hsotg->dev, " Control setup transaction\n");
599 chan->data_pid_start = DWC2_HC_PID_SETUP;
600 if (hsotg->core_params->dma_enable > 0)
601 chan->xfer_dma = urb->setup_dma;
603 chan->xfer_buf = urb->setup_packet;
608 case DWC2_CONTROL_DATA:
609 dev_vdbg(hsotg->dev, " Control data transaction\n");
610 chan->data_pid_start = qtd->data_toggle;
613 case DWC2_CONTROL_STATUS:
615 * Direction is opposite of data direction or IN if no
618 dev_vdbg(hsotg->dev, " Control status transaction\n");
619 if (urb->length == 0)
623 dwc2_hcd_is_pipe_out(&urb->pipe_info);
626 chan->data_pid_start = DWC2_HC_PID_DATA1;
628 if (hsotg->core_params->dma_enable > 0)
629 chan->xfer_dma = hsotg->status_buf_dma;
631 chan->xfer_buf = hsotg->status_buf;
637 case USB_ENDPOINT_XFER_BULK:
638 chan->ep_type = USB_ENDPOINT_XFER_BULK;
641 case USB_ENDPOINT_XFER_INT:
642 chan->ep_type = USB_ENDPOINT_XFER_INT;
645 case USB_ENDPOINT_XFER_ISOC:
646 chan->ep_type = USB_ENDPOINT_XFER_ISOC;
647 if (hsotg->core_params->dma_desc_enable > 0)
650 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
651 frame_desc->status = 0;
653 if (hsotg->core_params->dma_enable > 0) {
654 chan->xfer_dma = urb->dma;
655 chan->xfer_dma += frame_desc->offset +
656 qtd->isoc_split_offset;
658 chan->xfer_buf = urb->buf;
659 chan->xfer_buf += frame_desc->offset +
660 qtd->isoc_split_offset;
663 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset;
665 /* For non-dword aligned buffers */
666 if (hsotg->core_params->dma_enable > 0 &&
667 (chan->xfer_dma & 0x3))
668 bufptr = (u8 *)urb->buf + frame_desc->offset +
669 qtd->isoc_split_offset;
673 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) {
674 if (chan->xfer_len <= 188)
675 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL;
677 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN;
685 static int dwc2_hc_setup_align_buf(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
686 struct dwc2_host_chan *chan, void *bufptr)
690 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC)
691 buf_size = hsotg->core_params->max_transfer_size;
695 if (!qh->dw_align_buf) {
696 qh->dw_align_buf = dma_alloc_coherent(hsotg->dev, buf_size,
697 &qh->dw_align_buf_dma,
699 if (!qh->dw_align_buf)
703 if (!chan->ep_is_in && chan->xfer_len) {
704 dma_sync_single_for_cpu(hsotg->dev, chan->xfer_dma, buf_size,
706 memcpy(qh->dw_align_buf, bufptr, chan->xfer_len);
707 dma_sync_single_for_device(hsotg->dev, chan->xfer_dma, buf_size,
711 chan->align_buf = qh->dw_align_buf_dma;
716 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
717 * channel and initializes the host channel to perform the transactions. The
718 * host channel is removed from the free list.
720 * @hsotg: The HCD state structure
721 * @qh: Transactions from the first QTD for this QH are selected and assigned
722 * to a free host channel
724 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
726 struct dwc2_host_chan *chan;
727 struct dwc2_hcd_urb *urb;
728 struct dwc2_qtd *qtd;
732 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);
734 if (list_empty(&qh->qtd_list)) {
735 dev_dbg(hsotg->dev, "No QTDs in QH list\n");
739 if (list_empty(&hsotg->free_hc_list)) {
740 dev_dbg(hsotg->dev, "No free channel to assign\n");
744 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan,
747 /* Remove host channel from free list */
748 list_del_init(&chan->hc_list_entry);
750 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
756 * Use usb_pipedevice to determine device address. This address is
757 * 0 before the SET_ADDRESS command and the correct address afterward.
759 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info);
760 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info);
761 chan->speed = qh->dev_speed;
762 chan->max_packet = dwc2_max_packet(qh->maxp);
764 chan->xfer_started = 0;
765 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
766 chan->error_state = (qtd->error_count > 0);
767 chan->halt_on_queue = 0;
768 chan->halt_pending = 0;
772 * The following values may be modified in the transfer type section
773 * below. The xfer_len value may be reduced when the transfer is
774 * started to accommodate the max widths of the XferSize and PktCnt
775 * fields in the HCTSIZn register.
778 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0);
782 chan->do_ping = qh->ping_state;
784 chan->data_pid_start = qh->data_toggle;
785 chan->multi_count = 1;
787 if (urb->actual_length > urb->length &&
788 !dwc2_hcd_is_pipe_in(&urb->pipe_info))
789 urb->actual_length = urb->length;
791 if (hsotg->core_params->dma_enable > 0) {
792 chan->xfer_dma = urb->dma + urb->actual_length;
794 /* For non-dword aligned case */
795 if (hsotg->core_params->dma_desc_enable <= 0 &&
796 (chan->xfer_dma & 0x3))
797 bufptr = (u8 *)urb->buf + urb->actual_length;
799 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length;
802 chan->xfer_len = urb->length - urb->actual_length;
803 chan->xfer_count = 0;
805 /* Set the split attributes if required */
807 dwc2_hc_init_split(hsotg, chan, qtd, urb);
811 /* Set the transfer attributes */
812 bufptr = dwc2_hc_init_xfer(hsotg, chan, qtd, bufptr);
814 /* Non DWORD-aligned buffer case */
816 dev_vdbg(hsotg->dev, "Non-aligned buffer\n");
817 if (dwc2_hc_setup_align_buf(hsotg, qh, chan, bufptr)) {
819 "%s: Failed to allocate memory to handle non-dword aligned buffer\n",
821 /* Add channel back to free list */
823 chan->multi_count = 0;
824 list_add_tail(&chan->hc_list_entry,
825 &hsotg->free_hc_list);
834 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
835 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
837 * This value may be modified when the transfer is started
838 * to reflect the actual transfer length
840 chan->multi_count = dwc2_hb_mult(qh->maxp);
842 if (hsotg->core_params->dma_desc_enable > 0)
843 chan->desc_list_addr = qh->desc_list_dma;
845 dwc2_hc_init(hsotg, chan);
852 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
853 * schedule and assigns them to available host channels. Called from the HCD
854 * interrupt handler functions.
856 * @hsotg: The HCD state structure
858 * Return: The types of new transactions that were assigned to host channels
860 enum dwc2_transaction_type dwc2_hcd_select_transactions(
861 struct dwc2_hsotg *hsotg)
863 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE;
864 struct list_head *qh_ptr;
868 #ifdef DWC2_DEBUG_SOF
869 dev_vdbg(hsotg->dev, " Select Transactions\n");
872 /* Process entries in the periodic ready list */
873 qh_ptr = hsotg->periodic_sched_ready.next;
874 while (qh_ptr != &hsotg->periodic_sched_ready) {
875 if (list_empty(&hsotg->free_hc_list))
877 if (hsotg->core_params->uframe_sched > 0) {
878 if (hsotg->available_host_channels <= 1)
880 hsotg->available_host_channels--;
882 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
883 if (dwc2_assign_and_init_hc(hsotg, qh))
887 * Move the QH from the periodic ready schedule to the
888 * periodic assigned schedule
890 qh_ptr = qh_ptr->next;
891 list_move(&qh->qh_list_entry, &hsotg->periodic_sched_assigned);
892 ret_val = DWC2_TRANSACTION_PERIODIC;
896 * Process entries in the inactive portion of the non-periodic
897 * schedule. Some free host channels may not be used if they are
898 * reserved for periodic transfers.
900 num_channels = hsotg->core_params->host_channels;
901 qh_ptr = hsotg->non_periodic_sched_inactive.next;
902 while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
903 if (hsotg->core_params->uframe_sched <= 0 &&
904 hsotg->non_periodic_channels >= num_channels -
905 hsotg->periodic_channels)
907 if (list_empty(&hsotg->free_hc_list))
909 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
910 if (hsotg->core_params->uframe_sched > 0) {
911 if (hsotg->available_host_channels < 1)
913 hsotg->available_host_channels--;
916 if (dwc2_assign_and_init_hc(hsotg, qh))
920 * Move the QH from the non-periodic inactive schedule to the
921 * non-periodic active schedule
923 qh_ptr = qh_ptr->next;
924 list_move(&qh->qh_list_entry,
925 &hsotg->non_periodic_sched_active);
927 if (ret_val == DWC2_TRANSACTION_NONE)
928 ret_val = DWC2_TRANSACTION_NON_PERIODIC;
930 ret_val = DWC2_TRANSACTION_ALL;
932 if (hsotg->core_params->uframe_sched <= 0)
933 hsotg->non_periodic_channels++;
940 * dwc2_queue_transaction() - Attempts to queue a single transaction request for
941 * a host channel associated with either a periodic or non-periodic transfer
943 * @hsotg: The HCD state structure
944 * @chan: Host channel descriptor associated with either a periodic or
945 * non-periodic transfer
946 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO
947 * for periodic transfers or the non-periodic Tx FIFO
948 * for non-periodic transfers
950 * Return: 1 if a request is queued and more requests may be needed to
951 * complete the transfer, 0 if no more requests are required for this
952 * transfer, -1 if there is insufficient space in the Tx FIFO
954 * This function assumes that there is space available in the appropriate
955 * request queue. For an OUT transfer or SETUP transaction in Slave mode,
956 * it checks whether space is available in the appropriate Tx FIFO.
958 * Must be called with interrupt disabled and spinlock held
960 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
961 struct dwc2_host_chan *chan,
962 u16 fifo_dwords_avail)
966 if (hsotg->core_params->dma_enable > 0) {
967 if (hsotg->core_params->dma_desc_enable > 0) {
968 if (!chan->xfer_started ||
969 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
970 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
971 chan->qh->ping_state = 0;
973 } else if (!chan->xfer_started) {
974 dwc2_hc_start_transfer(hsotg, chan);
975 chan->qh->ping_state = 0;
977 } else if (chan->halt_pending) {
978 /* Don't queue a request if the channel has been halted */
979 } else if (chan->halt_on_queue) {
980 dwc2_hc_halt(hsotg, chan, chan->halt_status);
981 } else if (chan->do_ping) {
982 if (!chan->xfer_started)
983 dwc2_hc_start_transfer(hsotg, chan);
984 } else if (!chan->ep_is_in ||
985 chan->data_pid_start == DWC2_HC_PID_SETUP) {
986 if ((fifo_dwords_avail * 4) >= chan->max_packet) {
987 if (!chan->xfer_started) {
988 dwc2_hc_start_transfer(hsotg, chan);
991 retval = dwc2_hc_continue_transfer(hsotg, chan);
997 if (!chan->xfer_started) {
998 dwc2_hc_start_transfer(hsotg, chan);
1001 retval = dwc2_hc_continue_transfer(hsotg, chan);
1009 * Processes periodic channels for the next frame and queues transactions for
1010 * these channels to the DWC_otg controller. After queueing transactions, the
1011 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
1012 * to queue as Periodic Tx FIFO or request queue space becomes available.
1013 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
1015 * Must be called with interrupt disabled and spinlock held
1017 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
1019 struct list_head *qh_ptr;
1025 int no_queue_space = 0;
1026 int no_fifo_space = 0;
1030 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
1032 tx_status = readl(hsotg->regs + HPTXSTS);
1033 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1034 TXSTS_QSPCAVAIL_SHIFT;
1035 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1036 TXSTS_FSPCAVAIL_SHIFT;
1039 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n",
1041 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n",
1045 qh_ptr = hsotg->periodic_sched_assigned.next;
1046 while (qh_ptr != &hsotg->periodic_sched_assigned) {
1047 tx_status = readl(hsotg->regs + HPTXSTS);
1048 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1049 TXSTS_QSPCAVAIL_SHIFT;
1050 if (qspcavail == 0) {
1055 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
1057 qh_ptr = qh_ptr->next;
1061 /* Make sure EP's TT buffer is clean before queueing qtds */
1062 if (qh->tt_buffer_dirty) {
1063 qh_ptr = qh_ptr->next;
1068 * Set a flag if we're queuing high-bandwidth in slave mode.
1069 * The flag prevents any halts to get into the request queue in
1070 * the middle of multiple high-bandwidth packets getting queued.
1072 if (hsotg->core_params->dma_enable <= 0 &&
1073 qh->channel->multi_count > 1)
1074 hsotg->queuing_high_bandwidth = 1;
1076 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1077 TXSTS_FSPCAVAIL_SHIFT;
1078 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
1085 * In Slave mode, stay on the current transfer until there is
1086 * nothing more to do or the high-bandwidth request count is
1087 * reached. In DMA mode, only need to queue one request. The
1088 * controller automatically handles multiple packets for
1089 * high-bandwidth transfers.
1091 if (hsotg->core_params->dma_enable > 0 || status == 0 ||
1092 qh->channel->requests == qh->channel->multi_count) {
1093 qh_ptr = qh_ptr->next;
1095 * Move the QH from the periodic assigned schedule to
1096 * the periodic queued schedule
1098 list_move(&qh->qh_list_entry,
1099 &hsotg->periodic_sched_queued);
1101 /* done queuing high bandwidth */
1102 hsotg->queuing_high_bandwidth = 0;
1106 if (hsotg->core_params->dma_enable <= 0) {
1107 tx_status = readl(hsotg->regs + HPTXSTS);
1108 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1109 TXSTS_QSPCAVAIL_SHIFT;
1110 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1111 TXSTS_FSPCAVAIL_SHIFT;
1113 dev_vdbg(hsotg->dev,
1114 " P Tx Req Queue Space Avail (after queue): %d\n",
1116 dev_vdbg(hsotg->dev,
1117 " P Tx FIFO Space Avail (after queue): %d\n",
1121 if (!list_empty(&hsotg->periodic_sched_assigned) ||
1122 no_queue_space || no_fifo_space) {
1124 * May need to queue more transactions as the request
1125 * queue or Tx FIFO empties. Enable the periodic Tx
1126 * FIFO empty interrupt. (Always use the half-empty
1127 * level to ensure that new requests are loaded as
1128 * soon as possible.)
1130 gintmsk = readl(hsotg->regs + GINTMSK);
1131 gintmsk |= GINTSTS_PTXFEMP;
1132 writel(gintmsk, hsotg->regs + GINTMSK);
1135 * Disable the Tx FIFO empty interrupt since there are
1136 * no more transactions that need to be queued right
1137 * now. This function is called from interrupt
1138 * handlers to queue more transactions as transfer
1141 gintmsk = readl(hsotg->regs + GINTMSK);
1142 gintmsk &= ~GINTSTS_PTXFEMP;
1143 writel(gintmsk, hsotg->regs + GINTMSK);
1149 * Processes active non-periodic channels and queues transactions for these
1150 * channels to the DWC_otg controller. After queueing transactions, the NP Tx
1151 * FIFO Empty interrupt is enabled if there are more transactions to queue as
1152 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
1153 * FIFO Empty interrupt is disabled.
1155 * Must be called with interrupt disabled and spinlock held
1157 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
1159 struct list_head *orig_qh_ptr;
1166 int no_queue_space = 0;
1167 int no_fifo_space = 0;
1170 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
1172 tx_status = readl(hsotg->regs + GNPTXSTS);
1173 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1174 TXSTS_QSPCAVAIL_SHIFT;
1175 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1176 TXSTS_FSPCAVAIL_SHIFT;
1177 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n",
1179 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n",
1183 * Keep track of the starting point. Skip over the start-of-list
1186 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active)
1187 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
1188 orig_qh_ptr = hsotg->non_periodic_qh_ptr;
1191 * Process once through the active list or until no more space is
1192 * available in the request queue or the Tx FIFO
1195 tx_status = readl(hsotg->regs + GNPTXSTS);
1196 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1197 TXSTS_QSPCAVAIL_SHIFT;
1198 if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) {
1203 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh,
1208 /* Make sure EP's TT buffer is clean before queueing qtds */
1209 if (qh->tt_buffer_dirty)
1212 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1213 TXSTS_FSPCAVAIL_SHIFT;
1214 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
1218 } else if (status < 0) {
1223 /* Advance to next QH, skipping start-of-list entry */
1224 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
1225 if (hsotg->non_periodic_qh_ptr ==
1226 &hsotg->non_periodic_sched_active)
1227 hsotg->non_periodic_qh_ptr =
1228 hsotg->non_periodic_qh_ptr->next;
1229 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
1231 if (hsotg->core_params->dma_enable <= 0) {
1232 tx_status = readl(hsotg->regs + GNPTXSTS);
1233 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1234 TXSTS_QSPCAVAIL_SHIFT;
1235 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1236 TXSTS_FSPCAVAIL_SHIFT;
1237 dev_vdbg(hsotg->dev,
1238 " NP Tx Req Queue Space Avail (after queue): %d\n",
1240 dev_vdbg(hsotg->dev,
1241 " NP Tx FIFO Space Avail (after queue): %d\n",
1244 if (more_to_do || no_queue_space || no_fifo_space) {
1246 * May need to queue more transactions as the request
1247 * queue or Tx FIFO empties. Enable the non-periodic
1248 * Tx FIFO empty interrupt. (Always use the half-empty
1249 * level to ensure that new requests are loaded as
1250 * soon as possible.)
1252 gintmsk = readl(hsotg->regs + GINTMSK);
1253 gintmsk |= GINTSTS_NPTXFEMP;
1254 writel(gintmsk, hsotg->regs + GINTMSK);
1257 * Disable the Tx FIFO empty interrupt since there are
1258 * no more transactions that need to be queued right
1259 * now. This function is called from interrupt
1260 * handlers to queue more transactions as transfer
1263 gintmsk = readl(hsotg->regs + GINTMSK);
1264 gintmsk &= ~GINTSTS_NPTXFEMP;
1265 writel(gintmsk, hsotg->regs + GINTMSK);
1271 * dwc2_hcd_queue_transactions() - Processes the currently active host channels
1272 * and queues transactions for these channels to the DWC_otg controller. Called
1273 * from the HCD interrupt handler functions.
1275 * @hsotg: The HCD state structure
1276 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
1279 * Must be called with interrupt disabled and spinlock held
1281 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
1282 enum dwc2_transaction_type tr_type)
1284 #ifdef DWC2_DEBUG_SOF
1285 dev_vdbg(hsotg->dev, "Queue Transactions\n");
1287 /* Process host channels associated with periodic transfers */
1288 if ((tr_type == DWC2_TRANSACTION_PERIODIC ||
1289 tr_type == DWC2_TRANSACTION_ALL) &&
1290 !list_empty(&hsotg->periodic_sched_assigned))
1291 dwc2_process_periodic_channels(hsotg);
1293 /* Process host channels associated with non-periodic transfers */
1294 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC ||
1295 tr_type == DWC2_TRANSACTION_ALL) {
1296 if (!list_empty(&hsotg->non_periodic_sched_active)) {
1297 dwc2_process_non_periodic_channels(hsotg);
1300 * Ensure NP Tx FIFO empty interrupt is disabled when
1301 * there are no non-periodic transfers to process
1303 u32 gintmsk = readl(hsotg->regs + GINTMSK);
1305 gintmsk &= ~GINTSTS_NPTXFEMP;
1306 writel(gintmsk, hsotg->regs + GINTMSK);
1311 static void dwc2_conn_id_status_change(struct work_struct *work)
1313 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
1318 dev_dbg(hsotg->dev, "%s()\n", __func__);
1320 gotgctl = readl(hsotg->regs + GOTGCTL);
1321 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
1322 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
1323 !!(gotgctl & GOTGCTL_CONID_B));
1325 /* B-Device connector (Device Mode) */
1326 if (gotgctl & GOTGCTL_CONID_B) {
1327 /* Wait for switch to device mode */
1328 dev_dbg(hsotg->dev, "connId B\n");
1329 while (!dwc2_is_device_mode(hsotg)) {
1330 dev_info(hsotg->dev,
1331 "Waiting for Peripheral Mode, Mode=%s\n",
1332 dwc2_is_host_mode(hsotg) ? "Host" :
1334 usleep_range(20000, 40000);
1340 "Connection id status change timed out\n");
1341 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
1342 dwc2_core_init(hsotg, false, -1);
1343 dwc2_enable_global_interrupts(hsotg);
1345 /* A-Device connector (Host Mode) */
1346 dev_dbg(hsotg->dev, "connId A\n");
1347 while (!dwc2_is_host_mode(hsotg)) {
1348 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n",
1349 dwc2_is_host_mode(hsotg) ?
1350 "Host" : "Peripheral");
1351 usleep_range(20000, 40000);
1357 "Connection id status change timed out\n");
1358 hsotg->op_state = OTG_STATE_A_HOST;
1360 /* Initialize the Core for Host mode */
1361 dwc2_core_init(hsotg, false, -1);
1362 dwc2_enable_global_interrupts(hsotg);
1363 dwc2_hcd_start(hsotg);
1367 static void dwc2_wakeup_detected(unsigned long data)
1369 struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data;
1372 dev_dbg(hsotg->dev, "%s()\n", __func__);
1375 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
1376 * so that OPT tests pass with all PHYs.)
1378 hprt0 = dwc2_read_hprt0(hsotg);
1379 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
1380 hprt0 &= ~HPRT0_RES;
1381 writel(hprt0, hsotg->regs + HPRT0);
1382 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
1383 readl(hsotg->regs + HPRT0));
1385 dwc2_hcd_rem_wakeup(hsotg);
1387 /* Change to L0 state */
1388 hsotg->lx_state = DWC2_L0;
1391 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
1393 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
1395 return hcd->self.b_hnp_enable;
1398 /* Must NOT be called with interrupt disabled or spinlock held */
1399 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
1401 unsigned long flags;
1406 dev_dbg(hsotg->dev, "%s()\n", __func__);
1408 spin_lock_irqsave(&hsotg->lock, flags);
1410 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
1411 gotgctl = readl(hsotg->regs + GOTGCTL);
1412 gotgctl |= GOTGCTL_HSTSETHNPEN;
1413 writel(gotgctl, hsotg->regs + GOTGCTL);
1414 hsotg->op_state = OTG_STATE_A_SUSPEND;
1417 hprt0 = dwc2_read_hprt0(hsotg);
1418 hprt0 |= HPRT0_SUSP;
1419 writel(hprt0, hsotg->regs + HPRT0);
1421 /* Update lx_state */
1422 hsotg->lx_state = DWC2_L2;
1424 /* Suspend the Phy Clock */
1425 pcgctl = readl(hsotg->regs + PCGCTL);
1426 pcgctl |= PCGCTL_STOPPCLK;
1427 writel(pcgctl, hsotg->regs + PCGCTL);
1430 /* For HNP the bus must be suspended for at least 200ms */
1431 if (dwc2_host_is_b_hnp_enabled(hsotg)) {
1432 pcgctl = readl(hsotg->regs + PCGCTL);
1433 pcgctl &= ~PCGCTL_STOPPCLK;
1434 writel(pcgctl, hsotg->regs + PCGCTL);
1436 spin_unlock_irqrestore(&hsotg->lock, flags);
1438 usleep_range(200000, 250000);
1440 spin_unlock_irqrestore(&hsotg->lock, flags);
1444 /* Handles hub class-specific requests */
1445 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
1446 u16 wvalue, u16 windex, char *buf, u16 wlength)
1448 struct usb_hub_descriptor *hub_desc;
1456 case ClearHubFeature:
1457 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue);
1460 case C_HUB_LOCAL_POWER:
1461 case C_HUB_OVER_CURRENT:
1462 /* Nothing required here */
1468 "ClearHubFeature request %1xh unknown\n",
1473 case ClearPortFeature:
1474 if (wvalue != USB_PORT_FEAT_L1)
1475 if (!windex || windex > 1)
1478 case USB_PORT_FEAT_ENABLE:
1480 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
1481 hprt0 = dwc2_read_hprt0(hsotg);
1483 writel(hprt0, hsotg->regs + HPRT0);
1486 case USB_PORT_FEAT_SUSPEND:
1488 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
1489 writel(0, hsotg->regs + PCGCTL);
1490 usleep_range(20000, 40000);
1492 hprt0 = dwc2_read_hprt0(hsotg);
1494 writel(hprt0, hsotg->regs + HPRT0);
1495 hprt0 &= ~HPRT0_SUSP;
1496 usleep_range(100000, 150000);
1498 hprt0 &= ~HPRT0_RES;
1499 writel(hprt0, hsotg->regs + HPRT0);
1502 case USB_PORT_FEAT_POWER:
1504 "ClearPortFeature USB_PORT_FEAT_POWER\n");
1505 hprt0 = dwc2_read_hprt0(hsotg);
1506 hprt0 &= ~HPRT0_PWR;
1507 writel(hprt0, hsotg->regs + HPRT0);
1510 case USB_PORT_FEAT_INDICATOR:
1512 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
1513 /* Port indicator not supported */
1516 case USB_PORT_FEAT_C_CONNECTION:
1518 * Clears driver's internal Connect Status Change flag
1521 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
1522 hsotg->flags.b.port_connect_status_change = 0;
1525 case USB_PORT_FEAT_C_RESET:
1526 /* Clears driver's internal Port Reset Change flag */
1528 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
1529 hsotg->flags.b.port_reset_change = 0;
1532 case USB_PORT_FEAT_C_ENABLE:
1534 * Clears the driver's internal Port Enable/Disable
1538 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
1539 hsotg->flags.b.port_enable_change = 0;
1542 case USB_PORT_FEAT_C_SUSPEND:
1544 * Clears the driver's internal Port Suspend Change
1545 * flag, which is set when resume signaling on the host
1549 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
1550 hsotg->flags.b.port_suspend_change = 0;
1553 case USB_PORT_FEAT_C_PORT_L1:
1555 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n");
1556 hsotg->flags.b.port_l1_change = 0;
1559 case USB_PORT_FEAT_C_OVER_CURRENT:
1561 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
1562 hsotg->flags.b.port_over_current_change = 0;
1568 "ClearPortFeature request %1xh unknown or unsupported\n",
1573 case GetHubDescriptor:
1574 dev_dbg(hsotg->dev, "GetHubDescriptor\n");
1575 hub_desc = (struct usb_hub_descriptor *)buf;
1576 hub_desc->bDescLength = 9;
1577 hub_desc->bDescriptorType = 0x29;
1578 hub_desc->bNbrPorts = 1;
1579 hub_desc->wHubCharacteristics = cpu_to_le16(0x08);
1580 hub_desc->bPwrOn2PwrGood = 1;
1581 hub_desc->bHubContrCurrent = 0;
1582 hub_desc->u.hs.DeviceRemovable[0] = 0;
1583 hub_desc->u.hs.DeviceRemovable[1] = 0xff;
1587 dev_dbg(hsotg->dev, "GetHubStatus\n");
1592 dev_vdbg(hsotg->dev,
1593 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex,
1595 if (!windex || windex > 1)
1599 if (hsotg->flags.b.port_connect_status_change)
1600 port_status |= USB_PORT_STAT_C_CONNECTION << 16;
1601 if (hsotg->flags.b.port_enable_change)
1602 port_status |= USB_PORT_STAT_C_ENABLE << 16;
1603 if (hsotg->flags.b.port_suspend_change)
1604 port_status |= USB_PORT_STAT_C_SUSPEND << 16;
1605 if (hsotg->flags.b.port_l1_change)
1606 port_status |= USB_PORT_STAT_C_L1 << 16;
1607 if (hsotg->flags.b.port_reset_change)
1608 port_status |= USB_PORT_STAT_C_RESET << 16;
1609 if (hsotg->flags.b.port_over_current_change) {
1610 dev_warn(hsotg->dev, "Overcurrent change detected\n");
1611 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16;
1614 if (!hsotg->flags.b.port_connect_status) {
1616 * The port is disconnected, which means the core is
1617 * either in device mode or it soon will be. Just
1618 * return 0's for the remainder of the port status
1619 * since the port register can't be read if the core
1620 * is in device mode.
1622 *(__le32 *)buf = cpu_to_le32(port_status);
1626 hprt0 = readl(hsotg->regs + HPRT0);
1627 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0);
1629 if (hprt0 & HPRT0_CONNSTS)
1630 port_status |= USB_PORT_STAT_CONNECTION;
1631 if (hprt0 & HPRT0_ENA)
1632 port_status |= USB_PORT_STAT_ENABLE;
1633 if (hprt0 & HPRT0_SUSP)
1634 port_status |= USB_PORT_STAT_SUSPEND;
1635 if (hprt0 & HPRT0_OVRCURRACT)
1636 port_status |= USB_PORT_STAT_OVERCURRENT;
1637 if (hprt0 & HPRT0_RST)
1638 port_status |= USB_PORT_STAT_RESET;
1639 if (hprt0 & HPRT0_PWR)
1640 port_status |= USB_PORT_STAT_POWER;
1642 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
1643 if (speed == HPRT0_SPD_HIGH_SPEED)
1644 port_status |= USB_PORT_STAT_HIGH_SPEED;
1645 else if (speed == HPRT0_SPD_LOW_SPEED)
1646 port_status |= USB_PORT_STAT_LOW_SPEED;
1648 if (hprt0 & HPRT0_TSTCTL_MASK)
1649 port_status |= USB_PORT_STAT_TEST;
1650 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
1652 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status);
1653 *(__le32 *)buf = cpu_to_le32(port_status);
1657 dev_dbg(hsotg->dev, "SetHubFeature\n");
1658 /* No HUB features supported */
1661 case SetPortFeature:
1662 dev_dbg(hsotg->dev, "SetPortFeature\n");
1663 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1))
1666 if (!hsotg->flags.b.port_connect_status) {
1668 * The port is disconnected, which means the core is
1669 * either in device mode or it soon will be. Just
1670 * return without doing anything since the port
1671 * register can't be written if the core is in device
1678 case USB_PORT_FEAT_SUSPEND:
1680 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
1681 if (windex != hsotg->otg_port)
1683 dwc2_port_suspend(hsotg, windex);
1686 case USB_PORT_FEAT_POWER:
1688 "SetPortFeature - USB_PORT_FEAT_POWER\n");
1689 hprt0 = dwc2_read_hprt0(hsotg);
1691 writel(hprt0, hsotg->regs + HPRT0);
1694 case USB_PORT_FEAT_RESET:
1695 hprt0 = dwc2_read_hprt0(hsotg);
1697 "SetPortFeature - USB_PORT_FEAT_RESET\n");
1698 pcgctl = readl(hsotg->regs + PCGCTL);
1699 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
1700 writel(pcgctl, hsotg->regs + PCGCTL);
1701 /* ??? Original driver does this */
1702 writel(0, hsotg->regs + PCGCTL);
1704 hprt0 = dwc2_read_hprt0(hsotg);
1705 /* Clear suspend bit if resetting from suspend state */
1706 hprt0 &= ~HPRT0_SUSP;
1709 * When B-Host the Port reset bit is set in the Start
1710 * HCD Callback function, so that the reset is started
1711 * within 1ms of the HNP success interrupt
1713 if (!dwc2_hcd_is_b_host(hsotg)) {
1714 hprt0 |= HPRT0_PWR | HPRT0_RST;
1716 "In host mode, hprt0=%08x\n", hprt0);
1717 writel(hprt0, hsotg->regs + HPRT0);
1720 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
1721 usleep_range(50000, 70000);
1722 hprt0 &= ~HPRT0_RST;
1723 writel(hprt0, hsotg->regs + HPRT0);
1724 hsotg->lx_state = DWC2_L0; /* Now back to On state */
1727 case USB_PORT_FEAT_INDICATOR:
1729 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
1736 "SetPortFeature %1xh unknown or unsupported\n",
1746 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n",
1747 typereq, windex, wvalue);
1754 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
1761 retval = (hsotg->flags.b.port_connect_status_change ||
1762 hsotg->flags.b.port_reset_change ||
1763 hsotg->flags.b.port_enable_change ||
1764 hsotg->flags.b.port_suspend_change ||
1765 hsotg->flags.b.port_over_current_change);
1769 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n");
1770 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n",
1771 hsotg->flags.b.port_connect_status_change);
1772 dev_dbg(hsotg->dev, " port_reset_change: %d\n",
1773 hsotg->flags.b.port_reset_change);
1774 dev_dbg(hsotg->dev, " port_enable_change: %d\n",
1775 hsotg->flags.b.port_enable_change);
1776 dev_dbg(hsotg->dev, " port_suspend_change: %d\n",
1777 hsotg->flags.b.port_suspend_change);
1778 dev_dbg(hsotg->dev, " port_over_current_change: %d\n",
1779 hsotg->flags.b.port_over_current_change);
1785 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1787 u32 hfnum = readl(hsotg->regs + HFNUM);
1789 #ifdef DWC2_DEBUG_SOF
1790 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
1791 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT);
1793 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
1796 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg)
1798 return (hsotg->op_state == OTG_STATE_B_HOST);
1801 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg,
1805 struct dwc2_hcd_urb *urb;
1806 u32 size = sizeof(*urb) + iso_desc_count *
1807 sizeof(struct dwc2_hcd_iso_packet_desc);
1809 urb = kzalloc(size, mem_flags);
1811 urb->packet_count = iso_desc_count;
1815 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg,
1816 struct dwc2_hcd_urb *urb, u8 dev_addr,
1817 u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps)
1820 ep_type == USB_ENDPOINT_XFER_BULK ||
1821 ep_type == USB_ENDPOINT_XFER_CONTROL)
1822 dev_vdbg(hsotg->dev,
1823 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n",
1824 dev_addr, ep_num, ep_dir, ep_type, mps);
1825 urb->pipe_info.dev_addr = dev_addr;
1826 urb->pipe_info.ep_num = ep_num;
1827 urb->pipe_info.pipe_type = ep_type;
1828 urb->pipe_info.pipe_dir = ep_dir;
1829 urb->pipe_info.mps = mps;
1833 * NOTE: This function will be removed once the peripheral controller code
1834 * is integrated and the driver is stable
1836 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
1839 struct dwc2_host_chan *chan;
1840 struct dwc2_hcd_urb *urb;
1841 struct dwc2_qtd *qtd;
1847 num_channels = hsotg->core_params->host_channels;
1848 dev_dbg(hsotg->dev, "\n");
1850 "************************************************************\n");
1851 dev_dbg(hsotg->dev, "HCD State:\n");
1852 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels);
1854 for (i = 0; i < num_channels; i++) {
1855 chan = hsotg->hc_ptr_array[i];
1856 dev_dbg(hsotg->dev, " Channel %d:\n", i);
1858 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
1859 chan->dev_addr, chan->ep_num, chan->ep_is_in);
1860 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed);
1861 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
1862 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
1863 dev_dbg(hsotg->dev, " data_pid_start: %d\n",
1864 chan->data_pid_start);
1865 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count);
1866 dev_dbg(hsotg->dev, " xfer_started: %d\n",
1867 chan->xfer_started);
1868 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
1869 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
1870 (unsigned long)chan->xfer_dma);
1871 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
1872 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count);
1873 dev_dbg(hsotg->dev, " halt_on_queue: %d\n",
1874 chan->halt_on_queue);
1875 dev_dbg(hsotg->dev, " halt_pending: %d\n",
1876 chan->halt_pending);
1877 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
1878 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split);
1879 dev_dbg(hsotg->dev, " complete_split: %d\n",
1880 chan->complete_split);
1881 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr);
1882 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port);
1883 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos);
1884 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests);
1885 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
1887 if (chan->xfer_started) {
1888 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
1890 hfnum = readl(hsotg->regs + HFNUM);
1891 hcchar = readl(hsotg->regs + HCCHAR(i));
1892 hctsiz = readl(hsotg->regs + HCTSIZ(i));
1893 hcint = readl(hsotg->regs + HCINT(i));
1894 hcintmsk = readl(hsotg->regs + HCINTMSK(i));
1895 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum);
1896 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar);
1897 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz);
1898 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint);
1899 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk);
1902 if (!(chan->xfer_started && chan->qh))
1905 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) {
1906 if (!qtd->in_process)
1909 dev_dbg(hsotg->dev, " URB Info:\n");
1910 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n",
1914 " Dev: %d, EP: %d %s\n",
1915 dwc2_hcd_get_dev_addr(&urb->pipe_info),
1916 dwc2_hcd_get_ep_num(&urb->pipe_info),
1917 dwc2_hcd_is_pipe_in(&urb->pipe_info) ?
1920 " Max packet size: %d\n",
1921 dwc2_hcd_get_mps(&urb->pipe_info));
1923 " transfer_buffer: %p\n",
1926 " transfer_dma: %08lx\n",
1927 (unsigned long)urb->dma);
1929 " transfer_buffer_length: %d\n",
1931 dev_dbg(hsotg->dev, " actual_length: %d\n",
1932 urb->actual_length);
1937 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n",
1938 hsotg->non_periodic_channels);
1939 dev_dbg(hsotg->dev, " periodic_channels: %d\n",
1940 hsotg->periodic_channels);
1941 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs);
1942 np_tx_status = readl(hsotg->regs + GNPTXSTS);
1943 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n",
1944 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
1945 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n",
1946 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
1947 p_tx_status = readl(hsotg->regs + HPTXSTS);
1948 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n",
1949 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
1950 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n",
1951 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
1952 dwc2_hcd_dump_frrem(hsotg);
1953 dwc2_dump_global_registers(hsotg);
1954 dwc2_dump_host_registers(hsotg);
1956 "************************************************************\n");
1957 dev_dbg(hsotg->dev, "\n");
1962 * NOTE: This function will be removed once the peripheral controller code
1963 * is integrated and the driver is stable
1965 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg)
1967 #ifdef DWC2_DUMP_FRREM
1968 dev_dbg(hsotg->dev, "Frame remaining at SOF:\n");
1969 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
1970 hsotg->frrem_samples, hsotg->frrem_accum,
1971 hsotg->frrem_samples > 0 ?
1972 hsotg->frrem_accum / hsotg->frrem_samples : 0);
1973 dev_dbg(hsotg->dev, "\n");
1974 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n");
1975 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
1976 hsotg->hfnum_7_samples,
1977 hsotg->hfnum_7_frrem_accum,
1978 hsotg->hfnum_7_samples > 0 ?
1979 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0);
1980 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n");
1981 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
1982 hsotg->hfnum_0_samples,
1983 hsotg->hfnum_0_frrem_accum,
1984 hsotg->hfnum_0_samples > 0 ?
1985 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0);
1986 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n");
1987 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
1988 hsotg->hfnum_other_samples,
1989 hsotg->hfnum_other_frrem_accum,
1990 hsotg->hfnum_other_samples > 0 ?
1991 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples :
1993 dev_dbg(hsotg->dev, "\n");
1994 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n");
1995 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
1996 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a,
1997 hsotg->hfnum_7_samples_a > 0 ?
1998 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0);
1999 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n");
2000 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2001 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a,
2002 hsotg->hfnum_0_samples_a > 0 ?
2003 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0);
2004 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n");
2005 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2006 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a,
2007 hsotg->hfnum_other_samples_a > 0 ?
2008 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a
2010 dev_dbg(hsotg->dev, "\n");
2011 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n");
2012 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2013 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b,
2014 hsotg->hfnum_7_samples_b > 0 ?
2015 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0);
2016 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n");
2017 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2018 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b,
2019 (hsotg->hfnum_0_samples_b > 0) ?
2020 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0);
2021 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n");
2022 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2023 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b,
2024 (hsotg->hfnum_other_samples_b > 0) ?
2025 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b
2030 struct wrapper_priv_data {
2031 struct dwc2_hsotg *hsotg;
2034 /* Gets the dwc2_hsotg from a usb_hcd */
2035 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd)
2037 struct wrapper_priv_data *p;
2039 p = (struct wrapper_priv_data *) &hcd->hcd_priv;
2043 static int _dwc2_hcd_start(struct usb_hcd *hcd);
2045 void dwc2_host_start(struct dwc2_hsotg *hsotg)
2047 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
2049 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg);
2050 _dwc2_hcd_start(hcd);
2053 void dwc2_host_disconnect(struct dwc2_hsotg *hsotg)
2055 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
2057 hcd->self.is_b_host = 0;
2060 void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr,
2063 struct urb *urb = context;
2066 *hub_addr = urb->dev->tt->hub->devnum;
2069 *hub_port = urb->dev->ttport;
2072 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
2074 struct urb *urb = context;
2076 return urb->dev->speed;
2079 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
2082 struct usb_bus *bus = hcd_to_bus(hcd);
2085 bus->bandwidth_allocated += bw / urb->interval;
2086 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2087 bus->bandwidth_isoc_reqs++;
2089 bus->bandwidth_int_reqs++;
2092 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
2095 struct usb_bus *bus = hcd_to_bus(hcd);
2098 bus->bandwidth_allocated -= bw / urb->interval;
2099 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2100 bus->bandwidth_isoc_reqs--;
2102 bus->bandwidth_int_reqs--;
2106 * Sets the final status of an URB and returns it to the upper layer. Any
2107 * required cleanup of the URB is performed.
2109 * Must be called with interrupt disabled and spinlock held
2111 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
2118 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
2123 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
2127 urb = qtd->urb->priv;
2129 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
2133 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb);
2136 dev_vdbg(hsotg->dev,
2137 "%s: urb %p device %d ep %d-%s status %d actual %d\n",
2138 __func__, urb, usb_pipedevice(urb->pipe),
2139 usb_pipeendpoint(urb->pipe),
2140 usb_pipein(urb->pipe) ? "IN" : "OUT", status,
2141 urb->actual_length);
2143 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) {
2144 for (i = 0; i < urb->number_of_packets; i++)
2145 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
2146 i, urb->iso_frame_desc[i].status);
2149 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2150 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb);
2151 for (i = 0; i < urb->number_of_packets; ++i) {
2152 urb->iso_frame_desc[i].actual_length =
2153 dwc2_hcd_urb_get_iso_desc_actual_length(
2155 urb->iso_frame_desc[i].status =
2156 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i);
2160 urb->status = status;
2162 if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
2163 urb->actual_length < urb->transfer_buffer_length)
2164 urb->status = -EREMOTEIO;
2167 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
2168 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
2169 struct usb_host_endpoint *ep = urb->ep;
2172 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
2173 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
2177 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb);
2182 spin_unlock(&hsotg->lock);
2183 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status);
2184 spin_lock(&hsotg->lock);
2188 * Work queue function for starting the HCD when A-Cable is connected
2190 static void dwc2_hcd_start_func(struct work_struct *work)
2192 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
2195 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg);
2196 dwc2_host_start(hsotg);
2200 * Reset work queue function
2202 static void dwc2_hcd_reset_func(struct work_struct *work)
2204 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
2208 dev_dbg(hsotg->dev, "USB RESET function called\n");
2209 hprt0 = dwc2_read_hprt0(hsotg);
2210 hprt0 &= ~HPRT0_RST;
2211 writel(hprt0, hsotg->regs + HPRT0);
2212 hsotg->flags.b.port_reset_change = 1;
2216 * =========================================================================
2217 * Linux HC Driver Functions
2218 * =========================================================================
2222 * Initializes the DWC_otg controller and its root hub and prepares it for host
2223 * mode operation. Activates the root port. Returns 0 on success and a negative
2224 * error code on failure.
2226 static int _dwc2_hcd_start(struct usb_hcd *hcd)
2228 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2229 struct usb_bus *bus = hcd_to_bus(hcd);
2230 unsigned long flags;
2232 dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
2234 spin_lock_irqsave(&hsotg->lock, flags);
2236 hcd->state = HC_STATE_RUNNING;
2238 if (dwc2_is_device_mode(hsotg)) {
2239 spin_unlock_irqrestore(&hsotg->lock, flags);
2240 return 0; /* why 0 ?? */
2243 dwc2_hcd_reinit(hsotg);
2245 /* Initialize and connect root hub if one is not already attached */
2246 if (bus->root_hub) {
2247 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n");
2248 /* Inform the HUB driver to resume */
2249 usb_hcd_resume_root_hub(hcd);
2252 spin_unlock_irqrestore(&hsotg->lock, flags);
2257 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
2260 static void _dwc2_hcd_stop(struct usb_hcd *hcd)
2262 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2263 unsigned long flags;
2265 spin_lock_irqsave(&hsotg->lock, flags);
2266 dwc2_hcd_stop(hsotg);
2267 spin_unlock_irqrestore(&hsotg->lock, flags);
2269 usleep_range(1000, 3000);
2272 /* Returns the current frame number */
2273 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
2275 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2277 return dwc2_hcd_get_frame_number(hsotg);
2280 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb,
2283 #ifdef VERBOSE_DEBUG
2284 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2288 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb);
2289 dev_vdbg(hsotg->dev, " Device address: %d\n",
2290 usb_pipedevice(urb->pipe));
2291 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n",
2292 usb_pipeendpoint(urb->pipe),
2293 usb_pipein(urb->pipe) ? "IN" : "OUT");
2295 switch (usb_pipetype(urb->pipe)) {
2297 pipetype = "CONTROL";
2302 case PIPE_INTERRUPT:
2303 pipetype = "INTERRUPT";
2305 case PIPE_ISOCHRONOUS:
2306 pipetype = "ISOCHRONOUS";
2309 pipetype = "UNKNOWN";
2313 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype,
2314 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ?
2317 switch (urb->dev->speed) {
2318 case USB_SPEED_HIGH:
2321 case USB_SPEED_FULL:
2332 dev_vdbg(hsotg->dev, " Speed: %s\n", speed);
2333 dev_vdbg(hsotg->dev, " Max packet size: %d\n",
2334 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
2335 dev_vdbg(hsotg->dev, " Data buffer length: %d\n",
2336 urb->transfer_buffer_length);
2337 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n",
2338 urb->transfer_buffer, (unsigned long)urb->transfer_dma);
2339 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n",
2340 urb->setup_packet, (unsigned long)urb->setup_dma);
2341 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval);
2343 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2346 for (i = 0; i < urb->number_of_packets; i++) {
2347 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i);
2348 dev_vdbg(hsotg->dev, " offset: %d, length %d\n",
2349 urb->iso_frame_desc[i].offset,
2350 urb->iso_frame_desc[i].length);
2357 * Starts processing a USB transfer request specified by a USB Request Block
2358 * (URB). mem_flags indicates the type of memory allocation to use while
2359 * processing this URB.
2361 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
2364 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2365 struct usb_host_endpoint *ep = urb->ep;
2366 struct dwc2_hcd_urb *dwc2_urb;
2369 int alloc_bandwidth = 0;
2373 unsigned long flags;
2376 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");
2377 dwc2_dump_urb_info(hcd, urb, "urb_enqueue");
2383 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
2384 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
2385 spin_lock_irqsave(&hsotg->lock, flags);
2386 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep))
2387 alloc_bandwidth = 1;
2388 spin_unlock_irqrestore(&hsotg->lock, flags);
2391 switch (usb_pipetype(urb->pipe)) {
2393 ep_type = USB_ENDPOINT_XFER_CONTROL;
2395 case PIPE_ISOCHRONOUS:
2396 ep_type = USB_ENDPOINT_XFER_ISOC;
2399 ep_type = USB_ENDPOINT_XFER_BULK;
2401 case PIPE_INTERRUPT:
2402 ep_type = USB_ENDPOINT_XFER_INT;
2405 dev_warn(hsotg->dev, "Wrong ep type\n");
2408 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets,
2413 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe),
2414 usb_pipeendpoint(urb->pipe), ep_type,
2415 usb_pipein(urb->pipe),
2416 usb_maxpacket(urb->dev, urb->pipe,
2417 !(usb_pipein(urb->pipe))));
2419 buf = urb->transfer_buffer;
2421 if (hcd->self.uses_dma) {
2422 if (!buf && (urb->transfer_dma & 3)) {
2424 "%s: unaligned transfer with no transfer_buffer",
2431 if (!(urb->transfer_flags & URB_NO_INTERRUPT))
2432 tflags |= URB_GIVEBACK_ASAP;
2433 if (urb->transfer_flags & URB_ZERO_PACKET)
2434 tflags |= URB_SEND_ZERO_PACKET;
2436 dwc2_urb->priv = urb;
2437 dwc2_urb->buf = buf;
2438 dwc2_urb->dma = urb->transfer_dma;
2439 dwc2_urb->length = urb->transfer_buffer_length;
2440 dwc2_urb->setup_packet = urb->setup_packet;
2441 dwc2_urb->setup_dma = urb->setup_dma;
2442 dwc2_urb->flags = tflags;
2443 dwc2_urb->interval = urb->interval;
2444 dwc2_urb->status = -EINPROGRESS;
2446 for (i = 0; i < urb->number_of_packets; ++i)
2447 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i,
2448 urb->iso_frame_desc[i].offset,
2449 urb->iso_frame_desc[i].length);
2451 urb->hcpriv = dwc2_urb;
2453 spin_lock_irqsave(&hsotg->lock, flags);
2454 retval = usb_hcd_link_urb_to_ep(hcd, urb);
2455 spin_unlock_irqrestore(&hsotg->lock, flags);
2459 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, &ep->hcpriv, mem_flags);
2463 if (alloc_bandwidth) {
2464 spin_lock_irqsave(&hsotg->lock, flags);
2465 dwc2_allocate_bus_bandwidth(hcd,
2466 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
2468 spin_unlock_irqrestore(&hsotg->lock, flags);
2474 spin_lock_irqsave(&hsotg->lock, flags);
2475 dwc2_urb->priv = NULL;
2476 usb_hcd_unlink_urb_from_ep(hcd, urb);
2477 spin_unlock_irqrestore(&hsotg->lock, flags);
2486 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success.
2488 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
2491 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2493 unsigned long flags;
2495 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n");
2496 dwc2_dump_urb_info(hcd, urb, "urb_dequeue");
2498 spin_lock_irqsave(&hsotg->lock, flags);
2500 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
2505 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n");
2509 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv);
2511 usb_hcd_unlink_urb_from_ep(hcd, urb);
2516 /* Higher layer software sets URB status */
2517 spin_unlock(&hsotg->lock);
2518 usb_hcd_giveback_urb(hcd, urb, status);
2519 spin_lock(&hsotg->lock);
2521 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n");
2522 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status);
2524 spin_unlock_irqrestore(&hsotg->lock, flags);
2530 * Frees resources in the DWC_otg controller related to a given endpoint. Also
2531 * clears state in the HCD related to the endpoint. Any URBs for the endpoint
2532 * must already be dequeued.
2534 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd,
2535 struct usb_host_endpoint *ep)
2537 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2540 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n",
2541 ep->desc.bEndpointAddress, ep->hcpriv);
2542 dwc2_hcd_endpoint_disable(hsotg, ep, 250);
2546 * Resets endpoint specific parameter values, in current version used to reset
2547 * the data toggle (as a WA). This function can be called from usb_clear_halt
2550 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd,
2551 struct usb_host_endpoint *ep)
2553 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2554 int is_control = usb_endpoint_xfer_control(&ep->desc);
2555 int is_out = usb_endpoint_dir_out(&ep->desc);
2556 int epnum = usb_endpoint_num(&ep->desc);
2557 struct usb_device *udev;
2558 unsigned long flags;
2561 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
2562 ep->desc.bEndpointAddress);
2564 udev = to_usb_device(hsotg->dev);
2566 spin_lock_irqsave(&hsotg->lock, flags);
2568 usb_settoggle(udev, epnum, is_out, 0);
2570 usb_settoggle(udev, epnum, !is_out, 0);
2571 dwc2_hcd_endpoint_reset(hsotg, ep);
2573 spin_unlock_irqrestore(&hsotg->lock, flags);
2577 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
2578 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
2581 * This function is called by the USB core when an interrupt occurs
2583 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd)
2585 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2587 return dwc2_handle_hcd_intr(hsotg);
2591 * Creates Status Change bitmap for the root hub and root port. The bitmap is
2592 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
2593 * is the status change indicator for the single root port. Returns 1 if either
2594 * change indicator is 1, otherwise returns 0.
2596 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
2598 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2600 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1;
2604 /* Handles hub class-specific requests */
2605 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue,
2606 u16 windex, char *buf, u16 wlength)
2608 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq,
2609 wvalue, windex, buf, wlength);
2613 /* Handles hub TT buffer clear completions */
2614 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd,
2615 struct usb_host_endpoint *ep)
2617 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2619 unsigned long flags;
2625 spin_lock_irqsave(&hsotg->lock, flags);
2626 qh->tt_buffer_dirty = 0;
2628 if (hsotg->flags.b.port_connect_status)
2629 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL);
2631 spin_unlock_irqrestore(&hsotg->lock, flags);
2634 static struct hc_driver dwc2_hc_driver = {
2635 .description = "dwc2_hsotg",
2636 .product_desc = "DWC OTG Controller",
2637 .hcd_priv_size = sizeof(struct wrapper_priv_data),
2639 .irq = _dwc2_hcd_irq,
2640 .flags = HCD_MEMORY | HCD_USB2,
2642 .start = _dwc2_hcd_start,
2643 .stop = _dwc2_hcd_stop,
2644 .urb_enqueue = _dwc2_hcd_urb_enqueue,
2645 .urb_dequeue = _dwc2_hcd_urb_dequeue,
2646 .endpoint_disable = _dwc2_hcd_endpoint_disable,
2647 .endpoint_reset = _dwc2_hcd_endpoint_reset,
2648 .get_frame_number = _dwc2_hcd_get_frame_number,
2650 .hub_status_data = _dwc2_hcd_hub_status_data,
2651 .hub_control = _dwc2_hcd_hub_control,
2652 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
2656 * Frees secondary storage associated with the dwc2_hsotg structure contained
2657 * in the struct usb_hcd field
2659 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
2665 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n");
2667 /* Free memory for QH/QTD lists */
2668 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);
2669 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);
2670 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);
2671 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
2672 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned);
2673 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued);
2675 /* Free memory for the host channels */
2676 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
2677 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
2680 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
2682 hsotg->hc_ptr_array[i] = NULL;
2687 if (hsotg->core_params->dma_enable > 0) {
2688 if (hsotg->status_buf) {
2689 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,
2691 hsotg->status_buf_dma);
2692 hsotg->status_buf = NULL;
2695 kfree(hsotg->status_buf);
2696 hsotg->status_buf = NULL;
2699 ahbcfg = readl(hsotg->regs + GAHBCFG);
2701 /* Disable all interrupts */
2702 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
2703 writel(ahbcfg, hsotg->regs + GAHBCFG);
2704 writel(0, hsotg->regs + GINTMSK);
2706 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
2707 dctl = readl(hsotg->regs + DCTL);
2708 dctl |= DCTL_SFTDISCON;
2709 writel(dctl, hsotg->regs + DCTL);
2712 if (hsotg->wq_otg) {
2713 if (!cancel_work_sync(&hsotg->wf_otg))
2714 flush_workqueue(hsotg->wq_otg);
2715 destroy_workqueue(hsotg->wq_otg);
2718 kfree(hsotg->core_params);
2719 hsotg->core_params = NULL;
2720 del_timer(&hsotg->wkp_timer);
2723 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg)
2725 /* Turn off all host-specific interrupts */
2726 dwc2_disable_host_interrupts(hsotg);
2728 dwc2_hcd_free(hsotg);
2732 * Sets all parameters to the given value.
2734 * Assumes that the dwc2_core_params struct contains only integers.
2736 void dwc2_set_all_params(struct dwc2_core_params *params, int value)
2738 int *p = (int *)params;
2739 size_t size = sizeof(*params) / sizeof(*p);
2742 for (i = 0; i < size; i++)
2745 EXPORT_SYMBOL_GPL(dwc2_set_all_params);
2748 * Initializes the HCD. This function allocates memory for and initializes the
2749 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the
2750 * USB bus with the core and calls the hc_driver->start() function. It returns
2751 * a negative error on failure.
2753 int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq,
2754 const struct dwc2_core_params *params)
2756 struct usb_hcd *hcd;
2757 struct dwc2_host_chan *channel;
2759 int i, num_channels;
2762 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
2764 /* Detect config values from hardware */
2765 retval = dwc2_get_hwparams(hsotg);
2772 hcfg = readl(hsotg->regs + HCFG);
2773 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
2775 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
2776 hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) *
2777 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
2778 if (!hsotg->frame_num_array)
2780 hsotg->last_frame_num_array = kzalloc(
2781 sizeof(*hsotg->last_frame_num_array) *
2782 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
2783 if (!hsotg->last_frame_num_array)
2785 hsotg->last_frame_num = HFNUM_MAX_FRNUM;
2788 hsotg->core_params = kzalloc(sizeof(*hsotg->core_params), GFP_KERNEL);
2789 if (!hsotg->core_params)
2792 dwc2_set_all_params(hsotg->core_params, -1);
2794 /* Validate parameter values */
2795 dwc2_set_parameters(hsotg, params);
2797 /* Check if the bus driver or platform code has setup a dma_mask */
2798 if (hsotg->core_params->dma_enable > 0 &&
2799 hsotg->dev->dma_mask == NULL) {
2800 dev_warn(hsotg->dev,
2801 "dma_mask not set, disabling DMA\n");
2802 hsotg->core_params->dma_enable = 0;
2803 hsotg->core_params->dma_desc_enable = 0;
2806 /* Set device flags indicating whether the HCD supports DMA */
2807 if (hsotg->core_params->dma_enable > 0) {
2808 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
2809 dev_warn(hsotg->dev, "can't set DMA mask\n");
2810 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
2811 dev_warn(hsotg->dev, "can't set coherent DMA mask\n");
2814 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev));
2818 if (hsotg->core_params->dma_enable <= 0)
2819 hcd->self.uses_dma = 0;
2823 spin_lock_init(&hsotg->lock);
2824 ((struct wrapper_priv_data *) &hcd->hcd_priv)->hsotg = hsotg;
2828 * Disable the global interrupt until all the interrupt handlers are
2831 dwc2_disable_global_interrupts(hsotg);
2833 /* Initialize the DWC_otg core, and select the Phy type */
2834 retval = dwc2_core_init(hsotg, true, irq);
2838 /* Create new workqueue and init work */
2840 hsotg->wq_otg = create_singlethread_workqueue("dwc2");
2841 if (!hsotg->wq_otg) {
2842 dev_err(hsotg->dev, "Failed to create workqueue\n");
2845 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change);
2847 setup_timer(&hsotg->wkp_timer, dwc2_wakeup_detected,
2848 (unsigned long)hsotg);
2850 /* Initialize the non-periodic schedule */
2851 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);
2852 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);
2854 /* Initialize the periodic schedule */
2855 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive);
2856 INIT_LIST_HEAD(&hsotg->periodic_sched_ready);
2857 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned);
2858 INIT_LIST_HEAD(&hsotg->periodic_sched_queued);
2861 * Create a host channel descriptor for each host channel implemented
2862 * in the controller. Initialize the channel descriptor array.
2864 INIT_LIST_HEAD(&hsotg->free_hc_list);
2865 num_channels = hsotg->core_params->host_channels;
2866 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
2868 for (i = 0; i < num_channels; i++) {
2869 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
2870 if (channel == NULL)
2872 channel->hc_num = i;
2873 hsotg->hc_ptr_array[i] = channel;
2876 if (hsotg->core_params->uframe_sched > 0)
2877 dwc2_hcd_init_usecs(hsotg);
2879 /* Initialize hsotg start work */
2880 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
2882 /* Initialize port reset work */
2883 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
2886 * Allocate space for storing data on status transactions. Normally no
2887 * data is sent, but this space acts as a bit bucket. This must be
2888 * done after usb_add_hcd since that function allocates the DMA buffer
2891 if (hsotg->core_params->dma_enable > 0)
2892 hsotg->status_buf = dma_alloc_coherent(hsotg->dev,
2893 DWC2_HCD_STATUS_BUF_SIZE,
2894 &hsotg->status_buf_dma, GFP_KERNEL);
2896 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE,
2899 if (!hsotg->status_buf)
2902 hsotg->otg_port = 1;
2903 hsotg->frame_list = NULL;
2904 hsotg->frame_list_dma = 0;
2905 hsotg->periodic_qh_count = 0;
2907 /* Initiate lx_state to L3 disconnected state */
2908 hsotg->lx_state = DWC2_L3;
2910 hcd->self.otg_port = hsotg->otg_port;
2912 /* Don't support SG list at this point */
2913 hcd->self.sg_tablesize = 0;
2916 * Finish generic HCD initialization and start the HCD. This function
2917 * allocates the DMA buffer pool, registers the USB bus, requests the
2918 * IRQ line, and calls hcd_start method.
2920 retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
2924 dwc2_hcd_dump_state(hsotg);
2926 dwc2_enable_global_interrupts(hsotg);
2931 dwc2_hcd_release(hsotg);
2935 kfree(hsotg->core_params);
2937 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
2938 kfree(hsotg->last_frame_num_array);
2939 kfree(hsotg->frame_num_array);
2942 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval);
2945 EXPORT_SYMBOL_GPL(dwc2_hcd_init);
2949 * Frees memory and resources associated with the HCD and deregisters the bus.
2951 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg)
2953 struct usb_hcd *hcd;
2955 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n");
2957 hcd = dwc2_hsotg_to_hcd(hsotg);
2958 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd);
2961 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
2966 usb_remove_hcd(hcd);
2968 dwc2_hcd_release(hsotg);
2971 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
2972 kfree(hsotg->last_frame_num_array);
2973 kfree(hsotg->frame_num_array);
2976 EXPORT_SYMBOL_GPL(dwc2_hcd_remove);