drivers/staging/dwc2/hcd_intr.c

   1 /*
   2  * hcd_intr.c - DesignWare HS OTG Controller host-mode interrupt handling
   3  *
   4  * Copyright (C) 2004-2013 Synopsys, Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions, and the following disclaimer,
  11  *    without modification.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The names of the above-listed copyright holders may not be used
  16  *    to endorse or promote products derived from this software without
  17  *    specific prior written permission.
  18  *
  19  * ALTERNATIVELY, this software may be distributed under the terms of the
  20  * GNU General Public License ("GPL") as published by the Free Software
  21  * Foundation; either version 2 of the License, or (at your option) any
  22  * later version.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  25  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  28  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  29  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  30  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  32  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  33  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  34  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 /*
  38  * This file contains the interrupt handlers for Host mode
  39  */
  40 #include <linux/kernel.h>
  41 #include <linux/module.h>
  42 #include <linux/spinlock.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/dma-mapping.h>
  45 #include <linux/io.h>
  46 #include <linux/slab.h>
  47 #include <linux/usb.h>
  48
  49 #include <linux/usb/hcd.h>
  50 #include <linux/usb/ch11.h>
  51
  52 #include "core.h"
  53 #include "hcd.h"
  54
  55 /* This function is for debug only */
  56 static void dwc2_track_missed_sofs(struct dwc2_hsotg *hsotg)
  57 {
  58 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
  59         u16 curr_frame_number = hsotg->frame_number;
  60
  61         if (hsotg->frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
  62                 if (((hsotg->last_frame_num + 1) & HFNUM_MAX_FRNUM) !=
  63                     curr_frame_number) {
  64                         hsotg->frame_num_array[hsotg->frame_num_idx] =
  65                                         curr_frame_number;
  66                         hsotg->last_frame_num_array[hsotg->frame_num_idx] =
  67                                         hsotg->last_frame_num;
  68                         hsotg->frame_num_idx++;
  69                 }
  70         } else if (!hsotg->dumped_frame_num_array) {
  71                 int i;
  72
  73                 dev_info(hsotg->dev, "Frame     Last Frame\n");
  74                 dev_info(hsotg->dev, "-----     ----------\n");
  75                 for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
  76                         dev_info(hsotg->dev, "0x%04x    0x%04x\n",
  77                                  hsotg->frame_num_array[i],
  78                                  hsotg->last_frame_num_array[i]);
  79                 }
  80                 hsotg->dumped_frame_num_array = 1;
  81         }
  82         hsotg->last_frame_num = curr_frame_number;
  83 #endif
  84 }
  85
  86 static void dwc2_hc_handle_tt_clear(struct dwc2_hsotg *hsotg,
  87                                     struct dwc2_host_chan *chan,
  88                                     struct dwc2_qtd *qtd)
  89 {
  90         struct urb *usb_urb;
  91
  92         if (!chan->qh || !qtd->urb)
  93                 return;
  94
  95         usb_urb = qtd->urb->priv;
  96         if (!usb_urb || !usb_urb->dev)
  97                 return;
  98
  99         if (chan->qh->dev_speed != USB_SPEED_HIGH &&
 100             qtd->urb->status != -EPIPE && qtd->urb->status != -EREMOTEIO) {
 101                 chan->qh->tt_buffer_dirty = 1;
 102                 if (usb_hub_clear_tt_buffer(usb_urb))
 103                         /* Clear failed; let's hope things work anyway */
 104                         chan->qh->tt_buffer_dirty = 0;
 105         }
 106 }
 107
 108 /*
 109  * Handles the start-of-frame interrupt in host mode. Non-periodic
 110  * transactions may be queued to the DWC_otg controller for the current
 111  * (micro)frame. Periodic transactions may be queued to the controller
 112  * for the next (micro)frame.
 113  */
 114 static void dwc2_sof_intr(struct dwc2_hsotg *hsotg)
 115 {
 116         struct list_head *qh_entry;
 117         struct dwc2_qh *qh;
 118         enum dwc2_transaction_type tr_type;
 119
 120 #ifdef DEBUG_SOF
 121         dev_vdbg(hsotg->dev, "--Start of Frame Interrupt--\n");
 122 #endif
 123
 124         hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg);
 125
 126         dwc2_track_missed_sofs(hsotg);
 127
 128         /* Determine whether any periodic QHs should be executed */
 129         qh_entry = hsotg->periodic_sched_inactive.next;
 130         while (qh_entry != &hsotg->periodic_sched_inactive) {
 131                 qh = list_entry(qh_entry, struct dwc2_qh, qh_list_entry);
 132                 qh_entry = qh_entry->next;
 133                 if (dwc2_frame_num_le(qh->sched_frame, hsotg->frame_number))
 134                         /*
 135                          * Move QH to the ready list to be executed next
 136                          * (micro)frame
 137                          */
 138                         list_move(&qh->qh_list_entry,
 139                                   &hsotg->periodic_sched_ready);
 140         }
 141         tr_type = dwc2_hcd_select_transactions(hsotg);
 142         if (tr_type != DWC2_TRANSACTION_NONE)
 143                 dwc2_hcd_queue_transactions(hsotg, tr_type);
 144
 145         /* Clear interrupt */
 146         writel(GINTSTS_SOF, hsotg->regs + GINTSTS);
 147 }
 148
 149 /*
 150  * Handles the Rx FIFO Level Interrupt, which indicates that there is
 151  * at least one packet in the Rx FIFO. The packets are moved from the FIFO to
 152  * memory if the DWC_otg controller is operating in Slave mode.
 153  */
 154 static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg)
 155 {
 156         u32 grxsts, chnum, bcnt, dpid, pktsts;
 157         struct dwc2_host_chan *chan;
 158
 159         if (dbg_perio())
 160                 dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n");
 161
 162         grxsts = readl(hsotg->regs + GRXSTSP);
 163         chnum = grxsts >> GRXSTS_HCHNUM_SHIFT &
 164                 GRXSTS_HCHNUM_MASK >> GRXSTS_HCHNUM_SHIFT;
 165         chan = hsotg->hc_ptr_array[chnum];
 166         if (!chan) {
 167                 dev_err(hsotg->dev, "Unable to get corresponding channel\n");
 168                 return;
 169         }
 170
 171         bcnt = grxsts >> GRXSTS_BYTECNT_SHIFT &
 172                GRXSTS_BYTECNT_MASK >> GRXSTS_BYTECNT_SHIFT;
 173         dpid = grxsts >> GRXSTS_DPID_SHIFT &
 174                GRXSTS_DPID_MASK >> GRXSTS_DPID_SHIFT;
 175         pktsts = grxsts & GRXSTS_PKTSTS_MASK;
 176
 177         /* Packet Status */
 178         if (dbg_perio()) {
 179                 dev_vdbg(hsotg->dev, "    Ch num = %d\n", chnum);
 180                 dev_vdbg(hsotg->dev, "    Count = %d\n", bcnt);
 181                 dev_vdbg(hsotg->dev, "    DPID = %d, chan.dpid = %d\n", dpid,
 182                          chan->data_pid_start);
 183                 dev_vdbg(hsotg->dev, "    PStatus = %d\n",
 184                          pktsts >> GRXSTS_PKTSTS_SHIFT &
 185                          GRXSTS_PKTSTS_MASK >> GRXSTS_PKTSTS_SHIFT);
 186         }
 187
 188         switch (pktsts) {
 189         case GRXSTS_PKTSTS_HCHIN:
 190                 /* Read the data into the host buffer */
 191                 if (bcnt > 0) {
 192                         dwc2_read_packet(hsotg, chan->xfer_buf, bcnt);
 193
 194                         /* Update the HC fields for the next packet received */
 195                         chan->xfer_count += bcnt;
 196                         chan->xfer_buf += bcnt;
 197                 }
 198                 break;
 199         case GRXSTS_PKTSTS_HCHIN_XFER_COMP:
 200         case GRXSTS_PKTSTS_DATATOGGLEERR:
 201         case GRXSTS_PKTSTS_HCHHALTED:
 202                 /* Handled in interrupt, just ignore data */
 203                 break;
 204         default:
 205                 dev_err(hsotg->dev,
 206                         "RxFIFO Level Interrupt: Unknown status %d\n", pktsts);
 207                 break;
 208         }
 209 }
 210
 211 /*
 212  * This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
 213  * data packets may be written to the FIFO for OUT transfers. More requests
 214  * may be written to the non-periodic request queue for IN transfers. This
 215  * interrupt is enabled only in Slave mode.
 216  */
 217 static void dwc2_np_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
 218 {
 219         dev_vdbg(hsotg->dev, "--Non-Periodic TxFIFO Empty Interrupt--\n");
 220         dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_NON_PERIODIC);
 221 }
 222
 223 /*
 224  * This interrupt occurs when the periodic Tx FIFO is half-empty. More data
 225  * packets may be written to the FIFO for OUT transfers. More requests may be
 226  * written to the periodic request queue for IN transfers. This interrupt is
 227  * enabled only in Slave mode.
 228  */
 229 static void dwc2_perio_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
 230 {
 231         if (dbg_perio())
 232                 dev_vdbg(hsotg->dev, "--Periodic TxFIFO Empty Interrupt--\n");
 233         dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_PERIODIC);
 234 }
 235
 236 static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
 237                               u32 *hprt0_modify)
 238 {
 239         struct dwc2_core_params *params = hsotg->core_params;
 240         int do_reset = 0;
 241         u32 usbcfg;
 242         u32 prtspd;
 243         u32 hcfg;
 244         u32 fslspclksel;
 245         u32 hfir;
 246
 247         dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
 248
 249         /* Every time when port enables calculate HFIR.FrInterval */
 250         hfir = readl(hsotg->regs + HFIR);
 251         hfir &= ~HFIR_FRINT_MASK;
 252         hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT &
 253                 HFIR_FRINT_MASK;
 254         writel(hfir, hsotg->regs + HFIR);
 255
 256         /* Check if we need to adjust the PHY clock speed for low power */
 257         if (!params->host_support_fs_ls_low_power) {
 258                 /* Port has been enabled, set the reset change flag */
 259                 hsotg->flags.b.port_reset_change = 1;
 260                 return;
 261         }
 262
 263         usbcfg = readl(hsotg->regs + GUSBCFG);
 264         prtspd = hprt0 & HPRT0_SPD_MASK;
 265
 266         if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) {
 267                 /* Low power */
 268                 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL)) {
 269                         /* Set PHY low power clock select for FS/LS devices */
 270                         usbcfg |= GUSBCFG_PHY_LP_CLK_SEL;
 271                         writel(usbcfg, hsotg->regs + GUSBCFG);
 272                         do_reset = 1;
 273                 }
 274
 275                 hcfg = readl(hsotg->regs + HCFG);
 276                 fslspclksel = hcfg & HCFG_FSLSPCLKSEL_MASK;
 277
 278                 if (prtspd == HPRT0_SPD_LOW_SPEED &&
 279                     params->host_ls_low_power_phy_clk ==
 280                     DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ) {
 281                         /* 6 MHZ */
 282                         dev_vdbg(hsotg->dev,
 283                                  "FS_PHY programming HCFG to 6 MHz\n");
 284                         if (fslspclksel != HCFG_FSLSPCLKSEL_6_MHZ) {
 285                                 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
 286                                 hcfg |= HCFG_FSLSPCLKSEL_6_MHZ;
 287                                 writel(hcfg, hsotg->regs + HCFG);
 288                                 do_reset = 1;
 289                         }
 290                 } else {
 291                         /* 48 MHZ */
 292                         dev_vdbg(hsotg->dev,
 293                                  "FS_PHY programming HCFG to 48 MHz\n");
 294                         if (fslspclksel != HCFG_FSLSPCLKSEL_48_MHZ) {
 295                                 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
 296                                 hcfg |= HCFG_FSLSPCLKSEL_48_MHZ;
 297                                 writel(hcfg, hsotg->regs + HCFG);
 298                                 do_reset = 1;
 299                         }
 300                 }
 301         } else {
 302                 /* Not low power */
 303                 if (usbcfg & GUSBCFG_PHY_LP_CLK_SEL) {
 304                         usbcfg &= ~GUSBCFG_PHY_LP_CLK_SEL;
 305                         writel(usbcfg, hsotg->regs + GUSBCFG);
 306                         do_reset = 1;
 307                 }
 308         }
 309
 310         if (do_reset) {
 311                 *hprt0_modify |= HPRT0_RST;
 312                 queue_delayed_work(hsotg->wq_otg, &hsotg->reset_work,
 313                                    msecs_to_jiffies(60));
 314         } else {
 315                 /* Port has been enabled, set the reset change flag */
 316                 hsotg->flags.b.port_reset_change = 1;
 317         }
 318 }
 319
 320 /*
 321  * There are multiple conditions that can cause a port interrupt. This function
 322  * determines which interrupt conditions have occurred and handles them
 323  * appropriately.
 324  */
 325 static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
 326 {
 327         u32 hprt0;
 328         u32 hprt0_modify;
 329
 330         dev_vdbg(hsotg->dev, "--Port Interrupt--\n");
 331
 332         hprt0 = readl(hsotg->regs + HPRT0);
 333         hprt0_modify = hprt0;
 334
 335         /*
 336          * Clear appropriate bits in HPRT0 to clear the interrupt bit in
 337          * GINTSTS
 338          */
 339         hprt0_modify &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG |
 340                           HPRT0_OVRCURRCHG);
 341
 342         /*
 343          * Port Connect Detected
 344          * Set flag and clear if detected
 345          */
 346         if (hprt0 & HPRT0_CONNDET) {
 347                 dev_vdbg(hsotg->dev,
 348                          "--Port Interrupt HPRT0=0x%08x Port Connect Detected--\n",
 349                          hprt0);
 350                 hsotg->flags.b.port_connect_status_change = 1;
 351                 hsotg->flags.b.port_connect_status = 1;
 352                 hprt0_modify |= HPRT0_CONNDET;
 353
 354                 /*
 355                  * The Hub driver asserts a reset when it sees port connect
 356                  * status change flag
 357                  */
 358         }
 359
 360         /*
 361          * Port Enable Changed
 362          * Clear if detected - Set internal flag if disabled
 363          */
 364         if (hprt0 & HPRT0_ENACHG) {
 365                 dev_vdbg(hsotg->dev,
 366                          "  --Port Interrupt HPRT0=0x%08x Port Enable Changed (now %d)--\n",
 367                          hprt0, !!(hprt0 & HPRT0_ENA));
 368                 hprt0_modify |= HPRT0_ENACHG;
 369                 if (hprt0 & HPRT0_ENA)
 370                         dwc2_hprt0_enable(hsotg, hprt0, &hprt0_modify);
 371                 else
 372                         hsotg->flags.b.port_enable_change = 1;
 373         }
 374
 375         /* Overcurrent Change Interrupt */
 376         if (hprt0 & HPRT0_OVRCURRCHG) {
 377                 dev_vdbg(hsotg->dev,
 378                          "  --Port Interrupt HPRT0=0x%08x Port Overcurrent Changed--\n",
 379                          hprt0);
 380                 hsotg->flags.b.port_over_current_change = 1;
 381                 hprt0_modify |= HPRT0_OVRCURRCHG;
 382         }
 383
 384         /* Clear Port Interrupts */
 385         writel(hprt0_modify, hsotg->regs + HPRT0);
 386 }
 387
 388 /*
 389  * Gets the actual length of a transfer after the transfer halts. halt_status
 390  * holds the reason for the halt.
 391  *
 392  * For IN transfers where halt_status is DWC2_HC_XFER_COMPLETE, *short_read
 393  * is set to 1 upon return if less than the requested number of bytes were
 394  * transferred. short_read may also be NULL on entry, in which case it remains
 395  * unchanged.
 396  */
 397 static u32 dwc2_get_actual_xfer_length(struct dwc2_hsotg *hsotg,
 398                                        struct dwc2_host_chan *chan, int chnum,
 399                                        struct dwc2_qtd *qtd,
 400                                        enum dwc2_halt_status halt_status,
 401                                        int *short_read)
 402 {
 403         u32 hctsiz, count, length;
 404
 405         hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
 406
 407         if (halt_status == DWC2_HC_XFER_COMPLETE) {
 408                 if (chan->ep_is_in) {
 409                         count = hctsiz >> TSIZ_XFERSIZE_SHIFT &
 410                                 TSIZ_XFERSIZE_MASK >> TSIZ_XFERSIZE_SHIFT;
 411                         length = chan->xfer_len - count;
 412                         if (short_read != NULL)
 413                                 *short_read = (count != 0);
 414                 } else if (chan->qh->do_split) {
 415                         length = qtd->ssplit_out_xfer_count;
 416                 } else {
 417                         length = chan->xfer_len;
 418                 }
 419         } else {
 420                 /*
 421                  * Must use the hctsiz.pktcnt field to determine how much data
 422                  * has been transferred. This field reflects the number of
 423                  * packets that have been transferred via the USB. This is
 424                  * always an integral number of packets if the transfer was
 425                  * halted before its normal completion. (Can't use the
 426                  * hctsiz.xfersize field because that reflects the number of
 427                  * bytes transferred via the AHB, not the USB).
 428                  */
 429                 count = hctsiz >> TSIZ_PKTCNT_SHIFT &
 430                         TSIZ_PKTCNT_MASK >> TSIZ_PKTCNT_SHIFT;
 431                 length = (chan->start_pkt_count - count) * chan->max_packet;
 432         }
 433
 434         return length;
 435 }
 436
 437 /**
 438  * dwc2_update_urb_state() - Updates the state of the URB after a Transfer
 439  * Complete interrupt on the host channel. Updates the actual_length field
 440  * of the URB based on the number of bytes transferred via the host channel.
 441  * Sets the URB status if the data transfer is finished.
 442  *
 443  * Return: 1 if the data transfer specified by the URB is completely finished,
 444  * 0 otherwise
 445  */
 446 static int dwc2_update_urb_state(struct dwc2_hsotg *hsotg,
 447                                  struct dwc2_host_chan *chan, int chnum,
 448                                  struct dwc2_hcd_urb *urb,
 449                                  struct dwc2_qtd *qtd)
 450 {
 451         u32 hctsiz;
 452         int xfer_done = 0;
 453         int short_read = 0;
 454         int xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
 455                                                       DWC2_HC_XFER_COMPLETE,
 456                                                       &short_read);
 457
 458         if (urb->actual_length + xfer_length > urb->length) {
 459                 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__);
 460                 xfer_length = urb->length - urb->actual_length;
 461         }
 462
 463         /* Non DWORD-aligned buffer case handling */
 464         if (chan->align_buf && xfer_length && chan->ep_is_in) {
 465                 dev_dbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
 466                 dma_sync_single_for_cpu(hsotg->dev, urb->dma, urb->length,
 467                                         DMA_FROM_DEVICE);
 468                 memcpy(urb->buf + urb->actual_length, chan->qh->dw_align_buf,
 469                        xfer_length);
 470                 dma_sync_single_for_device(hsotg->dev, urb->dma, urb->length,
 471                                            DMA_FROM_DEVICE);
 472         }
 473
 474         dev_vdbg(hsotg->dev, "urb->actual_length=%d xfer_length=%d\n",
 475                  urb->actual_length, xfer_length);
 476         urb->actual_length += xfer_length;
 477
 478         if (xfer_length && chan->ep_type == USB_ENDPOINT_XFER_BULK &&
 479             (urb->flags & URB_SEND_ZERO_PACKET) &&
 480             urb->actual_length >= urb->length &&
 481             !(urb->length % chan->max_packet)) {
 482                 xfer_done = 0;
 483         } else if (short_read || urb->actual_length >= urb->length) {
 484                 xfer_done = 1;
 485                 urb->status = 0;
 486         }
 487
 488         hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
 489         dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
 490                  __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
 491         dev_vdbg(hsotg->dev, "  chan->xfer_len %d\n", chan->xfer_len);
 492         dev_vdbg(hsotg->dev, "  hctsiz.xfersize %d\n",
 493                  hctsiz >> TSIZ_XFERSIZE_SHIFT &
 494                  TSIZ_XFERSIZE_MASK >> TSIZ_XFERSIZE_SHIFT);
 495         dev_vdbg(hsotg->dev, "  urb->transfer_buffer_length %d\n", urb->length);
 496         dev_vdbg(hsotg->dev, "  urb->actual_length %d\n", urb->actual_length);
 497         dev_vdbg(hsotg->dev, "  short_read %d, xfer_done %d\n", short_read,
 498                  xfer_done);
 499
 500         return xfer_done;
 501 }
 502
 503 /*
 504  * Save the starting data toggle for the next transfer. The data toggle is
 505  * saved in the QH for non-control transfers and it's saved in the QTD for
 506  * control transfers.
 507  */
 508 void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
 509                                struct dwc2_host_chan *chan, int chnum,
 510                                struct dwc2_qtd *qtd)
 511 {
 512         u32 hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
 513         u32 pid = hctsiz & TSIZ_SC_MC_PID_MASK;
 514
 515         if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) {
 516                 if (pid == TSIZ_SC_MC_PID_DATA0)
 517                         chan->qh->data_toggle = DWC2_HC_PID_DATA0;
 518                 else
 519                         chan->qh->data_toggle = DWC2_HC_PID_DATA1;
 520         } else {
 521                 if (pid == TSIZ_SC_MC_PID_DATA0)
 522                         qtd->data_toggle = DWC2_HC_PID_DATA0;
 523                 else
 524                         qtd->data_toggle = DWC2_HC_PID_DATA1;
 525         }
 526 }
 527
 528 /**
 529  * dwc2_update_isoc_urb_state() - Updates the state of an Isochronous URB when
 530  * the transfer is stopped for any reason. The fields of the current entry in
 531  * the frame descriptor array are set based on the transfer state and the input
 532  * halt_status. Completes the Isochronous URB if all the URB frames have been
 533  * completed.
 534  *
 535  * Return: DWC2_HC_XFER_COMPLETE if there are more frames remaining to be
 536  * transferred in the URB. Otherwise return DWC2_HC_XFER_URB_COMPLETE.
 537  */
 538 static enum dwc2_halt_status dwc2_update_isoc_urb_state(
 539                 struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
 540                 int chnum, struct dwc2_qtd *qtd,
 541                 enum dwc2_halt_status halt_status)
 542 {
 543         struct dwc2_hcd_iso_packet_desc *frame_desc;
 544         struct dwc2_hcd_urb *urb = qtd->urb;
 545
 546         if (!urb)
 547                 return DWC2_HC_XFER_NO_HALT_STATUS;
 548
 549         frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
 550
 551         switch (halt_status) {
 552         case DWC2_HC_XFER_COMPLETE:
 553                 frame_desc->status = 0;
 554                 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
 555                                         chan, chnum, qtd, halt_status, NULL);
 556
 557                 /* Non DWORD-aligned buffer case handling */
 558                 if (chan->align_buf && frame_desc->actual_length &&
 559                     chan->ep_is_in) {
 560                         dev_dbg(hsotg->dev, "%s(): non-aligned buffer\n",
 561                                 __func__);
 562                         dma_sync_single_for_cpu(hsotg->dev, urb->dma,
 563                                                 urb->length, DMA_FROM_DEVICE);
 564                         memcpy(urb->buf + frame_desc->offset +
 565                                qtd->isoc_split_offset, chan->qh->dw_align_buf,
 566                                frame_desc->actual_length);
 567                         dma_sync_single_for_device(hsotg->dev, urb->dma,
 568                                                    urb->length,
 569                                                    DMA_FROM_DEVICE);
 570                 }
 571                 break;
 572         case DWC2_HC_XFER_FRAME_OVERRUN:
 573                 urb->error_count++;
 574                 if (chan->ep_is_in)
 575                         frame_desc->status = -ENOSR;
 576                 else
 577                         frame_desc->status = -ECOMM;
 578                 frame_desc->actual_length = 0;
 579                 break;
 580         case DWC2_HC_XFER_BABBLE_ERR:
 581                 urb->error_count++;
 582                 frame_desc->status = -EOVERFLOW;
 583                 /* Don't need to update actual_length in this case */
 584                 break;
 585         case DWC2_HC_XFER_XACT_ERR:
 586                 urb->error_count++;
 587                 frame_desc->status = -EPROTO;
 588                 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
 589                                         chan, chnum, qtd, halt_status, NULL);
 590
 591                 /* Non DWORD-aligned buffer case handling */
 592                 if (chan->align_buf && frame_desc->actual_length &&
 593                     chan->ep_is_in) {
 594                         dev_dbg(hsotg->dev, "%s(): non-aligned buffer\n",
 595                                 __func__);
 596                         dma_sync_single_for_cpu(hsotg->dev, urb->dma,
 597                                                 urb->length, DMA_FROM_DEVICE);
 598                         memcpy(urb->buf + frame_desc->offset +
 599                                qtd->isoc_split_offset, chan->qh->dw_align_buf,
 600                                frame_desc->actual_length);
 601                         dma_sync_single_for_device(hsotg->dev, urb->dma,
 602                                                    urb->length,
 603                                                    DMA_FROM_DEVICE);
 604                 }
 605
 606                 /* Skip whole frame */
 607                 if (chan->qh->do_split &&
 608                     chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
 609                     hsotg->core_params->dma_enable > 0) {
 610                         qtd->complete_split = 0;
 611                         qtd->isoc_split_offset = 0;
 612                 }
 613
 614                 break;
 615         default:
 616                 dev_err(hsotg->dev, "Unhandled halt_status (%d)\n",
 617                         halt_status);
 618                 break;
 619         }
 620
 621         if (++qtd->isoc_frame_index == urb->packet_count) {
 622                 /*
 623                  * urb->status is not used for isoc transfers. The individual
 624                  * frame_desc statuses are used instead.
 625                  */
 626                 dwc2_host_complete(hsotg, qtd, 0);
 627                 halt_status = DWC2_HC_XFER_URB_COMPLETE;
 628         } else {
 629                 halt_status = DWC2_HC_XFER_COMPLETE;
 630         }
 631
 632         return halt_status;
 633 }
 634
 635 /*
 636  * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
 637  * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
 638  * still linked to the QH, the QH is added to the end of the inactive
 639  * non-periodic schedule. For periodic QHs, removes the QH from the periodic
 640  * schedule if no more QTDs are linked to the QH.
 641  */
 642 static void dwc2_deactivate_qh(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
 643                                int free_qtd)
 644 {
 645         int continue_split = 0;
 646         struct dwc2_qtd *qtd;
 647
 648         if (dbg_qh(qh))
 649                 dev_vdbg(hsotg->dev, "  %s(%p,%p,%d)\n", __func__,
 650                          hsotg, qh, free_qtd);
 651
 652         if (list_empty(&qh->qtd_list)) {
 653                 dev_dbg(hsotg->dev, "## QTD list empty ##\n");
 654                 goto no_qtd;
 655         }
 656
 657         qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
 658
 659         if (qtd->complete_split)
 660                 continue_split = 1;
 661         else if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_MID ||
 662                  qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_END)
 663                 continue_split = 1;
 664
 665         if (free_qtd) {
 666                 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
 667                 continue_split = 0;
 668         }
 669
 670 no_qtd:
 671         if (qh->channel)
 672                 qh->channel->align_buf = 0;
 673         qh->channel = NULL;
 674         dwc2_hcd_qh_deactivate(hsotg, qh, continue_split);
 675 }
 676
 677 /**
 678  * dwc2_release_channel() - Releases a host channel for use by other transfers
 679  *
 680  * @hsotg:       The HCD state structure
 681  * @chan:        The host channel to release
 682  * @qtd:         The QTD associated with the host channel. This QTD may be
 683  *               freed if the transfer is complete or an error has occurred.
 684  * @halt_status: Reason the channel is being released. This status
 685  *               determines the actions taken by this function.
 686  *
 687  * Also attempts to select and queue more transactions since at least one host
 688  * channel is available.
 689  */
 690 static void dwc2_release_channel(struct dwc2_hsotg *hsotg,
 691                                  struct dwc2_host_chan *chan,
 692                                  struct dwc2_qtd *qtd,
 693                                  enum dwc2_halt_status halt_status)
 694 {
 695         enum dwc2_transaction_type tr_type;
 696         u32 haintmsk;
 697         int free_qtd = 0;
 698
 699         if (dbg_hc(chan))
 700                 dev_vdbg(hsotg->dev, "  %s: channel %d, halt_status %d\n",
 701                          __func__, chan->hc_num, halt_status);
 702
 703         switch (halt_status) {
 704         case DWC2_HC_XFER_URB_COMPLETE:
 705                 free_qtd = 1;
 706                 break;
 707         case DWC2_HC_XFER_AHB_ERR:
 708         case DWC2_HC_XFER_STALL:
 709         case DWC2_HC_XFER_BABBLE_ERR:
 710                 free_qtd = 1;
 711                 break;
 712         case DWC2_HC_XFER_XACT_ERR:
 713                 if (qtd && qtd->error_count >= 3) {
 714                         dev_vdbg(hsotg->dev,
 715                                  "  Complete URB with transaction error\n");
 716                         free_qtd = 1;
 717                         dwc2_host_complete(hsotg, qtd, -EPROTO);
 718                 }
 719                 break;
 720         case DWC2_HC_XFER_URB_DEQUEUE:
 721                 /*
 722                  * The QTD has already been removed and the QH has been
 723                  * deactivated. Don't want to do anything except release the
 724                  * host channel and try to queue more transfers.
 725                  */
 726                 goto cleanup;
 727         case DWC2_HC_XFER_PERIODIC_INCOMPLETE:
 728                 dev_vdbg(hsotg->dev, "  Complete URB with I/O error\n");
 729                 free_qtd = 1;
 730                 dwc2_host_complete(hsotg, qtd, -EIO);
 731                 break;
 732         case DWC2_HC_XFER_NO_HALT_STATUS:
 733         default:
 734                 break;
 735         }
 736
 737         dwc2_deactivate_qh(hsotg, chan->qh, free_qtd);
 738
 739 cleanup:
 740         /*
 741          * Release the host channel for use by other transfers. The cleanup
 742          * function clears the channel interrupt enables and conditions, so
 743          * there's no need to clear the Channel Halted interrupt separately.
 744          */
 745         if (!list_empty(&chan->hc_list_entry))
 746                 list_del(&chan->hc_list_entry);
 747         dwc2_hc_cleanup(hsotg, chan);
 748         list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
 749
 750         switch (chan->ep_type) {
 751         case USB_ENDPOINT_XFER_CONTROL:
 752         case USB_ENDPOINT_XFER_BULK:
 753                 hsotg->non_periodic_channels--;
 754                 break;
 755         default:
 756                 /*
 757                  * Don't release reservations for periodic channels here.
 758                  * That's done when a periodic transfer is descheduled (i.e.
 759                  * when the QH is removed from the periodic schedule).
 760                  */
 761                 break;
 762         }
 763
 764         haintmsk = readl(hsotg->regs + HAINTMSK);
 765         haintmsk &= ~(1 << chan->hc_num);
 766         writel(haintmsk, hsotg->regs + HAINTMSK);
 767
 768         /* Try to queue more transfers now that there's a free channel */
 769         tr_type = dwc2_hcd_select_transactions(hsotg);
 770         if (tr_type != DWC2_TRANSACTION_NONE)
 771                 dwc2_hcd_queue_transactions(hsotg, tr_type);
 772 }
 773
 774 /*
 775  * Halts a host channel. If the channel cannot be halted immediately because
 776  * the request queue is full, this function ensures that the FIFO empty
 777  * interrupt for the appropriate queue is enabled so that the halt request can
 778  * be queued when there is space in the request queue.
 779  *
 780  * This function may also be called in DMA mode. In that case, the channel is
 781  * simply released since the core always halts the channel automatically in
 782  * DMA mode.
 783  */
 784 static void dwc2_halt_channel(struct dwc2_hsotg *hsotg,
 785                               struct dwc2_host_chan *chan, struct dwc2_qtd *qtd,
 786                               enum dwc2_halt_status halt_status)
 787 {
 788         if (dbg_hc(chan))
 789                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
 790
 791         if (hsotg->core_params->dma_enable > 0) {
 792                 if (dbg_hc(chan))
 793                         dev_vdbg(hsotg->dev, "DMA enabled\n");
 794                 dwc2_release_channel(hsotg, chan, qtd, halt_status);
 795                 return;
 796         }
 797
 798         /* Slave mode processing */
 799         dwc2_hc_halt(hsotg, chan, halt_status);
 800
 801         if (chan->halt_on_queue) {
 802                 u32 gintmsk;
 803
 804                 dev_vdbg(hsotg->dev, "Halt on queue\n");
 805                 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
 806                     chan->ep_type == USB_ENDPOINT_XFER_BULK) {
 807                         dev_vdbg(hsotg->dev, "control/bulk\n");
 808                         /*
 809                          * Make sure the Non-periodic Tx FIFO empty interrupt
 810                          * is enabled so that the non-periodic schedule will
 811                          * be processed
 812                          */
 813                         gintmsk = readl(hsotg->regs + GINTMSK);
 814                         gintmsk |= GINTSTS_NPTXFEMP;
 815                         writel(gintmsk, hsotg->regs + GINTMSK);
 816                 } else {
 817                         dev_vdbg(hsotg->dev, "isoc/intr\n");
 818                         /*
 819                          * Move the QH from the periodic queued schedule to
 820                          * the periodic assigned schedule. This allows the
 821                          * halt to be queued when the periodic schedule is
 822                          * processed.
 823                          */
 824                         list_move(&chan->qh->qh_list_entry,
 825                                   &hsotg->periodic_sched_assigned);
 826
 827                         /*
 828                          * Make sure the Periodic Tx FIFO Empty interrupt is
 829                          * enabled so that the periodic schedule will be
 830                          * processed
 831                          */
 832                         gintmsk = readl(hsotg->regs + GINTMSK);
 833                         gintmsk |= GINTSTS_PTXFEMP;
 834                         writel(gintmsk, hsotg->regs + GINTMSK);
 835                 }
 836         }
 837 }
 838
 839 /*
 840  * Performs common cleanup for non-periodic transfers after a Transfer
 841  * Complete interrupt. This function should be called after any endpoint type
 842  * specific handling is finished to release the host channel.
 843  */
 844 static void dwc2_complete_non_periodic_xfer(struct dwc2_hsotg *hsotg,
 845                                             struct dwc2_host_chan *chan,
 846                                             int chnum, struct dwc2_qtd *qtd,
 847                                             enum dwc2_halt_status halt_status)
 848 {
 849         dev_vdbg(hsotg->dev, "%s()\n", __func__);
 850
 851         qtd->error_count = 0;
 852
 853         if (chan->hcint & HCINTMSK_NYET) {
 854                 /*
 855                  * Got a NYET on the last transaction of the transfer. This
 856                  * means that the endpoint should be in the PING state at the
 857                  * beginning of the next transfer.
 858                  */
 859                 dev_vdbg(hsotg->dev, "got NYET\n");
 860                 chan->qh->ping_state = 1;
 861         }
 862
 863         /*
 864          * Always halt and release the host channel to make it available for
 865          * more transfers. There may still be more phases for a control
 866          * transfer or more data packets for a bulk transfer at this point,
 867          * but the host channel is still halted. A channel will be reassigned
 868          * to the transfer when the non-periodic schedule is processed after
 869          * the channel is released. This allows transactions to be queued
 870          * properly via dwc2_hcd_queue_transactions, which also enables the
 871          * Tx FIFO Empty interrupt if necessary.
 872          */
 873         if (chan->ep_is_in) {
 874                 /*
 875                  * IN transfers in Slave mode require an explicit disable to
 876                  * halt the channel. (In DMA mode, this call simply releases
 877                  * the channel.)
 878                  */
 879                 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
 880         } else {
 881                 /*
 882                  * The channel is automatically disabled by the core for OUT
 883                  * transfers in Slave mode
 884                  */
 885                 dwc2_release_channel(hsotg, chan, qtd, halt_status);
 886         }
 887 }
 888
 889 /*
 890  * Performs common cleanup for periodic transfers after a Transfer Complete
 891  * interrupt. This function should be called after any endpoint type specific
 892  * handling is finished to release the host channel.
 893  */
 894 static void dwc2_complete_periodic_xfer(struct dwc2_hsotg *hsotg,
 895                                         struct dwc2_host_chan *chan, int chnum,
 896                                         struct dwc2_qtd *qtd,
 897                                         enum dwc2_halt_status halt_status)
 898 {
 899         u32 hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
 900
 901         qtd->error_count = 0;
 902
 903         if (!chan->ep_is_in || (hctsiz & TSIZ_PKTCNT_MASK) == 0)
 904                 /* Core halts channel in these cases */
 905                 dwc2_release_channel(hsotg, chan, qtd, halt_status);
 906         else
 907                 /* Flush any outstanding requests from the Tx queue */
 908                 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
 909 }
 910
 911 static int dwc2_xfercomp_isoc_split_in(struct dwc2_hsotg *hsotg,
 912                                        struct dwc2_host_chan *chan, int chnum,
 913                                        struct dwc2_qtd *qtd)
 914 {
 915         struct dwc2_hcd_iso_packet_desc *frame_desc;
 916         u32 len;
 917
 918         if (!qtd->urb)
 919                 return 0;
 920
 921         frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
 922         len = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
 923                                           DWC2_HC_XFER_COMPLETE, NULL);
 924         if (!len) {
 925                 qtd->complete_split = 0;
 926                 qtd->isoc_split_offset = 0;
 927                 return 0;
 928         }
 929
 930         frame_desc->actual_length += len;
 931
 932         if (chan->align_buf && len) {
 933                 dev_dbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
 934                 dma_sync_single_for_cpu(hsotg->dev, qtd->urb->dma,
 935                                         qtd->urb->length, DMA_FROM_DEVICE);
 936                 memcpy(qtd->urb->buf + frame_desc->offset +
 937                        qtd->isoc_split_offset, chan->qh->dw_align_buf, len);
 938                 dma_sync_single_for_device(hsotg->dev, qtd->urb->dma,
 939                                            qtd->urb->length, DMA_FROM_DEVICE);
 940         }
 941
 942         qtd->isoc_split_offset += len;
 943
 944         if (frame_desc->actual_length >= frame_desc->length) {
 945                 frame_desc->status = 0;
 946                 qtd->isoc_frame_index++;
 947                 qtd->complete_split = 0;
 948                 qtd->isoc_split_offset = 0;
 949         }
 950
 951         if (qtd->isoc_frame_index == qtd->urb->packet_count) {
 952                 dwc2_host_complete(hsotg, qtd, 0);
 953                 dwc2_release_channel(hsotg, chan, qtd,
 954                                      DWC2_HC_XFER_URB_COMPLETE);
 955         } else {
 956                 dwc2_release_channel(hsotg, chan, qtd,
 957                                      DWC2_HC_XFER_NO_HALT_STATUS);
 958         }
 959
 960         return 1;       /* Indicates that channel released */
 961 }
 962
 963 /*
 964  * Handles a host channel Transfer Complete interrupt. This handler may be
 965  * called in either DMA mode or Slave mode.
 966  */
 967 static void dwc2_hc_xfercomp_intr(struct dwc2_hsotg *hsotg,
 968                                   struct dwc2_host_chan *chan, int chnum,
 969                                   struct dwc2_qtd *qtd)
 970 {
 971         struct dwc2_hcd_urb *urb = qtd->urb;
 972         int pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
 973         enum dwc2_halt_status halt_status = DWC2_HC_XFER_COMPLETE;
 974         int urb_xfer_done;
 975
 976         if (dbg_hc(chan))
 977                 dev_vdbg(hsotg->dev,
 978                          "--Host Channel %d Interrupt: Transfer Complete--\n",
 979                          chnum);
 980
 981         if (hsotg->core_params->dma_desc_enable > 0) {
 982                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, halt_status);
 983                 if (pipe_type == USB_ENDPOINT_XFER_ISOC)
 984                         /* Do not disable the interrupt, just clear it */
 985                         return;
 986                 goto handle_xfercomp_done;
 987         }
 988
 989         /* Handle xfer complete on CSPLIT */
 990         if (chan->qh->do_split) {
 991                 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
 992                     hsotg->core_params->dma_enable > 0) {
 993                         if (qtd->complete_split &&
 994                             dwc2_xfercomp_isoc_split_in(hsotg, chan, chnum,
 995                                                         qtd))
 996                                 goto handle_xfercomp_done;
 997                 } else {
 998                         qtd->complete_split = 0;
 999                 }
1000         }
1001
1002         if (!urb)
1003                 goto handle_xfercomp_done;
1004
1005         /* Update the QTD and URB states */
1006         switch (pipe_type) {
1007         case USB_ENDPOINT_XFER_CONTROL:
1008                 switch (qtd->control_phase) {
1009                 case DWC2_CONTROL_SETUP:
1010                         if (urb->length > 0)
1011                                 qtd->control_phase = DWC2_CONTROL_DATA;
1012                         else
1013                                 qtd->control_phase = DWC2_CONTROL_STATUS;
1014                         dev_vdbg(hsotg->dev,
1015                                  "  Control setup transaction done\n");
1016                         halt_status = DWC2_HC_XFER_COMPLETE;
1017                         break;
1018                 case DWC2_CONTROL_DATA:
1019                         urb_xfer_done = dwc2_update_urb_state(hsotg, chan,
1020                                                               chnum, urb, qtd);
1021                         if (urb_xfer_done) {
1022                                 qtd->control_phase = DWC2_CONTROL_STATUS;
1023                                 dev_vdbg(hsotg->dev,
1024                                          "  Control data transfer done\n");
1025                         } else {
1026                                 dwc2_hcd_save_data_toggle(hsotg, chan, chnum,
1027                                                           qtd);
1028                         }
1029                         halt_status = DWC2_HC_XFER_COMPLETE;
1030                         break;
1031                 case DWC2_CONTROL_STATUS:
1032                         dev_vdbg(hsotg->dev, "  Control transfer complete\n");
1033                         if (urb->status == -EINPROGRESS)
1034                                 urb->status = 0;
1035                         dwc2_host_complete(hsotg, qtd, urb->status);
1036                         halt_status = DWC2_HC_XFER_URB_COMPLETE;
1037                         break;
1038                 }
1039
1040                 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1041                                                 halt_status);
1042                 break;
1043         case USB_ENDPOINT_XFER_BULK:
1044                 dev_vdbg(hsotg->dev, "  Bulk transfer complete\n");
1045                 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1046                                                       qtd);
1047                 if (urb_xfer_done) {
1048                         dwc2_host_complete(hsotg, qtd, urb->status);
1049                         halt_status = DWC2_HC_XFER_URB_COMPLETE;
1050                 } else {
1051                         halt_status = DWC2_HC_XFER_COMPLETE;
1052                 }
1053
1054                 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1055                 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1056                                                 halt_status);
1057                 break;
1058         case USB_ENDPOINT_XFER_INT:
1059                 dev_vdbg(hsotg->dev, "  Interrupt transfer complete\n");
1060                 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1061                                                       qtd);
1062
1063                 /*
1064                  * Interrupt URB is done on the first transfer complete
1065                  * interrupt
1066                  */
1067                 if (urb_xfer_done) {
1068                         dwc2_host_complete(hsotg, qtd, urb->status);
1069                         halt_status = DWC2_HC_XFER_URB_COMPLETE;
1070                 } else {
1071                         halt_status = DWC2_HC_XFER_COMPLETE;
1072                 }
1073
1074                 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1075                 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1076                                             halt_status);
1077                 break;
1078         case USB_ENDPOINT_XFER_ISOC:
1079                 if (dbg_perio())
1080                         dev_vdbg(hsotg->dev, "  Isochronous transfer complete\n");
1081                 if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_ALL)
1082                         halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1083                                         chnum, qtd, DWC2_HC_XFER_COMPLETE);
1084                 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1085                                             halt_status);
1086                 break;
1087         }
1088
1089 handle_xfercomp_done:
1090         disable_hc_int(hsotg, chnum, HCINTMSK_XFERCOMPL);
1091 }
1092
1093 /*
1094  * Handles a host channel STALL interrupt. This handler may be called in
1095  * either DMA mode or Slave mode.
1096  */
1097 static void dwc2_hc_stall_intr(struct dwc2_hsotg *hsotg,
1098                                struct dwc2_host_chan *chan, int chnum,
1099                                struct dwc2_qtd *qtd)
1100 {
1101         struct dwc2_hcd_urb *urb = qtd->urb;
1102         int pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
1103
1104         dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: STALL Received--\n",
1105                 chnum);
1106
1107         if (hsotg->core_params->dma_desc_enable > 0) {
1108                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1109                                             DWC2_HC_XFER_STALL);
1110                 goto handle_stall_done;
1111         }
1112
1113         if (!urb)
1114                 goto handle_stall_halt;
1115
1116         if (pipe_type == USB_ENDPOINT_XFER_CONTROL)
1117                 dwc2_host_complete(hsotg, qtd, -EPIPE);
1118
1119         if (pipe_type == USB_ENDPOINT_XFER_BULK ||
1120             pipe_type == USB_ENDPOINT_XFER_INT) {
1121                 dwc2_host_complete(hsotg, qtd, -EPIPE);
1122                 /*
1123                  * USB protocol requires resetting the data toggle for bulk
1124                  * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
1125                  * setup command is issued to the endpoint. Anticipate the
1126                  * CLEAR_FEATURE command since a STALL has occurred and reset
1127                  * the data toggle now.
1128                  */
1129                 chan->qh->data_toggle = 0;
1130         }
1131
1132 handle_stall_halt:
1133         dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_STALL);
1134
1135 handle_stall_done:
1136         disable_hc_int(hsotg, chnum, HCINTMSK_STALL);
1137 }
1138
1139 /*
1140  * Updates the state of the URB when a transfer has been stopped due to an
1141  * abnormal condition before the transfer completes. Modifies the
1142  * actual_length field of the URB to reflect the number of bytes that have
1143  * actually been transferred via the host channel.
1144  */
1145 static void dwc2_update_urb_state_abn(struct dwc2_hsotg *hsotg,
1146                                       struct dwc2_host_chan *chan, int chnum,
1147                                       struct dwc2_hcd_urb *urb,
1148                                       struct dwc2_qtd *qtd,
1149                                       enum dwc2_halt_status halt_status)
1150 {
1151         u32 xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum,
1152                                                       qtd, halt_status, NULL);
1153         u32 hctsiz;
1154
1155         if (urb->actual_length + xfer_length > urb->length) {
1156                 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__);
1157                 xfer_length = urb->length - urb->actual_length;
1158         }
1159
1160         /* Non DWORD-aligned buffer case handling */
1161         if (chan->align_buf && xfer_length && chan->ep_is_in) {
1162                 dev_dbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
1163                 dma_sync_single_for_cpu(hsotg->dev, urb->dma, urb->length,
1164                                         DMA_FROM_DEVICE);
1165                 memcpy(urb->buf + urb->actual_length, chan->qh->dw_align_buf,
1166                        xfer_length);
1167                 dma_sync_single_for_device(hsotg->dev, urb->dma, urb->length,
1168                                            DMA_FROM_DEVICE);
1169         }
1170
1171         urb->actual_length += xfer_length;
1172
1173         hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
1174         dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
1175                  __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
1176         dev_vdbg(hsotg->dev, "  chan->start_pkt_count %d\n",
1177                  chan->start_pkt_count);
1178         dev_vdbg(hsotg->dev, "  hctsiz.pktcnt %d\n",
1179                  hctsiz >> TSIZ_PKTCNT_SHIFT &
1180                  TSIZ_PKTCNT_MASK >> TSIZ_PKTCNT_SHIFT);
1181         dev_vdbg(hsotg->dev, "  chan->max_packet %d\n", chan->max_packet);
1182         dev_vdbg(hsotg->dev, "  bytes_transferred %d\n",
1183                  xfer_length);
1184         dev_vdbg(hsotg->dev, "  urb->actual_length %d\n",
1185                  urb->actual_length);
1186         dev_vdbg(hsotg->dev, "  urb->transfer_buffer_length %d\n",
1187                  urb->length);
1188 }
1189
1190 /*
1191  * Handles a host channel NAK interrupt. This handler may be called in either
1192  * DMA mode or Slave mode.
1193  */
1194 static void dwc2_hc_nak_intr(struct dwc2_hsotg *hsotg,
1195                              struct dwc2_host_chan *chan, int chnum,
1196                              struct dwc2_qtd *qtd)
1197 {
1198         if (dbg_hc(chan))
1199                 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NAK Received--\n",
1200                          chnum);
1201
1202         /*
1203          * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
1204          * interrupt. Re-start the SSPLIT transfer.
1205          */
1206         if (chan->do_split) {
1207                 if (chan->complete_split)
1208                         qtd->error_count = 0;
1209                 qtd->complete_split = 0;
1210                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1211                 goto handle_nak_done;
1212         }
1213
1214         switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1215         case USB_ENDPOINT_XFER_CONTROL:
1216         case USB_ENDPOINT_XFER_BULK:
1217                 if (hsotg->core_params->dma_enable > 0 && chan->ep_is_in) {
1218                         /*
1219                          * NAK interrupts are enabled on bulk/control IN
1220                          * transfers in DMA mode for the sole purpose of
1221                          * resetting the error count after a transaction error
1222                          * occurs. The core will continue transferring data.
1223                          */
1224                         qtd->error_count = 0;
1225                         break;
1226                 }
1227
1228                 /*
1229                  * NAK interrupts normally occur during OUT transfers in DMA
1230                  * or Slave mode. For IN transfers, more requests will be
1231                  * queued as request queue space is available.
1232                  */
1233                 qtd->error_count = 0;
1234
1235                 if (!chan->qh->ping_state) {
1236                         dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1237                                                   qtd, DWC2_HC_XFER_NAK);
1238                         dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1239
1240                         if (chan->speed == USB_SPEED_HIGH)
1241                                 chan->qh->ping_state = 1;
1242                 }
1243
1244                 /*
1245                  * Halt the channel so the transfer can be re-started from
1246                  * the appropriate point or the PING protocol will
1247                  * start/continue
1248                  */
1249                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1250                 break;
1251         case USB_ENDPOINT_XFER_INT:
1252                 qtd->error_count = 0;
1253                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1254                 break;
1255         case USB_ENDPOINT_XFER_ISOC:
1256                 /* Should never get called for isochronous transfers */
1257                 dev_err(hsotg->dev, "NACK interrupt for ISOC transfer\n");
1258                 break;
1259         }
1260
1261 handle_nak_done:
1262         disable_hc_int(hsotg, chnum, HCINTMSK_NAK);
1263 }
1264
1265 /*
1266  * Handles a host channel ACK interrupt. This interrupt is enabled when
1267  * performing the PING protocol in Slave mode, when errors occur during
1268  * either Slave mode or DMA mode, and during Start Split transactions.
1269  */
1270 static void dwc2_hc_ack_intr(struct dwc2_hsotg *hsotg,
1271                              struct dwc2_host_chan *chan, int chnum,
1272                              struct dwc2_qtd *qtd)
1273 {
1274         struct dwc2_hcd_iso_packet_desc *frame_desc;
1275
1276         if (dbg_hc(chan))
1277                 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: ACK Received--\n",
1278                          chnum);
1279
1280         if (chan->do_split) {
1281                 /* Handle ACK on SSPLIT. ACK should not occur in CSPLIT. */
1282                 if (!chan->ep_is_in &&
1283                     chan->data_pid_start != DWC2_HC_PID_SETUP)
1284                         qtd->ssplit_out_xfer_count = chan->xfer_len;
1285
1286                 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC || chan->ep_is_in) {
1287                         qtd->complete_split = 1;
1288                         dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1289                 } else {
1290                         /* ISOC OUT */
1291                         switch (chan->xact_pos) {
1292                         case DWC2_HCSPLT_XACTPOS_ALL:
1293                                 break;
1294                         case DWC2_HCSPLT_XACTPOS_END:
1295                                 qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL;
1296                                 qtd->isoc_split_offset = 0;
1297                                 break;
1298                         case DWC2_HCSPLT_XACTPOS_BEGIN:
1299                         case DWC2_HCSPLT_XACTPOS_MID:
1300                                 /*
1301                                  * For BEGIN or MID, calculate the length for
1302                                  * the next microframe to determine the correct
1303                                  * SSPLIT token, either MID or END
1304                                  */
1305                                 frame_desc = &qtd->urb->iso_descs[
1306                                                 qtd->isoc_frame_index];
1307                                 qtd->isoc_split_offset += 188;
1308
1309                                 if (frame_desc->length - qtd->isoc_split_offset
1310                                                         <= 188)
1311                                         qtd->isoc_split_pos =
1312                                                         DWC2_HCSPLT_XACTPOS_END;
1313                                 else
1314                                         qtd->isoc_split_pos =
1315                                                         DWC2_HCSPLT_XACTPOS_MID;
1316                                 break;
1317                         }
1318                 }
1319         } else {
1320                 qtd->error_count = 0;
1321
1322                 if (chan->qh->ping_state) {
1323                         chan->qh->ping_state = 0;
1324                         /*
1325                          * Halt the channel so the transfer can be re-started
1326                          * from the appropriate point. This only happens in
1327                          * Slave mode. In DMA mode, the ping_state is cleared
1328                          * when the transfer is started because the core
1329                          * automatically executes the PING, then the transfer.
1330                          */
1331                         dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1332                 }
1333         }
1334
1335         /*
1336          * If the ACK occurred when _not_ in the PING state, let the channel
1337          * continue transferring data after clearing the error count
1338          */
1339         disable_hc_int(hsotg, chnum, HCINTMSK_ACK);
1340 }
1341
1342 /*
1343  * Handles a host channel NYET interrupt. This interrupt should only occur on
1344  * Bulk and Control OUT endpoints and for complete split transactions. If a
1345  * NYET occurs at the same time as a Transfer Complete interrupt, it is
1346  * handled in the xfercomp interrupt handler, not here. This handler may be
1347  * called in either DMA mode or Slave mode.
1348  */
1349 static void dwc2_hc_nyet_intr(struct dwc2_hsotg *hsotg,
1350                               struct dwc2_host_chan *chan, int chnum,
1351                               struct dwc2_qtd *qtd)
1352 {
1353         if (dbg_hc(chan))
1354                 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NYET Received--\n",
1355                          chnum);
1356
1357         /*
1358          * NYET on CSPLIT
1359          * re-do the CSPLIT immediately on non-periodic
1360          */
1361         if (chan->do_split && chan->complete_split) {
1362                 if (chan->ep_is_in && chan->ep_type == USB_ENDPOINT_XFER_ISOC &&
1363                     hsotg->core_params->dma_enable > 0) {
1364                         qtd->complete_split = 0;
1365                         qtd->isoc_split_offset = 0;
1366                         qtd->isoc_frame_index++;
1367                         if (qtd->urb &&
1368                             qtd->isoc_frame_index == qtd->urb->packet_count) {
1369                                 dwc2_host_complete(hsotg, qtd, 0);
1370                                 dwc2_release_channel(hsotg, chan, qtd,
1371                                                      DWC2_HC_XFER_URB_COMPLETE);
1372                         } else {
1373                                 dwc2_release_channel(hsotg, chan, qtd,
1374                                                 DWC2_HC_XFER_NO_HALT_STATUS);
1375                         }
1376                         goto handle_nyet_done;
1377                 }
1378
1379                 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1380                     chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1381                         int frnum = dwc2_hcd_get_frame_number(hsotg);
1382
1383                         if (dwc2_full_frame_num(frnum) !=
1384                             dwc2_full_frame_num(chan->qh->sched_frame)) {
1385                                 /*
1386                                  * No longer in the same full speed frame.
1387                                  * Treat this as a transaction error.
1388                                  */
1389 #if 0
1390                                 /*
1391                                  * Todo: Fix system performance so this can
1392                                  * be treated as an error. Right now complete
1393                                  * splits cannot be scheduled precisely enough
1394                                  * due to other system activity, so this error
1395                                  * occurs regularly in Slave mode.
1396                                  */
1397                                 qtd->error_count++;
1398 #endif
1399                                 qtd->complete_split = 0;
1400                                 dwc2_halt_channel(hsotg, chan, qtd,
1401                                                   DWC2_HC_XFER_XACT_ERR);
1402                                 /* Todo: add support for isoc release */
1403                                 goto handle_nyet_done;
1404                         }
1405                 }
1406
1407                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1408                 goto handle_nyet_done;
1409         }
1410
1411         chan->qh->ping_state = 1;
1412         qtd->error_count = 0;
1413
1414         dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, qtd,
1415                                   DWC2_HC_XFER_NYET);
1416         dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1417
1418         /*
1419          * Halt the channel and re-start the transfer so the PING protocol
1420          * will start
1421          */
1422         dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1423
1424 handle_nyet_done:
1425         disable_hc_int(hsotg, chnum, HCINTMSK_NYET);
1426 }
1427
1428 /*
1429  * Handles a host channel babble interrupt. This handler may be called in
1430  * either DMA mode or Slave mode.
1431  */
1432 static void dwc2_hc_babble_intr(struct dwc2_hsotg *hsotg,
1433                                 struct dwc2_host_chan *chan, int chnum,
1434                                 struct dwc2_qtd *qtd)
1435 {
1436         dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Babble Error--\n",
1437                 chnum);
1438
1439         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1440
1441         if (hsotg->core_params->dma_desc_enable > 0) {
1442                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1443                                             DWC2_HC_XFER_BABBLE_ERR);
1444                 goto disable_int;
1445         }
1446
1447         if (chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
1448                 dwc2_host_complete(hsotg, qtd, -EOVERFLOW);
1449                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_BABBLE_ERR);
1450         } else {
1451                 enum dwc2_halt_status halt_status;
1452
1453                 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1454                                                 qtd, DWC2_HC_XFER_BABBLE_ERR);
1455                 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1456         }
1457
1458 disable_int:
1459         disable_hc_int(hsotg, chnum, HCINTMSK_BBLERR);
1460 }
1461
1462 /*
1463  * Handles a host channel AHB error interrupt. This handler is only called in
1464  * DMA mode.
1465  */
1466 static void dwc2_hc_ahberr_intr(struct dwc2_hsotg *hsotg,
1467                                 struct dwc2_host_chan *chan, int chnum,
1468                                 struct dwc2_qtd *qtd)
1469 {
1470         struct dwc2_hcd_urb *urb = qtd->urb;
1471         char *pipetype, *speed;
1472         u32 hcchar;
1473         u32 hcsplt;
1474         u32 hctsiz;
1475         u32 hc_dma;
1476
1477         dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: AHB Error--\n",
1478                 chnum);
1479
1480         if (!urb)
1481                 goto handle_ahberr_halt;
1482
1483         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1484
1485         hcchar = readl(hsotg->regs + HCCHAR(chnum));
1486         hcsplt = readl(hsotg->regs + HCSPLT(chnum));
1487         hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
1488         hc_dma = readl(hsotg->regs + HCDMA(chnum));
1489
1490         dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum);
1491         dev_err(hsotg->dev, "  hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt);
1492         dev_err(hsotg->dev, "  hctsiz 0x%08x, hc_dma 0x%08x\n", hctsiz, hc_dma);
1493         dev_err(hsotg->dev, "  Device address: %d\n",
1494                 dwc2_hcd_get_dev_addr(&urb->pipe_info));
1495         dev_err(hsotg->dev, "  Endpoint: %d, %s\n",
1496                 dwc2_hcd_get_ep_num(&urb->pipe_info),
1497                 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
1498
1499         switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
1500         case USB_ENDPOINT_XFER_CONTROL:
1501                 pipetype = "CONTROL";
1502                 break;
1503         case USB_ENDPOINT_XFER_BULK:
1504                 pipetype = "BULK";
1505                 break;
1506         case USB_ENDPOINT_XFER_INT:
1507                 pipetype = "INTERRUPT";
1508                 break;
1509         case USB_ENDPOINT_XFER_ISOC:
1510                 pipetype = "ISOCHRONOUS";
1511                 break;
1512         default:
1513                 pipetype = "UNKNOWN";
1514                 break;
1515         }
1516
1517         dev_err(hsotg->dev, "  Endpoint type: %s\n", pipetype);
1518
1519         switch (chan->speed) {
1520         case USB_SPEED_HIGH:
1521                 speed = "HIGH";
1522                 break;
1523         case USB_SPEED_FULL:
1524                 speed = "FULL";
1525                 break;
1526         case USB_SPEED_LOW:
1527                 speed = "LOW";
1528                 break;
1529         default:
1530                 speed = "UNKNOWN";
1531                 break;
1532         }
1533
1534         dev_err(hsotg->dev, "  Speed: %s\n", speed);
1535
1536         dev_err(hsotg->dev, "  Max packet size: %d\n",
1537                 dwc2_hcd_get_mps(&urb->pipe_info));
1538         dev_err(hsotg->dev, "  Data buffer length: %d\n", urb->length);
1539         dev_err(hsotg->dev, "  Transfer buffer: %p, Transfer DMA: %08lx\n",
1540                 urb->buf, (unsigned long)urb->dma);
1541         dev_err(hsotg->dev, "  Setup buffer: %p, Setup DMA: %08lx\n",
1542                 urb->setup_packet, (unsigned long)urb->setup_dma);
1543         dev_err(hsotg->dev, "  Interval: %d\n", urb->interval);
1544
1545         /* Core halts the channel for Descriptor DMA mode */
1546         if (hsotg->core_params->dma_desc_enable > 0) {
1547                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1548                                             DWC2_HC_XFER_AHB_ERR);
1549                 goto handle_ahberr_done;
1550         }
1551
1552         dwc2_host_complete(hsotg, qtd, -EIO);
1553
1554 handle_ahberr_halt:
1555         /*
1556          * Force a channel halt. Don't call dwc2_halt_channel because that won't
1557          * write to the HCCHARn register in DMA mode to force the halt.
1558          */
1559         dwc2_hc_halt(hsotg, chan, DWC2_HC_XFER_AHB_ERR);
1560
1561 handle_ahberr_done:
1562         disable_hc_int(hsotg, chnum, HCINTMSK_AHBERR);
1563 }
1564
1565 /*
1566  * Handles a host channel transaction error interrupt. This handler may be
1567  * called in either DMA mode or Slave mode.
1568  */
1569 static void dwc2_hc_xacterr_intr(struct dwc2_hsotg *hsotg,
1570                                  struct dwc2_host_chan *chan, int chnum,
1571                                  struct dwc2_qtd *qtd)
1572 {
1573         dev_dbg(hsotg->dev,
1574                 "--Host Channel %d Interrupt: Transaction Error--\n", chnum);
1575
1576         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1577
1578         if (hsotg->core_params->dma_desc_enable > 0) {
1579                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1580                                             DWC2_HC_XFER_XACT_ERR);
1581                 goto handle_xacterr_done;
1582         }
1583
1584         switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1585         case USB_ENDPOINT_XFER_CONTROL:
1586         case USB_ENDPOINT_XFER_BULK:
1587                 qtd->error_count++;
1588                 if (!chan->qh->ping_state) {
1589
1590                         dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1591                                                   qtd, DWC2_HC_XFER_XACT_ERR);
1592                         dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1593                         if (!chan->ep_is_in && chan->speed == USB_SPEED_HIGH)
1594                                 chan->qh->ping_state = 1;
1595                 }
1596
1597                 /*
1598                  * Halt the channel so the transfer can be re-started from
1599                  * the appropriate point or the PING protocol will start
1600                  */
1601                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1602                 break;
1603         case USB_ENDPOINT_XFER_INT:
1604                 qtd->error_count++;
1605                 if (chan->do_split && chan->complete_split)
1606                         qtd->complete_split = 0;
1607                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1608                 break;
1609         case USB_ENDPOINT_XFER_ISOC:
1610                 {
1611                         enum dwc2_halt_status halt_status;
1612
1613                         halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1614                                         chnum, qtd, DWC2_HC_XFER_XACT_ERR);
1615                         dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1616                 }
1617                 break;
1618         }
1619
1620 handle_xacterr_done:
1621         disable_hc_int(hsotg, chnum, HCINTMSK_XACTERR);
1622 }
1623
1624 /*
1625  * Handles a host channel frame overrun interrupt. This handler may be called
1626  * in either DMA mode or Slave mode.
1627  */
1628 static void dwc2_hc_frmovrun_intr(struct dwc2_hsotg *hsotg,
1629                                   struct dwc2_host_chan *chan, int chnum,
1630                                   struct dwc2_qtd *qtd)
1631 {
1632         enum dwc2_halt_status halt_status;
1633
1634         if (dbg_hc(chan))
1635                 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Frame Overrun--\n",
1636                         chnum);
1637
1638         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1639
1640         switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1641         case USB_ENDPOINT_XFER_CONTROL:
1642         case USB_ENDPOINT_XFER_BULK:
1643                 break;
1644         case USB_ENDPOINT_XFER_INT:
1645                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1646                 break;
1647         case USB_ENDPOINT_XFER_ISOC:
1648                 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1649                                         qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1650                 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1651                 break;
1652         }
1653
1654         disable_hc_int(hsotg, chnum, HCINTMSK_FRMOVRUN);
1655 }
1656
1657 /*
1658  * Handles a host channel data toggle error interrupt. This handler may be
1659  * called in either DMA mode or Slave mode.
1660  */
1661 static void dwc2_hc_datatglerr_intr(struct dwc2_hsotg *hsotg,
1662                                     struct dwc2_host_chan *chan, int chnum,
1663                                     struct dwc2_qtd *qtd)
1664 {
1665         dev_dbg(hsotg->dev,
1666                 "--Host Channel %d Interrupt: Data Toggle Error--\n", chnum);
1667
1668         if (chan->ep_is_in)
1669                 qtd->error_count = 0;
1670         else
1671                 dev_err(hsotg->dev,
1672                         "Data Toggle Error on OUT transfer, channel %d\n",
1673                         chnum);
1674
1675         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1676         disable_hc_int(hsotg, chnum, HCINTMSK_DATATGLERR);
1677 }
1678
1679 /*
1680  * For debug only. It checks that a valid halt status is set and that
1681  * HCCHARn.chdis is clear. If there's a problem, corrective action is
1682  * taken and a warning is issued.
1683  *
1684  * Return: true if halt status is ok, false otherwise
1685  */
1686 static bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg,
1687                                 struct dwc2_host_chan *chan, int chnum,
1688                                 struct dwc2_qtd *qtd)
1689 {
1690 #ifdef DEBUG
1691         u32 hcchar;
1692         u32 hctsiz;
1693         u32 hcintmsk;
1694         u32 hcsplt;
1695
1696         if (chan->halt_status == DWC2_HC_XFER_NO_HALT_STATUS) {
1697                 /*
1698                  * This code is here only as a check. This condition should
1699                  * never happen. Ignore the halt if it does occur.
1700                  */
1701                 hcchar = readl(hsotg->regs + HCCHAR(chnum));
1702                 hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
1703                 hcintmsk = readl(hsotg->regs + HCINTMSK(chnum));
1704                 hcsplt = readl(hsotg->regs + HCSPLT(chnum));
1705                 dev_dbg(hsotg->dev,
1706                         "%s: chan->halt_status DWC2_HC_XFER_NO_HALT_STATUS,\n",
1707                          __func__);
1708                 dev_dbg(hsotg->dev,
1709                         "channel %d, hcchar 0x%08x, hctsiz 0x%08x,\n",
1710                         chnum, hcchar, hctsiz);
1711                 dev_dbg(hsotg->dev,
1712                         "hcint 0x%08x, hcintmsk 0x%08x, hcsplt 0x%08x,\n",
1713                         chan->hcint, hcintmsk, hcsplt);
1714                 if (qtd)
1715                         dev_dbg(hsotg->dev, "qtd->complete_split %d\n",
1716                                 qtd->complete_split);
1717                 dev_warn(hsotg->dev,
1718                          "%s: no halt status, channel %d, ignoring interrupt\n",
1719                          __func__, chnum);
1720                 return false;
1721         }
1722
1723         /*
1724          * This code is here only as a check. hcchar.chdis should never be set
1725          * when the halt interrupt occurs. Halt the channel again if it does
1726          * occur.
1727          */
1728         hcchar = readl(hsotg->regs + HCCHAR(chnum));
1729         if (hcchar & HCCHAR_CHDIS) {
1730                 dev_warn(hsotg->dev,
1731                          "%s: hcchar.chdis set unexpectedly, hcchar 0x%08x, trying to halt again\n",
1732                          __func__, hcchar);
1733                 chan->halt_pending = 0;
1734                 dwc2_halt_channel(hsotg, chan, qtd, chan->halt_status);
1735                 return false;
1736         }
1737 #endif
1738
1739         return true;
1740 }
1741
1742 /*
1743  * Handles a host Channel Halted interrupt in DMA mode. This handler
1744  * determines the reason the channel halted and proceeds accordingly.
1745  */
1746 static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg,
1747                                     struct dwc2_host_chan *chan, int chnum,
1748                                     struct dwc2_qtd *qtd)
1749 {
1750         u32 hcintmsk;
1751         int out_nak_enh = 0;
1752
1753         if (dbg_hc(chan))
1754                 dev_vdbg(hsotg->dev,
1755                          "--Host Channel %d Interrupt: DMA Channel Halted--\n",
1756                          chnum);
1757
1758         /*
1759          * For core with OUT NAK enhancement, the flow for high-speed
1760          * CONTROL/BULK OUT is handled a little differently
1761          */
1762         if (hsotg->snpsid >= DWC2_CORE_REV_2_71a) {
1763                 if (chan->speed == USB_SPEED_HIGH && !chan->ep_is_in &&
1764                     (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1765                      chan->ep_type == USB_ENDPOINT_XFER_BULK)) {
1766                         out_nak_enh = 1;
1767                 }
1768         }
1769
1770         if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
1771             (chan->halt_status == DWC2_HC_XFER_AHB_ERR &&
1772              hsotg->core_params->dma_desc_enable <= 0)) {
1773                 if (hsotg->core_params->dma_desc_enable > 0)
1774                         dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1775                                                     chan->halt_status);
1776                 else
1777                         /*
1778                          * Just release the channel. A dequeue can happen on a
1779                          * transfer timeout. In the case of an AHB Error, the
1780                          * channel was forced to halt because there's no way to
1781                          * gracefully recover.
1782                          */
1783                         dwc2_release_channel(hsotg, chan, qtd,
1784                                              chan->halt_status);
1785                 return;
1786         }
1787
1788         hcintmsk = readl(hsotg->regs + HCINTMSK(chnum));
1789
1790         if (chan->hcint & HCINTMSK_XFERCOMPL) {
1791                 /*
1792                  * Todo: This is here because of a possible hardware bug. Spec
1793                  * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
1794                  * interrupt w/ACK bit set should occur, but I only see the
1795                  * XFERCOMP bit, even with it masked out. This is a workaround
1796                  * for that behavior. Should fix this when hardware is fixed.
1797                  */
1798                 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && !chan->ep_is_in)
1799                         dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1800                 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
1801         } else if (chan->hcint & HCINTMSK_STALL) {
1802                 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
1803         } else if ((chan->hcint & HCINTMSK_XACTERR) &&
1804                    hsotg->core_params->dma_desc_enable <= 0) {
1805                 if (out_nak_enh) {
1806                         if (chan->hcint &
1807                             (HCINTMSK_NYET | HCINTMSK_NAK | HCINTMSK_ACK)) {
1808                                 dev_vdbg(hsotg->dev,
1809                                          "XactErr with NYET/NAK/ACK\n");
1810                                 qtd->error_count = 0;
1811                         } else {
1812                                 dev_vdbg(hsotg->dev,
1813                                          "XactErr without NYET/NAK/ACK\n");
1814                         }
1815                 }
1816
1817                 /*
1818                  * Must handle xacterr before nak or ack. Could get a xacterr
1819                  * at the same time as either of these on a BULK/CONTROL OUT
1820                  * that started with a PING. The xacterr takes precedence.
1821                  */
1822                 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1823         } else if ((chan->hcint & HCINTMSK_XCS_XACT) &&
1824                    hsotg->core_params->dma_desc_enable > 0) {
1825                 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1826         } else if ((chan->hcint & HCINTMSK_AHBERR) &&
1827                    hsotg->core_params->dma_desc_enable > 0) {
1828                 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
1829         } else if (chan->hcint & HCINTMSK_BBLERR) {
1830                 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
1831         } else if (chan->hcint & HCINTMSK_FRMOVRUN) {
1832                 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
1833         } else if (!out_nak_enh) {
1834                 if (chan->hcint & HCINTMSK_NYET) {
1835                         /*
1836                          * Must handle nyet before nak or ack. Could get a nyet
1837                          * at the same time as either of those on a BULK/CONTROL
1838                          * OUT that started with a PING. The nyet takes
1839                          * precedence.
1840                          */
1841                         dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
1842                 } else if ((chan->hcint & HCINTMSK_NAK) &&
1843                            !(hcintmsk & HCINTMSK_NAK)) {
1844                         /*
1845                          * If nak is not masked, it's because a non-split IN
1846                          * transfer is in an error state. In that case, the nak
1847                          * is handled by the nak interrupt handler, not here.
1848                          * Handle nak here for BULK/CONTROL OUT transfers, which
1849                          * halt on a NAK to allow rewinding the buffer pointer.
1850                          */
1851                         dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
1852                 } else if ((chan->hcint & HCINTMSK_ACK) &&
1853                            !(hcintmsk & HCINTMSK_ACK)) {
1854                         /*
1855                          * If ack is not masked, it's because a non-split IN
1856                          * transfer is in an error state. In that case, the ack
1857                          * is handled by the ack interrupt handler, not here.
1858                          * Handle ack here for split transfers. Start splits
1859                          * halt on ACK.
1860                          */
1861                         dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1862                 } else {
1863                         if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1864                             chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1865                                 /*
1866                                  * A periodic transfer halted with no other
1867                                  * channel interrupts set. Assume it was halted
1868                                  * by the core because it could not be completed
1869                                  * in its scheduled (micro)frame.
1870                                  */
1871                                 dev_dbg(hsotg->dev,
1872                                         "%s: Halt channel %d (assume incomplete periodic transfer)\n",
1873                                         __func__, chnum);
1874                                 dwc2_halt_channel(hsotg, chan, qtd,
1875                                         DWC2_HC_XFER_PERIODIC_INCOMPLETE);
1876                         } else {
1877                                 dev_err(hsotg->dev,
1878                                         "%s: Channel %d - ChHltd set, but reason is unknown\n",
1879                                         __func__, chnum);
1880                                 dev_err(hsotg->dev,
1881                                         "hcint 0x%08x, intsts 0x%08x\n",
1882                                         chan->hcint,
1883                                         readl(hsotg->regs + GINTSTS));
1884                         }
1885                 }
1886         } else {
1887                 dev_info(hsotg->dev,
1888                          "NYET/NAK/ACK/other in non-error case, 0x%08x\n",
1889                          chan->hcint);
1890         }
1891 }
1892
1893 /*
1894  * Handles a host channel Channel Halted interrupt
1895  *
1896  * In slave mode, this handler is called only when the driver specifically
1897  * requests a halt. This occurs during handling other host channel interrupts
1898  * (e.g. nak, xacterr, stall, nyet, etc.).
1899  *
1900  * In DMA mode, this is the interrupt that occurs when the core has finished
1901  * processing a transfer on a channel. Other host channel interrupts (except
1902  * ahberr) are disabled in DMA mode.
1903  */
1904 static void dwc2_hc_chhltd_intr(struct dwc2_hsotg *hsotg,
1905                                 struct dwc2_host_chan *chan, int chnum,
1906                                 struct dwc2_qtd *qtd)
1907 {
1908         if (dbg_hc(chan))
1909                 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: Channel Halted--\n",
1910                          chnum);
1911
1912         if (hsotg->core_params->dma_enable > 0) {
1913                 dwc2_hc_chhltd_intr_dma(hsotg, chan, chnum, qtd);
1914         } else {
1915                 if (!dwc2_halt_status_ok(hsotg, chan, chnum, qtd))
1916                         return;
1917                 dwc2_release_channel(hsotg, chan, qtd, chan->halt_status);
1918         }
1919 }
1920
1921 /* Handles interrupt for a specific Host Channel */
1922 static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum)
1923 {
1924         struct dwc2_qtd *qtd;
1925         struct dwc2_host_chan *chan;
1926         u32 hcint, hcintmsk;
1927
1928         chan = hsotg->hc_ptr_array[chnum];
1929
1930         if (dbg_hc(chan))
1931                 dev_vdbg(hsotg->dev, "--Host Channel Interrupt--, Channel %d\n",
1932                          chnum);
1933
1934         hcint = readl(hsotg->regs + HCINT(chnum));
1935         hcintmsk = readl(hsotg->regs + HCINTMSK(chnum));
1936         if (dbg_hc(chan))
1937                 dev_vdbg(hsotg->dev,
1938                          "  hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
1939                          hcint, hcintmsk, hcint & hcintmsk);
1940
1941         if (!chan) {
1942                 dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n");
1943                 writel(hcint, hsotg->regs + HCINT(chnum));
1944                 return;
1945         }
1946
1947         writel(hcint, hsotg->regs + HCINT(chnum));
1948         chan->hcint = hcint;
1949         hcint &= hcintmsk;
1950
1951         /*
1952          * If the channel was halted due to a dequeue, the qtd list might
1953          * be empty or at least the first entry will not be the active qtd.
1954          * In this case, take a shortcut and just release the channel.
1955          */
1956         if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE) {
1957                 /*
1958                  * If the channel was halted, this should be the only
1959                  * interrupt unmasked
1960                  */
1961                 WARN_ON(hcint != HCINTMSK_CHHLTD);
1962                 if (hsotg->core_params->dma_desc_enable > 0)
1963                         dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1964                                                     chan->halt_status);
1965                 else
1966                         dwc2_release_channel(hsotg, chan, NULL,
1967                                              chan->halt_status);
1968                 return;
1969         }
1970
1971         if (list_empty(&chan->qh->qtd_list)) {
1972                 /*
1973                  * TODO: Will this ever happen with the
1974                  * DWC2_HC_XFER_URB_DEQUEUE handling above?
1975                  */
1976                 dev_dbg(hsotg->dev, "## no QTD queued for channel %d ##\n",
1977                         chnum);
1978                 dev_dbg(hsotg->dev,
1979                         "  hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
1980                         chan->hcint, hcintmsk, hcint);
1981                 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
1982                 disable_hc_int(hsotg, chnum, HCINTMSK_CHHLTD);
1983                 chan->hcint = 0;
1984                 return;
1985         }
1986
1987         qtd = list_first_entry(&chan->qh->qtd_list, struct dwc2_qtd,
1988                                qtd_list_entry);
1989
1990         if (hsotg->core_params->dma_enable <= 0) {
1991                 if ((hcint & HCINTMSK_CHHLTD) && hcint != HCINTMSK_CHHLTD)
1992                         hcint &= ~HCINTMSK_CHHLTD;
1993         }
1994
1995         if (hcint & HCINTMSK_XFERCOMPL) {
1996                 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
1997                 /*
1998                  * If NYET occurred at same time as Xfer Complete, the NYET is
1999                  * handled by the Xfer Complete interrupt handler. Don't want
2000                  * to call the NYET interrupt handler in this case.
2001                  */
2002                 hcint &= ~HCINTMSK_NYET;
2003         }
2004         if (hcint & HCINTMSK_CHHLTD)
2005                 dwc2_hc_chhltd_intr(hsotg, chan, chnum, qtd);
2006         if (hcint & HCINTMSK_AHBERR)
2007                 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
2008         if (hcint & HCINTMSK_STALL)
2009                 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
2010         if (hcint & HCINTMSK_NAK)
2011                 dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
2012         if (hcint & HCINTMSK_ACK)
2013                 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
2014         if (hcint & HCINTMSK_NYET)
2015                 dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
2016         if (hcint & HCINTMSK_XACTERR)
2017                 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
2018         if (hcint & HCINTMSK_BBLERR)
2019                 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
2020         if (hcint & HCINTMSK_FRMOVRUN)
2021                 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
2022         if (hcint & HCINTMSK_DATATGLERR)
2023                 dwc2_hc_datatglerr_intr(hsotg, chan, chnum, qtd);
2024
2025         chan->hcint = 0;
2026 }
2027
2028 /*
2029  * This interrupt indicates that one or more host channels has a pending
2030  * interrupt. There are multiple conditions that can cause each host channel
2031  * interrupt. This function determines which conditions have occurred for each
2032  * host channel interrupt and handles them appropriately.
2033  */
2034 static void dwc2_hc_intr(struct dwc2_hsotg *hsotg)
2035 {
2036         u32 haint;
2037         int i;
2038
2039         haint = readl(hsotg->regs + HAINT);
2040         if (dbg_perio()) {
2041                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
2042
2043                 dev_vdbg(hsotg->dev, "HAINT=%08x\n", haint);
2044         }
2045
2046         for (i = 0; i < hsotg->core_params->host_channels; i++) {
2047                 if (haint & (1 << i))
2048                         dwc2_hc_n_intr(hsotg, i);
2049         }
2050 }
2051
2052 /* This function handles interrupts for the HCD */
2053 irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg)
2054 {
2055         u32 gintsts, dbg_gintsts;
2056         irqreturn_t retval = IRQ_NONE;
2057
2058         if (dwc2_check_core_status(hsotg) < 0) {
2059                 dev_warn(hsotg->dev, "Controller is disconnected\n");
2060                 return retval;
2061         }
2062
2063         spin_lock(&hsotg->lock);
2064
2065         /* Check if HOST Mode */
2066         if (dwc2_is_host_mode(hsotg)) {
2067                 gintsts = dwc2_read_core_intr(hsotg);
2068                 if (!gintsts) {
2069                         spin_unlock(&hsotg->lock);
2070                         return retval;
2071                 }
2072
2073                 retval = IRQ_HANDLED;
2074
2075                 dbg_gintsts = gintsts;
2076 #ifndef DEBUG_SOF
2077                 dbg_gintsts &= ~GINTSTS_SOF;
2078 #endif
2079                 if (!dbg_perio())
2080                         dbg_gintsts &= ~(GINTSTS_HCHINT | GINTSTS_RXFLVL |
2081                                          GINTSTS_PTXFEMP);
2082
2083                 /* Only print if there are any non-suppressed interrupts left */
2084                 if (dbg_gintsts)
2085                         dev_vdbg(hsotg->dev,
2086                                  "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n",
2087                                  gintsts);
2088
2089                 if (gintsts & GINTSTS_SOF)
2090                         dwc2_sof_intr(hsotg);
2091                 if (gintsts & GINTSTS_RXFLVL)
2092                         dwc2_rx_fifo_level_intr(hsotg);
2093                 if (gintsts & GINTSTS_NPTXFEMP)
2094                         dwc2_np_tx_fifo_empty_intr(hsotg);
2095                 if (gintsts & GINTSTS_PRTINT)
2096                         dwc2_port_intr(hsotg);
2097                 if (gintsts & GINTSTS_HCHINT)
2098                         dwc2_hc_intr(hsotg);
2099                 if (gintsts & GINTSTS_PTXFEMP)
2100                         dwc2_perio_tx_fifo_empty_intr(hsotg);
2101
2102                 if (dbg_gintsts) {
2103                         dev_vdbg(hsotg->dev,
2104                                  "DWC OTG HCD Finished Servicing Interrupts\n");
2105                         dev_vdbg(hsotg->dev,
2106                                  "DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n",
2107                                  readl(hsotg->regs + GINTSTS),
2108                                  readl(hsotg->regs + GINTMSK));
2109                 }
2110         }
2111
2112         spin_unlock(&hsotg->lock);
2113
2114         return retval;
2115 }