2 * hcd_intr.c - DesignWare HS OTG Controller host-mode interrupt handling
4 * Copyright (C) 2004-2013 Synopsys, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
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19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 * This file contains the interrupt handlers for Host mode
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/spinlock.h>
43 #include <linux/interrupt.h>
44 #include <linux/dma-mapping.h>
46 #include <linux/slab.h>
47 #include <linux/usb.h>
49 #include <linux/usb/hcd.h>
50 #include <linux/usb/ch11.h>
55 /* This function is for debug only */
56 static void dwc2_track_missed_sofs(struct dwc2_hsotg *hsotg)
58 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
59 u16 curr_frame_number = hsotg->frame_number;
61 if (hsotg->frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
62 if (((hsotg->last_frame_num + 1) & HFNUM_MAX_FRNUM) !=
64 hsotg->frame_num_array[hsotg->frame_num_idx] =
66 hsotg->last_frame_num_array[hsotg->frame_num_idx] =
67 hsotg->last_frame_num;
68 hsotg->frame_num_idx++;
70 } else if (!hsotg->dumped_frame_num_array) {
73 dev_info(hsotg->dev, "Frame Last Frame\n");
74 dev_info(hsotg->dev, "----- ----------\n");
75 for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
76 dev_info(hsotg->dev, "0x%04x 0x%04x\n",
77 hsotg->frame_num_array[i],
78 hsotg->last_frame_num_array[i]);
80 hsotg->dumped_frame_num_array = 1;
82 hsotg->last_frame_num = curr_frame_number;
86 static void dwc2_hc_handle_tt_clear(struct dwc2_hsotg *hsotg,
87 struct dwc2_host_chan *chan,
92 if (!chan->qh || !qtd->urb)
95 usb_urb = qtd->urb->priv;
96 if (!usb_urb || !usb_urb->dev)
99 if (chan->qh->dev_speed != USB_SPEED_HIGH &&
100 qtd->urb->status != -EPIPE && qtd->urb->status != -EREMOTEIO) {
101 chan->qh->tt_buffer_dirty = 1;
102 if (usb_hub_clear_tt_buffer(usb_urb))
103 /* Clear failed; let's hope things work anyway */
104 chan->qh->tt_buffer_dirty = 0;
109 * Handles the start-of-frame interrupt in host mode. Non-periodic
110 * transactions may be queued to the DWC_otg controller for the current
111 * (micro)frame. Periodic transactions may be queued to the controller
112 * for the next (micro)frame.
114 static void dwc2_sof_intr(struct dwc2_hsotg *hsotg)
116 struct list_head *qh_entry;
118 enum dwc2_transaction_type tr_type;
121 dev_vdbg(hsotg->dev, "--Start of Frame Interrupt--\n");
124 hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg);
126 dwc2_track_missed_sofs(hsotg);
128 /* Determine whether any periodic QHs should be executed */
129 qh_entry = hsotg->periodic_sched_inactive.next;
130 while (qh_entry != &hsotg->periodic_sched_inactive) {
131 qh = list_entry(qh_entry, struct dwc2_qh, qh_list_entry);
132 qh_entry = qh_entry->next;
133 if (dwc2_frame_num_le(qh->sched_frame, hsotg->frame_number))
135 * Move QH to the ready list to be executed next
138 list_move(&qh->qh_list_entry,
139 &hsotg->periodic_sched_ready);
141 tr_type = dwc2_hcd_select_transactions(hsotg);
142 if (tr_type != DWC2_TRANSACTION_NONE)
143 dwc2_hcd_queue_transactions(hsotg, tr_type);
145 /* Clear interrupt */
146 writel(GINTSTS_SOF, hsotg->regs + GINTSTS);
150 * Handles the Rx FIFO Level Interrupt, which indicates that there is
151 * at least one packet in the Rx FIFO. The packets are moved from the FIFO to
152 * memory if the DWC_otg controller is operating in Slave mode.
154 static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg)
156 u32 grxsts, chnum, bcnt, dpid, pktsts;
157 struct dwc2_host_chan *chan;
160 dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n");
162 grxsts = readl(hsotg->regs + GRXSTSP);
163 chnum = grxsts >> GRXSTS_HCHNUM_SHIFT &
164 GRXSTS_HCHNUM_MASK >> GRXSTS_HCHNUM_SHIFT;
165 chan = hsotg->hc_ptr_array[chnum];
167 dev_err(hsotg->dev, "Unable to get corresponding channel\n");
171 bcnt = grxsts >> GRXSTS_BYTECNT_SHIFT &
172 GRXSTS_BYTECNT_MASK >> GRXSTS_BYTECNT_SHIFT;
173 dpid = grxsts >> GRXSTS_DPID_SHIFT &
174 GRXSTS_DPID_MASK >> GRXSTS_DPID_SHIFT;
175 pktsts = grxsts & GRXSTS_PKTSTS_MASK;
179 dev_vdbg(hsotg->dev, " Ch num = %d\n", chnum);
180 dev_vdbg(hsotg->dev, " Count = %d\n", bcnt);
181 dev_vdbg(hsotg->dev, " DPID = %d, chan.dpid = %d\n", dpid,
182 chan->data_pid_start);
183 dev_vdbg(hsotg->dev, " PStatus = %d\n",
184 pktsts >> GRXSTS_PKTSTS_SHIFT &
185 GRXSTS_PKTSTS_MASK >> GRXSTS_PKTSTS_SHIFT);
189 case GRXSTS_PKTSTS_HCHIN:
190 /* Read the data into the host buffer */
192 dwc2_read_packet(hsotg, chan->xfer_buf, bcnt);
194 /* Update the HC fields for the next packet received */
195 chan->xfer_count += bcnt;
196 chan->xfer_buf += bcnt;
199 case GRXSTS_PKTSTS_HCHIN_XFER_COMP:
200 case GRXSTS_PKTSTS_DATATOGGLEERR:
201 case GRXSTS_PKTSTS_HCHHALTED:
202 /* Handled in interrupt, just ignore data */
206 "RxFIFO Level Interrupt: Unknown status %d\n", pktsts);
212 * This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
213 * data packets may be written to the FIFO for OUT transfers. More requests
214 * may be written to the non-periodic request queue for IN transfers. This
215 * interrupt is enabled only in Slave mode.
217 static void dwc2_np_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
219 dev_vdbg(hsotg->dev, "--Non-Periodic TxFIFO Empty Interrupt--\n");
220 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_NON_PERIODIC);
224 * This interrupt occurs when the periodic Tx FIFO is half-empty. More data
225 * packets may be written to the FIFO for OUT transfers. More requests may be
226 * written to the periodic request queue for IN transfers. This interrupt is
227 * enabled only in Slave mode.
229 static void dwc2_perio_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
232 dev_vdbg(hsotg->dev, "--Periodic TxFIFO Empty Interrupt--\n");
233 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_PERIODIC);
236 static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
239 struct dwc2_core_params *params = hsotg->core_params;
247 dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
249 /* Every time when port enables calculate HFIR.FrInterval */
250 hfir = readl(hsotg->regs + HFIR);
251 hfir &= ~HFIR_FRINT_MASK;
252 hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT &
254 writel(hfir, hsotg->regs + HFIR);
256 /* Check if we need to adjust the PHY clock speed for low power */
257 if (!params->host_support_fs_ls_low_power) {
258 /* Port has been enabled, set the reset change flag */
259 hsotg->flags.b.port_reset_change = 1;
263 usbcfg = readl(hsotg->regs + GUSBCFG);
264 prtspd = hprt0 & HPRT0_SPD_MASK;
266 if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) {
268 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL)) {
269 /* Set PHY low power clock select for FS/LS devices */
270 usbcfg |= GUSBCFG_PHY_LP_CLK_SEL;
271 writel(usbcfg, hsotg->regs + GUSBCFG);
275 hcfg = readl(hsotg->regs + HCFG);
276 fslspclksel = hcfg & HCFG_FSLSPCLKSEL_MASK;
278 if (prtspd == HPRT0_SPD_LOW_SPEED &&
279 params->host_ls_low_power_phy_clk ==
280 DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ) {
283 "FS_PHY programming HCFG to 6 MHz\n");
284 if (fslspclksel != HCFG_FSLSPCLKSEL_6_MHZ) {
285 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
286 hcfg |= HCFG_FSLSPCLKSEL_6_MHZ;
287 writel(hcfg, hsotg->regs + HCFG);
293 "FS_PHY programming HCFG to 48 MHz\n");
294 if (fslspclksel != HCFG_FSLSPCLKSEL_48_MHZ) {
295 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
296 hcfg |= HCFG_FSLSPCLKSEL_48_MHZ;
297 writel(hcfg, hsotg->regs + HCFG);
303 if (usbcfg & GUSBCFG_PHY_LP_CLK_SEL) {
304 usbcfg &= ~GUSBCFG_PHY_LP_CLK_SEL;
305 writel(usbcfg, hsotg->regs + GUSBCFG);
311 *hprt0_modify |= HPRT0_RST;
312 queue_delayed_work(hsotg->wq_otg, &hsotg->reset_work,
313 msecs_to_jiffies(60));
315 /* Port has been enabled, set the reset change flag */
316 hsotg->flags.b.port_reset_change = 1;
321 * There are multiple conditions that can cause a port interrupt. This function
322 * determines which interrupt conditions have occurred and handles them
325 static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
330 dev_vdbg(hsotg->dev, "--Port Interrupt--\n");
332 hprt0 = readl(hsotg->regs + HPRT0);
333 hprt0_modify = hprt0;
336 * Clear appropriate bits in HPRT0 to clear the interrupt bit in
339 hprt0_modify &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG |
343 * Port Connect Detected
344 * Set flag and clear if detected
346 if (hprt0 & HPRT0_CONNDET) {
348 "--Port Interrupt HPRT0=0x%08x Port Connect Detected--\n",
350 hsotg->flags.b.port_connect_status_change = 1;
351 hsotg->flags.b.port_connect_status = 1;
352 hprt0_modify |= HPRT0_CONNDET;
355 * The Hub driver asserts a reset when it sees port connect
361 * Port Enable Changed
362 * Clear if detected - Set internal flag if disabled
364 if (hprt0 & HPRT0_ENACHG) {
366 " --Port Interrupt HPRT0=0x%08x Port Enable Changed (now %d)--\n",
367 hprt0, !!(hprt0 & HPRT0_ENA));
368 hprt0_modify |= HPRT0_ENACHG;
369 if (hprt0 & HPRT0_ENA)
370 dwc2_hprt0_enable(hsotg, hprt0, &hprt0_modify);
372 hsotg->flags.b.port_enable_change = 1;
375 /* Overcurrent Change Interrupt */
376 if (hprt0 & HPRT0_OVRCURRCHG) {
378 " --Port Interrupt HPRT0=0x%08x Port Overcurrent Changed--\n",
380 hsotg->flags.b.port_over_current_change = 1;
381 hprt0_modify |= HPRT0_OVRCURRCHG;
384 /* Clear Port Interrupts */
385 writel(hprt0_modify, hsotg->regs + HPRT0);
389 * Gets the actual length of a transfer after the transfer halts. halt_status
390 * holds the reason for the halt.
392 * For IN transfers where halt_status is DWC2_HC_XFER_COMPLETE, *short_read
393 * is set to 1 upon return if less than the requested number of bytes were
394 * transferred. short_read may also be NULL on entry, in which case it remains
397 static u32 dwc2_get_actual_xfer_length(struct dwc2_hsotg *hsotg,
398 struct dwc2_host_chan *chan, int chnum,
399 struct dwc2_qtd *qtd,
400 enum dwc2_halt_status halt_status,
403 u32 hctsiz, count, length;
405 hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
407 if (halt_status == DWC2_HC_XFER_COMPLETE) {
408 if (chan->ep_is_in) {
409 count = hctsiz >> TSIZ_XFERSIZE_SHIFT &
410 TSIZ_XFERSIZE_MASK >> TSIZ_XFERSIZE_SHIFT;
411 length = chan->xfer_len - count;
412 if (short_read != NULL)
413 *short_read = (count != 0);
414 } else if (chan->qh->do_split) {
415 length = qtd->ssplit_out_xfer_count;
417 length = chan->xfer_len;
421 * Must use the hctsiz.pktcnt field to determine how much data
422 * has been transferred. This field reflects the number of
423 * packets that have been transferred via the USB. This is
424 * always an integral number of packets if the transfer was
425 * halted before its normal completion. (Can't use the
426 * hctsiz.xfersize field because that reflects the number of
427 * bytes transferred via the AHB, not the USB).
429 count = hctsiz >> TSIZ_PKTCNT_SHIFT &
430 TSIZ_PKTCNT_MASK >> TSIZ_PKTCNT_SHIFT;
431 length = (chan->start_pkt_count - count) * chan->max_packet;
438 * dwc2_update_urb_state() - Updates the state of the URB after a Transfer
439 * Complete interrupt on the host channel. Updates the actual_length field
440 * of the URB based on the number of bytes transferred via the host channel.
441 * Sets the URB status if the data transfer is finished.
443 * Return: 1 if the data transfer specified by the URB is completely finished,
446 static int dwc2_update_urb_state(struct dwc2_hsotg *hsotg,
447 struct dwc2_host_chan *chan, int chnum,
448 struct dwc2_hcd_urb *urb,
449 struct dwc2_qtd *qtd)
454 int xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
455 DWC2_HC_XFER_COMPLETE,
458 if (urb->actual_length + xfer_length > urb->length) {
459 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__);
460 xfer_length = urb->length - urb->actual_length;
463 /* Non DWORD-aligned buffer case handling */
464 if (chan->align_buf && xfer_length && chan->ep_is_in) {
465 dev_dbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
466 dma_sync_single_for_cpu(hsotg->dev, urb->dma, urb->length,
468 memcpy(urb->buf + urb->actual_length, chan->qh->dw_align_buf,
470 dma_sync_single_for_device(hsotg->dev, urb->dma, urb->length,
474 dev_vdbg(hsotg->dev, "urb->actual_length=%d xfer_length=%d\n",
475 urb->actual_length, xfer_length);
476 urb->actual_length += xfer_length;
478 if (xfer_length && chan->ep_type == USB_ENDPOINT_XFER_BULK &&
479 (urb->flags & URB_SEND_ZERO_PACKET) &&
480 urb->actual_length >= urb->length &&
481 !(urb->length % chan->max_packet)) {
483 } else if (short_read || urb->actual_length >= urb->length) {
488 hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
489 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
490 __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
491 dev_vdbg(hsotg->dev, " chan->xfer_len %d\n", chan->xfer_len);
492 dev_vdbg(hsotg->dev, " hctsiz.xfersize %d\n",
493 hctsiz >> TSIZ_XFERSIZE_SHIFT &
494 TSIZ_XFERSIZE_MASK >> TSIZ_XFERSIZE_SHIFT);
495 dev_vdbg(hsotg->dev, " urb->transfer_buffer_length %d\n", urb->length);
496 dev_vdbg(hsotg->dev, " urb->actual_length %d\n", urb->actual_length);
497 dev_vdbg(hsotg->dev, " short_read %d, xfer_done %d\n", short_read,
504 * Save the starting data toggle for the next transfer. The data toggle is
505 * saved in the QH for non-control transfers and it's saved in the QTD for
508 void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
509 struct dwc2_host_chan *chan, int chnum,
510 struct dwc2_qtd *qtd)
512 u32 hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
513 u32 pid = hctsiz & TSIZ_SC_MC_PID_MASK;
515 if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) {
516 if (pid == TSIZ_SC_MC_PID_DATA0)
517 chan->qh->data_toggle = DWC2_HC_PID_DATA0;
519 chan->qh->data_toggle = DWC2_HC_PID_DATA1;
521 if (pid == TSIZ_SC_MC_PID_DATA0)
522 qtd->data_toggle = DWC2_HC_PID_DATA0;
524 qtd->data_toggle = DWC2_HC_PID_DATA1;
529 * dwc2_update_isoc_urb_state() - Updates the state of an Isochronous URB when
530 * the transfer is stopped for any reason. The fields of the current entry in
531 * the frame descriptor array are set based on the transfer state and the input
532 * halt_status. Completes the Isochronous URB if all the URB frames have been
535 * Return: DWC2_HC_XFER_COMPLETE if there are more frames remaining to be
536 * transferred in the URB. Otherwise return DWC2_HC_XFER_URB_COMPLETE.
538 static enum dwc2_halt_status dwc2_update_isoc_urb_state(
539 struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
540 int chnum, struct dwc2_qtd *qtd,
541 enum dwc2_halt_status halt_status)
543 struct dwc2_hcd_iso_packet_desc *frame_desc;
544 struct dwc2_hcd_urb *urb = qtd->urb;
547 return DWC2_HC_XFER_NO_HALT_STATUS;
549 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
551 switch (halt_status) {
552 case DWC2_HC_XFER_COMPLETE:
553 frame_desc->status = 0;
554 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
555 chan, chnum, qtd, halt_status, NULL);
557 /* Non DWORD-aligned buffer case handling */
558 if (chan->align_buf && frame_desc->actual_length &&
560 dev_dbg(hsotg->dev, "%s(): non-aligned buffer\n",
562 dma_sync_single_for_cpu(hsotg->dev, urb->dma,
563 urb->length, DMA_FROM_DEVICE);
564 memcpy(urb->buf + frame_desc->offset +
565 qtd->isoc_split_offset, chan->qh->dw_align_buf,
566 frame_desc->actual_length);
567 dma_sync_single_for_device(hsotg->dev, urb->dma,
572 case DWC2_HC_XFER_FRAME_OVERRUN:
575 frame_desc->status = -ENOSR;
577 frame_desc->status = -ECOMM;
578 frame_desc->actual_length = 0;
580 case DWC2_HC_XFER_BABBLE_ERR:
582 frame_desc->status = -EOVERFLOW;
583 /* Don't need to update actual_length in this case */
585 case DWC2_HC_XFER_XACT_ERR:
587 frame_desc->status = -EPROTO;
588 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
589 chan, chnum, qtd, halt_status, NULL);
591 /* Non DWORD-aligned buffer case handling */
592 if (chan->align_buf && frame_desc->actual_length &&
594 dev_dbg(hsotg->dev, "%s(): non-aligned buffer\n",
596 dma_sync_single_for_cpu(hsotg->dev, urb->dma,
597 urb->length, DMA_FROM_DEVICE);
598 memcpy(urb->buf + frame_desc->offset +
599 qtd->isoc_split_offset, chan->qh->dw_align_buf,
600 frame_desc->actual_length);
601 dma_sync_single_for_device(hsotg->dev, urb->dma,
606 /* Skip whole frame */
607 if (chan->qh->do_split &&
608 chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
609 hsotg->core_params->dma_enable > 0) {
610 qtd->complete_split = 0;
611 qtd->isoc_split_offset = 0;
616 dev_err(hsotg->dev, "Unhandled halt_status (%d)\n",
621 if (++qtd->isoc_frame_index == urb->packet_count) {
623 * urb->status is not used for isoc transfers. The individual
624 * frame_desc statuses are used instead.
626 dwc2_host_complete(hsotg, urb->priv, urb, 0);
627 halt_status = DWC2_HC_XFER_URB_COMPLETE;
629 halt_status = DWC2_HC_XFER_COMPLETE;
636 * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
637 * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
638 * still linked to the QH, the QH is added to the end of the inactive
639 * non-periodic schedule. For periodic QHs, removes the QH from the periodic
640 * schedule if no more QTDs are linked to the QH.
642 static void dwc2_deactivate_qh(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
645 int continue_split = 0;
646 struct dwc2_qtd *qtd;
649 dev_vdbg(hsotg->dev, " %s(%p,%p,%d)\n", __func__,
650 hsotg, qh, free_qtd);
652 if (list_empty(&qh->qtd_list)) {
653 dev_dbg(hsotg->dev, "## QTD list empty ##\n");
657 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
659 if (qtd->complete_split)
661 else if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_MID ||
662 qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_END)
666 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
672 qh->channel->align_buf = 0;
674 dwc2_hcd_qh_deactivate(hsotg, qh, continue_split);
678 * dwc2_release_channel() - Releases a host channel for use by other transfers
680 * @hsotg: The HCD state structure
681 * @chan: The host channel to release
682 * @qtd: The QTD associated with the host channel. This QTD may be
683 * freed if the transfer is complete or an error has occurred.
684 * @halt_status: Reason the channel is being released. This status
685 * determines the actions taken by this function.
687 * Also attempts to select and queue more transactions since at least one host
688 * channel is available.
690 static void dwc2_release_channel(struct dwc2_hsotg *hsotg,
691 struct dwc2_host_chan *chan,
692 struct dwc2_qtd *qtd,
693 enum dwc2_halt_status halt_status)
695 enum dwc2_transaction_type tr_type;
700 dev_vdbg(hsotg->dev, " %s: channel %d, halt_status %d\n",
701 __func__, chan->hc_num, halt_status);
703 switch (halt_status) {
704 case DWC2_HC_XFER_URB_COMPLETE:
707 case DWC2_HC_XFER_AHB_ERR:
708 case DWC2_HC_XFER_STALL:
709 case DWC2_HC_XFER_BABBLE_ERR:
712 case DWC2_HC_XFER_XACT_ERR:
713 if (qtd && qtd->error_count >= 3) {
715 " Complete URB with transaction error\n");
718 qtd->urb->status = -EPROTO;
719 dwc2_host_complete(hsotg, qtd->urb->priv,
724 case DWC2_HC_XFER_URB_DEQUEUE:
726 * The QTD has already been removed and the QH has been
727 * deactivated. Don't want to do anything except release the
728 * host channel and try to queue more transfers.
731 case DWC2_HC_XFER_PERIODIC_INCOMPLETE:
732 dev_vdbg(hsotg->dev, " Complete URB with I/O error\n");
734 if (qtd && qtd->urb) {
735 qtd->urb->status = -EIO;
736 dwc2_host_complete(hsotg, qtd->urb->priv, qtd->urb,
740 case DWC2_HC_XFER_NO_HALT_STATUS:
745 dwc2_deactivate_qh(hsotg, chan->qh, free_qtd);
749 * Release the host channel for use by other transfers. The cleanup
750 * function clears the channel interrupt enables and conditions, so
751 * there's no need to clear the Channel Halted interrupt separately.
753 if (!list_empty(&chan->hc_list_entry))
754 list_del(&chan->hc_list_entry);
755 dwc2_hc_cleanup(hsotg, chan);
756 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
758 switch (chan->ep_type) {
759 case USB_ENDPOINT_XFER_CONTROL:
760 case USB_ENDPOINT_XFER_BULK:
761 hsotg->non_periodic_channels--;
765 * Don't release reservations for periodic channels here.
766 * That's done when a periodic transfer is descheduled (i.e.
767 * when the QH is removed from the periodic schedule).
772 haintmsk = readl(hsotg->regs + HAINTMSK);
773 haintmsk &= ~(1 << chan->hc_num);
774 writel(haintmsk, hsotg->regs + HAINTMSK);
776 /* Try to queue more transfers now that there's a free channel */
777 tr_type = dwc2_hcd_select_transactions(hsotg);
778 if (tr_type != DWC2_TRANSACTION_NONE)
779 dwc2_hcd_queue_transactions(hsotg, tr_type);
783 * Halts a host channel. If the channel cannot be halted immediately because
784 * the request queue is full, this function ensures that the FIFO empty
785 * interrupt for the appropriate queue is enabled so that the halt request can
786 * be queued when there is space in the request queue.
788 * This function may also be called in DMA mode. In that case, the channel is
789 * simply released since the core always halts the channel automatically in
792 static void dwc2_halt_channel(struct dwc2_hsotg *hsotg,
793 struct dwc2_host_chan *chan, struct dwc2_qtd *qtd,
794 enum dwc2_halt_status halt_status)
797 dev_vdbg(hsotg->dev, "%s()\n", __func__);
799 if (hsotg->core_params->dma_enable > 0) {
801 dev_vdbg(hsotg->dev, "DMA enabled\n");
802 dwc2_release_channel(hsotg, chan, qtd, halt_status);
806 /* Slave mode processing */
807 dwc2_hc_halt(hsotg, chan, halt_status);
809 if (chan->halt_on_queue) {
812 dev_vdbg(hsotg->dev, "Halt on queue\n");
813 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
814 chan->ep_type == USB_ENDPOINT_XFER_BULK) {
815 dev_vdbg(hsotg->dev, "control/bulk\n");
817 * Make sure the Non-periodic Tx FIFO empty interrupt
818 * is enabled so that the non-periodic schedule will
821 gintmsk = readl(hsotg->regs + GINTMSK);
822 gintmsk |= GINTSTS_NPTXFEMP;
823 writel(gintmsk, hsotg->regs + GINTMSK);
825 dev_vdbg(hsotg->dev, "isoc/intr\n");
827 * Move the QH from the periodic queued schedule to
828 * the periodic assigned schedule. This allows the
829 * halt to be queued when the periodic schedule is
832 list_move(&chan->qh->qh_list_entry,
833 &hsotg->periodic_sched_assigned);
836 * Make sure the Periodic Tx FIFO Empty interrupt is
837 * enabled so that the periodic schedule will be
840 gintmsk = readl(hsotg->regs + GINTMSK);
841 gintmsk |= GINTSTS_PTXFEMP;
842 writel(gintmsk, hsotg->regs + GINTMSK);
848 * Performs common cleanup for non-periodic transfers after a Transfer
849 * Complete interrupt. This function should be called after any endpoint type
850 * specific handling is finished to release the host channel.
852 static void dwc2_complete_non_periodic_xfer(struct dwc2_hsotg *hsotg,
853 struct dwc2_host_chan *chan,
854 int chnum, struct dwc2_qtd *qtd,
855 enum dwc2_halt_status halt_status)
857 dev_vdbg(hsotg->dev, "%s()\n", __func__);
859 qtd->error_count = 0;
861 if (chan->hcint & HCINTMSK_NYET) {
863 * Got a NYET on the last transaction of the transfer. This
864 * means that the endpoint should be in the PING state at the
865 * beginning of the next transfer.
867 dev_vdbg(hsotg->dev, "got NYET\n");
868 chan->qh->ping_state = 1;
872 * Always halt and release the host channel to make it available for
873 * more transfers. There may still be more phases for a control
874 * transfer or more data packets for a bulk transfer at this point,
875 * but the host channel is still halted. A channel will be reassigned
876 * to the transfer when the non-periodic schedule is processed after
877 * the channel is released. This allows transactions to be queued
878 * properly via dwc2_hcd_queue_transactions, which also enables the
879 * Tx FIFO Empty interrupt if necessary.
881 if (chan->ep_is_in) {
883 * IN transfers in Slave mode require an explicit disable to
884 * halt the channel. (In DMA mode, this call simply releases
887 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
890 * The channel is automatically disabled by the core for OUT
891 * transfers in Slave mode
893 dwc2_release_channel(hsotg, chan, qtd, halt_status);
898 * Performs common cleanup for periodic transfers after a Transfer Complete
899 * interrupt. This function should be called after any endpoint type specific
900 * handling is finished to release the host channel.
902 static void dwc2_complete_periodic_xfer(struct dwc2_hsotg *hsotg,
903 struct dwc2_host_chan *chan, int chnum,
904 struct dwc2_qtd *qtd,
905 enum dwc2_halt_status halt_status)
907 u32 hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
909 qtd->error_count = 0;
911 if (!chan->ep_is_in || (hctsiz & TSIZ_PKTCNT_MASK) == 0)
912 /* Core halts channel in these cases */
913 dwc2_release_channel(hsotg, chan, qtd, halt_status);
915 /* Flush any outstanding requests from the Tx queue */
916 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
919 static int dwc2_xfercomp_isoc_split_in(struct dwc2_hsotg *hsotg,
920 struct dwc2_host_chan *chan, int chnum,
921 struct dwc2_qtd *qtd)
923 struct dwc2_hcd_iso_packet_desc *frame_desc;
929 frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
930 len = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
931 DWC2_HC_XFER_COMPLETE, NULL);
933 qtd->complete_split = 0;
934 qtd->isoc_split_offset = 0;
938 frame_desc->actual_length += len;
940 if (chan->align_buf && len) {
941 dev_dbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
942 dma_sync_single_for_cpu(hsotg->dev, qtd->urb->dma,
943 qtd->urb->length, DMA_FROM_DEVICE);
944 memcpy(qtd->urb->buf + frame_desc->offset +
945 qtd->isoc_split_offset, chan->qh->dw_align_buf, len);
946 dma_sync_single_for_device(hsotg->dev, qtd->urb->dma,
947 qtd->urb->length, DMA_FROM_DEVICE);
950 qtd->isoc_split_offset += len;
952 if (frame_desc->actual_length >= frame_desc->length) {
953 frame_desc->status = 0;
954 qtd->isoc_frame_index++;
955 qtd->complete_split = 0;
956 qtd->isoc_split_offset = 0;
959 if (qtd->isoc_frame_index == qtd->urb->packet_count) {
960 dwc2_host_complete(hsotg, qtd->urb->priv, qtd->urb, 0);
961 dwc2_release_channel(hsotg, chan, qtd,
962 DWC2_HC_XFER_URB_COMPLETE);
964 dwc2_release_channel(hsotg, chan, qtd,
965 DWC2_HC_XFER_NO_HALT_STATUS);
968 return 1; /* Indicates that channel released */
972 * Handles a host channel Transfer Complete interrupt. This handler may be
973 * called in either DMA mode or Slave mode.
975 static void dwc2_hc_xfercomp_intr(struct dwc2_hsotg *hsotg,
976 struct dwc2_host_chan *chan, int chnum,
977 struct dwc2_qtd *qtd)
979 struct dwc2_hcd_urb *urb = qtd->urb;
980 int pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
981 enum dwc2_halt_status halt_status = DWC2_HC_XFER_COMPLETE;
986 "--Host Channel %d Interrupt: Transfer Complete--\n",
989 if (hsotg->core_params->dma_desc_enable > 0) {
990 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, halt_status);
991 if (pipe_type == USB_ENDPOINT_XFER_ISOC)
992 /* Do not disable the interrupt, just clear it */
994 goto handle_xfercomp_done;
997 /* Handle xfer complete on CSPLIT */
998 if (chan->qh->do_split) {
999 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
1000 hsotg->core_params->dma_enable > 0) {
1001 if (qtd->complete_split &&
1002 dwc2_xfercomp_isoc_split_in(hsotg, chan, chnum,
1004 goto handle_xfercomp_done;
1006 qtd->complete_split = 0;
1011 goto handle_xfercomp_done;
1013 /* Update the QTD and URB states */
1014 switch (pipe_type) {
1015 case USB_ENDPOINT_XFER_CONTROL:
1016 switch (qtd->control_phase) {
1017 case DWC2_CONTROL_SETUP:
1018 if (urb->length > 0)
1019 qtd->control_phase = DWC2_CONTROL_DATA;
1021 qtd->control_phase = DWC2_CONTROL_STATUS;
1022 dev_vdbg(hsotg->dev,
1023 " Control setup transaction done\n");
1024 halt_status = DWC2_HC_XFER_COMPLETE;
1026 case DWC2_CONTROL_DATA:
1027 urb_xfer_done = dwc2_update_urb_state(hsotg, chan,
1029 if (urb_xfer_done) {
1030 qtd->control_phase = DWC2_CONTROL_STATUS;
1031 dev_vdbg(hsotg->dev,
1032 " Control data transfer done\n");
1034 dwc2_hcd_save_data_toggle(hsotg, chan, chnum,
1037 halt_status = DWC2_HC_XFER_COMPLETE;
1039 case DWC2_CONTROL_STATUS:
1040 dev_vdbg(hsotg->dev, " Control transfer complete\n");
1041 if (urb->status == -EINPROGRESS)
1043 dwc2_host_complete(hsotg, urb->priv, urb, urb->status);
1044 halt_status = DWC2_HC_XFER_URB_COMPLETE;
1048 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1051 case USB_ENDPOINT_XFER_BULK:
1052 dev_vdbg(hsotg->dev, " Bulk transfer complete\n");
1053 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1055 if (urb_xfer_done) {
1056 dwc2_host_complete(hsotg, urb->priv, urb, urb->status);
1057 halt_status = DWC2_HC_XFER_URB_COMPLETE;
1059 halt_status = DWC2_HC_XFER_COMPLETE;
1062 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1063 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1066 case USB_ENDPOINT_XFER_INT:
1067 dev_vdbg(hsotg->dev, " Interrupt transfer complete\n");
1068 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1072 * Interrupt URB is done on the first transfer complete
1075 if (urb_xfer_done) {
1076 dwc2_host_complete(hsotg, urb->priv, urb,
1078 halt_status = DWC2_HC_XFER_URB_COMPLETE;
1080 halt_status = DWC2_HC_XFER_COMPLETE;
1083 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1084 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1087 case USB_ENDPOINT_XFER_ISOC:
1089 dev_vdbg(hsotg->dev, " Isochronous transfer complete\n");
1090 if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_ALL)
1091 halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1092 chnum, qtd, DWC2_HC_XFER_COMPLETE);
1093 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1098 handle_xfercomp_done:
1099 disable_hc_int(hsotg, chnum, HCINTMSK_XFERCOMPL);
1103 * Handles a host channel STALL interrupt. This handler may be called in
1104 * either DMA mode or Slave mode.
1106 static void dwc2_hc_stall_intr(struct dwc2_hsotg *hsotg,
1107 struct dwc2_host_chan *chan, int chnum,
1108 struct dwc2_qtd *qtd)
1110 struct dwc2_hcd_urb *urb = qtd->urb;
1111 int pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
1113 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: STALL Received--\n",
1116 if (hsotg->core_params->dma_desc_enable > 0) {
1117 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1118 DWC2_HC_XFER_STALL);
1119 goto handle_stall_done;
1123 goto handle_stall_halt;
1125 if (pipe_type == USB_ENDPOINT_XFER_CONTROL)
1126 dwc2_host_complete(hsotg, urb->priv, urb, -EPIPE);
1128 if (pipe_type == USB_ENDPOINT_XFER_BULK ||
1129 pipe_type == USB_ENDPOINT_XFER_INT) {
1130 dwc2_host_complete(hsotg, urb->priv, urb, -EPIPE);
1132 * USB protocol requires resetting the data toggle for bulk
1133 * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
1134 * setup command is issued to the endpoint. Anticipate the
1135 * CLEAR_FEATURE command since a STALL has occurred and reset
1136 * the data toggle now.
1138 chan->qh->data_toggle = 0;
1142 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_STALL);
1145 disable_hc_int(hsotg, chnum, HCINTMSK_STALL);
1149 * Updates the state of the URB when a transfer has been stopped due to an
1150 * abnormal condition before the transfer completes. Modifies the
1151 * actual_length field of the URB to reflect the number of bytes that have
1152 * actually been transferred via the host channel.
1154 static void dwc2_update_urb_state_abn(struct dwc2_hsotg *hsotg,
1155 struct dwc2_host_chan *chan, int chnum,
1156 struct dwc2_hcd_urb *urb,
1157 struct dwc2_qtd *qtd,
1158 enum dwc2_halt_status halt_status)
1160 u32 xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum,
1161 qtd, halt_status, NULL);
1164 if (urb->actual_length + xfer_length > urb->length) {
1165 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__);
1166 xfer_length = urb->length - urb->actual_length;
1169 /* Non DWORD-aligned buffer case handling */
1170 if (chan->align_buf && xfer_length && chan->ep_is_in) {
1171 dev_dbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
1172 dma_sync_single_for_cpu(hsotg->dev, urb->dma, urb->length,
1174 memcpy(urb->buf + urb->actual_length, chan->qh->dw_align_buf,
1176 dma_sync_single_for_device(hsotg->dev, urb->dma, urb->length,
1180 urb->actual_length += xfer_length;
1182 hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
1183 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
1184 __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
1185 dev_vdbg(hsotg->dev, " chan->start_pkt_count %d\n",
1186 chan->start_pkt_count);
1187 dev_vdbg(hsotg->dev, " hctsiz.pktcnt %d\n",
1188 hctsiz >> TSIZ_PKTCNT_SHIFT &
1189 TSIZ_PKTCNT_MASK >> TSIZ_PKTCNT_SHIFT);
1190 dev_vdbg(hsotg->dev, " chan->max_packet %d\n", chan->max_packet);
1191 dev_vdbg(hsotg->dev, " bytes_transferred %d\n",
1193 dev_vdbg(hsotg->dev, " urb->actual_length %d\n",
1194 urb->actual_length);
1195 dev_vdbg(hsotg->dev, " urb->transfer_buffer_length %d\n",
1200 * Handles a host channel NAK interrupt. This handler may be called in either
1201 * DMA mode or Slave mode.
1203 static void dwc2_hc_nak_intr(struct dwc2_hsotg *hsotg,
1204 struct dwc2_host_chan *chan, int chnum,
1205 struct dwc2_qtd *qtd)
1208 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NAK Received--\n",
1212 * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
1213 * interrupt. Re-start the SSPLIT transfer.
1215 if (chan->do_split) {
1216 if (chan->complete_split)
1217 qtd->error_count = 0;
1218 qtd->complete_split = 0;
1219 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1220 goto handle_nak_done;
1223 switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1224 case USB_ENDPOINT_XFER_CONTROL:
1225 case USB_ENDPOINT_XFER_BULK:
1226 if (hsotg->core_params->dma_enable > 0 && chan->ep_is_in) {
1228 * NAK interrupts are enabled on bulk/control IN
1229 * transfers in DMA mode for the sole purpose of
1230 * resetting the error count after a transaction error
1231 * occurs. The core will continue transferring data.
1233 qtd->error_count = 0;
1238 * NAK interrupts normally occur during OUT transfers in DMA
1239 * or Slave mode. For IN transfers, more requests will be
1240 * queued as request queue space is available.
1242 qtd->error_count = 0;
1244 if (!chan->qh->ping_state) {
1245 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1246 qtd, DWC2_HC_XFER_NAK);
1247 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1249 if (chan->speed == USB_SPEED_HIGH)
1250 chan->qh->ping_state = 1;
1254 * Halt the channel so the transfer can be re-started from
1255 * the appropriate point or the PING protocol will
1258 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1260 case USB_ENDPOINT_XFER_INT:
1261 qtd->error_count = 0;
1262 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1264 case USB_ENDPOINT_XFER_ISOC:
1265 /* Should never get called for isochronous transfers */
1266 dev_err(hsotg->dev, "NACK interrupt for ISOC transfer\n");
1271 disable_hc_int(hsotg, chnum, HCINTMSK_NAK);
1275 * Handles a host channel ACK interrupt. This interrupt is enabled when
1276 * performing the PING protocol in Slave mode, when errors occur during
1277 * either Slave mode or DMA mode, and during Start Split transactions.
1279 static void dwc2_hc_ack_intr(struct dwc2_hsotg *hsotg,
1280 struct dwc2_host_chan *chan, int chnum,
1281 struct dwc2_qtd *qtd)
1283 struct dwc2_hcd_iso_packet_desc *frame_desc;
1286 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: ACK Received--\n",
1289 if (chan->do_split) {
1290 /* Handle ACK on SSPLIT. ACK should not occur in CSPLIT. */
1291 if (!chan->ep_is_in &&
1292 chan->data_pid_start != DWC2_HC_PID_SETUP)
1293 qtd->ssplit_out_xfer_count = chan->xfer_len;
1295 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC || chan->ep_is_in) {
1296 qtd->complete_split = 1;
1297 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1300 switch (chan->xact_pos) {
1301 case DWC2_HCSPLT_XACTPOS_ALL:
1303 case DWC2_HCSPLT_XACTPOS_END:
1304 qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL;
1305 qtd->isoc_split_offset = 0;
1307 case DWC2_HCSPLT_XACTPOS_BEGIN:
1308 case DWC2_HCSPLT_XACTPOS_MID:
1310 * For BEGIN or MID, calculate the length for
1311 * the next microframe to determine the correct
1312 * SSPLIT token, either MID or END
1314 frame_desc = &qtd->urb->iso_descs[
1315 qtd->isoc_frame_index];
1316 qtd->isoc_split_offset += 188;
1318 if (frame_desc->length - qtd->isoc_split_offset
1320 qtd->isoc_split_pos =
1321 DWC2_HCSPLT_XACTPOS_END;
1323 qtd->isoc_split_pos =
1324 DWC2_HCSPLT_XACTPOS_MID;
1329 qtd->error_count = 0;
1331 if (chan->qh->ping_state) {
1332 chan->qh->ping_state = 0;
1334 * Halt the channel so the transfer can be re-started
1335 * from the appropriate point. This only happens in
1336 * Slave mode. In DMA mode, the ping_state is cleared
1337 * when the transfer is started because the core
1338 * automatically executes the PING, then the transfer.
1340 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1345 * If the ACK occurred when _not_ in the PING state, let the channel
1346 * continue transferring data after clearing the error count
1348 disable_hc_int(hsotg, chnum, HCINTMSK_ACK);
1352 * Handles a host channel NYET interrupt. This interrupt should only occur on
1353 * Bulk and Control OUT endpoints and for complete split transactions. If a
1354 * NYET occurs at the same time as a Transfer Complete interrupt, it is
1355 * handled in the xfercomp interrupt handler, not here. This handler may be
1356 * called in either DMA mode or Slave mode.
1358 static void dwc2_hc_nyet_intr(struct dwc2_hsotg *hsotg,
1359 struct dwc2_host_chan *chan, int chnum,
1360 struct dwc2_qtd *qtd)
1363 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NYET Received--\n",
1368 * re-do the CSPLIT immediately on non-periodic
1370 if (chan->do_split && chan->complete_split) {
1371 if (chan->ep_is_in && chan->ep_type == USB_ENDPOINT_XFER_ISOC &&
1372 hsotg->core_params->dma_enable > 0) {
1373 qtd->complete_split = 0;
1374 qtd->isoc_split_offset = 0;
1376 ++qtd->isoc_frame_index == qtd->urb->packet_count) {
1377 dwc2_host_complete(hsotg, qtd->urb->priv,
1379 dwc2_release_channel(hsotg, chan, qtd,
1380 DWC2_HC_XFER_URB_COMPLETE);
1382 dwc2_release_channel(hsotg, chan, qtd,
1383 DWC2_HC_XFER_NO_HALT_STATUS);
1385 goto handle_nyet_done;
1388 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1389 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1390 int frnum = dwc2_hcd_get_frame_number(hsotg);
1392 if (dwc2_full_frame_num(frnum) !=
1393 dwc2_full_frame_num(chan->qh->sched_frame)) {
1395 * No longer in the same full speed frame.
1396 * Treat this as a transaction error.
1400 * Todo: Fix system performance so this can
1401 * be treated as an error. Right now complete
1402 * splits cannot be scheduled precisely enough
1403 * due to other system activity, so this error
1404 * occurs regularly in Slave mode.
1408 qtd->complete_split = 0;
1409 dwc2_halt_channel(hsotg, chan, qtd,
1410 DWC2_HC_XFER_XACT_ERR);
1411 /* Todo: add support for isoc release */
1412 goto handle_nyet_done;
1416 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1417 goto handle_nyet_done;
1420 chan->qh->ping_state = 1;
1421 qtd->error_count = 0;
1423 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, qtd,
1425 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1428 * Halt the channel and re-start the transfer so the PING protocol
1431 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1434 disable_hc_int(hsotg, chnum, HCINTMSK_NYET);
1438 * Handles a host channel babble interrupt. This handler may be called in
1439 * either DMA mode or Slave mode.
1441 static void dwc2_hc_babble_intr(struct dwc2_hsotg *hsotg,
1442 struct dwc2_host_chan *chan, int chnum,
1443 struct dwc2_qtd *qtd)
1445 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Babble Error--\n",
1448 if (hsotg->core_params->dma_desc_enable > 0) {
1449 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1450 DWC2_HC_XFER_BABBLE_ERR);
1451 goto handle_babble_done;
1454 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
1456 dwc2_host_complete(hsotg, qtd->urb->priv, qtd->urb,
1458 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_BABBLE_ERR);
1460 enum dwc2_halt_status halt_status;
1462 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1463 qtd, DWC2_HC_XFER_BABBLE_ERR);
1464 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1468 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1469 disable_hc_int(hsotg, chnum, HCINTMSK_BBLERR);
1473 * Handles a host channel AHB error interrupt. This handler is only called in
1476 static void dwc2_hc_ahberr_intr(struct dwc2_hsotg *hsotg,
1477 struct dwc2_host_chan *chan, int chnum,
1478 struct dwc2_qtd *qtd)
1480 struct dwc2_hcd_urb *urb = qtd->urb;
1481 char *pipetype, *speed;
1487 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: AHB Error--\n",
1491 goto handle_ahberr_halt;
1493 hcchar = readl(hsotg->regs + HCCHAR(chnum));
1494 hcsplt = readl(hsotg->regs + HCSPLT(chnum));
1495 hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
1496 hc_dma = readl(hsotg->regs + HCDMA(chnum));
1498 dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum);
1499 dev_err(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt);
1500 dev_err(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", hctsiz, hc_dma);
1501 dev_err(hsotg->dev, " Device address: %d\n",
1502 dwc2_hcd_get_dev_addr(&urb->pipe_info));
1503 dev_err(hsotg->dev, " Endpoint: %d, %s\n",
1504 dwc2_hcd_get_ep_num(&urb->pipe_info),
1505 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
1507 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
1508 case USB_ENDPOINT_XFER_CONTROL:
1509 pipetype = "CONTROL";
1511 case USB_ENDPOINT_XFER_BULK:
1514 case USB_ENDPOINT_XFER_INT:
1515 pipetype = "INTERRUPT";
1517 case USB_ENDPOINT_XFER_ISOC:
1518 pipetype = "ISOCHRONOUS";
1521 pipetype = "UNKNOWN";
1525 dev_err(hsotg->dev, " Endpoint type: %s\n", pipetype);
1527 switch (chan->speed) {
1528 case USB_SPEED_HIGH:
1531 case USB_SPEED_FULL:
1542 dev_err(hsotg->dev, " Speed: %s\n", speed);
1544 dev_err(hsotg->dev, " Max packet size: %d\n",
1545 dwc2_hcd_get_mps(&urb->pipe_info));
1546 dev_err(hsotg->dev, " Data buffer length: %d\n", urb->length);
1547 dev_err(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n",
1548 urb->buf, (unsigned long)urb->dma);
1549 dev_err(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n",
1550 urb->setup_packet, (unsigned long)urb->setup_dma);
1551 dev_err(hsotg->dev, " Interval: %d\n", urb->interval);
1553 /* Core halts the channel for Descriptor DMA mode */
1554 if (hsotg->core_params->dma_desc_enable > 0) {
1555 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1556 DWC2_HC_XFER_AHB_ERR);
1557 goto handle_ahberr_done;
1560 dwc2_host_complete(hsotg, urb->priv, urb, -EIO);
1564 * Force a channel halt. Don't call dwc2_halt_channel because that won't
1565 * write to the HCCHARn register in DMA mode to force the halt.
1567 dwc2_hc_halt(hsotg, chan, DWC2_HC_XFER_AHB_ERR);
1570 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1571 disable_hc_int(hsotg, chnum, HCINTMSK_AHBERR);
1575 * Handles a host channel transaction error interrupt. This handler may be
1576 * called in either DMA mode or Slave mode.
1578 static void dwc2_hc_xacterr_intr(struct dwc2_hsotg *hsotg,
1579 struct dwc2_host_chan *chan, int chnum,
1580 struct dwc2_qtd *qtd)
1583 "--Host Channel %d Interrupt: Transaction Error--\n", chnum);
1585 if (hsotg->core_params->dma_desc_enable > 0) {
1586 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1587 DWC2_HC_XFER_XACT_ERR);
1588 goto handle_xacterr_done;
1591 switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1592 case USB_ENDPOINT_XFER_CONTROL:
1593 case USB_ENDPOINT_XFER_BULK:
1595 if (!chan->qh->ping_state) {
1597 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1598 qtd, DWC2_HC_XFER_XACT_ERR);
1599 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1600 if (!chan->ep_is_in && chan->speed == USB_SPEED_HIGH)
1601 chan->qh->ping_state = 1;
1605 * Halt the channel so the transfer can be re-started from
1606 * the appropriate point or the PING protocol will start
1608 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1610 case USB_ENDPOINT_XFER_INT:
1612 if (chan->do_split && chan->complete_split)
1613 qtd->complete_split = 0;
1614 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1616 case USB_ENDPOINT_XFER_ISOC:
1618 enum dwc2_halt_status halt_status;
1620 halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1621 chnum, qtd, DWC2_HC_XFER_XACT_ERR);
1622 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1627 handle_xacterr_done:
1628 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1629 disable_hc_int(hsotg, chnum, HCINTMSK_XACTERR);
1633 * Handles a host channel frame overrun interrupt. This handler may be called
1634 * in either DMA mode or Slave mode.
1636 static void dwc2_hc_frmovrun_intr(struct dwc2_hsotg *hsotg,
1637 struct dwc2_host_chan *chan, int chnum,
1638 struct dwc2_qtd *qtd)
1640 enum dwc2_halt_status halt_status;
1643 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Frame Overrun--\n",
1646 switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1647 case USB_ENDPOINT_XFER_CONTROL:
1648 case USB_ENDPOINT_XFER_BULK:
1650 case USB_ENDPOINT_XFER_INT:
1651 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1653 case USB_ENDPOINT_XFER_ISOC:
1654 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1655 qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1656 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1660 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1661 disable_hc_int(hsotg, chnum, HCINTMSK_FRMOVRUN);
1665 * Handles a host channel data toggle error interrupt. This handler may be
1666 * called in either DMA mode or Slave mode.
1668 static void dwc2_hc_datatglerr_intr(struct dwc2_hsotg *hsotg,
1669 struct dwc2_host_chan *chan, int chnum,
1670 struct dwc2_qtd *qtd)
1673 "--Host Channel %d Interrupt: Data Toggle Error--\n", chnum);
1676 qtd->error_count = 0;
1679 "Data Toggle Error on OUT transfer, channel %d\n",
1682 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1683 disable_hc_int(hsotg, chnum, HCINTMSK_DATATGLERR);
1687 * For debug only. It checks that a valid halt status is set and that
1688 * HCCHARn.chdis is clear. If there's a problem, corrective action is
1689 * taken and a warning is issued.
1691 * Return: true if halt status is ok, false otherwise
1693 static bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg,
1694 struct dwc2_host_chan *chan, int chnum,
1695 struct dwc2_qtd *qtd)
1703 if (chan->halt_status == DWC2_HC_XFER_NO_HALT_STATUS) {
1705 * This code is here only as a check. This condition should
1706 * never happen. Ignore the halt if it does occur.
1708 hcchar = readl(hsotg->regs + HCCHAR(chnum));
1709 hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
1710 hcintmsk = readl(hsotg->regs + HCINTMSK(chnum));
1711 hcsplt = readl(hsotg->regs + HCSPLT(chnum));
1713 "%s: chan->halt_status DWC2_HC_XFER_NO_HALT_STATUS,\n",
1716 "channel %d, hcchar 0x%08x, hctsiz 0x%08x,\n",
1717 chnum, hcchar, hctsiz);
1719 "hcint 0x%08x, hcintmsk 0x%08x, hcsplt 0x%08x,\n",
1720 chan->hcint, hcintmsk, hcsplt);
1722 dev_dbg(hsotg->dev, "qtd->complete_split %d\n",
1723 qtd->complete_split);
1724 dev_warn(hsotg->dev,
1725 "%s: no halt status, channel %d, ignoring interrupt\n",
1731 * This code is here only as a check. hcchar.chdis should never be set
1732 * when the halt interrupt occurs. Halt the channel again if it does
1735 hcchar = readl(hsotg->regs + HCCHAR(chnum));
1736 if (hcchar & HCCHAR_CHDIS) {
1737 dev_warn(hsotg->dev,
1738 "%s: hcchar.chdis set unexpectedly, hcchar 0x%08x, trying to halt again\n",
1740 chan->halt_pending = 0;
1741 dwc2_halt_channel(hsotg, chan, qtd, chan->halt_status);
1750 * Handles a host Channel Halted interrupt in DMA mode. This handler
1751 * determines the reason the channel halted and proceeds accordingly.
1753 static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg,
1754 struct dwc2_host_chan *chan, int chnum,
1755 struct dwc2_qtd *qtd)
1758 int out_nak_enh = 0;
1761 dev_vdbg(hsotg->dev,
1762 "--Host Channel %d Interrupt: DMA Channel Halted--\n",
1766 * For core with OUT NAK enhancement, the flow for high-speed
1767 * CONTROL/BULK OUT is handled a little differently
1769 if (hsotg->snpsid >= DWC2_CORE_REV_2_71a) {
1770 if (chan->speed == USB_SPEED_HIGH && !chan->ep_is_in &&
1771 (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1772 chan->ep_type == USB_ENDPOINT_XFER_BULK)) {
1777 if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
1778 (chan->halt_status == DWC2_HC_XFER_AHB_ERR &&
1779 hsotg->core_params->dma_desc_enable <= 0)) {
1780 if (hsotg->core_params->dma_desc_enable > 0)
1781 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1785 * Just release the channel. A dequeue can happen on a
1786 * transfer timeout. In the case of an AHB Error, the
1787 * channel was forced to halt because there's no way to
1788 * gracefully recover.
1790 dwc2_release_channel(hsotg, chan, qtd,
1795 hcintmsk = readl(hsotg->regs + HCINTMSK(chnum));
1797 if (chan->hcint & HCINTMSK_XFERCOMPL) {
1799 * Todo: This is here because of a possible hardware bug. Spec
1800 * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
1801 * interrupt w/ACK bit set should occur, but I only see the
1802 * XFERCOMP bit, even with it masked out. This is a workaround
1803 * for that behavior. Should fix this when hardware is fixed.
1805 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && !chan->ep_is_in)
1806 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1807 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
1808 } else if (chan->hcint & HCINTMSK_STALL) {
1809 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
1810 } else if ((chan->hcint & HCINTMSK_XACTERR) &&
1811 hsotg->core_params->dma_desc_enable <= 0) {
1814 (HCINTMSK_NYET | HCINTMSK_NAK | HCINTMSK_ACK)) {
1815 dev_vdbg(hsotg->dev,
1816 "XactErr with NYET/NAK/ACK\n");
1817 qtd->error_count = 0;
1819 dev_vdbg(hsotg->dev,
1820 "XactErr without NYET/NAK/ACK\n");
1825 * Must handle xacterr before nak or ack. Could get a xacterr
1826 * at the same time as either of these on a BULK/CONTROL OUT
1827 * that started with a PING. The xacterr takes precedence.
1829 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1830 } else if ((chan->hcint & HCINTMSK_XCS_XACT) &&
1831 hsotg->core_params->dma_desc_enable > 0) {
1832 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1833 } else if ((chan->hcint & HCINTMSK_AHBERR) &&
1834 hsotg->core_params->dma_desc_enable > 0) {
1835 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
1836 } else if (chan->hcint & HCINTMSK_BBLERR) {
1837 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
1838 } else if (chan->hcint & HCINTMSK_FRMOVRUN) {
1839 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
1840 } else if (!out_nak_enh) {
1841 if (chan->hcint & HCINTMSK_NYET) {
1843 * Must handle nyet before nak or ack. Could get a nyet
1844 * at the same time as either of those on a BULK/CONTROL
1845 * OUT that started with a PING. The nyet takes
1848 dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
1849 } else if ((chan->hcint & HCINTMSK_NAK) &&
1850 !(hcintmsk & HCINTMSK_NAK)) {
1852 * If nak is not masked, it's because a non-split IN
1853 * transfer is in an error state. In that case, the nak
1854 * is handled by the nak interrupt handler, not here.
1855 * Handle nak here for BULK/CONTROL OUT transfers, which
1856 * halt on a NAK to allow rewinding the buffer pointer.
1858 dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
1859 } else if ((chan->hcint & HCINTMSK_ACK) &&
1860 !(hcintmsk & HCINTMSK_ACK)) {
1862 * If ack is not masked, it's because a non-split IN
1863 * transfer is in an error state. In that case, the ack
1864 * is handled by the ack interrupt handler, not here.
1865 * Handle ack here for split transfers. Start splits
1868 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1870 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1871 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1873 * A periodic transfer halted with no other
1874 * channel interrupts set. Assume it was halted
1875 * by the core because it could not be completed
1876 * in its scheduled (micro)frame.
1879 "%s: Halt channel %d (assume incomplete periodic transfer)\n",
1881 dwc2_halt_channel(hsotg, chan, qtd,
1882 DWC2_HC_XFER_PERIODIC_INCOMPLETE);
1885 "%s: Channel %d - ChHltd set, but reason is unknown\n",
1888 "hcint 0x%08x, intsts 0x%08x\n",
1890 readl(hsotg->regs + GINTSTS));
1894 dev_info(hsotg->dev,
1895 "NYET/NAK/ACK/other in non-error case, 0x%08x\n",
1901 * Handles a host channel Channel Halted interrupt
1903 * In slave mode, this handler is called only when the driver specifically
1904 * requests a halt. This occurs during handling other host channel interrupts
1905 * (e.g. nak, xacterr, stall, nyet, etc.).
1907 * In DMA mode, this is the interrupt that occurs when the core has finished
1908 * processing a transfer on a channel. Other host channel interrupts (except
1909 * ahberr) are disabled in DMA mode.
1911 static void dwc2_hc_chhltd_intr(struct dwc2_hsotg *hsotg,
1912 struct dwc2_host_chan *chan, int chnum,
1913 struct dwc2_qtd *qtd)
1916 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: Channel Halted--\n",
1919 if (hsotg->core_params->dma_enable > 0) {
1920 dwc2_hc_chhltd_intr_dma(hsotg, chan, chnum, qtd);
1922 if (!dwc2_halt_status_ok(hsotg, chan, chnum, qtd))
1924 dwc2_release_channel(hsotg, chan, qtd, chan->halt_status);
1928 /* Handles interrupt for a specific Host Channel */
1929 static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum)
1931 struct dwc2_qtd *qtd;
1932 struct dwc2_host_chan *chan;
1933 u32 hcint, hcintmsk;
1935 chan = hsotg->hc_ptr_array[chnum];
1938 dev_vdbg(hsotg->dev, "--Host Channel Interrupt--, Channel %d\n",
1941 hcint = readl(hsotg->regs + HCINT(chnum));
1942 hcintmsk = readl(hsotg->regs + HCINTMSK(chnum));
1944 dev_vdbg(hsotg->dev,
1945 " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
1946 hcint, hcintmsk, hcint & hcintmsk);
1949 dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n");
1950 writel(hcint, hsotg->regs + HCINT(chnum));
1954 writel(hcint, hsotg->regs + HCINT(chnum));
1955 chan->hcint = hcint;
1959 * If the channel was halted due to a dequeue, the qtd list might
1960 * be empty or at least the first entry will not be the active qtd.
1961 * In this case, take a shortcut and just release the channel.
1963 if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE) {
1965 * If the channel was halted, this should be the only
1966 * interrupt unmasked
1968 WARN_ON(hcint != HCINTMSK_CHHLTD);
1969 if (hsotg->core_params->dma_desc_enable > 0)
1970 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1973 dwc2_release_channel(hsotg, chan, NULL,
1978 if (list_empty(&chan->qh->qtd_list)) {
1980 * TODO: Will this ever happen with the
1981 * DWC2_HC_XFER_URB_DEQUEUE handling above?
1983 dev_dbg(hsotg->dev, "## no QTD queued for channel %d ##\n",
1986 " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
1987 chan->hcint, hcintmsk, hcint);
1988 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
1989 disable_hc_int(hsotg, chnum, HCINTMSK_CHHLTD);
1994 qtd = list_first_entry(&chan->qh->qtd_list, struct dwc2_qtd,
1997 if (hsotg->core_params->dma_enable <= 0) {
1998 if ((hcint & HCINTMSK_CHHLTD) && hcint != HCINTMSK_CHHLTD)
1999 hcint &= ~HCINTMSK_CHHLTD;
2002 if (hcint & HCINTMSK_XFERCOMPL) {
2003 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
2005 * If NYET occurred at same time as Xfer Complete, the NYET is
2006 * handled by the Xfer Complete interrupt handler. Don't want
2007 * to call the NYET interrupt handler in this case.
2009 hcint &= ~HCINTMSK_NYET;
2011 if (hcint & HCINTMSK_CHHLTD)
2012 dwc2_hc_chhltd_intr(hsotg, chan, chnum, qtd);
2013 if (hcint & HCINTMSK_AHBERR)
2014 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
2015 if (hcint & HCINTMSK_STALL)
2016 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
2017 if (hcint & HCINTMSK_NAK)
2018 dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
2019 if (hcint & HCINTMSK_ACK)
2020 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
2021 if (hcint & HCINTMSK_NYET)
2022 dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
2023 if (hcint & HCINTMSK_XACTERR)
2024 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
2025 if (hcint & HCINTMSK_BBLERR)
2026 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
2027 if (hcint & HCINTMSK_FRMOVRUN)
2028 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
2029 if (hcint & HCINTMSK_DATATGLERR)
2030 dwc2_hc_datatglerr_intr(hsotg, chan, chnum, qtd);
2036 * This interrupt indicates that one or more host channels has a pending
2037 * interrupt. There are multiple conditions that can cause each host channel
2038 * interrupt. This function determines which conditions have occurred for each
2039 * host channel interrupt and handles them appropriately.
2041 static void dwc2_hc_intr(struct dwc2_hsotg *hsotg)
2046 haint = readl(hsotg->regs + HAINT);
2048 dev_vdbg(hsotg->dev, "%s()\n", __func__);
2050 dev_vdbg(hsotg->dev, "HAINT=%08x\n", haint);
2053 for (i = 0; i < hsotg->core_params->host_channels; i++) {
2054 if (haint & (1 << i))
2055 dwc2_hc_n_intr(hsotg, i);
2059 /* This function handles interrupts for the HCD */
2060 irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg)
2062 u32 gintsts, dbg_gintsts;
2063 irqreturn_t retval = IRQ_NONE;
2065 if (dwc2_check_core_status(hsotg) < 0) {
2066 dev_warn(hsotg->dev, "Controller is disconnected\n");
2070 spin_lock(&hsotg->lock);
2072 /* Check if HOST Mode */
2073 if (dwc2_is_host_mode(hsotg)) {
2074 gintsts = dwc2_read_core_intr(hsotg);
2076 spin_unlock(&hsotg->lock);
2080 retval = IRQ_HANDLED;
2082 dbg_gintsts = gintsts;
2084 dbg_gintsts &= ~GINTSTS_SOF;
2087 dbg_gintsts &= ~(GINTSTS_HCHINT | GINTSTS_RXFLVL |
2090 /* Only print if there are any non-suppressed interrupts left */
2092 dev_vdbg(hsotg->dev,
2093 "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n",
2096 if (gintsts & GINTSTS_SOF)
2097 dwc2_sof_intr(hsotg);
2098 if (gintsts & GINTSTS_RXFLVL)
2099 dwc2_rx_fifo_level_intr(hsotg);
2100 if (gintsts & GINTSTS_NPTXFEMP)
2101 dwc2_np_tx_fifo_empty_intr(hsotg);
2102 if (gintsts & GINTSTS_PRTINT)
2103 dwc2_port_intr(hsotg);
2104 if (gintsts & GINTSTS_HCHINT)
2105 dwc2_hc_intr(hsotg);
2106 if (gintsts & GINTSTS_PTXFEMP)
2107 dwc2_perio_tx_fifo_empty_intr(hsotg);
2110 dev_vdbg(hsotg->dev,
2111 "DWC OTG HCD Finished Servicing Interrupts\n");
2112 dev_vdbg(hsotg->dev,
2113 "DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n",
2114 readl(hsotg->regs + GINTSTS),
2115 readl(hsotg->regs + GINTMSK));
2119 spin_unlock(&hsotg->lock);