2 * EMXX FCD (Function Controller Driver) for USB.
4 * Copyright (C) 2010 Renesas Electronics Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2
8 * as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
24 /*---------------------------------------------------------------------------*/
25 /*----------------- Default undef */
28 #define UDC_DEBUG_DUMP
31 /*----------------- Default define */
33 #define USE_SUSPEND_WAIT 1
43 /*------------ Board dependence(Resource) */
44 #define VBUS_VALUE GPIO_VBUS
46 /* below hacked up for staging integration */
47 #define GPIO_VBUS 0 /* GPIO_P153 on KZM9D */
48 #define INT_VBUS 0 /* IRQ for GPIO_P153 */
50 /*------------ Board dependence(Wait) */
52 /* CHATTERING wait time ms */
53 #define VBUS_CHATTERING_MDELAY 1
54 /* DMA Abort wait time ms */
55 #define DMA_DISABLE_TIME 10
59 /*------------ Controller dependence */
60 #define NUM_ENDPOINTS 14 /* Endpoint */
61 #define REG_EP_NUM 15 /* Endpoint Register */
62 #define DMA_MAX_COUNT 256 /* DMA Block */
66 #define EPC_RST_DISABLE_TIME 1 /* 1 usec */
67 #define EPC_DIRPD_DISABLE_TIME 1 /* 1 msec */
68 #define EPC_PLL_LOCK_COUNT 1000 /* 1000 */
69 #define IN_DATA_EMPTY_COUNT 1000 /* 1000 */
71 #define CHATGER_TIME 700 /* 700msec */
72 #define USB_SUSPEND_TIME 2000 /* 2 sec */
81 #define BIT00 0x00000001
82 #define BIT01 0x00000002
83 #define BIT02 0x00000004
84 #define BIT03 0x00000008
85 #define BIT04 0x00000010
86 #define BIT05 0x00000020
87 #define BIT06 0x00000040
88 #define BIT07 0x00000080
89 #define BIT08 0x00000100
90 #define BIT09 0x00000200
91 #define BIT10 0x00000400
92 #define BIT11 0x00000800
93 #define BIT12 0x00001000
94 #define BIT13 0x00002000
95 #define BIT14 0x00004000
96 #define BIT15 0x00008000
97 #define BIT16 0x00010000
98 #define BIT17 0x00020000
99 #define BIT18 0x00040000
100 #define BIT19 0x00080000
101 #define BIT20 0x00100000
102 #define BIT21 0x00200000
103 #define BIT22 0x00400000
104 #define BIT23 0x00800000
105 #define BIT24 0x01000000
106 #define BIT25 0x02000000
107 #define BIT26 0x04000000
108 #define BIT27 0x08000000
109 #define BIT28 0x10000000
110 #define BIT29 0x20000000
111 #define BIT30 0x40000000
112 #define BIT31 0x80000000
114 #define TEST_FORCE_ENABLE (BIT18+BIT16)
116 #define INT_SEL BIT10
117 #define CONSTFS BIT09
118 #define SOF_RCV BIT08
119 #define RSUM_IN BIT07
120 #define SUSPEND BIT06
122 #define DEFAULT BIT04
123 #define CONNECTB BIT03
126 #define MAX_TEST_MODE_NUM 0x05
127 #define TEST_MODE_SHIFT 16
129 /*------- (0x0004) USB Status Register */
130 #define SPEED_MODE BIT06
131 #define HIGH_SPEED BIT06
134 #define DEFAULT BIT04
135 #define USB_RST BIT03
136 #define SPND_OUT BIT02
137 #define RSUM_OUT BIT01
139 /*------- (0x0008) USB Address Register */
140 #define USB_ADDR 0x007F0000
141 #define SOF_STATUS BIT15
142 #define UFRAME (BIT14+BIT13+BIT12)
143 #define FRAME 0x000007FF
145 #define USB_ADRS_SHIFT 16
147 /*------- (0x000C) UTMI Characteristic 1 Register */
148 #define SQUSET (BIT07+BIT06+BIT05+BIT04)
150 #define USB_SQUSET (BIT06+BIT05+BIT04)
152 /*------- (0x0010) TEST Control Register */
153 #define FORCEHS BIT02
154 #define CS_TESTMODEEN BIT01
155 #define LOOPBACK BIT00
157 /*------- (0x0018) Setup Data 0 Register */
158 /*------- (0x001C) Setup Data 1 Register */
160 /*------- (0x0020) USB Interrupt Status Register */
161 #define EPn_INT 0x00FFFF00
162 #define EP15_INT BIT23
163 #define EP14_INT BIT22
164 #define EP13_INT BIT21
165 #define EP12_INT BIT20
166 #define EP11_INT BIT19
167 #define EP10_INT BIT18
168 #define EP9_INT BIT17
169 #define EP8_INT BIT16
170 #define EP7_INT BIT15
171 #define EP6_INT BIT14
172 #define EP5_INT BIT13
173 #define EP4_INT BIT12
174 #define EP3_INT BIT11
175 #define EP2_INT BIT10
176 #define EP1_INT BIT09
177 #define EP0_INT BIT08
178 #define SPEED_MODE_INT BIT06
179 #define SOF_ERROR_INT BIT05
180 #define SOF_INT BIT04
181 #define USB_RST_INT BIT03
182 #define SPND_INT BIT02
183 #define RSUM_INT BIT01
185 #define USB_INT_STA_RW 0x7E
187 /*------- (0x0024) USB Interrupt Enable Register */
188 #define EP15_0_EN 0x00FFFF00
189 #define EP15_EN BIT23
190 #define EP14_EN BIT22
191 #define EP13_EN BIT21
192 #define EP12_EN BIT20
193 #define EP11_EN BIT19
194 #define EP10_EN BIT18
205 #define SPEED_MODE_EN BIT06
206 #define SOF_ERROR_EN BIT05
208 #define USB_RST_EN BIT03
209 #define SPND_EN BIT02
210 #define RSUM_EN BIT01
212 #define USB_INT_EN_BIT \
213 (EP0_EN|SPEED_MODE_EN|USB_RST_EN|SPND_EN|RSUM_EN)
215 /*------- (0x0028) EP0 Control Register */
216 #define EP0_STGSEL BIT18
217 #define EP0_OVERSEL BIT17
218 #define EP0_AUTO BIT16
219 #define EP0_PIDCLR BIT09
220 #define EP0_BCLR BIT08
221 #define EP0_DEND BIT07
222 #define EP0_DW (BIT06+BIT05)
224 #define EP0_DW3 (BIT06+BIT05)
225 #define EP0_DW2 BIT06
226 #define EP0_DW1 BIT05
228 #define EP0_INAK_EN BIT04
229 #define EP0_PERR_NAK_CLR BIT03
230 #define EP0_STL BIT02
231 #define EP0_INAK BIT01
232 #define EP0_ONAK BIT00
234 /*------- (0x002C) EP0 Status Register */
235 #define EP0_PID BIT18
236 #define EP0_PERR_NAK BIT17
237 #define EP0_PERR_NAK_INT BIT16
238 #define EP0_OUT_NAK_INT BIT15
239 #define EP0_OUT_NULL BIT14
240 #define EP0_OUT_FULL BIT13
241 #define EP0_OUT_EMPTY BIT12
242 #define EP0_IN_NAK_INT BIT11
243 #define EP0_IN_DATA BIT10
244 #define EP0_IN_FULL BIT09
245 #define EP0_IN_EMPTY BIT08
246 #define EP0_OUT_NULL_INT BIT07
247 #define EP0_OUT_OR_INT BIT06
248 #define EP0_OUT_INT BIT05
249 #define EP0_IN_INT BIT04
250 #define EP0_STALL_INT BIT03
251 #define STG_END_INT BIT02
252 #define STG_START_INT BIT01
253 #define SETUP_INT BIT00
255 #define EP0_STATUS_RW_BIT (BIT16|BIT15|BIT11|0xFF)
257 /*------- (0x0030) EP0 Interrupt Enable Register */
258 #define EP0_PERR_NAK_EN BIT16
259 #define EP0_OUT_NAK_EN BIT15
261 #define EP0_IN_NAK_EN BIT11
263 #define EP0_OUT_NULL_EN BIT07
264 #define EP0_OUT_OR_EN BIT06
265 #define EP0_OUT_EN BIT05
266 #define EP0_IN_EN BIT04
267 #define EP0_STALL_EN BIT03
268 #define STG_END_EN BIT02
269 #define STG_START_EN BIT01
270 #define SETUP_EN BIT00
272 #define EP0_INT_EN_BIT \
273 (EP0_OUT_OR_EN|EP0_OUT_EN|EP0_IN_EN|STG_END_EN|SETUP_EN)
275 /*------- (0x0034) EP0 Length Register */
276 #define EP0_LDATA 0x0000007F
278 /*------- (0x0038) EP0 Read Register */
279 /*------- (0x003C) EP0 Write Register */
281 /*------- (0x0040:) EPn Control Register */
283 #define EPn_BUF_TYPE BIT30
284 #define EPn_BUF_SINGLE BIT30
286 #define EPn_DIR0 BIT26
287 #define EPn_MODE (BIT25+BIT24)
289 #define EPn_INTERRUPT BIT24
290 #define EPn_ISO BIT25
292 #define EPn_OVERSEL BIT17
293 #define EPn_AUTO BIT16
295 #define EPn_IPIDCLR BIT11
296 #define EPn_OPIDCLR BIT10
297 #define EPn_BCLR BIT09
298 #define EPn_CBCLR BIT08
299 #define EPn_DEND BIT07
300 #define EPn_DW (BIT06+BIT05)
302 #define EPn_DW3 (BIT06+BIT05)
303 #define EPn_DW2 BIT06
304 #define EPn_DW1 BIT05
306 #define EPn_OSTL_EN BIT04
307 #define EPn_ISTL BIT03
308 #define EPn_OSTL BIT02
310 #define EPn_ONAK BIT00
312 /*------- (0x0044:) EPn Status Register */
313 #define EPn_ISO_PIDERR BIT29 /* R */
314 #define EPn_OPID BIT28 /* R */
315 #define EPn_OUT_NOTKN BIT27 /* R */
316 #define EPn_ISO_OR BIT26 /* R */
318 #define EPn_ISO_CRC BIT24 /* R */
319 #define EPn_OUT_END_INT BIT23 /* RW */
320 #define EPn_OUT_OR_INT BIT22 /* RW */
321 #define EPn_OUT_NAK_ERR_INT BIT21 /* RW */
322 #define EPn_OUT_STALL_INT BIT20 /* RW */
323 #define EPn_OUT_INT BIT19 /* RW */
324 #define EPn_OUT_NULL_INT BIT18 /* RW */
325 #define EPn_OUT_FULL BIT17 /* R */
326 #define EPn_OUT_EMPTY BIT16 /* R */
328 #define EPn_IPID BIT10 /* R */
329 #define EPn_IN_NOTKN BIT09 /* R */
330 #define EPn_ISO_UR BIT08 /* R */
331 #define EPn_IN_END_INT BIT07 /* RW */
333 #define EPn_IN_NAK_ERR_INT BIT05 /* RW */
334 #define EPn_IN_STALL_INT BIT04 /* RW */
335 #define EPn_IN_INT BIT03 /* RW */
336 #define EPn_IN_DATA BIT02 /* R */
337 #define EPn_IN_FULL BIT01 /* R */
338 #define EPn_IN_EMPTY BIT00 /* R */
341 (EPn_OUT_END_INT|EPn_OUT_INT|EPn_IN_END_INT|EPn_IN_INT)
343 /*------- (0x0048:) EPn Interrupt Enable Register */
344 #define EPn_OUT_END_EN BIT23 /* RW */
345 #define EPn_OUT_OR_EN BIT22 /* RW */
346 #define EPn_OUT_NAK_ERR_EN BIT21 /* RW */
347 #define EPn_OUT_STALL_EN BIT20 /* RW */
348 #define EPn_OUT_EN BIT19 /* RW */
349 #define EPn_OUT_NULL_EN BIT18 /* RW */
351 #define EPn_IN_END_EN BIT07 /* RW */
353 #define EPn_IN_NAK_ERR_EN BIT05 /* RW */
354 #define EPn_IN_STALL_EN BIT04 /* RW */
355 #define EPn_IN_EN BIT03 /* RW */
357 /*------- (0x004C:) EPn Interrupt Enable Register */
358 #define EPn_STOP_MODE BIT11
359 #define EPn_DEND_SET BIT10
360 #define EPn_BURST_SET BIT09
361 #define EPn_STOP_SET BIT08
363 #define EPn_DMA_EN BIT04
365 #define EPn_DMAMODE0 BIT00
367 /*------- (0x0050:) EPn MaxPacket & BaseAddress Register */
368 #define EPn_BASEAD 0x1FFF0000
369 #define EPn_MPKT 0x000007FF
371 /*------- (0x0054:) EPn Length & DMA Count Register */
372 #define EPn_DMACNT 0x01FF0000
373 #define EPn_LDATA 0x000007FF
375 /*------- (0x0058:) EPn Read Register */
376 /*------- (0x005C:) EPn Write Register */
378 /*------- (0x1000) AHBSCTR Register */
379 #define WAIT_MODE BIT00
381 /*------- (0x1004) AHBMCTR Register */
382 #define ARBITER_CTR BIT31 /* RW */
383 #define MCYCLE_RST BIT12 /* RW */
385 #define ENDIAN_CTR (BIT09+BIT08) /* RW */
386 #define ENDIAN_BYTE_SWAP BIT09
387 #define ENDIAN_HALF_WORD_SWAP ENDIAN_CTR
389 #define HBUSREQ_MODE BIT05 /* RW */
390 #define HTRANS_MODE BIT04 /* RW */
392 #define WBURST_TYPE BIT02 /* RW */
393 #define BURST_TYPE (BIT01+BIT00) /* RW */
394 #define BURST_MAX_16 0
395 #define BURST_MAX_8 BIT00
396 #define BURST_MAX_4 BIT01
397 #define BURST_SINGLE BURST_TYPE
399 /*------- (0x1008) AHBBINT Register */
400 #define DMA_ENDINT 0xFFFE0000 /* RW */
402 #define AHB_VBUS_INT BIT13 /* RW */
404 #define MBUS_ERRINT BIT06 /* RW */
406 #define SBUS_ERRINT0 BIT04 /* RW */
407 #define ERR_MASTER 0x0000000F /* R */
409 /*------- (0x100C) AHBBINTEN Register */
410 #define DMA_ENDINTEN 0xFFFE0000 /* RW */
412 #define VBUS_INTEN BIT13 /* RW */
414 #define MBUS_ERRINTEN BIT06 /* RW */
416 #define SBUS_ERRINT0EN BIT04 /* RW */
418 /*------- (0x1010) EPCTR Register */
419 #define DIRPD BIT12 /* RW */
421 #define VBUS_LEVEL BIT08 /* R */
423 #define PLL_RESUME BIT05 /* RW */
424 #define PLL_LOCK BIT04 /* R */
426 #define EPC_RST BIT00 /* RW */
428 /*------- (0x1014) USBF_EPTEST Register */
429 #define LINESTATE (BIT09+BIT08) /* R */
430 #define DM_LEVEL BIT09 /* R */
431 #define DP_LEVEL BIT08 /* R */
433 #define PHY_TST BIT01 /* RW */
434 #define PHY_TSTCLK BIT00 /* RW */
436 /*------- (0x1020) USBSSVER Register */
437 #define AHBB_VER 0x00FF0000 /* R */
438 #define EPC_VER 0x0000FF00 /* R */
439 #define SS_VER 0x000000FF /* R */
441 /*------- (0x1024) USBSSCONF Register */
442 #define EP_AVAILABLE 0xFFFF0000 /* R */
443 #define DMA_AVAILABLE 0x0000FFFF /* R */
445 /*------- (0x1110:) EPnDCR1 Register */
446 #define DCR1_EPn_DMACNT 0x00FF0000 /* RW */
448 #define DCR1_EPn_DIR0 BIT01 /* RW */
449 #define DCR1_EPn_REQEN BIT00 /* RW */
451 /*------- (0x1114:) EPnDCR2 Register */
452 #define DCR2_EPn_LMPKT 0x07FF0000 /* RW */
454 #define DCR2_EPn_MPKT 0x000007FF /* RW */
456 /*------- (0x1118:) EPnTADR Register */
457 #define EPn_TADR 0xFFFFFFFF /* RW */
461 /*===========================================================================*/
465 u32 EP_CONTROL; /* EP Control */
466 u32 EP_STATUS; /* EP Status */
467 u32 EP_INT_ENA; /* EP Interrupt Enable */
468 u32 EP_DMA_CTRL; /* EP DMA Control */
469 u32 EP_PCKT_ADRS; /* EP Maxpacket & BaseAddress */
470 u32 EP_LEN_DCNT; /* EP Length & DMA count */
471 u32 EP_READ; /* EP Read */
472 u32 EP_WRITE; /* EP Write */
477 u32 EP_DCR1; /* EP_DCR1 */
478 u32 EP_DCR2; /* EP_DCR2 */
479 u32 EP_TADR; /* EP_TADR */
480 u32 Reserved; /* Reserved */
483 /*------- Function Registers */
485 u32 USB_CONTROL; /* (0x0000) USB Control */
486 u32 USB_STATUS; /* (0x0004) USB Status */
487 u32 USB_ADDRESS; /* (0x0008) USB Address */
488 u32 UTMI_CHARACTER_1; /* (0x000C) UTMI Setting */
489 u32 TEST_CONTROL; /* (0x0010) TEST Control */
490 u32 Reserved_14; /* (0x0014) Reserved */
491 u32 SETUP_DATA0; /* (0x0018) Setup Data0 */
492 u32 SETUP_DATA1; /* (0x001C) Setup Data1 */
493 u32 USB_INT_STA; /* (0x0020) USB Interrupt Status */
494 u32 USB_INT_ENA; /* (0x0024) USB Interrupt Enable */
495 u32 EP0_CONTROL; /* (0x0028) EP0 Control */
496 u32 EP0_STATUS; /* (0x002C) EP0 Status */
497 u32 EP0_INT_ENA; /* (0x0030) EP0 Interrupt Enable */
498 u32 EP0_LENGTH; /* (0x0034) EP0 Length */
499 u32 EP0_READ; /* (0x0038) EP0 Read */
500 u32 EP0_WRITE; /* (0x003C) EP0 Write */
502 struct ep_regs EP_REGS[REG_EP_NUM]; /* Endpoint Register */
504 u8 Reserved220[0x1000-0x220]; /* (0x0220:0x0FFF) Reserved */
506 u32 AHBSCTR; /* (0x1000) AHBSCTR */
507 u32 AHBMCTR; /* (0x1004) AHBMCTR */
508 u32 AHBBINT; /* (0x1008) AHBBINT */
509 u32 AHBBINTEN; /* (0x100C) AHBBINTEN */
510 u32 EPCTR; /* (0x1010) EPCTR */
511 u32 USBF_EPTEST; /* (0x1014) USBF_EPTEST */
513 u8 Reserved1018[0x20-0x18]; /* (0x1018:0x101F) Reserved */
515 u32 USBSSVER; /* (0x1020) USBSSVER */
516 u32 USBSSCONF; /* (0x1024) USBSSCONF */
518 u8 Reserved1028[0x110-0x28]; /* (0x1028:0x110F) Reserved */
520 struct ep_dcr EP_DCR[REG_EP_NUM]; /* */
522 u8 Reserved1200[0x1000-0x200]; /* Reserved */
532 #define EP0_PACKETSIZE 64
533 #define EP_PACKETSIZE 1024
536 #define D_RAM_SIZE_CTRL 64
538 /* EPn Bulk Endpoint Max Packet Size */
539 #define D_FS_RAM_SIZE_BULK 64
540 #define D_HS_RAM_SIZE_BULK 512
551 EP0_OUT_STATUS_PAHSE,
558 struct usb_request req;
559 struct list_head queue;
572 struct list_head queue;
574 struct nbu2ss_udc *udc;
576 const struct usb_endpoint_descriptor *desc;
592 struct usb_gadget gadget;
593 struct usb_gadget_driver *driver;
594 struct platform_device *pdev;
597 struct completion *pdone;
599 enum ep0_state ep0state;
600 enum usb_device_state devstate;
601 struct usb_ctrlrequest ctrl;
602 struct nbu2ss_req ep0_req;
603 u8 ep0_buf[EP0_PACKETSIZE];
605 struct nbu2ss_ep ep[NUM_ENDPOINTS];
607 unsigned softconnect:1;
608 unsigned vbus_active:1;
609 unsigned linux_suspended:1;
610 unsigned linux_resume:1;
611 unsigned usb_suspended:1;
612 unsigned remote_wakeup:1;
613 unsigned udc_enabled:1;
617 u32 curr_config; /* Current Configuration Number */
619 struct fc_regs *p_regs;
622 /* USB register access structure */
623 union usb_reg_access {
625 unsigned char DATA[4];
630 /*-------------------------------------------------------------------------*/
632 #endif /* _LINUX_EMXX_H */